Manufacturing method of floating gate split-gate flash memory

Abstract

The present invention discloses a method for manufacturing a floating gate split-gate flash memory, comprising the following steps: depositing and etching to form a third sidewall dielectric layer; using the first sidewall dielectric layer, the select gate dielectric layer, the silicon oxide layer, and the third sidewall dielectric layer as a hard mask, removing the remaining floating gate polysilicon layer, the inter-polysilicon ONO layer, and the polysilicon layer on both sides, and performing LDD injection to form an LDD region; removing the photoresist in the advanced CMOS region, re-applying photoresist, and developing so that the flash memory region covers the LDD and Halo injected into the advanced CMOS device with the photoresist; depositing and etching to form a fourth sidewall dielectric layer, and injecting source and drain to form a source-drain region. The present invention reduces the thickness of the sidewall dielectric layer of the floating gate split-gate flash memory, so that the length of the control gate is equal to the thickness of the first sidewall dielectric layer plus the thickness of the advanced third sidewall dielectric layer, thereby increasing the CG length, which is beneficial for improving the CG-FG coupling coefficient, enhancing the CG control capability, and reducing device leakage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a floating gate split-gate flash memory. Background Art

[0002] Split-gate floating-gate (FG) flash memory technology is widely used in various embedded electronic products such as financial IC cards and automotive electronics. This flash memory can improve storage integration density, save chip area and reduce manufacturing costs.

[0003] like Figures 1 to 7 The existing method for manufacturing a 2-bit / cell (two bits per storage cell) split-gate floating gate flash memory includes the following steps:

[0004] In step 1, a P-type well 101 is formed by implantation on a P-type substrate, a floating gate oxide layer 102 is grown on the P-type well 101 by thermal oxidation, and a polysilicon (Poly) layer 103 and a first silicon nitride layer 502 are deposited. An STI (Shallow-Trench-Isolation) process is performed to form a shallow trench 501. At the same time, the active areas of the flash memory and the peripheral logic area are defined.

[0005] Step 2: Deposit an ONO (Oxide-Nitride-Oxide) layer 104 between polysilicon layers, a floating gate polysilicon layer 105, and a thick silicon nitride layer 503 in sequence; define the flash memory cell area by photolithography, and etch away the thick silicon nitride layer in the opening area.

[0006] Step three, deposit a silicon oxide layer, and use anisotropic etching to form a first sidewall dielectric layer 113. The bottom width of the sidewall dielectric layer defines the length of the control gate. Using the first sidewall dielectric layer as a hard mask, anisotropically etch the control gate polysilicon to form a self-aligned control gate, and etch the ONO layer between the polysilicon. Deposit an insulating dielectric layer, and anisotropically etch to form a second sidewall dielectric layer 106. Using the second sidewall dielectric layer and the first sidewall dielectric layer together as a hard mask, self-aligned etching is performed to form a floating gate. Deposit a select gate dielectric layer 107 and a select gate polysilicon layer 108 in sequence, and form a self-aligned select gate by CMP (Chemical Mechanical Polish). Thermal oxidation forms a silicon oxide layer 114 above the select gate polysilicon layer 108.

[0007] Step 4: Using the first spacer dielectric layer 113, the select gate dielectric layer 107, and the silicon oxide layer 114 as hard masks, the remaining thick silicon nitride layer 503 on both sides is removed by wet isotropic etching;

[0008] In step five, the first sidewall dielectric layer 113, the gate dielectric layer 107, and the silicon oxide layer 114 are used as hard masks (while the advanced CMOS area is covered with photoresist), and the remaining floating gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the polysilicon layer 103 on both sides are removed by anisotropic etching, and LDD implantation is performed in sequence to form an LDD region 109.

[0009] Step six: deposit and etch to form a third spacer dielectric layer 110 (ie, the first spacer dielectric layer of the advanced CMOS device), and selectively implant LDD / Halo regions in the advanced CMOS region.

[0010] Step seven: depositing and etching to form a fourth spacer dielectric layer 111 (ie, the second spacer dielectric layer of the advanced CMOS device), and implanting source and drain to form source and drain regions 112.

[0011] Further scaling of 2-bit / cell floating-gate split-gate flash memory devices revealed that the CG-to-FG coupling coefficient decreased significantly due to the reduction in the overlap area between the CG (Control Gate) and the FG. While the overlap area between the WL (Word Line) and the FG remained essentially unchanged, the WL-to-FG coupling coefficient increased rapidly. This rapid increase in the WL coupling coefficient degraded the device's CG turn-off capability (CG control capability), leading to severe leakage and, in other words, deteriorated the current characteristics of the flash memory subdomains. Therefore, increasing the CG coupling coefficient (i.e., increasing the overlap area between the CG and the FG) and reducing the WL coupling coefficient are crucial for further scaling of floating-gate split-gate flash memory. In this device, the first and second spacer dielectric layers in advanced CMOS devices serve as the third and fourth spacer dielectric layers, respectively, of the flash memory cells. Due to the relatively thick third and fourth spacers, this hinders device scaling and warrants further improvement. Summary of the Invention

[0012] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a method for manufacturing a floating gate split-gate flash memory.

[0013] The present invention solves the above technical problems through the following technical solutions: a method for manufacturing a floating gate split-gate flash memory, characterized in that it includes the following steps:

[0014] Step 11: implanting a P-type well on the P-type substrate, growing a floating gate oxide layer on the P-type well by thermal oxidation, and depositing a polysilicon layer and a first silicon nitride layer; performing an STI process to form a shallow trench;

[0015] Step 12, sequentially depositing an inter-polysilicon ONO layer, a floating gate polysilicon layer, and a thick silicon nitride layer;

[0016] Step 13: depositing a silicon oxide layer and forming a first spacer dielectric layer by anisotropic etching; using the first spacer dielectric layer as a hard mask, anisotropically etching the control gate polysilicon to form a self-aligned control gate, and etching the ONO layer between the polysilicon; depositing an insulating dielectric layer and anisotropically etching to form a second spacer dielectric layer; using the second spacer dielectric layer and the first spacer dielectric layer as a hard mask, self-aligned etching to form a floating gate and a floating gate dielectric layer; sequentially depositing a select gate dielectric layer and a select gate polysilicon layer, and forming a self-aligned select gate by CMP; thermally oxidizing to form a silicon oxide layer on the select gate polysilicon layer;

[0017] Step 14: Using the first spacer dielectric layer, the select gate dielectric layer, and the silicon oxide layer as hard masks, the remaining thick silicon nitride layer on both sides is removed by wet isotropic etching;

[0018] Step 15: depositing and etching to form a third sidewall dielectric layer;

[0019] Step 16: Photolithography is performed to open the flash memory area while covering the advanced CMOS area with photoresist. The first sidewall dielectric layer, the select gate dielectric layer, the silicon oxide layer, and the third sidewall dielectric layer are used as hard masks to remove the remaining floating gate polysilicon layer, the inter-polysilicon ONO layer, and the polysilicon layer. LDD implantation is then performed in the flash memory area to form an LDD region.

[0020] Step 17: remove the photoresist in the advanced CMOS area, apply photoresist again and develop it so that the flash memory area is covered with photoresist. At the same time, open the advanced CMOS area by photolithography, and self-align implant the LDD and Halo of the advanced CMOS device.

[0021] Step eighteen: depositing and etching to form a fourth sidewall dielectric layer, and implanting source and drain to form source and drain regions.

[0022] Preferably, the step eleven defines active areas of the flash memory and the peripheral logic area.

[0023] Preferably, the bottom width of the first spacer dielectric layer plus the bottom width of the third spacer dielectric layer defines the length of the control gate.

[0024] Preferably, the inter-polysilicon ONO layer includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer, and the second silicon nitride layer is located between the second silicon oxide layer and the third silicon oxide layer.

[0025] Preferably, in step twelve, the flash memory cell area is defined by photolithography, and the thick silicon nitride layer in the opening area is removed by etching.

[0026] Preferably, the select gate dielectric layer is arc-shaped.

[0027] Preferably, the steps 12, 13, 15 and 18 are all deposited using a chemical or physical vapor deposition process.

[0028] Preferably, the etching process for forming the third sidewall dielectric layer is placed before the sixteenth process of removing the remaining floating gate polysilicon layer, the inter-polysilicon ONO layer, and the polysilicon layer on both sides.

[0029] The present invention significantly improves the floating-gate split-gate flash memory by reducing the thickness of the spacer dielectric layer. By placing the existing third spacer dielectric layer process before the second CG / ONO / FG etching, the control gate length is equal to the thickness of the first spacer dielectric layer plus the thickness of the advanced third spacer dielectric layer. This increases the CG length, which improves the CG-FG coupling coefficient, enhances the CG control capability, and reduces device leakage. Because the increased CG length is equal to the reduced spacer thickness, the flash memory cell area is not increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 7 A diagram showing the process steps of a split-gate floating gate flash memory in the prior art.

[0031] Figures 8 to 11 This is a process diagram of the floating gate split-gate flash memory of the present invention. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0033] The manufacturing method of the floating gate type split gate flash memory of the present invention comprises the following steps:

[0034] In step 11 (same as step 1), a P-type well 101 is formed by implantation on the P-type substrate, a floating gate oxide layer 102 is grown on the P-type well 101 by thermal oxidation, and a polysilicon (Poly) layer 103 and a first silicon nitride layer 502 are deposited. An STI (Shallow-Trench-Isolation) process is performed to form a shallow trench 501. At the same time, the active areas of the flash memory and the peripheral logic area are defined.

[0035] In step 12 (same as step 2), an ONO (Oxide-Nitride-Oxide, oxide / nitride / oxide) layer 104 between polysilicon layers, a floating gate polysilicon layer 105, and a thick silicon nitride layer 503 are sequentially deposited; the flash memory cell area is defined by photolithography, and the thick silicon nitride layer in the opening area is removed by etching.

[0036] Step 13 (same as step 3): deposit a silicon oxide layer and use anisotropic etching to form a first spacer dielectric layer 113. The bottom width of the first spacer dielectric layer plus the bottom width of the third spacer dielectric layer defines the length of the control gate; use the first spacer dielectric layer as a hard mask to anisotropically etch the control gate polysilicon to form a self-aligned control gate, and etch the ONO layer between the polysilicon; deposit an insulating dielectric layer and anisotropically etch to form a second spacer dielectric layer 106. Use the second spacer dielectric layer and the first spacer dielectric layer together as a hard mask to self-alignedly etch to form a floating gate and a floating gate dielectric layer; deposit a select gate dielectric layer 107 and a select gate polysilicon layer 108 in sequence, and form a self-aligned select gate by CMP (Chemical Mechanical Polish); thermally oxidize to form a silicon oxide layer 114 on the select gate polysilicon layer 108.

[0037] Step 14 (same as step 4): using the first spacer dielectric layer 113, the select gate dielectric layer 107, and the silicon oxide layer 114 as hard masks, the remaining thick silicon nitride layer 503 on both sides is removed by wet isotropic etching;

[0038] Step 15: Figure 8 As shown, a third spacer dielectric layer 110 (ie, the second spacer dielectric layer of the advanced CMOS device) is formed by deposition and etching;

[0039] Step 16: Figure 9 As shown, the flash memory area is opened by photolithography, and the first spacer dielectric layer 113, the select gate dielectric layer 107, the silicon oxide layer 114, and the third spacer dielectric layer 110 are used as hard masks (while the advanced CMOS area is covered with photoresist), and the remaining floating gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the polysilicon layer 103 on both sides are removed, and LDD implantation is performed in the flash memory area to form an LDD region 109;

[0040] Step 17: Figure 10 As shown, the photoresist in the advanced CMOS region is removed, and the photoresist is applied again and developed so that the flash memory region is covered with the photoresist 505. At the same time, the advanced CMOS region is opened by photolithography, and LDD and Halo of the advanced CMOS device are self-alignedly implanted.

[0041] Step 18, such as Figure 11 As shown, a fourth spacer dielectric layer 111 (ie, a second spacer dielectric layer of the advanced CMOS device) is formed by deposition and etching, and source and drain regions 112 are formed by source and drain implantation.

[0042] The inter-polysilicon ONO layer 104 includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer. The second silicon nitride layer is located between the second silicon oxide layer and the third silicon oxide layer, and can obtain a higher critical electric field strength and a lower defect density.

[0043] The shape of the select gate dielectric layer 107 is arc-shaped. Since it is formed by deposition, it is deposited on the substrate, the second spacer dielectric layer 106 and other sidewall surfaces at the same time.

[0044] Step 12, step 13, step 15, and step 18 are all deposited using a chemical or physical vapor deposition process, which can control the density and purity of the coating.

[0045] In summary, the present invention reduces the thickness of the spacer dielectric layer in floating-gate split-gate flash memory and places the existing third spacer dielectric layer process before the second CG / ONO / FG etching. This ensures that the control gate length equals the thickness of the first spacer dielectric layer plus the thickness of the advanced third spacer dielectric layer. This increases the CG length, which helps improve the CG-FG coupling coefficient, enhances the CG's control capability, and reduces device leakage. Because the increased CG length is equal to the reduced spacer thickness, the flash memory cell area is not increased.

[0046] The above specific implementation manner is a preferred embodiment of the present invention and does not limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A method for manufacturing a floating gate split-gate flash memory, characterized in that: It includes the following steps: Step 11: implanting a P-type well on the P-type substrate, growing a floating gate oxide layer on the P-type well by thermal oxidation, and depositing a polysilicon layer and a first silicon nitride layer; performing an STI process to form a shallow trench; Step 12, sequentially depositing an inter-polysilicon ONO layer, a floating gate polysilicon layer, and a thick silicon nitride layer; Step 13: depositing a silicon oxide layer and forming a first sidewall dielectric layer by anisotropic etching; Using the first sidewall dielectric layer as a hard mask, anisotropically etching the control gate polysilicon to form a self-aligned control gate, and etching the ONO layer between the polysilicon; Depositing an insulating dielectric layer and anisotropically etching to form a second sidewall dielectric layer; using the second sidewall dielectric layer and the first sidewall dielectric layer together as a hard mask, self-aligned etching to form a floating gate and a floating gate dielectric layer; sequentially depositing a select gate dielectric layer and a select gate polysilicon layer, and forming a self-aligned select gate by CMP; thermally oxidizing the select gate polysilicon layer to form a silicon oxide layer above the select gate polysilicon layer; Step 14: Using the first spacer dielectric layer, the select gate dielectric layer, and the silicon oxide layer as hard masks, the remaining thick silicon nitride layer on both sides is removed by wet isotropic etching; Step 15: depositing and etching to form a third sidewall dielectric layer; Step 16: Photolithography is performed to open the flash memory area and cover the CMOS area with photoresist. The first sidewall dielectric layer, the select gate dielectric layer, the silicon oxide layer, and the third sidewall dielectric layer are used as hard masks to remove the remaining floating gate polysilicon layer, the inter-polysilicon ONO layer, and the polysilicon layer. LDD implantation is then performed on the flash memory area to form an LDD region. Step 17: remove the photoresist in the advanced CMOS area, apply photoresist again and develop it so that the flash memory area is covered with photoresist. At the same time, open the advanced CMOS area by photolithography, and self-align implant the LDD and Halo of the advanced CMOS device. Step eighteen: depositing and etching to form a fourth sidewall dielectric layer, and implanting source and drain to form source and drain regions.

2. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The step eleven defines the active areas of the flash memory and the peripheral logic area.

3. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The bottom width of the first spacer dielectric layer plus the bottom width of the third spacer dielectric layer defines the length of the control gate.

4. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The inter-polysilicon ONO layer includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer, and the second silicon nitride layer is located between the second silicon oxide layer and the third silicon oxide layer.

5. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The twelve step defines the flash memory cell area by photolithography, and removes the thick silicon nitride layer in the opening area by etching.

6. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The select gate dielectric layer is in an arc shape.

7. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The steps 12, 13, 15 and 18 are all deposited using chemical or physical vapor deposition processes.

8. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The etching process for forming the third sidewall dielectric layer is placed before the sixteenth process of removing the remaining floating gate polysilicon layer, the inter-polysilicon ONO layer, and the polysilicon layer on both sides.

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