3D NAND memory device and method of manufacturing the same

Abstract

The application provides a 3D NAND memory device and a manufacturing method thereof. A plurality of storage areas are separated by a pseudo storage area. A stack layer is etched to form a plurality of gate line isolation gaps and pseudo channel holes in the pseudo storage area. An insulating layer is formed on the sidewall of the gate line isolation gap to form a connection hole in the gate line isolation gap. A metal is filled in the connection hole to form a contact plug in the gate line isolation gap. Finally, an electrical connection is formed from one side surface of the 3D NAND memory device to the opposite side surface through a plurality of contact plugs. As can be seen, the application can form sufficient contact plugs in the 3D NAND memory device by forming the contact plug in the gate line isolation gap, and can avoid reducing the area of the storage area in the memory device, thereby improving the performance of the memory device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their manufacturing, and particularly to a 3D NAND memory device and its manufacturing method. Background Technology

[0002] NAND flash memory devices are non-volatile memory products with low power consumption, light weight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND flash memory devices have been proposed.

[0003] However, current 3D NAND storage devices have insufficient storage performance and cannot meet the needs of high-performance storage. Summary of the Invention

[0004] This application provides a 3D NAND memory device and a method for manufacturing the same, which can form sufficient contact plugs in the 3D NAND memory device to improve the performance of the memory device.

[0005] This application provides a method for manufacturing a 3D NAND memory device, including:

[0006] A substrate is provided on which a stack of sacrificial layers and dielectric layers are formed alternately;

[0007] The stacked layer is etched to form a plurality of gate isolation gaps and a plurality of pseudo-channel vias in the stacked layer. The gate isolation gaps and the pseudo-channel vias penetrate the stacked layer to the substrate. A gate isolation gap is formed between two adjacent pseudo-channel vias. The plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, which divides the stacked layer into a plurality of memory regions.

[0008] An insulating layer is formed on the sidewall of the gate line isolation gap to form a connection hole in the gate line isolation gap, the connection hole penetrating the insulating layer to the substrate; the connection hole is then filled with metal.

[0009] Optionally, the grid isolation gap includes a first isolation gap and a second isolation gap, wherein the first isolation gap is close to the storage area;

[0010] Also includes:

[0011] Etching is performed from the substrate to form a contact hole penetrating the substrate; the contact hole exposes the metal filling the connection hole of the second isolation gap;

[0012] The contact hole is then filled with metal.

[0013] Optionally, it also includes:

[0014] Etching is performed from the substrate to form a first isolation via through the substrate; the first isolation via is adjacent to the storage region and exposes the metal filling the connection hole of the first isolation gap;

[0015] The insulating material is filled into the first isolation through hole to form a first deep trench isolation layer.

[0016] Optionally, it also includes:

[0017] Etching is performed from the substrate to form a second isolation via through the substrate; the second isolation via exposes the dummy channel via;

[0018] The insulating material is filled into the second isolation via to form a second deep trench isolation layer, thereby isolating the two adjacent contact holes in the substrate.

[0019] Optionally, before performing metal filling of the contact hole, the method further includes:

[0020] Deposited insulating materials;

[0021] Remove the insulating material at the bottom of the contact hole, while retaining the insulating material on the sidewalls of the contact hole;

[0022] The contact holes are wet-cleaned.

[0023] Optionally, a channel hole is formed in the stacked layer of the storage region, the channel hole penetrates the stacked layer to the substrate, and a storage functional layer and a channel layer are sequentially formed in the channel hole;

[0024] Before filling the insulating layer into the grid line isolation gap, the method further includes:

[0025] The sacrificial layer is removed by using the grid lines to isolate the gaps, thus forming an opening;

[0026] A gate layer is formed in the opening.

[0027] Optionally, after filling the connection hole with metal, the process further includes:

[0028] A bonding layer is formed on the stacked layers, the bonding layer comprising a metal bonding layer;

[0029] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0030] This application provides a 3D NAND storage device, including:

[0031] A substrate on which a stack of sacrificial layers and dielectric layers are alternately stacked;

[0032] The stacked layer has a plurality of gate isolation gaps and a plurality of pseudo-channel vias formed therein. The gate isolation gaps and the pseudo-channel vias penetrate the stacked layer to the substrate. A gate isolation gap is formed between two adjacent pseudo-channel vias. The plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, which divides the stacked layer into a plurality of memory regions.

[0033] An insulating layer and a connection hole are formed in the gate line isolation gap; the connection hole penetrates the insulating layer to the substrate;

[0034] The connection hole is filled with metal.

[0035] Optionally, it also includes:

[0036] A contact hole that penetrates the substrate to expose the metal within the connection hole, and a first isolation contact hole and a second isolation contact hole that penetrate the substrate;

[0037] The contact hole is filled with metal, a first deep trench isolation layer is formed in the first isolation contact hole, and a second deep trench isolation layer is formed in the second isolation contact hole.

[0038] Optionally, it also includes:

[0039] A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer;

[0040] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0041] The 3D NAND memory device and its manufacturing method provided in this application separate multiple memory regions through pseudo memory regions. A stacked layer is etched to form multiple gate isolation gaps and pseudo-channel vias in the pseudo memory regions. An insulating layer is formed on the sidewalls of the gate isolation gaps to form connection holes within the gaps. Metal is filled into the connection holes to form contact plugs within the gate isolation gaps. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Therefore, by forming contact plugs within the gate isolation gaps, this application can form sufficient contact plugs in the 3D NAND memory device and avoid reducing the area occupied by the memory regions, thereby improving the performance of the memory device. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This paper shows a schematic diagram of the structure of a 3D NAND memory device according to an embodiment of this application;

[0044] Figure 2 A flowchart illustrating a method for manufacturing a 3D NAND memory device according to an embodiment of this application is shown;

[0045] Figures 3-6 This paper shows a schematic diagram of the structure of a 3D NAND memory device according to an embodiment of this application;

[0046] Figure 7 This paper shows a top view of a 3D NAND memory device according to an embodiment of this application;

[0047] Figures 8-12 A schematic diagram of the structure of another 3D NAND memory device according to an embodiment of this application is shown. Detailed Implementation

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0050] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0051] refer to Figure 1As shown, multiple storage regions 100 in a 3D NAND memory device are isolated and distinguished only by a gate isolation structure 210 and a small pseudo-storage region 200. This can increase the proportion of storage regions in the 3D NAND memory device and improve storage performance. However, in this type of 3D NAND memory device, there is no spare area to form sufficient contact plugs, which prevents electrical signals from being transmitted from one side of the 3D NAND memory device to the opposite side, ultimately leading to a decrease in memory device performance.

[0052] Based on this, embodiments of this application provide a 3D NAND memory device and its manufacturing method. Multiple memory regions are separated by pseudo-memory regions. A stacked layer is etched to form multiple gate isolation gaps and pseudo-channel vias in the pseudo-memory regions. An insulating layer is formed on the sidewalls of the gate isolation gaps to form connection holes within the gaps. Metal is filled into the connection holes to form contact plugs within the gate isolation gaps. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Therefore, by forming contact plugs within the gate isolation gaps, this application can form sufficient contact plugs in the 3D NAND memory device and avoid reducing the area occupied by the memory regions, thereby improving the performance of the memory device.

[0053] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0054] refer to Figure 2 The image shows a method for manufacturing a 3D NAND memory device according to an embodiment of this application. This method may include:

[0055] S201, a substrate 100 is provided, on which a stacked layer 110 of alternating sacrificial layers 111 and dielectric layers 112 is formed, reference. Figure 3 As shown.

[0056] In the embodiments of this application, the substrate 100 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also include substrates of other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as a Si / SiGe substrate, or other epitaxial structures, such as SGOI (Silicon On Germanium). In this embodiment, the substrate 100 is a silicon substrate.

[0057] In embodiments of this application, a stacked layer 110 may be formed on the substrate 100, as shown in the reference. Figure 3 As shown. A portion of the stacked layer 110 is used to form a string of memory cells perpendicular to the substrate direction. The string of memory cells has a storage function. The number of layers in the stacked layer 130 is determined by the number of memory cell layers in the formed 3D NAND memory device. The more layers in the stacked layer 130, the more memory cells are contained in the formed string of memory cells, and the higher the integration of the device.

[0058] The stacked layer 110 may include a sacrificial layer 111 and a dielectric layer 112. The sacrificial layer 111 occupies the site for the subsequent formation of the gate layer, and the dielectric layer 112 isolates the sacrificial layer 111. After the sacrificial layer 111 is replaced by the gate layer, the dielectric layer 112 isolates the gate layer to prevent gate layer contact. The dielectric layer 112 may be, for example, a silicon oxide layer, and the sacrificial layer 111 may be, for example, a silicon nitride layer.

[0059] The stacked layer 110 can be formed by a single deck, for example, by alternating layers of sacrificial layer 111 and dielectric layer 112, or by sequentially stacking dual-deck layers, or by sequentially stacking multiple sub-decks, for example, by first alternately stacking portions of sacrificial layer 111 and dielectric layer 112 to form a sub-deck. In a specific embodiment, chemical vapor deposition, atomic layer deposition, or other suitable deposition methods can be used to sequentially and alternately deposit sacrificial layer 111 and dielectric layer 112 to form the stacked layer 110.

[0060] S202, the stacked layer 110 is etched to form a plurality of gate isolation gaps 121 / 122 and a plurality of pseudo-channel vias 130 in the stacked layer 110. The gate isolation gaps 121 / 122 and the pseudo-channel vias 130 penetrate the stacked layer 110 to the substrate 100. A gate isolation gap 121 / 122 is formed between two adjacent pseudo-channel vias 130. The plurality of gate isolation gaps 121 / 122 and the plurality of pseudo-channel vias 130 are formed in a pseudo memory region 1000. The pseudo memory region 1000 divides the stacked layer 110 into a plurality of memory regions 2000. (Reference) Figure 4 As shown.

[0061] In embodiments of this application, after forming a stacked layer 110 on the substrate 100, the stacked layer 110 can be etched to form a plurality of gate line isolation gaps 121 / 122 and a plurality of pseudo-channel vias 130. The region where the plurality of gate line isolation gaps 121 / 122 and the plurality of pseudo-channel vias 130 are located is a pseudo memory region 1000. The pseudo memory region 1000 divides the stacked layer 110 into a plurality of memory regions 2000, and the stacked layer 110 of the memory regions is used to form memory cells.

[0062] In the embodiments of this application, the stacked layer 110 can be etched using etching techniques, such as reactive ion etching, until the surface of the substrate 100 is reached, thereby forming gate isolation gaps 121 / 122 and pseudo-channel vias 130 that penetrate from the stacked layer 110 to the substrate 100. (Refer to...) Figure 4 As shown, the formation processes of the grid isolation gaps 121 / 122 and the pseudo-channel holes 130 can be performed simultaneously to save on process steps and reduce manufacturing costs.

[0063] In the embodiments of this application, a grid line isolation gap 121 / 122 is formed between two adjacent pseudo-channel holes 130, that is, the grid line isolation gap 121 / 122 and the pseudo-channel hole 130 are spaced apart. The pseudo-channel hole 130 serves to support the pseudo storage region 1000 after subsequent filling with insulating material. The grid line isolation gap 121 / 122 is formed between the storage region 2000 and the pseudo-channel hole 130 closest to the storage region, so that the grid line isolation gap 121 / 122 isolates the pseudo storage region 1000 and the storage region 2000.

[0064] S203, an insulating layer 140 is formed on the sidewall of the gate line isolation gap 121 / 122 to form a connection hole 150 in the gate line isolation gap 121 / 122, the connection hole 150 penetrating the insulating layer 140 to the substrate 100, reference. Figure 5 As shown.

[0065] In embodiments of this application, after forming a plurality of gate line isolation gaps 121 / 122 by etching the stacked layer 110, in order to enable isolation through the gate line isolation gaps 121 / 122, insulating material can be deposited on the sidewalls of the gate line isolation gaps 121 / 122 to form an insulating layer 140 on the sidewalls of the gate line isolation gaps 121 / 122. (Refer to...) Figure 5 As shown. The insulating layer 140 can be a single-layer structure, such as silicon nitride, silicon oxide, silicon oxynitride, etc., or a multi-layer structure, such as a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. The insulating layer 140 can be deposited by chemical vapor deposition (CVD). In this embodiment, the insulating layer 140 is a silicon oxide layer.

[0066] In the embodiments of this application, after depositing insulating material on the sidewalls of the gate isolation gaps 121 / 122, insulating material is also deposited at the bottom of the gate isolation gaps 121 / 122. The insulating material at the bottom of the gate isolation gaps 121 / 122 can be removed using an etching process, leaving the substrate 100 at the bottom of the gate isolation gaps 121 / 122 intact, while retaining the insulating material on the sidewalls of the gate isolation gaps 121 / 122, thus forming an insulating layer 140 on the sidewalls of the gate isolation gaps 121 / 122. Specifically, a dry etching process can be used to remove the insulating material at the bottom of the gate isolation gaps 121 / 122. The dry etching process can utilize chlorine gas or a fluorine-containing gas, where the fluorine-containing gas can be carbon tetrafluoride (CF4).

[0067] In embodiments of this application, the gate isolation gaps 121 / 122 may include a first isolation gap 121 and a second isolation gap 122. The first isolation gap 121 is close to the storage region 2000 and is used to isolate memory cells subsequently formed in different storage regions. The second isolation gap 122 is away from the storage region 2000 and is used to form connection holes in the second isolation gap 122 to increase the number of contact plugs in the 3D NAND memory device, thereby improving device performance.

[0068] In the embodiments of this application, when depositing insulating material on the sidewalls of the gate isolation gaps 121 / 122, insulating material can also be filled in the pseudo-channel holes 130 to support the pseudo-memory region 1000. Such a process can reduce the device manufacturing cost.

[0069] In embodiments of this application, after depositing an insulating layer 140 on the sidewalls of a plurality of gate line isolation gaps 121 / 122, a connection hole 150 is formed in the gate line isolation gaps 121 / 122. The connection hole 150 extends to the substrate 100 and is used for subsequent formation of contact plugs, providing sufficient channels for realizing electrical connections between the first surface and the second surface of the memory device, which are two opposing surfaces of the memory device.

[0070] As one possible implementation, the insulating layer 140 can be formed only on the sidewall of the second isolation gap 122, thereby forming the connection hole 150 in the second isolation gap 122, while the first isolation gap 121 is completely filled with the insulating layer. (Refer to...) Figure 5 As shown.

[0071] In practical applications, the second isolation gap 122 will form a contact plug in the future. Therefore, when the second isolation gap 122 and the first isolation gap 121 are formed by etching the stacked layer 110, the size of the second isolation gap 122 is slightly larger than the size of the first isolation gap 121.

[0072] In embodiments of this application, forming a connection hole in the gate line isolation gap can also be achieved by filling the gate line isolation gap with an insulating layer, etching the insulating layer to form the connection hole, and the connection hole penetrating the insulating layer to the substrate. However, this method adds an additional etching process to form the connection hole, increasing manufacturing costs. Forming an insulating layer only on the sidewalls of the gate line isolation gap utilizes existing process steps and does not increase manufacturing costs.

[0073] S204, perform metal filling of the connection hole 150.

[0074] In the embodiments of this application, after forming an insulating layer 140 on the sidewall of the grid isolation gaps 121 / 122 to obtain the connection hole 150, the connection hole 150 can be filled. (Refer to...) Figure 6 As shown. Since the connection hole 150 is for forming a contact plug to achieve electrical connection between the first and second surfaces of the storage device, the filling layer 160 in the connection hole 150 is a conductive material, such as a metal material like copper or tungsten. In this embodiment, the material of the filling layer 160 is tungsten.

[0075] refer to Figure 7 The image shown is a top view of a 3D NAND memory device provided in an embodiment of this application. Figure 6 The schematic diagram of the 3D NAND memory device shown is from... Figure 7 It is obtained by truncating along the AA direction.

[0076] from Figure 7As can be seen, the first isolation gap 121 isolates the pseudo-memory region 1000 and the memory region 2000. Multiple second isolation gaps 122 are provided within the pseudo-memory region, and each second isolation gap 122 forms one or more connection holes 150. These connection holes 150 are filled with metal to form contact plugs. The shape of the connection holes is not specifically limited in this embodiment and can be set according to actual conditions. When multiple connection holes 150 are formed within each second isolation gap 122, the number of connection holes 150 and the distance between them can be set according to actual conditions. The connection holes 150 within different second isolation gaps 122 are isolated on the substrate by a deep trench isolation layer to isolate the signals transmitted by the metal within the connection holes 150 of different second isolation gaps 122 on the substrate. The connection holes 144 within different second isolation gaps 122 can be arranged in an array. Therefore, the method provided in this application embodiment separates multiple memory regions through pseudo memory regions. A stacked layer is etched to form multiple gate line isolation gaps and pseudo-channel vias in the pseudo memory regions. An insulating layer is formed on the sidewalls of the gate line isolation gaps to form connection holes within the gaps. Metal is filled into the connection holes to form contact plugs within the gate line isolation gaps. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Thus, this application, by forming contact plugs within the gate line isolation gaps, can form sufficient contact plugs within the 3D NAND memory device without utilizing separate areas to additionally form contact plugs, thus not reducing the area occupied by the memory regions on the memory device wafer. In other words, the method in this application embodiment can increase the number of contact plugs without reducing the area occupied by the memory regions on the memory device wafer, thereby improving the performance of the memory device.

[0077] In addition, during the formation of the connection hole, only an insulating layer needs to be formed on the sidewall of the gate line isolation gap, without the need to etch the stacked layer, thus reducing the process difficulty.

[0078] In the embodiments of this application, a connection hole 150 is formed in the gate isolation gap 121 / 122 of the stacked layer 110, and after the connection hole 150 is filled with metal, a bonding layer can be formed on the stacked layer 110. The material of the bonding layer can be a dielectric material. A metal bonding layer is formed in the bonding layer, and the metal bonding layer is electrically connected to the metal in the connection hole 150 for subsequent electrical connection when bonding with other wafers or devices.

[0079] In the embodiments of this application, after forming a connection hole 150 in the second isolation gap 122 and filling the connection hole 150 with metal, the substrate 100 can be etched to obtain a contact hole 170 penetrating the substrate 100, and the contact hole 170 is filled with metal to form an electrical connection between the metal in the contact hole 170 and the metal in the connection hole 150.

[0080] Specifically, substrate 100 has opposing first and second surfaces. A stacked layer 110 is formed on the first surface of substrate 100, followed by the formation of a connection hole 150. Etching is performed from the second surface of substrate 100 to form a contact hole 170 penetrating substrate 100. The contact hole 170 exposes the metal filling the connection hole 150 within the second isolation gap 122. (Refer to...) Figure 8 As shown.

[0081] After the contact hole 170 is formed, an insulating material 180 can be deposited, thus covering the bottom and sidewalls of the contact hole 170 with the insulating material 180. (See reference...) Figure 9 As shown. The insulating material 180 can be formed into a single-layer structure, such as silicon nitride, silicon oxide, silicon oxynitride, etc., or it can be formed into a multilayer structure, such as a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. In this embodiment, the insulating material can be silicon oxide. The insulating material can be deposited by chemical vapor deposition (CVD). The insulating material 180 is used for insulation and isolation between the metal filler material subsequently formed in the contact hole 170 and the substrate 100, thereby improving the reliability and performance of the device.

[0082] In embodiments of this application, after depositing the insulating material, the insulating material at the bottom of the contact hole 170 can be removed using an etching process to expose the metal filling the connection hole 150 of the second isolation gap 122, while retaining the insulating material 180 on the sidewalls of the contact hole 170. (Refer to...) Figure 10 As shown. Specifically, the insulating material at the bottom of contact hole 170 can be removed using a dry etching process. The dry etching process can utilize chlorine gas or a fluorine-containing gas, such as carbon tetrafluoride (CF4).

[0083] After removing the insulating material at the bottom of contact hole 170 using an etching process, contact hole 170 can be cleaned using a wet cleaning process to remove any residue left after etching. Following wet cleaning, metal is filled into contact hole 170 to form contact 190 for subsequent electrical lead-out. (See reference...) Figure 11 As shown. A conductive material, such as copper or tungsten, is filled into the contact hole 170. In this embodiment, the conductive material is tungsten.

[0084] In an embodiment of this application, a first isolation gap 121 is located near the storage region 2000. An insulating layer 140 is filled in the first isolation gap, and the insulating layer 140 is etched to obtain a connection hole 150. After the connection hole 150 is filled with metal, it is used to isolate the memory cells subsequently formed in different storage regions. To isolate the substrates 100 of different storage regions, etching can be performed on the substrate 100 to form a first isolation via 200 penetrating the substrate 100. The first isolation via 200 is located near the storage region 2000 and exposes the metal filled in the connection hole 150 of the first isolation gap 121. (Refer to...) Figure 8 As shown.

[0085] The first isolation via 200 can be etched simultaneously with the contact hole 170, or they can be etched separately. This application does not specifically limit the order in which the first isolation via 200 and the contact hole 170 are etched.

[0086] In embodiments of this application, after etching to obtain a first isolation via 200 penetrating the substrate 100, an insulating material can be deposited and filled in the first isolation via 200 to form a first deep trench isolation layer 210. The first deep trench isolation layer 210 is used to isolate different storage regions of the substrate 100, and also to isolate the storage region 2000 and the pseudo storage region 1000 in the substrate. (Refer to...) Figure 9 As shown.

[0087] In embodiments of this application, after etching the stacked layer 110 to obtain the dummy channel via 130, an insulating material is filled into the dummy channel via 130. To isolate different contact holes 170 in the substrate 100, etching can be performed from the substrate 100 to form a second isolation via 220 penetrating the substrate 100. The second isolation via 220 exposes the dummy channel via 130 and the insulating material within the dummy channel via 130. (Refer to...) Figure 8 As shown.

[0088] The second isolation via 220 can be etched simultaneously with the contact hole 170, or they can be etched separately. This application does not specifically limit the order in which the second isolation via 220 and the contact hole 170 are etched.

[0089] In embodiments of this application, after etching to obtain the second isolation via 220 penetrating the substrate 100, insulating material can be deposited and filled in the second isolation via 220 to form a second deep trench isolation layer 230. The second deep trench isolation layer 230 is used to isolate two adjacent contact holes 170 in the substrate 100 so that different signals can be transmitted using different contact holes and corresponding connection holes. (Refer to...) Figure 9 As shown.

[0090] In practical applications, the first isolation via 200 and the second isolation via 220 can be etched simultaneously with the contact via 170. Afterwards, insulating material can be deposited and filled simultaneously in the first isolation via 200, the second isolation via 220 and the contact via 170, saving process steps and reducing device manufacturing costs.

[0091] refer to Figure 12 As shown, a pseudo memory region 1000 is used to isolate multiple memory regions 2000. A channel hole 240 is formed in the stacked layer 110 of the multiple memory regions 2000. The channel hole 240 penetrates the stacked layer 110 to the substrate 100. A memory functional layer 241 and a channel layer 242 are formed sequentially in the channel hole 240.

[0092] Specifically, after forming a stacked layer 110 on the substrate 100, the stacked layer 110 can be etched to form a channel hole 240, which is used to form a memory cell string in the future.

[0093] The method for forming the channel via 240 can be as follows: a hard mask layer is formed on the surface of the stacked layer 110, such as a silicon oxide or silicon nitride layer; a photoresist layer is then spin-coated onto the surface of the hard mask layer, and a patterned photoresist layer is formed through exposure, development, and other steps. The pattern of the photoresist can be determined by a mask used to form the channel via in the 3D NAND memory manufacturing process; the pattern is transferred onto the hard mask layer; and then the stacked layer 110 is etched using the hard mask layer as a shield to form the channel via 240 penetrating through the stacked layer 110, which can extend into the substrate 100. After forming the channel via 240, the hard mask layer and the photoresist layer can be removed. In a specific implementation, the channel via 240 can penetrate through the stacked layer 110 into the substrate 100.

[0094] Subsequently, a storage functional layer 241 and a channel layer 242 are sequentially formed in the channel via 240. The storage functional layer 241 may include a barrier layer, a charge storage layer, and a tunneling layer stacked sequentially. In a specific embodiment, the barrier layer, charge storage layer, and tunneling layer may be an ONO stack, which is a stack of oxide, nitride, and oxide. The channel layer 242 may be a polysilicon layer.

[0095] In embodiments of this application, a storage functional layer 241 can be formed by sequentially stacking a barrier layer, a charge storage layer, and a tunneling layer in the channel via 240. Then, a channel layer 242 is formed on the sidewall of the storage functional layer 241. An insulating material filling layer, such as a silicon oxide layer, can be formed between the channel layers 242. In a specific embodiment, a conductive layer can be formed above the memory cell string. This conductive layer forms the upper selector device of the memory cell string and also forms interconnect structures to further form bit lines. Then, a dielectric layer can be formed above the stacked layer 110. This dielectric layer protects the formed storage functional layer and conductive layer. The dielectric layer can be, for example, silicon oxide or silicon nitride. In a specific embodiment, a dielectric layer material can be deposited above the stacked layer 110, followed by a planarization process to form a dielectric layer of uniform thickness above the stacked layer. For example, chemical mechanical polishing can be used to planarize the dielectric layer.

[0096] In embodiments of this application, a channel hole 240 may be formed before the gate isolation gaps 121 / 122 are formed, and a storage function layer and a channel layer may be formed within the channel hole 240.

[0097] In the embodiments of this application, before the insulating layer 140 is formed on the sidewall of the gate isolation gap 121 / 122, the sacrificial layer 111 in the stacked layer 110 can be removed by etching through the gate isolation gap 121 / 122 to form an opening so that the gate layer can be formed in the opening. Specifically, the gate layer is formed in the opening through the gate isolation gap 121 / 122, and the material of the gate layer is a metal material.

[0098] The manufacturing method of the embodiments of this application has been described in detail above. Furthermore, the embodiments of this application also provide a 3D NAND memory device formed by the above method. (See reference...) Figure 12 As shown, the storage device includes:

[0099] This application provides a 3D NAND storage device, including:

[0100] A substrate on which a stack of sacrificial layers and dielectric layers are alternately stacked;

[0101] The stacked layer has a plurality of gate isolation gaps and a plurality of pseudo-channel vias formed therein. The gate isolation gaps and the pseudo-channel vias penetrate the stacked layer to the substrate. A gate isolation gap is formed between two adjacent pseudo-channel vias. The plurality of gate isolation gaps and the plurality of pseudo-channel vias are formed in a pseudo memory region, which divides the stacked layer into a plurality of memory regions.

[0102] An insulating layer and a connection hole are formed in the gate line isolation gap; the connection hole penetrates the insulating layer to the substrate;

[0103] The connection hole is filled with metal.

[0104] Optionally, it also includes:

[0105] A contact hole that penetrates the substrate to expose the metal within the connection hole, and a first isolation contact hole and a second isolation contact hole that penetrate the substrate;

[0106] The contact hole is filled with metal, a first deep trench isolation layer is formed in the first isolation contact hole, and a second deep trench isolation layer is formed in the second isolation contact hole.

[0107] Optionally, it also includes:

[0108] A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer;

[0109] The metal bonding layer is electrically connected to the metal inside the connection hole.

[0110] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a 3D NAND memory device, characterized in that, Including: Providing a substrate on which a stacked layer of an alternating sacrificial layer and a dielectric layer is formed; Etching the stacked layer to form a plurality of gate line isolation gaps and a plurality of pseudo-channel holes in the stacked layer, the gate line isolation gaps and the pseudo-channel holes penetrating the stacked layer to the substrate, and the gate line isolation gaps being formed between two adjacent pseudo-channel holes; the plurality of gate line isolation gaps and the plurality of pseudo-channel holes are formed in a pseudo-storage area, and the pseudo-storage area divides the stacked layer into a plurality of storage areas; Forming an insulating layer on the sidewalls of the gate line isolation gaps to form connection holes in the gate line isolation gaps, the connection holes penetrating the insulating layer to the substrate; The gate line isolation gaps include a first isolation gap and a second isolation gap; Performing metal filling of the connection holes, and only forming contact plugs in the second isolation gap.

2. The manufacturing method according to claim 1, characterized in that, The gate line isolation gaps include a first isolation gap and a second isolation gap, and the first isolation gap is close to the storage area; Further including: Etching from the substrate to form contact holes penetrating the substrate; the contact holes expose the metal filled in the connection holes of the second isolation gap; Performing metal filling of the contact holes.

3. The manufacturing method according to claim 2, characterized in that, Further including: Etching from the substrate to form a first isolation through hole penetrating the substrate; The first isolation through hole is close to the storage area and exposes the metal filled in the connection holes of the first isolation gap; Performing insulating material filling of the first isolation through hole to form a first deep trench isolation layer.

4. The manufacturing method according to claim 3, characterized in that, Further including: Etching from the substrate to form a second isolation through hole penetrating the substrate; The second isolation through hole exposes the pseudo-channel holes; Performing insulating material filling of the second isolation through hole to form a second deep trench isolation layer to isolate the two adjacent contact holes in the substrate.

5. The manufacturing method according to claim 2, characterized in that, Before performing metal filling of the contact holes, further including: Depositing an insulating material; Removing the insulating material at the bottom of the contact holes and retaining the insulating material on the sidewalls of the contact holes; Performing wet cleaning of the contact holes.

6. The manufacturing method according to claim 1, characterized in that, Channel holes are formed in the stacked layer of the storage area, the channel holes penetrate the stacked layer to the substrate, and a storage functional layer and a channel layer are sequentially formed in the channel holes; Before filling the insulating layer into the gate line isolation gaps, further including: Using the gate line isolation gaps to remove the sacrificial layer to form openings; Forming a gate layer in the openings.

7. The method according to claim 1, characterized in that, After performing metal filling of the connection holes, further including: Forming a bonding layer on the stacked layer, the bonding layer including a metal bonding layer; The metal bonding layer is electrically connected to the metal in the connection holes.

8. A 3D NAND storage device, characterized in that, Including: A substrate on which a stacked layer of an alternating sacrificial layer and a dielectric layer is formed; A plurality of gate line isolation gaps and a plurality of pseudo-channel holes are formed in the stacked layer, the gate line isolation gaps and the pseudo-channel holes penetrate the stacked layer to the substrate, and the gate line isolation gaps are formed between two adjacent pseudo-channel holes; the plurality of gate line isolation gaps and the plurality of pseudo-channel holes are formed in a pseudo-storage area, and the pseudo-storage area divides the stacked layer into a plurality of storage areas; An insulating layer and a connection hole are formed in the gate line isolation gap; the connection hole extends to the substrate; The grid isolation gap includes a first isolation gap and a second isolation gap; The connection hole is filled with metal, and the contact plug is only present in the second isolation gap.

9. The device according to claim 8, characterized in that, Also includes: A contact hole that penetrates the substrate to expose the metal within the connection hole, and a first isolation contact hole and a second isolation contact hole that penetrate the substrate; The contact hole is filled with metal, a first deep trench isolation layer is formed in the first isolation contact hole, and a second deep trench isolation layer is formed in the second isolation contact hole.

10. The device according to claim 8, characterized in that, Also includes: A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer; The metal bonding layer is electrically connected to the metal inside the connection hole.

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