Schottky diode and method of manufacturing the same

Abstract

The application discloses a Schottky diode and a preparation method thereof. The Schottky diode comprises a substrate, an intermediate layer arranged on the upper side of the substrate, the intermediate layer comprising an epitaxial layer and an oxidation layer arranged in sequence from bottom to top, a groove extending upward and downward is arranged on the intermediate layer, and the groove extends to the inside of the epitaxial layer; a gate oxide layer is arranged on the inner side wall of the groove and defines a channel in the groove; a polysilicon layer is arranged in the channel and comprises a first polysilicon layer and a second polysilicon layer arranged in sequence from bottom to top, one of the first polysilicon layer and the second polysilicon layer is a high-resistance polysilicon layer, and the other is a low-resistance polysilicon layer, the resistance of the high-resistance polysilicon layer is greater than that of the low-resistance polysilicon layer; and a barrier metal layer is arranged on the upper side of the oxidation layer and covers the notch of the groove. The Schottky diode provided by the application can obviously reduce the conduction voltage drop through the high-resistance polysilicon layer and the low-resistance polysilicon layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a Schottky diode and a preparation method thereof. BACKGROUND

[0002] The Schottky diode is named after the inventor Dr. Schottky, and is made by using the metal-semiconductor barrier principle formed by the contact between metal and semiconductor. The VBR (reverse breakdown voltage), IR (leakage current) and VF (voltage drop) of the traditional planar Schottky diode are related to the barrier size of the selected Schottky metal, and the blocking ability is poor; the trench Schottky diode utilizes the MOS effect and the trench structure, and under the same conditions, realizes lower IR and VF, stronger anti-surge current ability and higher reliability.

[0003] The characteristics of the Schottky device are mainly affected by the Schottky contact barrier, and the contact potential is about 0.45V by using the titanium metal barrier structure. For a conventional 100V device, the leakage current is about 10 microamperes, and the on-state voltage drop of the device is about 0.6V. In such a system application, the device has good energy efficiency. However, for high-voltage 150-300V devices, the device needs a thicker epitaxial layer and a higher resistivity, and the bulk silicon resistance is large. When the device is working, compared with the low-voltage device, the contact potential is dominant, and the bulk silicon potential drop of the high-voltage device accounts for a large proportion. How to make the Schottky diode obtain a lower forward voltage drop and reduce the system energy consumption is a problem to be solved at present.

[0004] In order to make the trench Schottky diode obtain a lower forward voltage drop, one method is to modulate the N-type resistivity in the trench Schottky platform area by ion implantation. This method can reduce the on-state voltage drop of the device to a certain extent. Due to the limitation of the ion implantation depth, this effect can only reduce the resistance of the epitaxial layer to a certain depth, and is mainly applied to 45V-100V devices. For high-voltage devices, especially for devices with thick epitaxial layers, the on-state voltage drop reduction effect is generally low. Another method is to use a super-junction process, and the epitaxial layer adopts a PN staggered column structure to reduce the resistance of the N-type region. At present, there are two methods of trench super-junction process and epitaxial ion implantation annealing super-junction process for manufacturing. This structure is commonly used in high-voltage VDMOS (high-density plasma) devices, and the Schottky device can also use this structure to reduce the on-state voltage drop. This process has high manufacturing cost, and in addition, the Schottky device is a single-carrier device, and the P-type region in the super-junction will also inject holes under a large current, which reduces the working frequency of the device. SUMMARY

[0005] The main purpose of the present application is to provide a Schottky diode and a preparation method thereof, which aims to reduce the on-state voltage drop of the Schottky diode.

[0006] To achieve the above object, the application provides a Schottky diode, which comprises:

[0007] a substrate;

[0008] an intermediate layer arranged on the upper side of the substrate, the intermediate layer comprising an epitaxial layer and an oxidation layer arranged in sequence from bottom to top, and a groove extending upward and downward is arranged on the intermediate layer, and the groove extends to the inside of the epitaxial layer;

[0009] a gate oxide layer arranged on the inner sidewall of the groove and defining a channel in the groove;

[0010] a polysilicon layer arranged in the channel, comprising a first polysilicon layer and a second polysilicon layer arranged in sequence from bottom to top, one of the first polysilicon layer and the second polysilicon layer is a high-resistance polysilicon layer, and the other is a low-resistance polysilicon layer, the resistance of the high-resistance polysilicon layer is greater than that of the low-resistance polysilicon layer; and

[0011] a barrier metal layer arranged on the upper side of the oxidation layer and covering the opening of the groove.

[0012] Optionally, a plurality of polysilicon layers are arranged in sequence from bottom to top.

[0013] Optionally, the thickness of the oxidation layer is 0.5-2 nm.

[0014] Optionally, the resistance of the high-resistance polysilicon layer is greater than 10 6 Ω; and / or,

[0015] the resistance of the low-resistance polysilicon layer is 0.001-9 Ω; and / or,

[0016] the upper surface of the polysilicon layer is arranged flush with the upper surface of the intermediate layer; and / or,

[0017] the first polysilicon layer is a high-resistance polysilicon layer, and the second polysilicon layer is a low-resistance polysilicon layer.

[0018] Optionally, the material of the low-resistance polysilicon layer comprises P-type polysilicon or N-type polysilicon, at least one of boron and aluminum is doped in the P-type polysilicon, and at least one of phosphorus and arsenic is doped in the N-type polysilicon.

[0019] The application further provides a preparation method of the Schottky diode, which comprises the following steps:

[0020] S10, providing a substrate and preparing an epitaxial layer on the upper side of the substrate;

[0021] S20, preparing an oxidation layer on the upper side of the epitaxial layer to form an intermediate layer;

[0022] S30, etching a trench on the intermediate layer;

[0023] S40, preparing a gate oxide layer on the inner sidewall of the trench, so that the gate oxide layer defines a channel in the trench;

[0024] S50, preparing a polysilicon layer in the channel and on the top of the oxide layer by using high-density plasma deposition technology;

[0025] S60, removing the polysilicon layer on the top of the oxide layer by using surface planarization technology;

[0026] S70, preparing a barrier metal layer on the oxide layer and the top of the trench.

[0027] Optionally, step S30 comprises:

[0028] S31, after spin-coating photoresist on the top of the oxide layer, exposing to light to expose a trench etching window, etching the oxide layer to form a first trench on the oxide layer;

[0029] S32, removing the photoresist, etching a second trench on the epitaxial layer, the first trench and the second trench together forming the trench.

[0030] Optionally, step S50 comprises:

[0031] S51, preparing a polysilicon layer in the trench and on the top of the oxide layer by using high-density plasma deposition technology;

[0032] S52, ion implantation on the top of the polysilicon layer, so that the ions at least partially pass through the polysilicon layer to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions;

[0033] S53, repeating steps S51 and S52 to complete the preparation of the polysilicon layer.

[0034] Optionally, in step S51, the thickness of the polysilicon layer is 0.5-2 μm.

[0035] Optionally, in step S52,

[0036] the dose of the ion implantation is 10 13 -10 16 cm -2 ; and / or,

[0037] the energy of the ion implantation is 30-120 KeV.

[0038] The technical scheme provided by the present application provides a Schottky diode, a high-resistance polysilicon layer and a low-resistance polysilicon layer are formed in a groove in a stacked manner, so that, in a reverse blocking state of the Schottky diode, the existence of the high-resistance polysilicon layer reduces the anode and cathode leakage current, which is obviously lower than the Schottky leakage current, has no obvious influence on the overall leakage, and the resistance voltage division of the high-resistance polysilicon layer plays a role in uniform voltage division of the deep polysilicon layer in the groove; the low-resistance polysilicon layer sandwiched between the high-resistance polysilicon layers is potential equivalent, which can affect the electric field distribution in the crystalline silicon, generate a transverse electric field, and is similar to a super-junction structure, which adjusts the triangular longitudinal electric field distribution that should be reduced to a trapezoidal electric field distribution, and can improve the overall withstand voltage capability of the device. The Schottky diode provided by the present application forms a super-junction structure through the stacked high-resistance polysilicon layer and low-resistance polysilicon layer, which can obviously reduce the on-voltage drop. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other related drawings can also be obtained by those skilled in the art without creative labor.

[0040] Figure 1 The structure schematic diagram of an embodiment of the Schottky diode provided by the present application is shown in the figure.

[0041] Figure 2 The preparation process schematic diagram of an embodiment of the preparation method of the Schottky diode provided by the present application is shown in the figure.

[0042] Figure 3 The longitudinal electric field distribution diagram of the polysilicon layer of the Schottky diode obtained by the embodiment 1 of the present application is shown in the figure.

[0043] Explanation of reference numerals:

[0044] Reference Name Reference Name 1 oxide layer 6 low resistance polysilicon layer 2 epitaxial layer 7 barrier metal layer 3 substrate 8 polysilicon layer 4 gate oxide layer 9 trench 5 high resistance polysilicon layer

[0045] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely. The specific conditions not mentioned in the embodiments are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments not marked with the manufacturer are all conventional products that can be obtained by market purchase.

[0047] In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes, taking "A and / or B" as an example, including A scheme, or B scheme, or A and B scheme. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the premise that the person skilled in the art can realize it, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the present application.

[0048] In order to make the trench Schottky diode obtain lower forward voltage drop, one method is to modulate the N-type resistivity in the trench Schottky platform area by ion implantation, which can reduce the on-state voltage drop of the device to a certain extent. Due to the limitation of ion implantation depth, this effect can only reduce the resistance of a certain depth of epitaxial layer, and is mainly applied to 45V-100V devices. For high-voltage devices, especially for devices with thick epitaxial layers, the on-state voltage drop reduction effect is generally low. Another method is to use super junction technology, and the epitaxial layer uses PN staggered column structure to reduce the resistance of the N-type region. At present, there are two methods of trench super junction technology and epitaxial ion implantation annealing super junction technology for manufacturing. This structure is commonly used in high-voltage VDMOS (high-density plasma) devices, and Schottky devices can also use this structure to reduce the on-state voltage drop. This process has high manufacturing cost, and in addition, the Schottky device is a single-carrier device, and the P-type region in the super junction will also inject holes under high current, which will reduce the working frequency of the device.

[0049] Therefore, the present application provides a Schottky diode, which aims to reduce the on-state voltage drop of the Schottky diode. Figure 1 The structure diagram of an embodiment of the Schottky diode provided by the present application is shown in the figure. Figure 2 The preparation process diagram of an embodiment of the preparation method of the Schottky diode provided by the present application is shown in the figure. Figure 3 The longitudinal electric field distribution diagram of the polysilicon layer of the Schottky diode obtained in embodiment 1 of the present application is shown in the figure.

[0050] Please refer to Figure 1The Schottky diode comprises a substrate 3, an intermediate layer, a gate oxide layer 4, a polysilicon layer 8 and a barrier metal layer 7, wherein the intermediate layer is arranged on the upper side of the substrate 3, the intermediate layer comprises an epitaxial layer 2 and an oxide layer 1 arranged in sequence from bottom to top, a groove 9 extending from bottom to top is arranged on the intermediate layer, and the groove 9 extends into the epitaxial layer 2; the gate oxide layer 4 is arranged on the inner side wall of the groove 9 and defines a channel in the groove 9; the polysilicon layer 8 is arranged in the channel and comprises a first polysilicon layer and a second polysilicon layer arranged in sequence from bottom to top, one of the first polysilicon layer and the second polysilicon layer is a high-resistance polysilicon layer 5, and the other is a low-resistance polysilicon layer 6; the resistance of the high-resistance polysilicon layer 5 is greater than that of the low-resistance polysilicon layer 6; and the barrier metal layer 7 is arranged on the upper side of the oxide layer 1 and covers the groove opening of the groove 9.

[0051] The Schottky diode has the high-resistance polysilicon layer 5 and the low-resistance polysilicon layer 6 arranged in the groove 9, so that in the reverse blocking state of the Schottky diode, the existence of the high-resistance polysilicon layer 5 reduces the anode-cathode leakage current, which is obviously lower than the Schottky leakage current, has no obvious influence on the overall leakage, and the resistance voltage division of the high-resistance polysilicon layer plays a role in the voltage division of the deep polysilicon layer 8 in the groove 9; the low-resistance polysilicon layer 6 sandwiched between the high-resistance polysilicon layers has an equal potential, which can affect the electric field distribution in the crystalline silicon, generate a transverse electric field, and be similar to a super-junction structure, adjust the triangular longitudinal electric field distribution that should be reduced to a trapezoidal electric field distribution, and improve the overall withstand voltage capability of the device.

[0052] The Schottky diode has the high-resistance polysilicon layer 5 and the low-resistance polysilicon layer 6 arranged in the groove 9, so that in the reverse blocking state of the Schottky diode, the existence of the high-resistance polysilicon layer 5 reduces the anode-cathode leakage current, which is obviously lower than the Schottky leakage current, has no obvious influence on the overall leakage, and the resistance voltage division of the high-resistance polysilicon layer plays a role in the voltage division of the deep polysilicon layer 8 in the groove 9; the low-resistance polysilicon layer 6 sandwiched between the high-resistance polysilicon layers has an equal potential, which can affect the electric field distribution in the crystalline silicon, generate a transverse electric field, and be similar to a super-junction structure, adjust the triangular longitudinal electric field distribution that should be reduced to a trapezoidal electric field distribution, and improve the overall withstand voltage capability of the device.

[0053] The Schottky diode has the high-resistance polysilicon layer 5 and the low-resistance polysilicon layer 6 arranged in the groove 9, so that in the reverse blocking state of the Schottky diode, the existence of the high-resistance polysilicon layer 5 reduces the anode-cathode leakage current, which is obviously lower than the Schottky leakage current, has no obvious influence on the overall leakage, and the resistance voltage division of the high-resistance polysilicon layer plays a role in the voltage division of the deep polysilicon layer 8 in the groove 9; the low-resistance polysilicon layer 6 sandwiched between the high-resistance polysilicon layers has an equal potential, which can affect the electric field distribution in the crystalline silicon, generate a transverse electric field, and be similar to a super-junction structure, adjust the triangular longitudinal electric field distribution that should be reduced to a trapezoidal electric field distribution, and improve the overall withstand voltage capability of the device.

[0054] More preferably, the first polysilicon layer is a high-resistance polysilicon layer 5, and the second polysilicon layer is a low-resistance polysilicon layer 6. In this way, the high-resistance polysilicon layer 5 and the low-resistance polysilicon layer 6 can be prepared simultaneously by using a high-density plasma deposition technique, and then the surface of the polysilicon is treated to form a low-resistance polysilicon, so that the preparation method is simpler.

[0055] The oxidation layer 1 mainly serves as a photoetching barrier layer to protect the epitaxial layer 2. The thickness of the oxidation layer 1 is not limited in the present application, and is preferably , wherein the unit is Angstrom, With the above thickness, the protection effect is good.

[0056] Preferably, the resistance of the high-resistance polysilicon layer 5 is greater than 10 6 Ω; and the resistance of the low-resistance polysilicon layer 6 is 0.001-9 Ω. The resistance difference between the two is large, so that the on-voltage drop of the Schottky diode can be further reduced.

[0057] In addition, preferably, the upper surface of the polysilicon layer 8 is flush with the upper surface of the intermediate layer, so that the on-voltage drop of the Schottky diode is reduced more obviously.

[0058] Further, in the embodiment of the present application, the material of the low-resistance polysilicon layer 6 includes P-type polysilicon or N-type polysilicon, the P-type polysilicon is doped with at least one of boron and aluminum, and the N-type polysilicon is doped with at least one of phosphorus and arsenic. Research shows that the use of the above-mentioned doping elements can significantly reduce the on-voltage drop of the Schottky diode.

[0059] The Schottky diode provided in the embodiment of the present application has a significantly reduced on-voltage drop. Taking a 100V trench 9 gate Schottky diode as an example, a conventional device is simulated by using a device simulation software. The breakdown voltage of a conventional titanium Schottky metal device is 115V, and the breakdown voltage of the Schottky diode using the structure of the present application reaches 180V. By adjusting the thickness and resistivity of the epitaxial layer 2, the on-voltage drop of the conventional device 15A is 1.01V, while the breakdown voltage of the Schottky diode of the present application is 118V, and the on-voltage drop is 0.71V under the forward current of 15A, which is improved by 30%. It can be seen from the simulation that the new super-junction structure provided in the present application can significantly improve the on-voltage drop of the device.

[0060] The present application further provides a preparation method of the Schottky diode as described above, please refer to Figure 2 The preparation method of the Schottky diode provided in the present application comprises the following steps:

[0061] S10, providing a substrate and preparing an epitaxial layer on the upper side of the substrate.

[0062] S20, preparing an oxidation layer on the upside of the epitaxial layer to form an intermediate layer.

[0063] The preparation method of the epitaxial layer and the oxidation layer is not limited in the present application, and a method commonly used in the art can be adopted.

[0064] S30, etching a groove on the intermediate layer.

[0065] Specifically, the step S30 comprises:

[0066] S31, after spin-coating a photoresist on the upside of the oxidation layer, exposing a groove etching window by exposure, etching the oxidation layer, and forming a first groove on the oxidation layer;

[0067] S32, removing the photoresist, etching a second groove on the epitaxial layer, and the first groove and the second groove jointly constituting the groove.

[0068] The etching method of the photoresist can adopt dry etching, so that the etching effect is good, and the preparation method of the groove is adopted, the groove is flat, and the turn-on voltage drop of the Schottky diode is obviously reduced.

[0069] S40, preparing a gate oxide layer on the inner sidewall of the groove to define a channel in the groove by the gate oxide layer.

[0070] The thickness of the gate oxide layer determines the resistance modulation effect of the polysilicon layer and the voltage resistance of the device. In specific preparation, the gate oxide layer can be grown on the sidewall and bottom wall of the groove by a method commonly used in the art, and after the preparation is completed, the gate oxide layer on the bottom wall of the groove is removed by dry etching. During dry etching, part of the oxidation layer is also removed.

[0071] S50, preparing a polysilicon layer in the channel and on the upside of the oxidation layer by using a high-density plasma deposition technology.

[0072] The polysilicon layer comprises at least one high-resistance polysilicon layer and at least one low-resistance polysilicon layer. The material of the high-resistance polysilicon layer is polysilicon, and the material of the low-resistance polysilicon layer is doped polysilicon, which can be P-type polysilicon or N-type polysilicon. The P-type polysilicon is doped with at least one of boron and aluminum, and the N-type polysilicon is doped with at least one of phosphorus and arsenic.

[0073] In specific preparation, the high-resistance polysilicon layer can be directly prepared by using a high-density plasma deposition technology (HDP), and the low-resistance polysilicon layer can be prepared by first preparing pure polysilicon by using HDP, and then injecting doping ions into the pure polysilicon by using an ion implantation method. HDP has excellent groove filling performance.

[0074] Preferably, in the embodiment of the present application, the step S50 comprises:

[0075] S51, polycrystalline silicon is prepared in the trench and on the upper side of the oxide layer by using high-density plasma deposition technology;

[0076] S52, ion implantation is performed on the upper side of the polycrystalline silicon, so that the ions at least partially penetrate the polycrystalline silicon, so as to divide the polycrystalline silicon into a low-resistance polycrystalline silicon layer implanted with ions and a high-resistance polycrystalline silicon layer not implanted with ions;

[0077] S53, steps S51 and S52 are repeated to complete the preparation of the polycrystalline silicon layer.

[0078] The polycrystalline silicon layer prepared by the above method is provided with a plurality of high-resistance polycrystalline silicon layers and low-resistance polycrystalline silicon layers, and the number of the high-resistance polycrystalline silicon layers is equal to that of the low-resistance polycrystalline silicon layers, which are sequentially stacked from bottom to top. The method of the embodiment does not need to separately prepare the high-resistance polycrystalline silicon layer and the low-resistance polycrystalline silicon layer, and the preparation process is simpler. Moreover, the number of the high-resistance polycrystalline silicon layers is equal to that of the low-resistance polycrystalline silicon layers, which is conducive to forming a ladder-shaped electric field distribution in the trench, and significantly reducing the on-voltage drop of the Schottky diode.

[0079] In this step, the prepared polycrystalline silicon layer is a stacked structure of the low-resistance polycrystalline silicon layer and the high-resistance polycrystalline silicon layer.

[0080] The number of repetitions of steps S51 and S52 is not limited by the present application, and preferably, the preparation can be stopped when the upper surface of the polycrystalline silicon layer is flush with the upper surface of the intermediate layer.

[0081] In addition, the ion-implanted impurity is the same as the first-implanted impurity element, and the implantation energy and dose can be adjusted to control the thickness ratio of the high-resistance polycrystalline silicon layer to the low-resistance polycrystalline silicon layer. The number of polycrystalline silicon deposition times is related to the trench depth and the thickness of the deposited polycrystalline silicon.

[0082] The thickness of the polycrystalline silicon prepared in step S51 is not limited by the present application, and preferably, the thickness of the polycrystalline silicon is 0.5-2 μm. Under the above thickness, the on-voltage drop of the obtained Schottky diode is lower.

[0083] The dose and energy of the ion implantation in step S52 are also not limited by the present application, and preferably, the dose of the ion implantation is 10 13 -10 16 cm -2 ; and the energy of the ion implantation is 30-120 KeV. Under the above conditions, the resistance of the high-resistance polycrystalline silicon layer can be ensured to be significantly higher than that of the low-resistance polycrystalline silicon layer, and the on-voltage drop of the Schottky diode is significantly reduced.

[0084] It can be understood that the dose and energy of the ion implantation can satisfy both or only one of them, and as a preferred embodiment of the present application, both of them are satisfied, which can ensure that the resistance of the high-resistance polysilicon layer is obviously higher than that of the low-resistance polysilicon layer, and further reduce the on-voltage drop of the Schottky diode.

[0085] S60, removing the polysilicon layer on the upper side of the oxide layer by using a surface planarization technology.

[0086] The surface planarization technology CMP, with the help of micro-particle abrasive materials or slurry, helps to reduce the serious uneven surface morphology caused by the multi-layer structure.

[0087] S70, preparing a barrier metal layer on the upper side of the oxide layer and the trench.

[0088] Preferably, in the embodiment of the present application, before step S70 is performed, the previously prepared component is rapidly annealed to activate the impurities in the low-resistance polysilicon layer.

[0089] In addition, after annealing, a stop layer TEOS (tetraethoxysilane) can also be prepared on the upper side of the oxide layer and the trench, and then removed before S70 is performed.

[0090] The preparation method of the Schottky diode provided by the present application adopts the HDP high-density plasma deposition technology and the CMP surface planarization technology, forms a composite polysilicon resistance structure without increasing the photolithography level, and reduces the production cost. The prepared Schottky diode has all the beneficial effects of the above-mentioned Schottky diode, which will not be described here.

[0091] Please refer to Figure 2 for a schematic diagram of the preparation process of the Schottky diode, an embodiment of the preparation method of the Schottky diode provided by the present application is given as follows:

[0092] (1) providing a substrate and preparing an epitaxial layer on the upper side of the substrate;

[0093] (2) preparing an oxide layer on the upper side of the epitaxial layer, so that the gate oxide layer defines a channel in the trench, and the thickness of the oxide layer is

[0094] (3) after spin-coating a photoresist on the upper side of the oxide layer, exposing to light to expose the trench etching window, etching the oxide layer to form a first groove on the oxide layer; removing the photoresist and etching a second groove on the epitaxial layer, the first groove and the second groove together constitute a trench;

[0095] (4) growing a gate oxide layer on the side wall and bottom wall of the trench, so that the gate oxide layer defines a channel in the trench, and after the fabrication is completed, using dry etching to remove the gate oxide layer on the bottom wall of the channel;

[0096] (5) using high-density plasma deposition technology to prepare a polysilicon layer with a thickness of 0.5-2 μm in the channel and on the upper side of the oxide layer; performing ion implantation on the upper side of the polysilicon layer, so that the ions at least partially penetrate the polysilicon layer, to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions, the material of the low-resistance polysilicon layer comprises P-type polysilicon or N-type polysilicon, the P-type polysilicon is doped with at least one of boron and aluminum, and the N-type polysilicon is doped with at least one of phosphorus and arsenic, the dose of the ion implantation is 10 13 ~10 16 cm -3 ; the energy of the ion implantation is 30-120 KeV;

[0097] (6) repeating step (5) until the upper surface of the polysilicon layer is flush with the upper surface of the intermediate layer, the resistance of the high-resistance polysilicon layer is greater than 10 6 Ω; and the resistance of the low-resistance polysilicon layer is 0.001-9 Ω;

[0098] (7) using surface planarization technology to remove the polysilicon layer on the upper side of the oxide layer;

[0099] (8) rapidly annealing the previously prepared component to activate the impurities in the low-resistance polysilicon layer, and first preparing a TEOS (tetraethoxysilane) layer on the upper side of the oxide layer and the trench, and then removing the TEOS layer, and then preparing a barrier metal layer on the upper side of the oxide layer and the trench.

[0100] The technical solutions of the present application are further described in detail below in combination with specific embodiments and the accompanying drawings. It should be understood that the following embodiments are only used to explain the present application, and are not used to limit the present application.

[0101] Embodiment 1

[0102] (1) providing a substrate and preparing an epitaxial layer on the upper side of the substrate;

[0103] (2) preparing an oxide layer on the upper side of the epitaxial layer, so that the gate oxide layer defines a channel in the trench, and the thickness of the oxide layer is

[0104] (3) After spin-coating photoresist on the upper side of the oxide layer, expose to light to expose the trench etching window, etch the oxide layer, and form a first groove on the oxide layer; remove the photoresist and etch a second groove on the epitaxial layer, the first groove and the second groove together form a trench;

[0105] (4) Grow a gate oxide layer on the sidewall and bottom wall of the trench to define a channel in the trench, and after the preparation is completed, remove the gate oxide layer on the bottom wall of the channel by dry etching;

[0106] (5) Use high-density plasma deposition technology to prepare a 0.5 μm thick polysilicon layer in the channel and on the upper side of the oxide layer; perform ion implantation on the upper side of the polysilicon layer, so that the ions at least partially penetrate the polysilicon layer to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions, the material of the low-resistance polysilicon layer includes P-type polysilicon doped with boron and aluminum, the dose of the ion implantation is 10 13 cm -2 ; the energy of the ion implantation is 30 KeV;

[0107] (6) Repeat step (5) until the upper surface of the polysilicon layer is flush with the upper surface of the intermediate layer, the resistance of the high-resistance polysilicon layer is 10 7 Ω, and the resistance of the low-resistance polysilicon layer is 0.001 Ω;

[0108] (7) Use surface planarization technology to remove the polysilicon layer on the upper side of the oxide layer;

[0109] (8) Rapidly anneal the previously prepared component to activate the impurities in the low-resistance polysilicon layer, first prepare a TEOS (tetraethoxysilane) stop layer on the upper side of the oxide layer and the trench, and then remove it to prepare a barrier metal layer on the upper side of the oxide layer and the trench.

[0110] Example 2

[0111] (1) Provide a substrate and prepare an epitaxial layer on the upper side of the substrate;

[0112] (2) Prepare an oxide layer on the upper side of the epitaxial layer to define a channel in the trench with the gate oxide layer, and the thickness of the oxide layer is

[0113] (3) After spin-coating photoresist on the upper side of the oxide layer, expose to light to expose the trench etching window, etch the oxide layer, and form a first groove on the oxide layer; remove the photoresist and etch a second groove on the epitaxial layer, the first groove and the second groove together form a trench;

[0114] (4) growing gate oxide layer on the side wall and bottom wall of the trench, so that the gate oxide layer defines a channel in the trench, and after the preparation is finished, dry etching is used to remove the gate oxide layer on the bottom wall of the channel;

[0115] (5) using high-density plasma deposition technology, a 2 μm thick polysilicon layer is prepared in the channel and on the upper side of the oxide layer; ion implantation is performed on the upper side of the polysilicon layer, so that the ions at least partially penetrate the polysilicon layer, so as to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions, the material of the low-resistance polysilicon layer includes N-type polysilicon, the N-type polysilicon is doped with phosphorus and arsenic, the dose of the ion implantation is 10 16 cm -2 ; the energy of the ion implantation is 120 KeV;

[0116] (6) repeating step (5) until the upper surface of the polysilicon layer is flush with the upper surface of the intermediate layer, the resistance of the high-resistance polysilicon layer is 10 8 Ω; and the resistance of the low-resistance polysilicon layer is 9 Ω;

[0117] (7) using surface planarization technology, the polysilicon layer on the upper side of the oxide layer is removed;

[0118] (8) rapidly annealing the previously prepared component, so as to activate the impurities in the low-resistance polysilicon layer, and a TEOS (tetraethoxysilane) layer is first prepared on the upper side of the oxide layer and the trench, and then removed, and a barrier metal layer is then prepared on the upper side of the oxide layer and the trench.

[0119] Example 3

[0120] (1) providing a substrate, and preparing an epitaxial layer on the upper side of the substrate;

[0121] (2) preparing an oxide layer on the upper side of the epitaxial layer, so that the gate oxide layer defines a channel in the trench, and the thickness of the oxide layer is

[0122] (3) after spin-coating photoresist on the upper side of the oxide layer, exposing to light to expose a trench etching window, etching the oxide layer to form a first groove on the oxide layer; removing the photoresist, and etching a second groove on the epitaxial layer, the first groove and the second groove jointly constitute a trench;

[0123] (4) growing a gate oxide layer on the side wall and bottom wall of the trench, so that the gate oxide layer defines a channel in the trench, and after the preparation is finished, dry etching is used to remove the gate oxide layer on the bottom wall of the channel;

[0124] (5) using high-density plasma deposition technology, a polysilicon layer with a thickness of 1 μm is prepared on the inside of the channel and the upper side of the oxide layer; ion implantation is performed on the upper side of the polysilicon layer, so that the ions at least partially penetrate the polysilicon layer, so as to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions, the material of the low-resistance polysilicon layer includes P-type polysilicon, the P-type polysilicon is doped with boron, the dose of the ion implantation is 10 15 cm -2 ; the energy of the ion implantation is 75 KeV;

[0125] (6) repeating step (5) until the upper surface of the polysilicon layer is flush with the upper surface of the intermediate layer, the resistance of the high-resistance polysilicon layer is 10 10 Ω; and the resistance of the low-resistance polysilicon layer is 4.5 Ω;

[0126] (7) using surface planarization technology, the polysilicon layer on the upper side of the oxide layer is removed;

[0127] (8) rapidly annealing the previously prepared component, so as to activate the impurities in the low-resistance polysilicon layer, a TEOS (tetraethoxysilane) layer is first prepared on the upper side of the oxide layer and the trench, and then removed, and then a barrier metal layer is prepared on the upper side of the oxide layer and the trench.

[0128] Taking the Schottky diode obtained in Example 1 as an example, the superiority of the performance of the Schottky diode proposed in the application is illustrated.

[0129] The longitudinal electric field of the polysilicon layer of the Schottky diode of Example 1 is measured, and the longitudinal electric field is Figure 3 It can be clearly seen that the longitudinal electric field is a trapezoidal electric field distribution, which indicates that the overall withstand voltage performance of the Schottky diode is significantly improved.

[0130] Through device simulation software, a conventional device is simulated, the breakdown voltage of a conventional titanium Schottky metal device is 115 V, after the structure of the Schottky diode of the application is used, the withstand voltage of the device reaches 180 V. By adjusting the thickness and resistivity of the epitaxial layer, the on-state voltage drop of the conventional device is 1.01 V under 15 A, while the breakdown voltage of the Schottky diode of the application is 118 V, and the on-state voltage drop is 0.71 V under 15 A of forward current, which is improved by 30%. Through simulation, it can be seen that the new super-junction structure proposed in the application can significantly improve the on-state voltage drop of the device.

[0131] In conclusion, the Schottky diode provided by the application can obviously reduce the on-voltage drop by forming a super-junction structure similar to the super-junction structure through the stacked high-resistance polysilicon layer and low-resistance polysilicon layer. The preparation method adopts HDP high-density plasma deposition technology and CMP surface planarization technology to form a composite polysilicon resistance structure without increasing the photolithography level, thereby reducing the production cost.

[0132] The above merely describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the patent protection scope of the present application.

Claims

1. A Schottky diode, characterized by, The application relates to a substrate, an intermediate layer arranged on the upper side of the substrate, the intermediate layer comprising an epitaxial layer and an oxidation layer arranged in sequence from bottom to top, a groove extending upwards and downwards is formed on the intermediate layer, the groove extends to the inside of the epitaxial layer, a gate oxide layer is arranged on the inner side wall of the groove and defines a channel in the groove, a polysilicon layer is arranged in the channel, the polysilicon layer comprises a first polysilicon layer and a second polysilicon layer arranged in sequence from bottom to top, one of the first polysilicon layer and the second polysilicon layer is a high-resistance polysilicon layer, and the other is a low-resistance polysilicon layer, the resistance of the high-resistance polysilicon layer is greater than that of the low-resistance polysilicon layer, and a barrier metal layer is arranged on the upper side of the oxidation layer and covers the groove opening. The polysilicon layer is provided with a plurality of polysilicon layers arranged in sequence from bottom to top, and the upper surface of the polysilicon layer is flush with the upper surface of the intermediate layer. The resistance of the low-resistance polysilicon layer is 0.001-9 ohm, and / or The first polysilicon layer is a high-resistance polysilicon layer, and the second polysilicon layer is a low-resistance polysilicon layer. The material of the low-resistance polysilicon layer comprises P-type polysilicon or N-type polysilicon, at least one of boron and aluminum is doped in the P-type polysilicon, and at least one of phosphorus and arsenic is doped in the N-type polysilicon. The application further discloses a preparation method of the substrate. The method comprises the following steps: The thickness of the oxide layer is The high-resistance polysilicon layer has a resistance greater than 10 6 Ω; and / or, S10, providing a substrate and preparing an epitaxial layer on the upper side of the substrate; S20, preparing an oxidation layer on the upper side of the epitaxial layer to form an intermediate layer; 2. The Schottky diode of claim 1, wherein S30, etching a groove on the intermediate layer; 3. A method of manufacturing a Schottky diode as claimed in any one of claims 1 to 2, characterized in that, S40, preparing a gate oxide layer on the inner side wall of the groove so that the gate oxide layer defines a channel in the groove; S50, preparing a polysilicon layer in the channel and on the upper side of the oxidation layer by using a high-density plasma deposition technology; S60, removing the polysilicon layer on the upper side of the oxidation layer by using a surface planarization technology; S70, preparing a barrier metal layer on the upper side of the oxidation layer and the groove. Step S30 comprises: S31, after spin-coating a photoresist on the upper side of the oxidation layer, exposing to light to expose a groove etching window, etching the oxidation layer to form a first groove on the oxidation layer; S32, removing the photoresist and etching a second groove on the epitaxial layer, and the first groove and the second groove jointly form the groove. Step S50 comprises:

4. The method of manufacturing a Schottky diode according to claim 3, wherein S51, preparing a polysilicon layer in the groove and on the upper side of the oxidation layer by using a high-density plasma deposition technology; S52, performing ion implantation on the upper side of the polysilicon layer so that ions at least partially penetrate the polysilicon layer to divide the polysilicon layer into a low-resistance polysilicon layer implanted with ions and a high-resistance polysilicon layer not implanted with ions; S53, repeating steps S51 and S52 to complete the preparation of the polysilicon layer.

5. The method of manufacturing a Schottky diode according to claim 3, wherein the metal layer is formed by sputtering. In step S51, the thickness of the polysilicon layer is 0.5-2 mu m. In step S52, The energy of the ion implantation is 30-120 KeV. ​ 6. The method of manufacturing a Schottky diode according to claim 5, wherein ​ 7. The method of manufacturing a Schottky diode according to claim 5, wherein the metal layer is formed by sputtering. ​ The ion implantation dose is 10 13 ~ 10 16 cm -2 ; and / or, ​

Images