Oscillators and chips

Abstract

An embodiment of the present application provides an oscillator and chip, the oscillator comprising: a first inverse class-F oscillator and a second inverse class-F oscillator, the first inverse class-F oscillator comprising a first resonant cavity, a first N-type metal oxide semiconductor transistor, and a first P-type metal oxide semiconductor transistor; the second inverse class-F oscillator comprising a second resonant cavity, a second N-type metal oxide semiconductor transistor, and a second P-type metal oxide semiconductor transistor, the gate of the first N-type metal oxide semiconductor transistor being connected to the gate of the second P-type metal oxide semiconductor transistor, and the gate of the first P-type metal oxide semiconductor transistor being connected to the gate of the second N-type metal oxide semiconductor transistor. In this way, the quality factor (Q) of the resonant cavity at the second harmonic frequency can be increased without reducing the quality factor (Q) of the resonant cavity at the fundamental frequency, thereby optimizing the phase noise and quality factor (FoM) of the oscillator.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an oscillator and a chip. Background Art

[0002] With the continuous development of oscillator technology, existing wireless systems can benefit from low phase noise high-band local oscillators, which can use dense modulation schemes over wide signal bandwidths. When the local oscillator frequency increases from RF to mmWave, the capacitive device tends to dominate the resonant circuit quality factor of the voltage-controlled oscillator, resulting in a severe trade-off between phase noise and frequency tuning range. At the same time, this trade-off is further exacerbated at advanced processes because advanced process nodes require more metal layers to connect transistors at a higher density, and the metal thickness is reduced, resulting in a decrease in the quality factor of the metal oxide metal capacitor. In addition, the deteriorating flicker noise of the metal-oxide-semiconductor field-effect transistor (MOSFET) in advanced process nodes is another challenge facing the phase noise performance of the voltage-controlled oscillator. Therefore, compared with the voltage-controlled oscillators in the recent 65nm and 40nm[5] complementary metal oxide semiconductor (CMOS) processes, the phase noise and quality factor (FoM) of the voltage-controlled oscillator in the 28nm CMOS process are poor. Summary of the Invention

[0003] In order to solve the above technical problems, an embodiment of the present application provides an oscillator and a chip.

[0004] In a first aspect, an embodiment of the present application provides an oscillator, comprising: a first inverse class-F oscillator and a second inverse class-F oscillator, wherein the first inverse class-F oscillator comprises a first resonant cavity, a first N-type metal oxide semiconductor transistor, and a first P-type metal oxide semiconductor transistor, wherein ports of the first resonant cavity are respectively connected to a drain and a gate of the first N-type metal oxide semiconductor transistor and a drain and a gate of the first P-type metal oxide semiconductor transistor;

[0005] The second inverse class-F oscillator includes a second resonant cavity, a second N-type metal oxide semiconductor transistor, and a second P-type metal oxide semiconductor transistor, wherein ports of the second resonant cavity are respectively connected to the drain and gate of the second N-type metal oxide semiconductor transistor and the drain and gate of the second P-type metal oxide semiconductor transistor;

[0006] The gate of the first N-type metal oxide semiconductor transistor is connected to the gate of the second P-type metal oxide semiconductor transistor, and the gate of the first P-type metal oxide semiconductor transistor is connected to the gate of the second N-type metal oxide semiconductor transistor;

[0007] Sources of the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor are grounded respectively, and sources of the first P-type metal oxide semiconductor transistor and the second P-type metal oxide semiconductor transistor are connected to a power supply respectively.

[0008] In a second aspect, an embodiment of the present application provides a chip, which includes the oscillator provided in the first aspect.

[0009] The oscillator provided by the present application couples two inverse Class F oscillators together, i.e., connecting the gate of the first N-type metal oxide semiconductor transistor to the gate of the second P-type metal oxide semiconductor transistor, and connecting the gate of the first P-type metal oxide semiconductor transistor to the gate of the second N-type metal oxide semiconductor transistor. This can increase the quality factor (Q) of the resonant cavity at the second harmonic frequency without reducing the quality factor (Q) of the resonant cavity at the fundamental frequency, thereby optimizing the oscillator's phase noise and quality factor (FoM). Furthermore, the symmetrical circuit structure can also reduce the phase and amplitude errors between the oscillator's differential output voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solution of this application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be regarded as limiting the scope of protection of this application. In each of the drawings, similar components are numbered similarly.

[0011] Figure 1 A schematic structural diagram of an oscillator provided in an embodiment of the present application is shown;

[0012] Figure 2 A schematic structural diagram of a switched capacitor provided in an embodiment of the present application is shown;

[0013] Figure 3 Another structural diagram of an oscillator provided in an embodiment of the present application is shown;

[0014] Figure 4A A schematic diagram showing the principle of improving the quality factor of the resonant cavity second harmonic frequency of the oscillator provided by an embodiment of the present application;

[0015] Figure 4B The Q2 and R of the second harmonic resonance point obtained by simulation according to the embodiment of the present application are shown. P2 Schematic diagram of the changes;

[0016] Figure 5A shows an output signal waveform diagram of a single inverse F oscillator provided by an embodiment of the present application;

[0017] Figure 5B shows an output signal waveform diagram of an oscillator provided in an embodiment of the present application;

[0018] Figure 6A A schematic diagram showing a change in the quality factor of a single inverse F oscillator provided in an embodiment of the present application is shown;

[0019] Figure 6B A schematic diagram showing a change in the quality factor of an oscillator provided in an embodiment of the present application is shown;

[0020] Figure 7A A phase noise distribution diagram provided by an embodiment of the present application is shown;

[0021] Figure 7B Another phase noise distribution diagram provided by an embodiment of the present application is shown;

[0022] Figure 8A A schematic diagram of phase noise variation measured within the tuning range provided by an embodiment of the present application is shown;

[0023] Figure 8B A schematic diagram showing changes in the quality factor measured within the tuning range provided by an embodiment of the present application is shown;

[0024] Figure 9 A performance reference diagram of the oscillator provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0026] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0027] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0028] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0030] An embodiment of the present disclosure provides an oscillator.

[0031] For details, see Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of the oscillator provided in this embodiment. Figure 1 As shown, the oscillator includes: a first inverse class F oscillator and a second inverse class F oscillator. The first inverse class F oscillator includes a first resonant cavity, a first N-type metal oxide semiconductor transistor M N1 and a first P-type metal oxide semiconductor transistor M P1 , each port of the first resonant cavity is respectively connected to the first N-type metal oxide semiconductor transistor M N1 The drain and gate of the first P-type metal oxide semiconductor transistor M P1 The second inverse F-type oscillator includes a second resonant cavity, a second N-type metal oxide semiconductor transistor M N2 and a second P-type metal oxide semiconductor transistor M P2 , each port of the second resonant cavity is respectively connected to the second N-type metal oxide semiconductor transistor M N2 The drain and gate of the second P-type metal oxide semiconductor transistor M P2 The drain and gate connections.

[0032] The first N-type metal oxide semiconductor transistor M N1 The gate of the second P-type metal oxide semiconductor transistor M P2The gate of the first P-type metal oxide semiconductor transistor M P1 The gate of the second N-type metal oxide semiconductor transistor M N2 The gate of the first N-type metal oxide semiconductor transistor M N1 and the second N-type metal oxide semiconductor transistor M N2 The sources of the first P-type metal oxide semiconductor transistor M are grounded. P1 and the second P-type metal oxide semiconductor transistor M P2 The sources are respectively connected to the power supply.

[0033] The first resonant cavity and the second resonant cavity are described below.

[0034] In this embodiment, the first resonant cavity includes a first primary resonant cavity and a first secondary resonant cavity; the first end of the first primary resonant cavity is connected to the first N-type metal oxide semiconductor transistor M N1 The drain of the first drain node V DN1 The second end of the first primary resonant cavity and the first P-type metal oxide semiconductor transistor M P1 The drain of the second drain node V DP1 The first end of the first secondary resonant cavity and the first N-type metal oxide semiconductor transistor M N1 The gate is connected to the first gate node V GN1 The second end of the first secondary resonant cavity and the first P-type metal oxide semiconductor transistor M P1 The gate is connected to the second gate node V GP1 .

[0035] In this embodiment, the second resonant cavity includes a second primary resonant cavity and a second secondary resonant cavity; the first end of the second primary resonant cavity is connected to the second N-type metal oxide semiconductor transistor M N2 The drain of the transistor is connected to the third drain node V DN2 The second end of the second primary resonant cavity and the second P-type metal oxide semiconductor transistor M P2 The drain of the transistor is connected to the fourth drain node V DP2 The first end of the second secondary resonant cavity and the second N-type metal oxide semiconductor transistor M N2 The gate of the GN2 The second end of the second secondary resonant cavity and the second P-type metal oxide semiconductor transistor M P2 The gate of the GP2 .

[0036] In order to achieve a balanced coupling connection between the first inverse class-F oscillator and the second inverse class-F oscillator, in this embodiment, the first gate node V GN1 and the fourth gate node V GP2 Connect the second gate node V GP1 and the third gate node V GN2 connect.

[0037] When the above-mentioned balanced coupling connection mode is adopted, the first gate node V GN1 and the fourth gate node V GP2 Connect the second gate node V GP1 and the third gate node V GN2 After connection, the second gate node V GP1 and the third gate node V GN2 The connected branch determines the first signal output terminal of the oscillator, at the first gate node V GN1 and the fourth gate node V GP2 The connected branch determines the second signal output terminal of the oscillator.

[0038] In this way, the two inverse F oscillators are connected in a balanced coupling manner, so that the Q2 at the second harmonic frequency (2ω0) and the parallel impedance R of the resonant cavity at the second harmonic frequency are enhanced without affecting the quality factor Q1 of the resonant cavity at the fundamental frequency (ω0). P2 , the phase and amplitude imbalance between the two output ends of the oscillator are eliminated, thereby effectively improving the performance at high operating frequencies.

[0039] Please refer again Figure 1 The oscillator further includes: a first voltage output terminal V G+ And the second voltage output terminal V G- ; First voltage output terminal V G+ Located at the second gate node V GP1 and the third gate node V GN2 Any position of the first connecting branch; the second voltage output terminal V G- Located at the first gate node V GN1 and the fourth gate node V GP2 Any position of the second connecting branch.

[0040] In this embodiment, the first voltage output terminal V G+ And the second voltage output terminal V G- The geometric structure is completely symmetrical. The first voltage output terminal V G+ Or the second voltage output terminal V G-The two differential output ports are connected to the gate terminals of an N-type metal oxide semiconductor transistor and a P-type metal oxide semiconductor transistor, respectively. In this way, the phase and amplitude errors of the voltages of the two differential output ports can be eliminated by using a balanced coupling connection method.

[0041] The first primary resonant cavity and the first secondary resonant cavity are introduced in detail below.

[0042] Please refer again Figure 1 The first primary resonant cavity includes a first primary side coil inductor L P1 and the first primary side capacitor C P1 The first secondary resonant cavity includes a first secondary side coil inductor L S1 And the first secondary side capacitor C S1 .

[0043] Specifically, the first primary side coil inductance L P1 The first terminal and the first primary side capacitor C P1 The first end of the first primary resonant cavity is connected in parallel to the first end of the first primary side coil inductance L P1 The second end and the first primary side capacitor C P1 The second end of the first secondary side coil inductor L is connected in parallel to the second end of the first primary resonant cavity. S1 The first terminal and the first secondary side capacitor C S1 The parallel connection end after the first ends of the first secondary resonant cavity are connected in parallel, and the first secondary side coil inductance L S1 The second end and the first secondary side capacitor C S1 The parallel connected end after the second ends of are connected in parallel is the second end of the first secondary resonant cavity.

[0044] The second primary resonant cavity and the second secondary resonant cavity are introduced in detail below.

[0045] Please refer again Figure 1 , the second primary resonant cavity includes a second primary side coil inductor L P2 and the second primary side capacitor C P2 The second secondary resonant cavity includes a second secondary side coil inductor L S2 And the second secondary side capacitor C S2 .

[0046] Specifically, the second primary side coil inductance L P2 The first terminal and the second primary side capacitor C P2 The parallel connection end of the first end of the second primary resonant cavity is the first end of the second primary side coil inductance L P2 The second terminal and the second primary side capacitor C P2The second end of the second primary resonant cavity is connected in parallel to the second end of the second secondary side coil inductance L. S2 The first terminal and the second secondary side capacitor C S2 The parallel connection end after the first end of the second secondary resonant cavity is connected in parallel, and the second secondary side coil inductance L S2 The second end and the second secondary side capacitor C S2 The parallel connected end after the second ends of are connected in parallel is the second end of the second secondary resonant cavity.

[0047] In this embodiment, the first primary side coil inductance L P1 and the first secondary side coil inductance L S1 The first transformer is formed; the second primary side coil inductance L P2 and the second secondary side coil inductance L S2 A second transformer is formed.

[0048] In this embodiment, the first primary side capacitor C P1 , the first secondary side capacitor C S1 The second primary side capacitor C P2 or the second secondary side capacitor C S2 The tunable capacitor can be voltage-adjustable or digitally adjustable. In one embodiment, the oscillator can use differential switched capacitors for frequency adjustment. Compared to single-ended switched capacitors, differential switched capacitors have a higher quality factor (Q). Therefore, they can improve the quality factor (Q) of the entire resonant cavity at the fundamental frequency and second harmonic frequency, thereby reducing phase noise.

[0049] Specifically, the first primary side capacitor C P1 , the first secondary side capacitor C S1 The second primary side capacitor C P2 or the second secondary side capacitor C S2 is the switched capacitor.

[0050] See also Figure 2 , Figure 2 A schematic diagram of the structure of the switch capacitor provided in this embodiment. Figure 2 As shown, the switched capacitor includes: a switched capacitor array C A , a first varactor C1 and a second varactor C2; a first end of the first varactor C1 and a first end of the second varactor C2 are connected and connected to a tuning voltage V C The second end of the first varactor C1 and the switch capacitor array C A The first end of the second varactor C2 is connected to the switch capacitor array C A The second end of the

[0051] For example, the switched capacitor array C A It is a 5-bit differential switched capacitor array, wherein the first varactor C1 and the second varactor C2 are MOS varactor diodes.

[0052] In this embodiment, if Figure 2 As shown, the switched capacitor array C A The first capacitor branch includes the first capacitors C 31 , the first switch K1 and the second capacitor C 32 The second capacitor branch includes a third capacitor C connected in series 33 , the second switch K2 and the fourth capacitor C 34 The third capacitor branch includes a fifth capacitor C connected in series 35 , the third switch K3 and the sixth capacitor C 36 The fourth capacitor branch includes a seventh capacitor C connected in series 37 , the fourth switch K4 and the eighth capacitor C 38 The fifth capacitor branch includes a ninth capacitor C connected in series 39 , the fifth switch K5 and the tenth capacitor C 310 ;exist Figure 3 Other capacitor branches are omitted. The N-bit switch array can be a 5-bit switch array, which is not limited here. If the first capacitor C 31 and the second capacitor C 32 The sizes of the third capacitor C are C0, C 33 and the fourth capacitor C 34 The sizes of the fifth capacitor C are 2×C0 and C 35 and the sixth capacitor C 36 The size of each is 2 2 ×C0, the seventh capacitor C 37 and the eighth capacitor C 38 The size of each is 2 3 ×C0, the ninth capacitor C 39 and the tenth capacitor C 310 The size of each is 2 4 ×C0. Accordingly, the capacitance of the Nth capacitor branch is 2 N-1 ×C0.

[0053] like Figure 2 As shown, the corresponding control signal B can be input to the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, and the fifth switch K5. <0> 、B <1> 、B <2> 、B <3> and B <4> , to control the conduction and disconnection of each capacitor branch.

[0054] See also Figure 3 , Figure 3FIG. 1 is another structural diagram of the oscillator provided in this embodiment. Figure 1 The oscillator shown is compared to Figure 3 The parasitic capacitance of each transistor is shown in FIG. Figure 3 In the embodiment, the first N-type metal oxide semiconductor transistor M N1 There is a first parasitic capacitance C between the drain and gate GD,N1 , the first N-type metal oxide semiconductor transistor M N1 There is a second parasitic capacitance C between the source and gate GS,N1 The first P-type metal oxide semiconductor transistor M P1 There is a third parasitic capacitance C between the drain and gate GD,P1 , the first P-type metal oxide semiconductor transistor M P1 There is a fourth parasitic capacitance C between the source and gate GS,P1 The second N-type metal oxide semiconductor transistor M N2 There is a fifth parasitic capacitance C between the drain and gate GD,N2 , the second N-type metal oxide semiconductor transistor M N2 There is a sixth parasitic capacitance C between the source and gate GS,N2 The second P-type metal oxide semiconductor transistor M P2 There is a seventh parasitic capacitance C between the drain and gate GD,P2 , the second P-type metal oxide semiconductor transistor M P2 There is an eighth parasitic capacitance C between the source and gate GS,P2 .

[0055] In this embodiment, the Figure 1 The balanced coupling connection shown is in accordance with Figure 1 As shown, the first N-type metal oxide semiconductor transistor M N1 The gate of the second P-type metal oxide semiconductor transistor M P2 The gate of the first P-type metal oxide semiconductor transistor M P1 The gate of the second N-type metal oxide semiconductor transistor M N2 The gate connection of this symmetrical topology makes the first voltage output terminal V G+ And the second voltage output terminal V G- The second harmonic voltage is in phase, and the first drain node V DN1 , the second drain node V DP1 The phase difference between the second harmonic voltages at φ is still close to 180°.

[0056] See also Figure 4A , Figure 4AThe schematic diagram of the oscillator provided in this embodiment for improving the quality factor of the resonant cavity at the second harmonic frequency. The balanced coupling connection method is used so that the second harmonic voltage at the two gates of the oscillator is a common mode signal, so the secondary side capacitor C is not visible. S , which means the secondary side coil inductance L S No induced current is generated in the cavity, thus avoiding the reduction of the cavity quality factor Q2 at the second harmonic frequency (2ω0) (at this time Q2 = Q P ).in, Q P The primary coil inductance L P and the primary side capacitor C P The quality factor of the resonant cavity, the inductance L P The quality factor is The series resistance r CP The series resistance r of the equivalent inductor LP To estimate the quality factor of the entire resonant cavity, we get

[0057] See also Figure 4B , Figure 4B Shown are Q2 and R at the second harmonic resonance point obtained by simulation. P2 Schematic diagram of the change of , compared with the single inverse F oscillator (single-Core), the quality factor Q2 of the oscillator (Dual-Core) provided by this embodiment at the second harmonic frequency (2ω0) increases from 9.3 to 11.5, and the parallel impedance R of the resonant cavity at the second harmonic frequency P2 From 185 to 342Ω. In addition, since the first drain node V DN1 and the second drain node V DP1 The fundamental voltage in the first voltage output terminal V G+ And the second voltage output terminal V G- The output voltages remain out of phase, and they still ensure that the quality factor Q1 at the fundamental frequency (ω0) is 12, which is still relatively high.

[0058] In this embodiment, since the first voltage output terminal V G+ Or the second voltage output terminal V G- Both are connected to the NMOS transistor and the PMOS transistor, which have the same parasitic capacitance to ground. In addition, the first drain node V DN1 and the fourth drain node V DP2 (The second drain node V DP1 and the third drain node V DN2 ) are in phase, so the first voltage output terminal V G+ Or the second voltage output terminal V G-The same parasitic capacitance is also felt relative to the drain node of the MOS transistor. Figure 5A and Figure 5B , Figure 5A The output signal waveform of a single inverse F oscillator is shown in FIG. Figure 5B The output signal waveform of the oscillator provided in this embodiment. Figure 5A and Figure 5B It can be seen that compared with a single inverse F oscillator, the phase mismatch between gate voltages is reduced from 4.8° to 0.03°, and the amplitude ratio (V GP / V GN ) adaptation reduced from 1.03 to 1.00.

[0059] See also Figure 6A and Figure 6B , Figure 6A Schematic diagram of the quality factor change of a single inverse F oscillator obtained by simulation. Figure 6A In the figure, curves S1, S2, and S3 respectively represent the change curves of the quality factor of a single inverse F oscillator when the carrier is offset by 10 MHz, 1 MHz, and 100 kHz. Figure 6B A schematic diagram of the change in the quality factor of the oscillator provided in this embodiment, Figure 6B In the embodiment, curves S4, S5, and S6 respectively represent the quality factor change curves of the oscillator provided by this embodiment when the carrier is offset by 100KHz, 1MHz, and 10MHz. Figure 6A and Figure 6B It can be seen that the quality factor of the second harmonic resonance point of the oscillator provided by this embodiment is greatly enhanced, so that the oscillator provided by this embodiment can achieve a high quality factor from the offset frequency of 100 kHz to 10 MHz.

[0060] It is also noted that the oscillator of this embodiment can be tape-out verified using a 28nm CMOS process, and the chip core area is approximately 0.1mm 2 , which includes a 17.5pF decoupling capacitor. Reliable phase noise measurements are made using a signal analyzer and a downconverter. Figure 7A and Figure 7B Figure 2 depicts the phase noise distribution measured at the lowest operating frequency (15.22 GHz) and the highest operating frequency (18.23 GHz). Each figure is obtained by averaging 20 times. The flicker phase noise frequency boundaries are approximately 310 kHz and 500 kHz at the lowest and highest operating frequencies, respectively.

[0061] See also Figure 8A and Figure 8B , Figure 8A Schematic diagram of phase noise variation measured within the tuning range. Figure 8BSchematic diagram of the quality factor change measured within the tuning range. Figure 8A In FIG. 8 , curve S81 , curve S82 , and curve S83 respectively represent the phase noise variation curves corresponding to the offset from the carrier of 100 KHz, 1 MHz, and 10 MHz. Figure 8B In the figure, curves S84, S85, and S86 represent the corresponding quality factor variations at 10 MHz, 1 MHz, and 100 kHz offsets from the carrier, respectively. At its highest operating frequency, the voltage-controlled oscillator provided in this embodiment achieves peak quality factors of 186.2 and 188.1 dBc / Hz at 1 MHz and 10 MHz offsets, respectively. Over the entire tuning range, the quality factor variation at both 1 MHz and 10 MHz offsets is only approximately 1 dB.

[0062] See also Figure 9 , Figure 9 FIG. 1 is a performance reference diagram of the oscillator provided in this embodiment. Figure 9 As shown, the oscillator provided by this embodiment is compared with other voltage-controlled oscillators operating above 15 GHz. Among the voltage-controlled oscillators manufactured by 28 nm CMOS process, the oscillator provided by this embodiment achieves the highest quality factor and tuning quality factor (FoM T ), narrowing the performance gap with voltage-controlled oscillators produced using 65nm or 40nm CMOS processes. Furthermore, when the operating frequencies are normalized to an 18GHz carrier, the oscillator provided by this embodiment achieves the lowest phase noise at a 10MHz offset frequency.

[0063] The oscillator provided in this embodiment couples two inverse class F oscillators together, namely Figure 1 In the oscillator, the first N-type metal oxide semiconductor transistor M N1 The gate of the second P-type metal oxide semiconductor transistor M P2 The gate of the first P-type metal oxide semiconductor transistor M P1 The gate of the second N-type metal oxide semiconductor transistor M N2 The gate connection increases the resonant cavity's Q factor at the second harmonic frequency without reducing its Q factor at the fundamental frequency. Improving the resonant cavity's Q factor at the second harmonic frequency helps reduce the impact of transistor flicker noise on the oscillator's phase noise, thereby reducing the oscillator's output phase noise at smaller offset frequencies. Since the resonant cavity's Q factor at the fundamental frequency remains unchanged, the oscillator's output phase noise remains unchanged at larger offset frequencies. Furthermore, the symmetrical circuit structure reduces phase and amplitude errors between the oscillator's differential output voltages.

[0064] In addition, an embodiment of the present disclosure provides a chip, which includes the above-mentioned oscillator and thus has the corresponding functions and beneficial effects of the above-mentioned oscillator.

[0065] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or terminal comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or terminal comprising the element.

[0066] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An oscillator, characterized in that: include: a first inverse class-F oscillator and a second inverse class-F oscillator, wherein the first inverse class-F oscillator comprises a first resonant cavity, a first N-type metal oxide semiconductor transistor, and a first P-type metal oxide semiconductor transistor, wherein ports of the first resonant cavity are respectively connected to the drain and gate of the first N-type metal oxide semiconductor transistor and the drain and gate of the first P-type metal oxide semiconductor transistor; The second inverse class-F oscillator includes a second resonant cavity, a second N-type metal oxide semiconductor transistor, and a second P-type metal oxide semiconductor transistor, wherein ports of the second resonant cavity are respectively connected to the drain and gate of the second N-type metal oxide semiconductor transistor and the drain and gate of the second P-type metal oxide semiconductor transistor; The gate of the first N-type metal oxide semiconductor transistor is connected to the gate of the second P-type metal oxide semiconductor transistor, and the gate of the first P-type metal oxide semiconductor transistor is connected to the gate of the second N-type metal oxide semiconductor transistor; The sources of the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor are respectively grounded, and the sources of the first P-type metal oxide semiconductor transistor and the second P-type metal oxide semiconductor transistor are respectively connected to a power supply; The first resonant cavity includes a first primary resonant cavity and a first secondary resonant cavity; The first end of the first primary resonant cavity and the drain of the first N-type metal oxide semiconductor transistor are connected to a first drain node; The second end of the first primary resonant cavity and the drain of the first P-type metal oxide semiconductor transistor are connected to a second drain node; The first end of the first secondary resonant cavity and the gate of the first N-type metal oxide semiconductor transistor are connected to a first gate node; The second end of the first secondary resonant cavity and the gate of the first P-type metal oxide semiconductor transistor are connected to a second gate node; The second resonant cavity includes a second primary resonant cavity and a second secondary resonant cavity; The first end of the second primary resonant cavity and the drain of the second N-type metal oxide semiconductor transistor are connected to a third drain node; The second end of the second primary resonant cavity and the drain of the second P-type metal oxide semiconductor transistor are connected to a fourth drain node; The first end of the second secondary resonant cavity and the gate of the second N-type metal oxide semiconductor transistor are connected to a third gate node; The second end of the second secondary resonant cavity and the gate of the second P-type metal oxide semiconductor transistor are connected to a fourth gate node.

2. The oscillator according to claim 1, wherein The first gate node is connected to the fourth gate node; The second gate node is connected to the third gate node.

3. The oscillator according to claim 2, wherein: It also includes: a first voltage output terminal and a second voltage output terminal; The first voltage output terminal is located at any position of the first connecting branch between the second gate node and the third gate node; The second voltage output terminal is located at any position of the second connecting branch between the first gate node and the fourth gate node.

4. The oscillator according to claim 1, wherein: The first primary resonant cavity includes a first primary side coil inductance and a first primary side capacitor, and the first secondary resonant cavity includes a first secondary side coil inductance and a first secondary side capacitor; The first end of the first primary side coil inductor and the first end of the first primary side capacitor are connected in parallel to form the first end of the first primary resonant cavity, and the second end of the first primary side coil inductor and the second end of the first primary side capacitor are connected in parallel to form the second end of the first primary resonant cavity. The first end of the first secondary side coil inductor and the first end of the first secondary side capacitor are connected in parallel to form the first end of the first secondary resonant cavity, and the second end of the first secondary side coil inductor and the second end of the first secondary side capacitor are connected in parallel to form the second end of the first secondary resonant cavity.

5. The oscillator according to claim 4, characterized in that The second primary resonant cavity includes a second primary side coil inductance and a second primary side capacitor, and the second secondary resonant cavity includes a second secondary side coil inductance and a second secondary side capacitor; The first end of the second primary side coil inductor and the first end of the second primary side capacitor are connected in parallel to form the first end of the second primary resonant cavity, and the second end of the second primary side coil inductor and the second end of the second primary side capacitor are connected in parallel to form the second end of the second primary resonant cavity. The first end of the second secondary side coil inductor and the first end of the second secondary side capacitor are connected in parallel to form the first end of the second secondary resonant cavity, and the second end of the second secondary side coil inductor and the second end of the second secondary side capacitor are connected in parallel to form the second end of the second secondary resonant cavity.

6. The oscillator according to claim 5, characterized in that The first primary side capacitor, the first secondary side capacitor, the second primary side capacitor or the second secondary side capacitor is a switched capacitor; The switch capacitor includes: a switch capacitor array, a first varactor and a second varactor; The first end of the first varactor and the first end of the second varactor are connected and connected to a tuning voltage; The second end of the first varactor is connected to the first end of the switched capacitor array; The second end of the second varactor is connected to the second end of the switched capacitor array.

7. The oscillator according to claim 6, characterized in that The first primary side coil inductor and the first secondary side coil inductor constitute a first transformer; The second primary-side coil inductor and the second secondary-side coil inductor form a second transformer.

8. A chip, characterized in that: The oscillator comprises the oscillator according to any one of claims 1 to 7.

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