Offset Voltage Background Calibration Method for Pipeline Successive Approximation ADC

Abstract

The present invention discloses a background calibration method for the offset voltage of a pipelined successive approximation ADC, comprising: simultaneously sampling an input signal through a main DAC and a small-capacitor DAC, the output of the small-capacitor DAC being input to the main DAC after passing through a comparator and a logic circuit, the main DAC being amplified by an amplifier to generate a residual signal; the successive approximation ADC receiving the residual signal, finding the maximum and minimum voltage values ​​of the residual signal, averaging to obtain a mean value, comparing the mean value with the amplifier output mean value in the absence of an offset voltage, and determining the polarity of the offset voltage; and controlling the calibration DAC to output a calibration voltage based on the offset voltage polarity determination result, inputting the calibration voltage into a comparator, and offsetting the offset voltage of the comparator and the amplifier. The present invention is unaffected by PVT variations and jitter in the presence of an offset voltage, performs statistics and calculations on the polarity of the offset voltage in the digital domain, and calibrates the offset voltage of the comparator in the analog domain, with low cost and high accuracy.

Description

Technical Field

[0001] The invention provides a background calibration solution for Pipelined-SAR ADC offset voltage, belonging to the technical field of digital-analog hybrid integrated circuit design. Background Art

[0002] The pipelined-SAR ADC cascades multiple medium-resolution SAR ADCs in a pipelined fashion, combining the high speed and precision of pipelined ADCs with the energy efficiency of SAR ADCs. This architecture overcomes the exponential increase in cost of flash ADCs in traditional pipelined ADCs with the number of quantization bits. Furthermore, this architecture utilizes multiple stages of medium-resolution SAR ADCs to perform coarse and fine quantization on the sampled signal. Furthermore, the pipelined ADC utilizes inter-stage margin amplification to amplify the margin signal from the preceding SAR ADC before transferring it to the second-stage SAR ADC for quantization, thereby improving the overall ADC accuracy.

[0003] Pipelined-SAR ADCs have become a research hotspot in ADC design both domestically and internationally in recent years due to their potential to achieve high speed, high accuracy, and high energy efficiency. However, the offset voltage of the amplifiers and comparators in pipelined-SAR ADCs limits further performance improvements. Offset voltage can arise from a variety of sources, including process factors such as transistor size, and threshold mismatch caused by variations in threshold voltage. The presence of offset voltage creates a fixed horizontal offset between the actual margin signal transfer characteristic curve and the ideal transfer characteristic curve. When this offset is large, the amplifier output swing increases, introducing amplifier nonlinearity. When the offset increases to the point where the amplifier output exceeds the quantization range of the next stage, analog signal loss occurs, significantly degrading ADC accuracy. Reducing offset voltage can be achieved by increasing the area of ​​transistors or other passive components, but this significantly increases circuit hardware and power consumption. Calibration is a low-cost solution, but traditional front-end offset calibration cannot track process, voltage, and temperature (PVT) variations, requiring recalibration for every PVT change. Some traditional background offset calibration methods take up extra working phases, affecting the normal operation of the ADC and reducing circuit speed. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems mentioned in the background technology and provide a background calibration method for the offset voltage of a pipelined successive approximation ADC.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0006] The offset voltage background calibration method of a pipeline successive approximation ADC is characterized by comprising the following steps:

[0007] Step 1: The input signal is sampled simultaneously by the main DAC and the small-capacitor DAC. The small-capacitor DAC outputs a first analog signal. The first analog signal is converted into a first-stage digital output after passing through a comparator and a logic circuit. The first-stage digital output is input into the main DAC. The main DAC converts the sampled input signal and the first-stage digital output and subtracts them. The obtained second analog signal is amplified by an amplifier to generate a residual signal.

[0008] Step 2: Successive approximation ADC receives the residual signal and outputs the second-level digital output. The maximum value of the second-level digital output voltage is found through sample statistics. and voltage minimum ,Will and Add and average to get the mean ,Will Compare this with the amplifier output mean value (center boundary) when there is no offset voltage to determine the polarity of the offset voltage.

[0009] Step 3: Based on the offset voltage polarity determination result, the calibration DAC is controlled to output the calibration voltage, and the calibration voltage is input into the comparator to offset the offset voltage of the comparator and the amplifier.

[0010] To optimize the above technical solutions, specific measures taken also include:

[0011] The capacitance value of the small-capacitance DAC is smaller than the capacitance value of the main DAC.

[0012] In step 2, the specific method for determining the polarity of the offset voltage is to find the maximum output voltage of the amplifier by counting the digital output of the second stage. , voltage minimum , find the mean voltage , if the inter-stage gain G changes due to objective factors or there is jitter, and After being quantized by the successive approximation ADC, the corresponding digital output is obtained and It also becomes uncertain, so 、 The upper boundary of the amplifier output , lower boundary Comparison will lead to errors in offset voltage polarity judgment due to interference from gain G and jitter. Therefore, the voltage mean is used. Compare with the center boundary to eliminate the interference of inter-stage gain G and jitter, where the center boundary is the average of the upper and lower boundaries of the amplifier output signal when there is no offset voltage. In the case of offset voltage, taking jitter into account, the maximum output voltage of the amplifier , voltage minimum And the voltage mean for:

[0013] (1)

[0014] in is the ideal margin signal when the input signal is zero, is the first stage comparator offset voltage, is the interstage amplifier offset voltage, is the amplitude value of the jitter margin increase, G is the inter-stage gain, and the voltage mean value of formula (1) is It is only related to the offset voltage and inter-stage gain. In the digital domain, the quantized mean With center boundary By comparison we get:

[0015] (2)

[0016] Determine the polarity of the offset voltage according to formula (2).

[0017] The present invention compares the mean of the maximum and minimum values ​​with the center boundary to eliminate interference from signal gain and jitter, as well as filter out noise. In the presence of an offset voltage, the polarity of the offset voltage can be statistically calculated and computed in the digital domain, unaffected by PVT variations. During the amplifier's operating phase, the comparator is idle. Therefore, after determining the offset voltage polarity, this time can be used to calibrate the comparator's offset voltage in the analog domain. This does not interfere with the normal operation of the signal-sensitive amplifier and does not require an additional operating phase, thus maintaining the ADC's operating speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of the calibration method of the present invention;

[0019] Figure 2 This is a graph showing the effect of offset voltage on the amplifier output margin vs. input signal relationship curve;

[0020] Figure 3 This is a convergence diagram of offset voltage of the interstage gain 15 of the present invention simulated in MATLAB;

[0021] Figure 4This is a convergence diagram of offset voltage of the inter-stage gain of 16.5 simulated in MATLAB. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0023] The present invention provides a pipelined, successive-approximation ADC offset voltage background calibration method. This method performs background calibration on the offset of the ADC's comparator and amplifier. By cooperating with a main DAC and a small-capacitor DAC, the residual amplified by the amplifier after the comparator comparison is converted by the successive-approximation ADC. The maximum and minimum voltage values ​​are then found through sample statistics, added, and averaged. The resulting value is compared with the center boundary to determine the polarity of the offset voltage. The offset voltage polarity determination result controls the output of a calibration digital-to-analog converter (DAC). This calibration voltage is then input to the comparator input to offset the offset voltage of the comparator and amplifier.

[0024] like Figure 1 The following is a basic block diagram of the entire calibration scheme. The input signal is sampled simultaneously by the main DAC and the small-capacitor DAC. The main DAC has a larger capacitance value, which can limit the thermal noise of the sampling. The small-capacitor DAC, comparator, and SAR logic circuit are responsible for signal quantization. The small-capacitor DAC has a smaller capacitance value, which allows for a faster reference voltage establishment speed, allowing for a quick first-stage digital output to be obtained and then input into the main DAC. The main DAC converts and subtracts the sampled input signal from the first-stage digital output. The resulting second analog signal is amplified by an amplifier to produce a residual signal. Due to the offset voltage of the comparator and amplifier, the residual signal will be offset. The digital output obtained after the residual signal is quantized by the successive approximation ADC is statistically analyzed to find the maximum and minimum values ​​and calculate the average. The average of the maximum and minimum values ​​is then compared with the center boundary to determine the sign of the offset voltage. Finally, based on the comparison result, the calibration DAC is controlled to generate a calibration voltage that is input to the comparator input. Because the offset voltages of the amplifier and comparator affect the amplifier output in a similar manner, the polarity determination of the present invention takes into account the influence of both. Therefore, input voltage calibration at the comparator input can complete the entire calibration process.

[0025] like Figure 2 The figure shows the influence of offset voltage on the margin-to-input signal relationship curve of the amplifier output, which includes two curves: one for zero offset voltage and the other for offset voltage greater than zero.

[0026] The maximum output of the amplifier (Point A), minimum value (Point B) and the mean (Point C). If the inter-stage gain G changes due to factors such as process and temperature, or if there is jitter (dither injection), and After being quantized by the successive approximation ADC, the corresponding digital output is obtained and It also becomes uncertain. At this time, if the traditional upper and lower boundaries are used as reference methods, and Respectively with the upper boundary , lower boundary If the comparison is made, the offset voltage polarity may be incorrectly determined due to the interference of gain and jitter. The present invention uses the mean of the maximum and minimum values ​​to compare with the center boundary to eliminate the interference of signal gain and jitter. The center boundary is the mean of the upper and lower boundaries of the amplifier output signal when there is no offset voltage. ), taking jitter into account, the voltages corresponding to points A, B, and C ( 、 and )for:

[0027] (1)

[0028] in is the ideal margin signal when the input signal is zero, is the first stage comparator offset voltage, is the interstage amplifier offset voltage, is the amplitude value of the jitter margin increase, G is the inter-stage gain, and the voltage mean value of formula (1) is It is only related to the offset voltage and inter-stage gain. In the digital domain, the quantized mean With center boundary By comparison we get:

[0029] (2)

[0030] According to formula (2), the polarity of the offset voltage is determined. Therefore, a large or small gain G has no effect on polarity discrimination.

[0031] like Figure 3 、 4 Shown is the offset voltage convergence diagram of the present invention simulated in MATLAB. Figure 3 and Figure 4The two cases are respectively when the inter-stage gain of 12-bit Pipeline SAR ADC is 15 and 16.5 and there is jitter injection. By comparison, it is found that the change in gain and jitter injection does not lead to errors in the polarity judgment of the offset voltage, and the offset calibration can still work normally, which also proves the correctness of formula (2). The total offset voltage of the first-stage comparator and the inter-stage amplifier is set to 0.005V. In the stage before calibration, the margin voltage is overall upward, and then through the offset calibration scheme of the present invention, the margin voltage begins to gradually move downward until it returns to the normal range. The present invention controls the input calibration voltage by comparing the size of the mean and the center boundary to determine the polarity of the offset, thereby offsetting the value of the total offset voltage. In the simulation stage, the average value of the maximum and minimum values ​​is calculated every 800 cycles and the offset voltage is adjusted. The accuracy of each calibration is 0.001, so we can see that the offset voltage is calibrated to 0 after the fifth time.

[0032] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A pipelined successive approximation ADC offset voltage background calibration method, characterized by: The following steps are involved: Step 1: The input signal is sampled simultaneously by the main DAC and the small-capacitor DAC. The small-capacitor DAC outputs a first analog signal. The first analog signal is converted into a first-stage digital output after passing through a comparator and a logic circuit. The first-stage digital output is input into the main DAC. The main DAC converts the sampled input signal and the first-stage digital output and subtracts them. The obtained second analog signal is amplified by an amplifier to generate a residual signal. Step 2: Successive approximation ADC receives the residual signal and outputs the second-level digital output. The maximum value of the second-level digital output voltage is found through sample statistics. and voltage minimum ,Will and Add and average to get the mean ,Will Compare this with the amplifier output mean value (center boundary) when there is no offset voltage to determine the polarity of the offset voltage. Step 3: Based on the offset voltage polarity determination result, the calibration DAC is controlled to output the calibration voltage, and the calibration voltage is input into the comparator to offset the offset voltage of the comparator and the amplifier.

2. The offset voltage background calibration method of the pipelined successive approximation ADC according to claim 1, wherein: The capacitance value of the small capacitance DAC is smaller than the capacitance value of the main DAC.

3. The offset voltage background calibration method of the pipelined successive approximation ADC according to claim 1, wherein: In step 2, the specific method for determining the polarity of the offset voltage is to find the maximum output voltage of the amplifier by counting the digital output of the second stage. , voltage minimum , find the mean voltage , if the inter-stage gain G changes due to objective factors or there is jitter, and After being quantized by the successive approximation ADC, the corresponding digital output is obtained and It also becomes uncertain, so 、 The upper boundary of the amplifier output , lower boundary Comparison will lead to errors in offset voltage polarity judgment due to interference from gain G and jitter. Therefore, the voltage mean is used. Compare with the center boundary to eliminate the interference of inter-stage gain G and jitter, where the center boundary is the average of the upper and lower boundaries of the amplifier output signal when there is no offset voltage. In the case of offset voltage, taking jitter into account, the maximum output voltage of the amplifier , voltage minimum And the voltage mean for: (1) in is the ideal margin signal when the input signal is zero, is the first stage comparator offset voltage, is the interstage amplifier offset voltage, is the amplitude value of the jitter margin increase, G is the inter-stage gain, and the voltage mean value of formula (1) is It is only related to the offset voltage and inter-stage gain. In the digital domain, the quantized mean With center boundary By comparison we get: (2) Determine the polarity of the offset voltage according to formula (2).

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