A data processing method and device based on register

Abstract

The present invention discloses a data processing method and device based on a register, the method comprising: obtaining a write task request; determining a target write information set according to the write task request and a preset write rule; determining a write instruction set according to the target write information set; the write instruction set is used to indicate that a write operation is performed on the data information corresponding to the write task request in the register. It can be seen that the present invention can process the write task request using the write rule to obtain the target write information, and then determine to obtain a write instruction for indicating that a write operation is performed on the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, thereby improving system concurrency and parallel computing capabilities, and improving system performance.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a register-based data processing method and device. Background Art

[0002] When operating the shared registers in the critical section, the common practice in the industry is to lock and protect the relevant code for operating the register critical section, ensuring that there is only one execution flow entering the register critical section at any time, thereby avoiding concurrent access to the register critical section and ensuring the logical correctness of the operation of the register critical section resources. Although locking can avoid concurrent access to critical section resources, it also consumes CPU computing power and reduces system performance. Therefore, it is particularly important to provide a register-based data processing method and device to achieve lock-free concurrent processing of registers, release CPU computing power, and thereby improve the system's concurrency and parallel computing capabilities, and improve system performance. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a register-based data processing method and device, which can use write rules to process write task requests to obtain target write information, and then determine to obtain a write instruction for instructing to perform a write operation on the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and improving system performance.

[0004] In order to solve the above technical problem, a first aspect of an embodiment of the present invention discloses a register-based data processing method, the method comprising:

[0005] Get write task request;

[0006] Determining a target write information set according to the write task request and a preset write rule;

[0007] A write instruction set is determined according to the target write information set; the write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in a register.

[0008] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the write task request includes a set of task information to be written;

[0009] The step of determining a target write information set according to the write task request and a preset write rule includes:

[0010] Obtaining the number of operation bits corresponding to the register; the number of operation bits information includes L bit slots; L is an even positive integer greater than or equal to 2;

[0011] Determining a target task information set according to the to-be-written task information set and the operation bit number information;

[0012] According to the target task information set and the preset slot screening rule, a target write information set is determined; the target write information set includes a target slot information set and a target write value information set corresponding to the target slot information set.

[0013] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the set of task information to be written includes N pieces of task information to be written;

[0014] Determining a target task information set according to the to-be-written task information set and the operation bit number information includes:

[0015] Determine whether the N is greater than the L, and obtain a first determination result;

[0016] When the first judgment result indicates that N is greater than L, determining a target task information set according to a preset task screening rule and the task information set to be written;

[0017] When the first judgment result indicates that N is not greater than L, the to-be-written task information set is determined to be a target task information set.

[0018] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the target task information set includes target task quantity information and a to-be-written value information set;

[0019] Determining a target write information set according to the target task information set and a preset bit slot screening rule includes:

[0020] Determine a target slot information set according to the target task quantity information and the operation bit number information; the target slot information set includes M target slot information; M is less than or equal to half of L;

[0021] The target write value information set is determined according to the target slot information set and the to-be-written value information set; the target write value information set includes the M target write value information.

[0022] As an optional implementation, in the first aspect of the embodiment of the present invention, the set of value information to be written includes the M value information to be written; the information to be written includes code writing information and mask writing information;

[0023] The target bit slot information includes code bit slot information and mask bit slot information;

[0024] The target write value information includes target code information and target mask information;

[0025] The step of determining the target write value information set according to the target bit slot information set and the to-be-written value information set includes:

[0026] For any target bit slot information, filter out the to-be-written value information that matches the target bit slot information from the to-be-written value information set as the target write value information corresponding to the target bit slot information;

[0027] Determine the target code information corresponding to the target bit slot information according to the code writing information corresponding to the target write value information and the code bit slot information corresponding to the target bit slot information;

[0028] The target mask information corresponding to the target bit slot information is determined according to the mask write information corresponding to the target write value information and the mask bit slot information corresponding to the target bit slot information.

[0029] As an optional implementation manner, in the first aspect of the embodiment of the present invention, determining the write instruction set according to the target write information set includes:

[0030] Determine a write register instruction set according to the target write information set and a preset write instruction set to be selected; the write register instruction set includes a plurality of write register instructions;

[0031] A write operation instruction set is determined according to the write register instruction set.

[0032] As an optional implementation manner, in the first aspect of the embodiment of the present invention,

[0033] The target write information set includes a plurality of target bit slot information and target write value information;

[0034] The set of write instructions to be selected includes update instructions and / or vacancy instructions;

[0035] The step of determining a write register instruction set according to the target write information set and a preset write instruction set to be selected includes:

[0036] For any of the target bit slot information, determine whether the target bit slot information meets the register update condition to obtain a second determination result;

[0037] When the second judgment result indicates that the target bit slot information satisfies the register update condition, determining that the write register instruction corresponding to the target bit slot information is an update instruction; the update instruction is used to instruct to write the target write value information corresponding to the target bit slot information into the corresponding register;

[0038] When the second judgment result indicates that the target slot information does not satisfy the register update condition, it is determined that the write register instruction corresponding to the target slot information is a vacant instruction.

[0039] A second aspect of an embodiment of the present invention discloses a register-based data processing device, the device comprising:

[0040] An acquisition module is used to obtain a write task request;

[0041] A first determination module, configured to determine a target write information set according to the write task request and a preset write rule;

[0042] The second determination module is used to determine a write instruction set according to the target write information set; the write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in the register.

[0043] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the write task request includes a set of task information to be written;

[0044] The first determination module includes an acquisition submodule, a first determination submodule and a second determination submodule, wherein:

[0045] The acquisition submodule is used to acquire the operation bit number information corresponding to the register; the operation bit number information includes L bit slots; L is an even positive integer greater than or equal to 2;

[0046] The first determination submodule is used to determine a target task information set according to the to-be-written task information set and the operation bit number information;

[0047] The second determination submodule is used to determine a target write information set according to the target task information set and a preset slot screening rule; the target write information set includes a target slot information set and a target write value information set corresponding to the target slot information set.

[0048] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the set of task information to be written includes N pieces of task information to be written;

[0049] The specific manner in which the first determination submodule determines the target task information set according to the to-be-written task information set and the operation bit number information is as follows:

[0050] Determine whether the N is greater than the L, and obtain a first determination result;

[0051] When the first judgment result indicates that N is greater than L, determining a target task information set according to a preset task screening rule and the task information set to be written;

[0052] When the first judgment result indicates that N is not greater than L, the to-be-written task information set is determined to be a target task information set.

[0053] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the target task information set includes target task quantity information and a to-be-written value information set;

[0054] The specific manner in which the second determination submodule determines the target write information set according to the target task information set and the preset bit slot screening rule is:

[0055] Determine a target slot information set according to the target task quantity information and the operation bit number information; the target slot information set includes M target slot information; M is less than or equal to half of L;

[0056] The target write value information set is determined according to the target slot information set and the to-be-written value information set; the target write value information set includes the M target write value information.

[0057] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the set of value information to be written includes the M value information to be written; the information to be written includes code writing information and mask writing information;

[0058] The target bit slot information includes code bit slot information and mask bit slot information;

[0059] The target write value information includes target code information and target mask information;

[0060] The specific manner in which the second determination submodule determines the target write value information set according to the target bit slot information set and the to-be-written value information set is:

[0061] For any target bit slot information, filter out the to-be-written value information that matches the target bit slot information from the to-be-written value information set as the target write value information corresponding to the target bit slot information;

[0062] Determine the target code information corresponding to the target bit slot information according to the code writing information corresponding to the target write value information and the code bit slot information corresponding to the target bit slot information;

[0063] The target mask information corresponding to the target bit slot information is determined according to the mask write information corresponding to the target write value information and the mask bit slot information corresponding to the target bit slot information.

[0064] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the second determination module determines the write instruction set according to the target write information set in a specific manner as follows:

[0065] Determine a write register instruction set according to the target write information set and a preset write instruction set to be selected; the write register instruction set includes a plurality of write register instructions;

[0066] A write operation set is determined according to the write register instruction set.

[0067] As an optional implementation manner, in the second aspect of the embodiment of the present invention, the target write information set includes a plurality of target bit slot information and target write value information;

[0068] The set of write instructions to be selected includes update instructions and / or vacancy instructions;

[0069] The specific manner in which the second determination module determines the write register instruction set according to the target write information set and the preset write instruction set to be selected is:

[0070] For any of the target bit slot information, determine whether the target bit slot information meets the register update condition to obtain a second determination result;

[0071] When the second judgment result indicates that the target bit slot information satisfies the register update condition, determining that the write register instruction corresponding to the target bit slot information is an update instruction; the update instruction is used to instruct to write the target write value information corresponding to the target bit slot information into the corresponding register;

[0072] When the second judgment result indicates that the target slot information does not satisfy the register update condition, it is determined that the write register instruction corresponding to the target slot information is a vacant instruction.

[0073] A third aspect of the present invention discloses another register-based data processing device, the device comprising:

[0074] A memory storing executable program code;

[0075] a processor coupled to the memory;

[0076] The processor calls the executable program code stored in the memory to execute part or all of the steps in the register-based data processing method disclosed in the first aspect of the embodiment of the present invention.

[0077] The fourth aspect of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute some or all of the steps in the register-based data processing method disclosed in the first aspect of the embodiment of the present invention.

[0078] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0079] In an embodiment of the present invention, a write task request is obtained; a target write information set is determined according to the write task request and a preset write rule; a write instruction set is determined according to the target write information set; and the write instruction set is used to instruct a write operation to be performed on the data information corresponding to the write task request in the register. It can be seen that the present invention can process the write task request using the write rule to obtain the target write information, and then determine to obtain a write instruction for instructing a write operation to be performed on the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system concurrency and parallel computing capabilities, and improving system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0081] Figure 1 It is a flowchart of a register-based data processing method disclosed in an embodiment of the present invention;

[0082] Figure 2 It is a flowchart of another register-based data processing method disclosed in an embodiment of the present invention;

[0083] Figure 3 It is a structural schematic diagram of a register-based data processing device disclosed in an embodiment of the present invention;

[0084] Figure 4 is a schematic diagram of the structure of another register-based data processing device disclosed in an embodiment of the present invention;

[0085] Figure 5 A schematic diagram of the structure of another register-based data processing device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0086] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or equipment.

[0088] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0089] The present invention discloses a register-based data processing method and device, which can process a write task request using a write rule to obtain target write information, and then determine to obtain a write instruction for instructing to write the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thus improving system concurrency and parallel computing capabilities, and improving system performance. The following are detailed descriptions.

[0090] Embodiment 1

[0091] See also Figure 1 , Figure 1 : is a flow chart of a register-based data processing method disclosed in an embodiment of the present invention. Figure 1 The register-based data processing method described is applied to a data processing system, such as a local server or a cloud server for register-based data processing management, and the embodiments of the present invention are not limited thereto. Figure 1 As shown, the register-based data processing method may include the following operations:

[0092] 101. Get a write task request.

[0093] 102. Determine a target write information set according to the write task request and preset write rules.

[0094] 103. Determine a write instruction set according to the target write information set.

[0095] In the embodiment of the present invention, the above-mentioned write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in the register.

[0096] In the embodiment of the present invention, the above-mentioned write instruction set includes a write register instruction set and a write operation instruction set.

[0097] Optionally, the above-mentioned write register instruction is used to instruct writing target code information into a register.

[0098] Optionally, the above-mentioned write operation instruction is performed after the above-mentioned write register instruction is executed.

[0099] Optionally, the above target writing information set includes several target writing information.

[0100] Optionally, one target write information corresponds to only one write register instruction.

[0101] Optionally, the number of the above-mentioned write operation instructions is less than or equal to the number of write register instructions.

[0102] It can be seen that the register-based data processing method described in the embodiment of the present invention can use write rules to process write task requests to obtain target write information, and then determine to obtain a write instruction set for indicating a write operation to be performed on the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and enhancing system performance.

[0103] In an optional embodiment, the above-mentioned writing task request includes a set of task information to be written;

[0104] In the above step 102, according to the writing task request and the preset writing rule, a target writing information set is determined, including:

[0105] Get the operand bit information corresponding to the register; the operand bit information includes L bit slots; L is an even positive integer greater than or equal to 2;

[0106] Determine the target task information set according to the task information set to be written and the operation bit information;

[0107] According to the target task information set and the preset slot screening rules, a target write information set is determined; the target write information set includes a target slot information set and a target write value information set corresponding to the target slot information set.

[0108] Optionally, the above-mentioned slots include high-level slots and low-level slots.

[0109] Optionally, the above L is determined based on the CPU.

[0110] Preferably, the above L is 32 or 64.

[0111] It can be seen that the register-based data processing method described in the embodiment of the present invention can comprehensively process the task information to be written and the operation bit number information to obtain the target task information, and then use the bit slot screening rules to process the target task information to obtain the target bit slot information and the target write value information, which is conducive to realizing the lock-free concurrent processing of registers, releasing the CPU computing power, and then improving the system concurrency and parallel computing capabilities, and improving the system performance.

[0112] In another optional embodiment, the above-mentioned set of task information to be written includes N pieces of task information to be written;

[0113] The target task information set is determined based on the task information set to be written and the operation bit information, including:

[0114] Determine whether N is greater than L, and obtain a first determination result;

[0115] When the first judgment result indicates that N is greater than L, a target task information set is determined according to a preset task screening rule and a task information set to be written;

[0116] When the first judgment result indicates that N is not greater than L, the task information set to be written is determined to be the target task information set.

[0117] In this optional embodiment, as an optional implementation mode, the specific implementation mode of determining the target task information set according to the preset task screening rules and the task information set to be written is:

[0118] All the task information to be written in the task information set to be written are sorted in the order of generation time to obtain a time task sequence;

[0119] The first L task information to be written are selected from the above time task sequence as the target task information.

[0120] In this optional embodiment, as another optional implementation, the specific implementation method of determining the target task information set according to the preset task screening rules and the task information set to be written is:

[0121] Filter out all the task information to be written in the set of task information to be written whose mask writing information corresponding to the task information to be written meets the writing update condition as the task information to be selected for writing;

[0122] Determine whether the number of the above-mentioned to-be-selected writing task information is greater than L, and obtain a number determination result;

[0123] When the first judgment result indicates that the number of the above-mentioned to-be-selected writing task information is not greater than L, the to-be-selected writing task information is determined to be the target task information.

[0124] Optionally, the above write update condition is that the bit corresponding to Mask is 1.

[0125] It can be seen that the register-based data processing method described in the embodiment of the present invention can determine the target task information by judging the task information to be written and the number of bit slots, and combining the task screening rules to comprehensively determine the target task information, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and enhancing system performance.

[0126] In yet another optional embodiment, the target task information set includes target task quantity information and a to-be-written value information set;

[0127] The target writing information set is determined according to the target task information set and the preset bit slot screening rules, including:

[0128] According to the target task quantity information and the operation bit number information, a target bit slot information set is determined; the target bit slot information set includes M target bit slot information; M is less than or equal to one half of L;

[0129] According to the target bit slot information set and the to-be-written value information set, a target write value information set is determined; the target write value information set includes M target write value information.

[0130] Optionally, the above-mentioned one target slot information corresponds to only one target write value information.

[0131] It can be seen that the register-based data processing method described in the embodiment of the present invention can obtain the target bit slot information by comprehensively processing the target task quantity information and the operation bit number information, and then comprehensively determine the target write value information in combination with the information of the value to be written, which is more conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system concurrency and parallel computing capabilities, and improving system performance.

[0132] In yet another optional embodiment, the above-mentioned set of value information to be written includes M value information to be written; the information to be written includes code writing information and mask writing information;

[0133] The target bit slot information includes code bit slot information and mask bit slot information;

[0134] The target write value information includes target code information and target mask information;

[0135] The above-mentioned determining the target write value information set according to the target bit slot information set and the to-be-written value information set includes:

[0136] For any target bit slot information, select the to-be-written value information matching the target bit slot information from the to-be-written value information set as the target write value information corresponding to the target bit slot information;

[0137] Determine the target code information corresponding to the target bit slot information according to the code writing information corresponding to the target write value information and the code bit slot information corresponding to the target bit slot information;

[0138] The target mask information corresponding to the target bit slot information is determined according to the mask write information corresponding to the target write value information and the mask bit slot information corresponding to the target bit slot information.

[0139] Optionally, the mask writing information includes that the bit corresponding to the Mask is 0, or that the bit corresponding to the Mask is 1.

[0140] Optionally, the above-mentioned code slot information includes slot number information and / or code storage information, which is not limited in the embodiment of the present invention.

[0141] Optionally, the mask bit slot information includes bit slot number information and / or mask storage information, which is not limited in this embodiment of the present invention.

[0142] It can be seen that the register-based data processing method described in the embodiment of the present invention can filter out the target write value information corresponding to the target bit slot information from the set of value information to be written, and then determine the target code information and target mask information corresponding to the target bit slot information, which is more conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thus improving the system concurrency and parallel computing capabilities, and improving system performance.

[0143] Embodiment 2

[0144] See also Figure 2 , Figure 2 is a flow chart of another register-based data processing method disclosed in an embodiment of the present invention. Figure 2 The register-based data processing method described is applied to a data processing system, such as a local server or a cloud server for register-based data processing management, and the embodiments of the present invention are not limited thereto. Figure 2As shown, the register-based data processing method may include the following operations:

[0145] 201. Get a write task request.

[0146] 202. Determine a target write information set according to the write task request and a preset write rule.

[0147] 203. Determine a write register instruction set according to the target write information set and the preset candidate write instruction set.

[0148] In the embodiment of the present invention, the above-mentioned write register instruction set includes a plurality of write register instructions.

[0149] 204. Determine a write operation instruction set according to the write register instruction set.

[0150] In the embodiment of the present invention, for the specific technical details and technical terminology of step 201-step 202, reference can be made to the detailed description of step 101-step 102 in embodiment 1, and the embodiment of the present invention will not be repeated here.

[0151] Optionally, the specific implementation method of determining the write operation instruction set according to the write register instruction set is:

[0152] For any write register instruction, determine whether the instruction type corresponding to the write register instruction meets the write operation condition, and obtain a type determination result;

[0153] When the above type determination result indicates that the instruction type corresponding to the write register instruction satisfies the write operation condition, the write operation instruction corresponding to the write register instruction is determined.

[0154] Optionally, the above instruction type includes a write type and / or a blank type, which is not limited in the embodiment of the present invention.

[0155] Optionally, the above-mentioned write operation condition is that the instruction type corresponding to the write register instruction is a write type.

[0156] Optionally, the above instruction type is determined based on mask writing information.

[0157] It can be seen that the register-based data processing method described in the embodiment of the present invention can use write rules to process write task requests to obtain target write information, and then determine the write register instruction in combination with the selectable write instruction set, and finally determine the write operation instruction set, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and then improving the system concurrency and parallel computing capabilities, and improving system performance.

[0158] In an optional embodiment, the target write information set includes a plurality of target bit slot information and target write value information;

[0159] The above-mentioned set of write instructions to be selected includes update instructions and / or vacancy instructions;

[0160] In the above step 203, the write register instruction set is determined according to the target write information set and the preset write instruction set to be selected, including:

[0161] For any target bit slot information, determine whether the target bit slot information meets the register update condition to obtain a second determination result;

[0162] When the second judgment result indicates that the target bit slot information satisfies the register update condition, determining that the write register instruction corresponding to the target bit slot information is an update instruction; the update instruction is used to instruct to write the target write value information corresponding to the target bit slot information into the corresponding register;

[0163] When the second judgment result indicates that the target slot information does not meet the register update condition, it is determined that the write register instruction corresponding to the target slot information is a vacant instruction.

[0164] Optionally, the above update instruction is used to instruct writing target code information into a register.

[0165] Optionally, the above-mentioned vacancy instruction is used to instruct to perform vacancy processing on the code bit slot information.

[0166] Optionally, the above register update condition is related to the instruction type.

[0167] Optionally, the write register instructions in the above write register instruction set may be executed in parallel or in order according to a preset processing rule, which is not limited in the embodiment of the present invention.

[0168] It can be seen that the register-based data processing method described in the embodiment of the present invention can comprehensively determine the write register instruction corresponding to the target write information through the judgment of the target mask information and the register update condition, which is more conducive to realizing the lock-free concurrent processing of registers, releasing the CPU computing power, and then improving the system concurrency and parallel computing capabilities, thereby improving the system performance.

[0169] Embodiment 3

[0170] See also Figure 3 , Figure 3 is a schematic diagram of a structure of a register-based data processing device disclosed in an embodiment of the present invention. Figure 3The described device can be applied to a data processing system, such as a local server or a cloud server for register-based data processing management, etc., which is not limited in the embodiments of the present invention. Figure 3 As shown, the device may include:

[0171] An acquisition module 301 is used to acquire a write task request;

[0172] A first determination module 302 is used to determine a target write information set according to a write task request and a preset write rule;

[0173] The second determination module 303 is used to determine a write instruction set according to the target write information set; the write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in the register.

[0174] It can be seen that implementation Figure 3 The described register-based data processing device can use write rules to process write task requests to obtain target write information, and then determine to obtain a write instruction set for instructing to perform a write operation on the data information corresponding to the write task request in the register, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and improving system performance.

[0175] In another optional embodiment, Figure 4 As shown, the write task request includes a set of task information to be written;

[0176] The first determination module 302 includes an acquisition submodule 3021, a first determination submodule 3022, and a second determination submodule 3023, wherein:

[0177] The acquisition submodule 3021 is used to acquire the operation bit number information corresponding to the register; the operation bit number information includes L bit slots; L is an even positive integer greater than or equal to 2;

[0178] The first determination submodule 3022 is used to determine the target task information set according to the task information set to be written and the operation bit information;

[0179] The second determination submodule 3023 is used to determine a target write information set according to the target task information set and a preset slot screening rule; the target write information set includes a target slot information set and a target write value information set corresponding to the target slot information set.

[0180] It can be seen that implementation Figure 4The register-based data processing device described can comprehensively process the task information to be written and the operation bit number information to obtain the target task information, and then use the bit slot screening rules to process the target task information to obtain the target bit slot information and the target write value information, which is conducive to realizing the lock-free concurrent processing of registers, releasing the CPU computing power, and then improving the system concurrency and parallel computing capabilities, and improving the system performance.

[0181] In yet another optional embodiment, Figure 4 As shown, the set of task information to be written includes N pieces of task information to be written;

[0182] The first determination submodule 3022 determines the target task information set according to the task information set to be written and the operation bit information in the following specific manner:

[0183] Determine whether N is greater than L, and obtain a first determination result;

[0184] When the first judgment result indicates that N is greater than L, a target task information set is determined according to a preset task screening rule and a task information set to be written;

[0185] When the first judgment result indicates that N is not greater than L, the task information set to be written is determined to be the target task information set.

[0186] It can be seen that implementation Figure 4 The register-based data processing device described can determine the target task information by judging the task information to be written and the number of bit slots, and combining the task screening rules to comprehensively determine the target task information, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and improving system performance.

[0187] In yet another optional embodiment, Figure 4 As shown, the target task information set includes target task quantity information and a to-be-written value information set;

[0188] The second determination submodule 3023 determines the target writing information set according to the target task information set and the preset bit slot screening rule in the following specific manner:

[0189] According to the target task quantity information and the operation bit number information, a target bit slot information set is determined; the target bit slot information set includes M target bit slot information; M is less than or equal to one half of L;

[0190] According to the target bit slot information set and the to-be-written value information set, a target write value information set is determined; the target write value information set includes M target write value information.

[0191] It can be seen that implementation Figure 4The described register-based data processing device can obtain the target bit slot information by comprehensive processing of the target task quantity information and the operation bit number information, and then comprehensively determine the target write value information in combination with the information of the value to be written, which is more conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and improving system performance.

[0192] In yet another optional embodiment, Figure 4 As shown, the set of value information to be written includes M value information to be written; the information to be written includes code writing information and mask writing information;

[0193] The target bit slot information includes code bit slot information and mask bit slot information;

[0194] The target write value information includes target code information and target mask information;

[0195] The second determination submodule 3023 determines the target write value information set according to the target bit slot information set and the to-be-written value information set in the following specific manner:

[0196] For any target bit slot information, select the to-be-written value information matching the target bit slot information from the to-be-written value information set as the target write value information corresponding to the target bit slot information;

[0197] Determine the target code information corresponding to the target bit slot information according to the code writing information corresponding to the target write value information and the code bit slot information corresponding to the target bit slot information;

[0198] The target mask information corresponding to the target bit slot information is determined according to the mask write information corresponding to the target write value information and the mask bit slot information corresponding to the target bit slot information.

[0199] It can be seen that implementation Figure 4 The described register-based data processing device can filter out the target write value information corresponding to the target bit slot information from the set of value information to be written, and then determine the target code information and target mask information corresponding to the target bit slot information, which is more conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thus improving the system's concurrency and parallel computing capabilities, and improving system performance.

[0200] In yet another optional embodiment, Figure 4 As shown, the second determination module 303 determines the specific manner of the write instruction set according to the target write information set as follows:

[0201] Determine a write register instruction set according to the target write information set and the preset write instruction set to be selected; the write register instruction set includes a plurality of write register instructions;

[0202] According to the write register instruction set, a write operation set is determined.

[0203] It can be seen that implementation Figure 4 The register-based data processing device described can use write rules to process write task requests to obtain target write information, and then determine the write register instruction in combination with the selectable write instruction set, and finally determine the write operation instruction set, which is conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system concurrency and parallel computing capabilities and improving system performance.

[0204] In yet another optional embodiment, Figure 4 As shown, the target write information set includes a number of target bit slot information and target write value information;

[0205] The set of write instructions to be selected includes update instructions and / or vacancy instructions;

[0206] The second determination module 303 determines the specific manner of the write register instruction set according to the target write information set and the preset write instruction set to be selected as follows:

[0207] For any target bit slot information, determine whether the target bit slot information meets the register update condition to obtain a second determination result;

[0208] When the second judgment result indicates that the target bit slot information satisfies the register update condition, determining that the write register instruction corresponding to the target bit slot information is an update instruction; the update instruction is used to instruct to write the target write value information corresponding to the target bit slot information into the corresponding register;

[0209] When the second judgment result indicates that the target slot information does not satisfy the register update condition, it is determined that the write register instruction corresponding to the target slot information is a vacant instruction.

[0210] It can be seen that implementation Figure 4 The described register-based data processing device can comprehensively determine the write register instruction corresponding to the target write information by judging the target mask information and the register update condition, which is more conducive to realizing lock-free concurrent processing of registers, releasing CPU computing power, and thereby improving the system's concurrency and parallel computing capabilities and improving system performance.

[0211] Embodiment 4

[0212] See also Figure 5 , Figure 5 is a schematic diagram of the structure of another register-based data processing device disclosed in an embodiment of the present invention. Figure 5The described device can be applied to a data processing system, such as a local server or a cloud server for register-based data processing management, etc., which is not limited in the embodiments of the present invention. Figure 5 As shown, the device may include:

[0213] A memory 401 storing executable program codes;

[0214] a processor 402 coupled to the memory 401;

[0215] The processor 402 calls the executable program code stored in the memory 401 to execute the steps in the register-based data processing method described in the first or second embodiment.

[0216] Embodiment 5

[0217] An embodiment of the present invention discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the steps of the register-based data processing method described in the first or second embodiment.

[0218] Embodiment 6

[0219] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute the steps in the register-based data processing method described in Embodiment 1 or Embodiment 2.

[0220] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, i.e., they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0221] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or partly contributed to the prior art in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0222] Finally, it should be noted that the register-based data processing method and device disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A register-based data processing method, characterized in that: The method comprises: Obtaining a write task request, wherein the write task request includes a set of task information to be written; Determining a target write information set according to the write task request and a preset write rule; Determining a write instruction set according to the target write information set; the write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in the register; Wherein, determining a target write information set according to the write task request and a preset write rule includes: Obtaining the number of operation bits corresponding to the register; the number of operation bits information includes L bit slots; L is an even positive integer greater than or equal to 2; Determine a target task information set according to the to-be-written task information set and the operation bit number information; the target task information set includes target task quantity information and to-be-written value information set; According to the target task information set and the preset slot screening rule, a target write information set is determined; the target write information set includes a target slot information set and a target write value information set corresponding to the target slot information set; Wherein, determining the target writing information set according to the target task information set and the preset bit slot screening rule includes: Determine a target slot information set according to the target task quantity information and the operation bit number information; the target slot information set includes M target slot information; M is less than or equal to half of L; The target write value information set is determined according to the target slot information set and the to-be-written value information set; the target write value information set includes the M target write value information.

2. The register-based data processing method according to claim 1, characterized in that: The set of task information to be written includes N pieces of task information to be written; Determining a target task information set according to the to-be-written task information set and the operation bit number information includes: Determine whether the N is greater than the L, and obtain a first determination result; When the first judgment result indicates that N is greater than L, determining a target task information set according to a preset task screening rule and the task information set to be written; When the first judgment result indicates that N is not greater than L, the to-be-written task information set is determined to be a target task information set.

3. The register-based data processing method according to claim 1, characterized in that: The set of value information to be written includes the M value information to be written; the value information to be written includes code writing information and mask writing information; The target bit slot information includes code bit slot information and mask bit slot information; The target write value information includes target code information and target mask information; The step of determining the target write value information set according to the target bit slot information set and the to-be-written value information set includes: For any target bit slot information, filter out the to-be-written value information that matches the target bit slot information from the to-be-written value information set as the target write value information corresponding to the target bit slot information; Determine the target code information corresponding to the target bit slot information according to the code writing information corresponding to the target write value information and the code bit slot information corresponding to the target bit slot information; The target mask information corresponding to the target bit slot information is determined according to the mask write information corresponding to the target write value information and the mask bit slot information corresponding to the target bit slot information.

4. The register-based data processing method according to claim 1, characterized in that: The step of determining a write instruction set according to the target write information set includes: Determine a write register instruction set according to the target write information set and a preset write instruction set to be selected; the write register instruction set includes a plurality of write register instructions; A write operation instruction set is determined according to the write register instruction set.

5. The register-based data processing method according to claim 4, characterized in that: The target write information set includes a plurality of target bit slot information and target write value information; The set of write instructions to be selected includes update instructions and / or vacancy instructions; The step of determining a write register instruction set according to the target write information set and a preset write instruction set to be selected includes: For any of the target bit slot information, determine whether the target bit slot information meets the register update condition to obtain a second determination result; When the second judgment result indicates that the target bit slot information satisfies the register update condition, determining that the write register instruction corresponding to the target bit slot information is an update instruction; the update instruction is used to instruct to write the target write value information corresponding to the target bit slot information into the corresponding register; When the second judgment result indicates that the target slot information does not satisfy the register update condition, it is determined that the write register instruction corresponding to the target slot information is a vacant instruction.

6. A register-based data processing device, characterized in that: The device comprises: An acquisition module, used for acquiring a write task request; the write task request includes a set of task information to be written; A first determination module, configured to determine a target write information set according to the write task request and a preset write rule; A second determination module is used to determine a write instruction set according to the target write information set; the write instruction set is used to instruct to perform a write operation on the data information corresponding to the write task request in the register; The first determination module includes an acquisition submodule, a first determination submodule and a second determination submodule, wherein: The acquisition submodule is used to acquire the operation bit number information corresponding to the register; the operation bit number information includes L bit slots; L is an even positive integer greater than or equal to 2; The first determination submodule is used to determine a target task information set according to the to-be-written task information set and the operation bit number information; the target task information set includes target task quantity information and a to-be-written value information set; The second determination submodule is used to determine a target write information set according to the target task information set and a preset bit slot screening rule; the target write information set includes a target bit slot information set and a target write value information set corresponding to the target bit slot information set; The specific manner in which the second determination submodule determines the target write information set according to the target task information set and the preset bit slot screening rule is: Determine a target slot information set according to the target task quantity information and the operation bit number information; the target slot information set includes M target slot information; M is less than or equal to half of L; The target write value information set is determined according to the target slot information set and the to-be-written value information set; the target write value information set includes the M target write value information.

7. A register-based data processing device, characterized in that: The device comprises: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the register-based data processing method according to any one of claims 1 to 5.

8. A computer storable medium, characterized in that: The computer storable medium stores computer instructions, and when the computer instructions are called, they are used to execute the register-based data processing method according to any one of claims 1 to 5.

Images