An optimization system for the SHA-1 algorithm and an optimization server for the SHA-1 algorithm

Abstract

The present invention discloses an optimization system for the SHA-1 algorithm, comprising: an input / output interface; a selection control unit, which is connected to the input / output interface and configured to receive the information sent by the input / output interface and generate an algorithm instruction based on the information; an arithmetic unit, which is connected to the selection control unit and configured to receive the algorithm instruction of the selection control unit and perform an operation based on the SHA-1 algorithm, and return the operation result to the selection control unit; wherein, the selection control unit is configured to obtain the clock frequency through the input / output interface, select the algorithm merging rounds based on the clock frequency to generate the corresponding algorithm instruction, and send the operation result returned by the arithmetic unit to the input / output interface. The present invention also discloses an optimization server for the SHA-1 algorithm. The present invention has the characteristics of high compatibility, high efficiency, and convenience for algorithm upgrade, etc.

Description

Technical Field

[0001] The present invention relates to the field of cryptographic security technology, and particularly to an optimization system for the SHA-1 algorithm and an optimization server for the SHA-1 algorithm. Background Art

[0002] After the 21st century, information communication has become global network communication. With the development of the Internet, cryptographic algorithms have become increasingly important and are the security guarantee for trillions of communication devices.

[0003] A Hash function is a function used to detect whether the transmitted information has been tampered with, prevent forged electronic signatures, and information authentication codes. SHA (Secure Hash Algorithm) is the most widely used Hash function, designed by the National Institute of Standards and Technology (NIST) of the United States and published as a Federal Information Processing Standard.

[0004] The SHA-1 algorithm is a kind of SHA series algorithms and can generate information with a length of 160 bits. As the amount of data that needs to be processed for information security continues to increase, the requirement for the operation speed of the SHA-1 algorithm is getting higher and higher. The operation efficiency of traditional implementation schemes is not high. Therefore, one of the important goals is to improve the algorithm operation rate and throughput while maintaining stable performance. Summary of the Invention

[0005] In view of this, the purpose of the embodiments of the present invention is to provide an optimization system for the SHA-1 algorithm and an optimization server for the SHA-1 algorithm. The data to be operated is written into the storage RAM through the AHB interface, and then the control information is written into the control unit. The control unit starts the SHA-1 operation system according to the information written by the user, and has the characteristics of high compatibility, high efficiency, and easy algorithm upgrade.

[0006] Based on the above purpose, on the one hand, an embodiment of the present invention provides an optimization system for the SHA-1 algorithm, including: an input / output interface; a selection control unit, connected to the input / output interface, configured to receive the information sent by the input / output interface and generate an algorithm instruction based on the information; an operation unit, connected to the selection control unit, configured to receive the algorithm instruction of the selection control unit and perform an operation based on the SHA-1 algorithm, and return the operation result to the selection control unit; wherein, the selection control unit is configured to obtain the clock frequency through the input / output interface, select the algorithm merge rounds based on the clock frequency to generate the corresponding algorithm instruction, and send the operation result returned by the operation unit to the input / output interface.

[0007] In some embodiments, the selection control unit is further configured to: determine the clock frequency range of the clock frequency; if the clock frequency is less than a first threshold, combine every 8 rounds of the SHA-1 algorithm into one calculation period for calculation and generate low-frequency algorithm instructions; if the clock frequency is not less than the first threshold and less than a second threshold, combine every 4 rounds of the SHA-1 algorithm into one calculation period for calculation and generate medium-frequency algorithm instructions; if the clock frequency is not less than the second threshold and less than a third threshold, combine every 2 rounds of the SHA-1 algorithm into one calculation period for calculation and generate medium-frequency algorithm instructions; if the clock frequency is not less than the third threshold, no round combination operation is performed on the SHA-1 algorithm and high-frequency algorithm instructions are generated.

[0008] In some embodiments, the selection control unit includes: a control unit, which is respectively connected to the input / output interface and the arithmetic unit; a selection unit, which is respectively connected to the control unit and the arithmetic unit.

[0009] In some embodiments, the control unit is further configured to: obtain a user instruction through the input / output interface and send control commands to the selection unit and the arithmetic unit based on the user instruction.

[0010] In some embodiments, the selection unit is further configured to: receive the control command of the control unit and select the algorithm combination rounds based on the clock frequency; send the algorithm instructions based on the selected algorithm combination rounds to the arithmetic unit.

[0011] In some embodiments, the selection control unit further includes: a storage unit, which is respectively connected to the input / output interface, the selection unit and the arithmetic unit, and is configured to receive, store and transmit the data information transmitted by the input / output interface, the selection unit and the arithmetic unit.

[0012] In some embodiments, the storage unit is configured to store RAM.

[0013] In some embodiments, the arithmetic unit includes: a preprocessing module, which is configured to preprocess the data to be calculated to generate arithmetic data; a calculation module, which is configured to perform arithmetic operations on the arithmetic data based on the SHA-1 algorithm according to the algorithm instructions.

[0014] In some embodiments, the preprocessing module is further configured to: determine whether the data to be calculated meets a preset number of bits; if the data to be calculated does not meet the preset number of bits, perform a padding operation on the end of the data to be calculated to generate arithmetic data.

[0015] On the other hand, an embodiment of the present invention further provides an optimized server for the SHA-1 algorithm, including an optimized service device for the SHA-1 algorithm described below: an input / output interface; a selection control unit connected to the input / output interface, configured to receive information sent by the input / output interface and generate an algorithm instruction based on the information; an operation unit connected to the selection control unit, configured to receive the algorithm instruction of the selection control unit and perform an operation based on the SHA-1 algorithm, and return the operation result to the selection control unit; wherein, the selection control unit is configured to obtain a clock frequency through the input / output interface, select an algorithm merging round number based on the clock frequency to generate a corresponding algorithm instruction, and send the operation result returned by the operation unit to the input / output interface.

[0016] In some embodiments, the selection control unit is further configured to: determine the clock frequency range of the clock frequency; if the clock frequency is less than a first threshold, merge every 8 rounds of the SHA-1 algorithm into a calculation period for calculation and generate a low-frequency algorithm instruction; if the clock frequency is not less than the first threshold and less than a second threshold, merge every 4 rounds of the SHA-1 algorithm into a calculation period for calculation and generate a medium-frequency algorithm instruction; if the clock frequency is not less than the second threshold and less than a third threshold, merge every 2 rounds of the SHA-1 algorithm into a calculation period for calculation and generate a medium-frequency algorithm instruction; if the clock frequency is not less than the third threshold, do not perform a round merging operation on the SHA-1 algorithm and generate a high-frequency algorithm instruction.

[0017] In some embodiments, the selection control unit includes: a control unit respectively connected to the input / output interface and the operation unit; a selection unit respectively connected to the control unit and the operation unit.

[0018] In some embodiments, the control unit is further configured to: obtain a user instruction through the input / output interface and send a control command to the selection unit and the operation unit based on the user instruction.

[0019] In some embodiments, the selection unit is further configured to: receive the control command of the control unit and select an algorithm merging round number based on the clock frequency; send the algorithm instruction based on the selected algorithm merging round number to the operation unit.

[0020] In some embodiments, the selection control unit further includes: a storage unit, which is respectively connected to the input / output interface, the selection unit, and the arithmetic unit, and is configured to receive, store, and transfer the data information transmitted by the input / output interface, the selection unit, and the arithmetic unit.

[0021] In some embodiments, the storage unit is configured to store RAM.

[0022] In some embodiments, the arithmetic unit includes: a preprocessing module configured to preprocess the data to be calculated to generate arithmetic data; a calculation module configured to perform arithmetic operations on the arithmetic data based on the SHA-1 algorithm according to the algorithm instruction.

[0023] In some embodiments, the preprocessing module is further configured to: determine whether the data to be calculated meets a preset number of bits; if the data to be calculated does not meet the preset number of bits, perform a padding operation on the end of the data to be calculated to generate arithmetic data.

[0024] The present invention has the following beneficial technical effects: Compared with traditional software solutions, the operation rate of the SHA-1 algorithm can be flexibly increased according to the system working frequency. An optimized selection design for the SHA-1 algorithm is added. This unit can flexibly select the parallel level of the round calculation of the SHA-1 algorithm according to the system clock frequency, and can combine multiple rounds of operations into the same clock cycle, so that the entire design is flexible, controllable, and operates efficiently. The external uses a dedicated AHB interface, which can support the integration of most systems and has a wide range of applications. And when upgrading to the SHA-256 and SHA-512 algorithms in the later stage, since the algorithm unit and the control unit of this design are completely independent, the control unit can change the configuration by configuring parameters, and only need to fine-tune the algorithm unit when upgrading the algorithm in the later stage. The upgrade is easy, efficient, and will not have too much impact on the stability of the module. The SHA-1 optimization module can automatically and flexibly select a suitable SHA-1 parallel calculation scheme according to the working clock frequency, improving the operation efficiency and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0026] Figure 1 It is a schematic diagram of an embodiment of the optimized system of the SHA-1 algorithm provided by the present invention;

[0027] Figure 2 Schematic diagram of an embodiment of the optimization system for the SHA-1 algorithm provided by the present invention;

[0028] Figure 3 Flow chart of a single-round operation iteration of the SHA-1 algorithm;

[0029] Figure 4 Schematic diagram of an embodiment of the optimization server for the SHA-1 algorithm provided by the present invention. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further describes the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0031] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0032] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of the optimization system for the SHA-1 algorithm is proposed. Figure 1 Shown is a schematic diagram of an embodiment of the optimization system for the SHA-1 algorithm provided by the present invention. As Figure 1 shown, the embodiments of the present invention include:

[0033] Input / output interface 001;

[0034] Selection control unit 002, which is connected to the input / output interface 001 and is configured to receive the information sent by the input / output interface 001 and generate an algorithm instruction based on the information;

[0035] Operation unit 003, which is connected to the selection control unit 002 and is configured to receive the algorithm instruction of the selection control unit and perform an operation based on the SHA-1 algorithm, and return the operation result to the selection control unit 002;

[0036] Among them, the selection control unit 002 is configured to obtain the clock frequency through the input / output interface 001, select the algorithm merge rounds based on the clock frequency to generate the corresponding algorithm instruction, and send the operation result returned by the operation unit 003 to the input / output interface 001.

[0037] In some embodiments of the present invention, the selection control unit is further configured to: determine the clock frequency range of the clock frequency; if the clock frequency is less than the first threshold, merge every 8 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate low-frequency algorithm instructions; if the clock frequency is not less than the first threshold and less than the second threshold, merge every 4 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate medium-frequency algorithm instructions; if the clock frequency is not less than the second threshold and less than the third threshold, merge every 2 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate medium-frequency algorithm instructions; if the clock frequency is not less than the third threshold, do not perform the operation of merging the number of rounds of the SHA-1 algorithm, and generate high-frequency algorithm instructions.

[0038] In some embodiments of the present invention, the selection control unit includes: a control unit, the control unit is respectively connected to the input / output interface and the arithmetic unit; a selection unit, the selection unit is respectively connected to the control unit and the arithmetic unit.

[0039] In some embodiments of the present invention, the control unit is further configured to: obtain a user instruction through the input / output interface, and send control commands to the selection unit and the arithmetic unit based on the user instruction.

[0040] In some embodiments of the present invention, the selection unit is further configured to: receive the control command of the control unit, and select the number of merged rounds of the algorithm based on the clock frequency; send the algorithm instructions based on the selected number of merged rounds of the algorithm to the arithmetic unit.

[0041] In some embodiments of the present invention, the selection control unit further includes: a storage unit, the storage unit is respectively connected to the input / output interface, the selection unit and the arithmetic unit, and is configured to receive, store and transmit the data information transmitted by the input / output interface, the selection unit and the arithmetic unit.

[0042] In some embodiments of the present invention, the storage unit is configured to store RAM.

[0043] In some embodiments of the present invention, the arithmetic unit includes: a preprocessing module, configured to preprocess the data to be calculated to generate operation data; a calculation module, configured to perform operations on the operation data based on the SHA-1 algorithm according to the algorithm instructions.

[0044] In some embodiments of the present invention, the preprocessing module is further configured to: determine whether the data to be calculated meets the preset number of bits; if the data to be calculated does not meet the preset number of bits, perform a padding operation on the end of the data to be calculated to generate operation data.

[0045] The following further elaborates on the specific implementation manners of the present invention according to specific embodiments. Figure 2Shown is a schematic diagram of an embodiment of an optimized system for the SHA-1 algorithm, as Figure 2 shown, including:

[0046] Input / output interface 001, which uses the AHB interface protocol through the AHB control unit for effective data transmission, can support a relatively high clock cycle, and has a fast transmission rate.

[0047] Storage unit 123, which stores the information to be calculated transmitted from the AHB interface, and stores the output result of the SHA-1 operation unit.

[0048] Control unit 121, which obtains the user's control information from the AHB interface and controls the operation of the entire SHA-1 operation system.

[0049] Selection unit 122, which can select the appropriate number of combined calculation rounds of the SHA-1 algorithm according to the operating frequency of the chip, so as to achieve the purpose of improving the calculation speed.

[0050] Preprocessing module 131, when using the SHA-1 algorithm to process the message, preprocesses the data. SHA-1 needs to group the input data according to 512 bits, and perform padding operations on the end data that does not meet 512 bits. Designing the preprocessing operation as an independent module to process the message in advance saves the waiting time during SHA-1 operation and improves the operation efficiency.

[0051] Calculation module 132, which performs the preprocessing operation of the SHA-1 algorithm and the key 80-round iterative compression operation.

[0052] In this embodiment, the core operation of the SHA-1 algorithm is to divide each 512-bit message data into 16 sub-data blocks M0 to M15, and generate 80 new data blocks W0 to W79 according to the sub-data blocks M0 to M15. Then, these data are processed. The main loop has 4 rounds, each round of the main loop uses a K sequence, a total of four sequences K1 to K4, and performs 20 rounds of operations. The output of each round of operation is used as the input of the next operation. Figure 3 Shown is the iterative flowchart of a single-round operation of the SHA-1 algorithm, as Figure 3 shown:

[0053] 1. The 32-bit data A is directly used as the new data B

[0054] 2. The 32-bit data B is circularly shifted right by 2 bits to generate the new data C

[0055] 3. The 32-bit data C is directly used as the new data D

[0056] 4. The 32-bit data D is directly used as the new data E

[0057] The 5.32-bit data E is added to the sequence block Wi and the sequence Ki selected according to the number of rounds, and then added to the data obtained after the F operation on B, C, and D. The new data A is obtained.

[0058] Similar operations are repeated. After a total of 80 rounds of operations, the final output result of 160 bits is obtained.

[0059] To improve the operation efficiency, through the selection unit, when the clock is at a low frequency, the SHA-1 algorithm selects an operation method that combines every 5 rounds of calculation operations into one operation cycle. It is equivalent to that the calculation time of the original one round can calculate 5 rounds of data. In this way, 80 rounds of operations are simplified to 16 rounds, improving the operation efficiency of the system. When the clock is at a high frequency, in order to maintain the stability of the algorithm, the system also selects a method of not combining or only combining 2 rounds of data, so as to ensure that the corresponding operations can be completed within one clock cycle. This design scheme can flexibly target high-frequency and low-frequency clock scenarios, provide different optimization schemes, flexibly configure operation resources, and improve the operation efficiency and the overall performance of the system while ensuring the correctness of the operation.

[0060] Based on the above purpose, in the second aspect of the embodiments of the present invention, an optimized server for the SHA-1 algorithm is proposed. Figure 4 The following shows a schematic diagram of an embodiment of the optimized server for the SHA-1 algorithm provided by the present invention. As Figure 4 shown, the optimized server 011 for the SHA-1 algorithm includes the following optimized system 012 for the SHA-1 algorithm: an input / output interface; a selection control unit, the selection control unit is connected to the input / output interface and is configured to receive the information sent by the input / output interface and generate an algorithm instruction based on the information; an operation unit, the operation unit is connected to the selection control unit and is configured to receive the algorithm instruction of the selection control unit and perform operations based on the SHA-1 algorithm, and return the operation result to the selection control unit; wherein, the selection control unit is configured to obtain the clock frequency through the input / output interface, select the algorithm merge rounds based on the clock frequency to generate the corresponding algorithm instruction, and send the operation result returned by the operation unit to the input / output interface.

[0061] In some embodiments of the present invention, the selection control unit is further configured to: determine the clock frequency range of the clock frequency; if the clock frequency is less than the first threshold, combine every 8 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate low-frequency algorithm instructions; if the clock frequency is not less than the first threshold and less than the second threshold, combine every 4 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate medium-frequency algorithm instructions; if the clock frequency is not less than the second threshold and less than the third threshold, combine every 2 rounds of the SHA-1 algorithm into one calculation cycle for calculation, and generate medium-frequency algorithm instructions; if the clock frequency is not less than the third threshold, do not perform the operation of combining the number of rounds of the SHA-1 algorithm, and generate high-frequency algorithm instructions. In some embodiments of the present invention, the selection control unit includes: a control unit, which is respectively connected to the input / output interface and the arithmetic unit; a selection unit, which is respectively connected to the control unit and the arithmetic unit.

[0062] In some embodiments of the present invention, the control unit is further configured to: obtain a user instruction through the input / output interface, and send control commands to the selection unit and the arithmetic unit based on the user instruction.

[0063] In some embodiments of the present invention, the selection unit is further configured to: receive the control command of the control unit, and select the number of combined rounds of the algorithm based on the clock frequency; send the algorithm instruction based on the selected number of combined rounds of the algorithm to the arithmetic unit.

[0064] In some embodiments of the present invention, the selection control unit further includes: a storage unit, which is respectively connected to the input / output interface, the selection unit and the arithmetic unit, and is configured to receive, store and transmit the data information transmitted by the input / output interface, the selection unit and the arithmetic unit.

[0065] In some embodiments of the present invention, the storage unit is configured to store RAM.

[0066] In some embodiments of the present invention, the arithmetic unit includes: a preprocessing module, which is configured to preprocess the data to be calculated to generate operation data; a calculation module, which is configured to perform operations on the operation data based on the SHA-1 algorithm according to the algorithm instruction.

[0067] In some embodiments of the present invention, the preprocessing module is further configured to: determine whether the data to be calculated meets the preset number of bits; if the data to be calculated does not meet the preset number of bits, perform a padding operation on the end of the data to be calculated to generate operation data.

[0068] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any specific order. In addition, although the elements disclosed in the embodiments of the present invention may be described or claimed in individual form, they may also be construed as plural unless explicitly limited to the singular form.

[0069] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the related listed items.

[0070] The serial numbers of the above-disclosed embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments.

[0071] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0072] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. An optimized system for the SHA-1 algorithm, characterized in that, it includes: Input and output interfaces; A selection control unit, which is connected to the input and output interfaces, and is configured to receive the information sent by the input and output interfaces and generate algorithm instructions based on the information; An arithmetic unit, which is connected to the selection control unit, and is configured to receive the algorithm instructions of the selection control unit and perform arithmetic operations based on the SHA-1 algorithm, and return the operation results to the selection control unit; Among them, the selection control unit is configured to obtain the clock frequency through the input and output interfaces, select the algorithm merging rounds based on the clock frequency to generate corresponding algorithm instructions, and send the operation results returned by the arithmetic unit to the input and output interfaces; The selection control unit is further configured to: Judge the clock frequency range of the clock frequency; If the clock frequency is less than the first threshold, merge every 8 rounds of the SHA-1 algorithm into a calculation cycle for calculation, and generate low-frequency algorithm instructions; If the clock frequency is not less than the first threshold and less than the second threshold, merge every 4 rounds of the SHA-1 algorithm into a calculation cycle for calculation, and generate medium-frequency algorithm instructions; If the clock frequency is not less than the second threshold and less than the third threshold, merge every 2 rounds of the SHA-1 algorithm into a calculation cycle for calculation, and generate medium-frequency algorithm instructions; If the clock frequency is not less than the third threshold, no round merging operation is performed on the SHA-1 algorithm, and high-frequency algorithm instructions are generated.

2. The optimized system for the SHA-1 algorithm according to claim 1, characterized in that, The selection control unit includes: A control unit, which is respectively connected to the input and output interfaces and the arithmetic unit; A selection unit, which is respectively connected to the control unit and the arithmetic unit.

3. The optimized system for the SHA-1 algorithm according to claim 2, characterized in that, The control unit is further configured to: Obtain user instructions through the input and output interfaces, and send control commands to the selection unit and the arithmetic unit based on the user instructions.

4. The optimized system for the SHA-1 algorithm according to claim 3, characterized in that, The selection unit is further configured to: Receive the control commands of the control unit, and select the algorithm merging rounds based on the clock frequency; Send the algorithm instructions based on the selected algorithm merging rounds to the arithmetic unit.

5. The optimized system for the SHA-1 algorithm according to claim 2, characterized in that, The selection control unit further includes: A storage unit, which is respectively connected to the input and output interfaces, the selection unit and the arithmetic unit, and is configured to receive, store and transfer the data information transmitted by the input and output interfaces, the selection unit and the arithmetic unit.

6. The optimized system for the SHA-1 algorithm according to claim 5, characterized in that, The storage unit is configured to store RAM.

7. The optimized system for SHA-1 algorithm according to claim 1, wherein, the operation unit includes: a preprocessing module configured to preprocess the data to be calculated to generate operation data; a calculation module configured to perform operations on the operation data based on the SHA-1 algorithm according to the algorithm instruction.

8. The optimized system for SHA-1 algorithm according to claim 7, wherein, the preprocessing module is further configured to: judge whether the data to be calculated meets a preset bit number; if the data to be calculated does not meet the preset bit number, perform a padding operation on the end of the data to be calculated to generate operation data.

9. An optimized server for SHA-1 algorithm, wherein, it includes the optimized system for SHA-1 algorithm according to any one of claims 1-8.

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