Chip, chip optimization method and electronic device

Abstract

The present invention discloses a chip, a chip optimization method and an electronic device, wherein the chip comprises: an instantiation module, a common logic module and a bypass module; wherein: the instantiation module is configured to realize a preset processing function, and the instantiation module comprises a plurality of identical instantiation units; the common logic module is configured to control the instantiation module and to be shared by the instantiation units; the bypass module is configured to close the abnormal instantiation units in the instantiation module. The present invention can improve the availability of the chip under the same process yield.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip, a chip optimization method and an electronic device. Background Art

[0002] For some special multi-logic, large-memory chips, in order to improve data bandwidth and application-level performance, most of them will choose to repeatedly instantiate a large number of algorithm cores or storage units on the chip. For example, high-bandwidth multi-core computing chips with algorithm multi-array stacking and storage multi-array stacking. These types of chips tend to have a large area, and from the perspective of chip yield, the larger the chip area, the greater the probability of process manufacturing defects in each chip. Process defects can cause related circuits to fail, thereby causing the entire chip to fail or reduce chip performance, which also reduces the availability of the chip.

[0003] Therefore, current process defects easily lead to the problem of low availability of dedicated multi-logic and large memory chips. Summary of the invention

[0004] In view of the above problems, the present invention proposes a chip, a chip optimization method and an electronic device, which improve the availability of the chip under the same process yield.

[0005] In the first aspect, the present application provides the following technical solution through an embodiment:

[0006] A chip, comprising: an instantiation module, a common logic module and a bypass module; wherein:

[0007] The instantiation module is configured to implement a preset processing function, and the instantiation module includes a plurality of identical instantiation units; the common logic module is configured to control the instantiation module and to be shared by the instantiation units; the bypass module is configured to shield abnormal instantiation units in the instantiation module.

[0008] Optionally, the number of instantiated units is not less than Y, where Y=M+R*A*L, where R is the number of defects per unit area during the process manufacturing process, A is the upper limit of the chip area, and L is the upper limit of the area occupied by the instantiated module in the chip; M is the minimum number of instantiated units required to achieve preset performance requirements.

[0009] Optionally, the bypass module includes: a shielding submodule, the shielding submodule is arranged in the common logic module;

[0010] The shielding submodule is configured to store the identification number of the abnormal instantiation unit, so that the abnormal instantiation unit corresponding to the identification number is shielded.

[0011] Optionally, the bypass module includes: a shielding submodule, the shielding submodule is arranged in the common logic module, and the shielding submodule is implemented based on an enable register;

[0012] The enable register is configured to disable the exception instantiation unit so that the exception instantiation unit is shielded.

[0013] Optionally, the bypass module includes: a mapping submodule;

[0014] The mapping submodule is configured to map the access operation corresponding to the abnormal instantiation unit to the normal instantiation unit.

[0015] In the second aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0016] A chip optimization method, comprising:

[0017] Based on the realizability of functions and logics, the instantiation module and common logic module of the chip are determined; wherein, the common logic module is shared by the instantiation units in the instantiation module, and the instantiation units are used to implement preset processing functions; the bypass function of the instantiation module is configured; wherein, the bypass function is used to shield abnormal instantiation units in the instantiation module.

[0018] Optionally, the instantiation module for determining the chip includes:

[0019] Determine that the number of instantiation units in the instantiation module is not less than Y; wherein Y=M+R*A*L, R is the number of defects introduced per unit area during the process manufacturing process, A is the upper limit of the chip area, L is the upper limit of the area ratio of the instantiation module in the chip; and M is the minimum number of instantiation units required to achieve the preset performance requirements.

[0020] Optionally, configuring the bypass function of the instantiated module includes:

[0021] Record the identification number of the abnormal instantiation unit and configure it so that the abnormal instantiation unit corresponding to the identification number is shielded; or map the access operation corresponding to the abnormal instantiation unit to the normal instantiation unit.

[0022] Optionally, after determining the instantiation module and the common logic module of the chip, the method further includes: configuring a self-test function of the instantiation module; for any instantiation unit in the instantiation module, configuring the self-test function of the instantiation module includes:

[0023] The configuration includes accessing the instantiation unit and writing preset self-test data to the instantiation unit; the configuration includes reading the written self-test data in the instantiation unit to obtain verification data; and the configuration includes comparing whether the self-test data and the verification data are the same; wherein, if they are the same, the instantiation unit is determined to be a normal instantiation unit, otherwise, the instantiation unit is determined to be an abnormal instantiation unit.

[0024] In the third aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0025] An electronic device comprises a processor and a memory, wherein the memory is coupled to the processor and stores instructions, and when the instructions are executed by the processor, the electronic device executes the steps of any one of the methods described in the second aspect.

[0026] A chip provided in an embodiment of the present invention comprises: an instantiation module, a common logic module and a bypass module; wherein: the instantiation module is configured to implement a preset processing function, and the instantiation module comprises a plurality of identical instantiation units; the common logic module is configured to control the instantiation module and to be shared by the instantiation units; the bypass module is configured to shield abnormal instantiation units in the instantiation module. In the embodiment of the present invention, the logic that can be stripped and shared in each instantiation unit in the instantiation module is stripped and placed in the common logic module, thereby reducing the area of ​​the instantiation unit and increasing the number of instantiation units set; then, the abnormal instantiation unit is shielded by the bypass module, and other normal instantiation units can still provide sufficient performance, thereby improving the availability of the chip under the same process yield. That is, since the common function is stripped, the instantiation unit is designed to be smaller through functional optimization. In this way, the number of instantiation units can be increased under the same total area. Even if individual instantiation units are affected by process defects, there are still enough intact units left to be used.

[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0029] Figure 1 A schematic diagram of a chip provided by a first embodiment of the present invention is shown;

[0030] Figure 2 A schematic diagram comparing the computing units of chips A and B designed without adopting the scheme of the first embodiment and adopting the scheme of the first embodiment is shown;

[0031] Figure 3 A flow chart of a chip optimization method provided by the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0032] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] The technical solution of the present invention is particularly proposed for chips that require a large number of instantiated logic units or storage units (hereinafter collectively referred to as instantiated units). For example, the chip may be:

[0034] 1. GPU (Graphics Processing Unit): GPU is used to process large amounts of data of uniform type. Its powerful processing capability comes from its numerous repeated computing cores.

[0035] 2. Accelerator chip: Due to the limitation of memory access speed in traditional mode, many repeated processing units PE (Processing Elements) are designed inside the acceleration chip to speed up data processing.

[0036] 3. NPU (Neural Network Processing Unit) is similar to an acceleration chip. The NPU used for AI learning has a large number of repeated multiplication and addition units inside.

[0037] 4. Digital currency chip. The computing power of this type of chip is directly benefited from the large number of repeated computing units inside.

[0038] 5. High-bandwidth memory used in big data computing scenarios, such as HBM (High Bandwidth Memory) and 3DIC (three-dimensional integrated circuit), has a large number of duplicate memory control units (memory controllers) on the control side to meet the high bandwidth requirements.

[0039] The computing cores, processing units PE, multiplication and addition units, computing units, and memory control units in these chips are all repeated units in large quantities, and the arrays they form occupy a large area in the entire chip; therefore, the probability of process defects is also high. The present invention utilizes this characteristic to make process defects fall on individual instantiation units with a high probability, reducing the defects originally in chip units to those in instantiation units, and finally disabling these instantiation units at the application level, effectively improving the chip availability. This is described in detail below through more than one embodiment.

[0040] First embodiment

[0041] See also Figure 1 An embodiment of the present invention provides a chip 300, including: an instantiation module 301, a common logic module 302 and a bypass module 303, wherein the instantiation module 301 and the common logic module 302 are connected, and the instantiation module 301 is also connected to the common logic module 302 through the bypass module 303.

[0042] The instantiation module 301 is configured to implement a preset processing function. Specifically, the instantiation module 301 includes a plurality of identical instantiation units, each of which can implement a corresponding function or logic. The preset processing function is determined by the type of the chip 300, which is well known to those skilled in the art and will not be described in detail in this embodiment.

[0043] The working mode implemented by each instantiated unit in the instantiated module 301 in this embodiment is similar to a large number of repeated units in the aforementioned GPU, NPU, acceleration chip and other chips. The repeated units of these chips can be replaced with the chip 300 of this embodiment, which can improve the availability of the chip.

[0044] The common logic module 302 is configured to be shared by the instantiation units in the instantiation module 301, and is configured to control the instantiation modules and process common data. One or more common logics are arranged in the common logic module 302. Under the premise of feasibility, all logics that can be shared in the instantiation units are stripped and arranged in the common logic module 302. Feasibility refers to ensuring that the functions implemented by the chip 300 do not change and the logic is reasonable. Specifically, it can be implemented as a usable netlist, and the back-end stage can be implemented as a usable physical layout. For example, taking the NPU chip as an example, under the premise of meeting the performance requirements, the register configuration logic and certain algorithm logic can be stripped from the operator (corresponding to the instantiation unit). The common point of the register configuration logic and the algorithm logic is that similar functions exist in each operator. After stripping, it is set in the common logic module 302, and the two logics can be time-shared and multiplexed to each operator.

[0045] Furthermore, the chip 300 includes two areas: an instantiation unit area, which is used to place an instantiation module 301; and a common logic area, which is used to place a common logic module 302. When the common logic of the instantiation units is set as the common logic module 302, that is, after being set in the common logic area, each instantiation unit can be made smaller during manufacturing, so that the area of ​​the instantiation unit area will be greatly reduced as a whole; and the area of ​​the common logic area is limited to increase, so that more instantiation units can be designed in the instantiation unit area.

[0046] It is inevitable to introduce process defects in the manufacture of chip 300. In order to ensure the performance requirements of chip 300, when setting the number of instantiated units, it should be ensured that it is greater than the preset basic number, which is the number of instantiated units required to meet the performance requirements of chip 300. In this way, when any instantiated unit has a defect, the instantiated unit with the defect can be turned off; and then the instantiated unit with redundant design is used to supplement it to ensure the performance and reliability of chip 300. A formula is used as an explanation, and the formula can be used as a reference for confirming the final design number of instantiated units. Specifically, the number of instantiated units is not less than Y, Y=M+R*A*L, where Y is the number of instantiated units required to be designed in the end, M is the minimum number of instantiated units required to achieve the preset performance requirements, R is the number of defects per unit area in the manufacturing process, A is the upper limit of the area of ​​chip 300, L is the upper limit of the area proportion of the instantiated module 301 in chip 300, and R*A*L is the maximum number of defects in the instantiated module 301. Given that defects have a uniform distribution characteristic, it can be considered that R*A*L instantiation units may be damaged during the manufacturing process. In this way, the acceptable number of instantiation units is determined based on the process yield of the foundry. Even if a portion of the instantiation units are affected by process defects and reach the maximum number of defects, the remaining instantiation units can still meet the functional and performance requirements of the chip 300.

[0047] For example, due to power consumption or process limitations, the area of ​​chip 300 will have an upper limit. Under this upper limit, according to the current design, a maximum of 100 instantiation units can be placed, and due to process defects, 5 instantiation units may be damaged. If the remaining 95 units can meet the performance requirements of the design, then these 100 are an acceptable number. If all 100 instantiation units must work to meet the performance requirements, then a total of only 100 is unacceptable. The design needs to be optimized to reduce the area of ​​the instantiation units to ensure that at least 105 can be placed, and a number greater than or equal to 105 is an acceptable number.

[0048] See also Figure 2 ,exist Figure 2Each small square in the diagram represents an instantiation unit, and the circle in the diagram represents a process defect. If the process defect falls in a certain square, it means that the unit cannot be used. Chip A / B has the same function and area. Under the same process yield and the same number of process defects, chip B designed using this solution and its optimization ideas is more fragmented, that is, more instantiation units with smaller areas can be designed in chip B. Faced with the same number of process defects, although the number of instantiation units lost is the same, from an overall perspective, the remaining effective performance of chip B in the future is larger (the effective intact area size of the instantiation module 301 can represent its remaining performance), thereby ensuring the function and final performance of the entire chip 300 and improving the availability of chip 300.

[0049] The bypass module 303 is configured to shield the abnormal instantiation unit in the instantiation module 301. Specifically, the bypass module 303 may include a shielding submodule. Since each instantiation unit may be abnormal, the shielding submodule may be set in the common logic module 302. The shielding submodule is configured to store the identification number of the abnormal instantiation unit and turn off the abnormal instantiation unit corresponding to the identification number. By configuring the self-test function, a self-test can be performed each time the chip 300 starts working to identify and shield the abnormal instantiation unit to ensure the normal operation of the chip 300. There is no restriction on the implementation of the self-test function, for example: For a memory control unit in an HBM chip, an access to a certain memory control unit can be initiated through the control host of the HBM, self-test data can be written to certain addresses, and then the self-test data of these addresses can be read out to obtain verification data; the self-test data and the verification data are compared. If there is no error in these data, it proves that the memory control unit is normal.

[0050] Furthermore, the shielding submodule may be implemented by an enable register; that is, the enable register is configured to turn off the abnormal instantiation unit so that the abnormal instantiation unit is shielded.

[0051] Take the operators in the NPU chip as an example:

[0052] First, the operator enable register can be designed in the common logic area. If an operator is found to be damaged during self-test, the identification number of the operator can be recorded; then, the operator enable register is configured to turn off the operator corresponding to the number. During normal calculation, the chip control unit will check the operator enable register before sending the data to be calculated to the operator. If it is turned off, no data will be sent to the operator, and the operator will not perform related calculations.

[0053] In addition, the bypass module 303 also has the following implementation mode: the bypass module 303 includes: a mapping submodule; the mapping submodule is configured to map the access operation corresponding to the abnormal instantiation unit to the normal instantiation unit.

[0054] Take the memory control unit in HBM as an example:

[0055] First, a mapping submodule for address mapping can be designed; when a memory control unit is found to be damaged during self-test, the address of the damaged content control unit is recorded. Then, the address is written into the address mapping module and the mapping submodule is enabled; when the HBM chip accesses the address during application, it can automatically search for the corresponding target address in the mapping submodule, and the target address can point to another good memory control unit.

[0056] In summary, a chip 300 provided in this embodiment includes: an instantiation module, a common logic module and a bypass module; wherein: the instantiation module is configured to implement a preset processing function, and the instantiation module includes a plurality of identical instantiation units; the common logic module is configured to control the instantiation module and to be shared by the instantiation units; the bypass module is configured to shield abnormal instantiation units in the instantiation module. In the embodiment of the present invention, the logic that can be stripped and shared in each instantiation unit in the instantiation module is stripped and placed in the common logic module, thereby reducing the area of ​​the instantiation unit and increasing the number of instantiation units set; then, the abnormal instantiation unit is shielded by the bypass module, and other normal instantiation units can still provide sufficient performance, thereby improving the availability of the chip 300 under the same process yield. That is, since the common function is stripped, the instantiation unit is designed to be smaller through functional optimization. In this way, the number of instantiation units can be increased under the same total area. Even if individual instantiation units are affected by process defects, there are still enough intact units left to be used.

[0057] Second embodiment

[0058] See also Figure 3 In an embodiment of the present invention, a chip optimization method is provided. The relevant description and meaning of the terms in this embodiment can refer to the above-mentioned first embodiment. Specifically, this method includes:

[0059] Step S10: Based on the realizability of functions and logics, determine the instantiation module and common logic module of the chip; wherein the common logic module is shared by the instantiation units of the instantiation module, and the instantiation module is used to implement the preset processing function.

[0060] In step S10, when determining the instantiation module of the chip, the logic that can be shared in the instantiation unit in the instantiation module should be stripped as much as possible to form a separate common logic module. Thus, the instantiation module and the common logic module are divided into two areas: the instantiation area and the common logic area. Since the logic that can be shared in the instantiation unit is stripped, each instantiation unit is designed to be smaller through functional optimization. In this way, the number of instantiation units can be increased under the same total area. Even if individual instantiation units are affected by process defects, there are still enough intact units left to be used.

[0061] Furthermore, it is inevitable to introduce process defects in chip manufacturing. To ensure chip performance requirements, when setting the number of instantiated units, it should be ensured that it is greater than the preset basic number. The preset basic number is the number of instantiated units required to meet the chip performance requirements. The number of instantiated units should not be less than Y, Y = M + R*A*L; where Y is the number of instantiated units required for the final design, M is the minimum number of instantiated units required to achieve the preset performance requirements, R is the number of defects per unit area in the manufacturing process, A is the upper limit of the chip area, L is the upper limit of the area ratio of the instantiated module 301 in the chip, and R*A*L is the maximum number of defects in the instantiated module 301. In view of the uniform distribution of defects, it can be considered that R*A*L instantiated units may be damaged during the manufacturing process.

[0062] Step S20: configuring a bypass function of the instantiation module; wherein the bypass function is used to shield abnormal instantiation units in the instantiation module.

[0063] In step S20, the specific implementation may be: when the instantiation unit is abnormal, the identification number of the abnormal instantiation unit is recorded and configured so that the abnormal instantiation unit corresponding to the identification number is shielded; for example:

[0064] The bypass function can also be used as a public function and set in a public logic area. Taking each operator in the NPU chip as an example, the bypass function execution process is as follows:

[0065] First, the operator enable register can be designed in the common logic area. If an operator is found to be damaged during self-test, the identification number of the operator can be recorded; then, the operator enable register is configured to turn off the operator corresponding to the number. During normal calculation, the chip control unit will check the operator enable register before sending the data to be calculated to the operator. If it is turned off, no data will be sent to the operator, and the operator will not perform related calculations.

[0066] In addition, in step S20, the specific implementation may also be: when the instantiation unit is abnormal, the access operation corresponding to the abnormal instantiation unit is mapped to the normal instantiation unit. That is, stopping the abnormal instantiation unit in this embodiment includes directly shutting down, and making the abnormal instantiation unit inoperative by mapping to the normal instantiation unit.

[0067] Take the memory control unit in HBM as an example:

[0068] First, a mapping submodule for address mapping can be designed; when a memory control unit is found to be damaged during self-test, the address of the damaged content control unit is recorded. Then, the address is written into the address mapping module and the mapping submodule is enabled; when the HBM chip accesses the address during application, it can automatically search for the corresponding target address in the mapping submodule, and the target address can point to another good memory control unit.

[0069] To realize the bypass function and ensure the normal operation of the chip. After determining the instantiation module and the common logic module of the chip, it also includes: configuring the self-test function of the instantiation module. Through the configured self-test function, the chip performs a self-test every time it starts working, and there is no restriction on the implementation of the self-test function. This embodiment provides the following configuration method:

[0070] First, for each instantiation unit of the instantiation module, the instantiation unit is configured to be accessed and preset self-test data is written to the instantiation unit; then, the self-test data written in the instantiation unit is configured to be read to obtain verification data; finally, the self-test data and verification data of the instantiation unit are compared to see whether they are the same; if they are the same, the instantiation unit is determined to be a normal instantiation unit, otherwise it is an abnormal instantiation unit.

[0071] For example, for a memory control unit in an HBM chip, a certain memory control unit can be accessed through the HBM control unit, self-test data can be written to certain addresses, and then the self-test data of these addresses can be read out to obtain verification data; the self-test data and verification data before and after are compared. If these data are the same, that is, there is no error, then it proves that the memory control unit is normal.

[0072] It should be noted that the method of this embodiment can be used to design the chip in the first embodiment. In addition, the chip design process not mentioned in this embodiment can refer to the prior art and will not be repeated in this embodiment.

[0073] In summary, a chip optimization method provided in this embodiment determines the instantiation module and common logic module of the chip based on the realizability of functions and logic when determining the chip architecture; the common logic module is shared by the instantiation unit; the instantiation module includes multiple instantiation units, and the instantiation unit is used to implement the preset processing function; the logic that can be stripped and shared in each instantiation unit is stripped and placed in the common logic module, thereby reducing the area of ​​the instantiation unit and increasing the number of instantiation units. Then, the bypass function of the instantiation unit is configured so that the abnormal instantiation unit is shielded, and other normal instantiation units can still provide sufficient performance. Therefore, the availability of the chip is improved under the same process yield. That is to say, by optimizing the function (stripping the shared logic as much as possible), the instantiation unit is designed to be smaller. In this way, the number of instantiation units can be increased under the same total area. Even if some individual instantiation units are affected by process defects, there are still enough intact units left to be used.

[0074] Third embodiment

[0075] Based on the same inventive concept, an electronic device is also provided in this embodiment, including a processor and a memory, wherein the memory is coupled to the processor and stores instructions, and when the instructions are executed by the processor, the electronic device executes the steps of any one of the methods described in the second embodiment above.

[0076] It should be noted that, in the electronic device provided by the embodiment of the present invention, when the instruction is executed by the processor, the specific implementation of each step and the technical effect produced are the same as those in the aforementioned method embodiment. For the sake of brief description, the parts not mentioned in this embodiment can be referred to the corresponding contents in the aforementioned method embodiment.

[0077] The term "and / or" that appears in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship; the word "comprising" does not exclude the existence of elements or steps that are not listed in the claims. The word "one" or "an" placed before an element does not exclude the existence of multiple such elements. The present invention can be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0078] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0079] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0083] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A chip, characterized in that: include: instantiation modules, common logic modules and bypass modules; wherein: The instantiation module is configured to implement a preset processing function, and the instantiation module includes a plurality of identical instantiation units; The common logic module is configured to control the instantiation module and be shared by the instantiation units; The bypass module is configured to shield the abnormal instantiation unit in the instantiation module; The separable and shared logic in each instantiation unit in the instantiation module is removed and placed into a common logic module.

2. The chip according to claim 1, characterized in that: The number of the instantiation units is not less than Y, where Y=M+R*A*L, R is the number of defects per unit area during the process manufacturing process, A is the upper limit of the chip area, and L is the upper limit of the area occupied by the instantiation module in the chip; M is the minimum number of instantiation units required to achieve the preset performance requirements.

3. The chip according to claim 1, characterized in that: The bypass module includes: a shielding submodule, the shielding submodule is arranged in the common logic module; The shielding submodule is configured to store the identification number of the abnormal instantiation unit, so that the abnormal instantiation unit corresponding to the identification number is shielded.

4. The chip according to claim 3, characterized in that: The bypass module includes: a shielding submodule, the shielding submodule is arranged in the common logic module, and the shielding submodule is implemented based on an enable register; The enable register is configured to disable the exception instantiation unit so that the exception instantiation unit is shielded.

5. The chip according to claim 1, characterized in that: The bypass module includes: a mapping submodule; The mapping submodule is configured to map the access operation corresponding to the abnormal instantiation unit to the normal instantiation unit.

6. A chip optimization method, characterized in that: include: Based on the realizability of functions and logics, the instantiation module and the common logic module of the chip are determined; wherein the common logic module is shared by the instantiation units in the instantiation module, and the instantiation units are used to implement the preset processing functions; the logic that can be stripped and shared in each instantiation unit in the instantiation module is stripped and placed in the common logic module; A bypass function of the instantiation module is configured; wherein the bypass function is used to shield abnormal instantiation units in the instantiation module.

7. The method according to claim 6, characterized in that The instantiation module for determining the chip includes: Determine that the number of instantiated units in the instantiated module is not less than Y; wherein Y=M+R*A*L, wherein R is the number of defects introduced per unit area during the process manufacturing process, A is the upper limit of the chip area, and L is the upper limit of the area ratio of the instantiated module in the chip; and M is the minimum number of instantiated units required to achieve the preset performance requirements.

8. The method according to claim 6, characterized in that The configuring the bypass function of the instantiated module includes: Recording the identification number of the abnormal instantiation unit and configuring so that the abnormal instantiation unit corresponding to the identification number is shielded; Or, the access operation corresponding to the abnormal instantiation unit is mapped to the normal instantiation unit.

9. The method according to claim 6, characterized in that After determining the instantiation module and the common logic module of the chip, the method further includes: configuring a self-checking function of the instantiation module; for any instantiation unit in the instantiation module, configuring the self-checking function of the instantiation module includes: Configuration access to the instantiation unit, and writing preset self-test data to the instantiation unit; Configuring to read the self-test data written in the instantiation unit to obtain verification data; The self-check data and the verification data are configured to be compared to see if they are the same; if they are the same, the instantiation unit is determined to be a normal instantiation unit, otherwise, the instantiation unit is determined to be an abnormal instantiation unit.

10. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is coupled to the processor and stores instructions, and when the instructions are executed by the processor, the electronic device executes the steps of the method according to any one of claims 6 to 9.

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