Duty Cycle Adjustment Circuit, Chip and Duty Cycle Adjustment Method of Clock Signal

Abstract

The present invention provides a duty cycle adjustment circuit for a clock signal, a chip, and a duty cycle adjustment method. The circuit includes a decoding module and a duty cycle adjustment module. The decoding module receives a configuration signal and generates a control signal based on the configuration signal. The duty cycle adjustment module is connected to the decoding module and receives the clock signal. The duty cycle adjustment module delays the rising edge or the falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal. In the duty cycle adjustment circuit of the present application, since both the input and output of the duty cycle adjustment circuit are analog signals, the step of the duty cycle adjustment circuit can be made relatively small, thereby making the linearity of the step of the duty cycle adjustment circuit relatively good. The step of the duty cycle adjustment circuit changes very little with the operating voltage, temperature, and process corner. Especially when it is desired to adjust the duty cycle of a high-speed clock path in a large-size process, the duty cycle adjustment circuit of the present application is a very good choice.

Description

Technical Field

[0001] The present invention relates to the technical field of clock signal adjustment, and in particular, to a duty cycle adjustment circuit, a chip, and a duty cycle adjustment method for a clock signal. Background Art

[0002] In the design of high-speed DRAM products, in order to meet the chip speed requirements, a delay line needs to be placed on the clock path to adjust the duty cycle of the input clock. With the upgrade of the DRAM product interface, the speed of the input clock is getting higher and higher, and the linearity requirement for the step of the delay line is also getting higher and higher. At the same time, it is required that the step of the delay line changes as little as possible with PVT variations.

[0003] Currently, digital delay lines are generally used in high-speed DRAM products to complete the adjustment of the clock duty cycle. The working principle of the digital delay line is mainly to add a capacitive load behind the inverter, thereby changing the slopes of the rising edge and the falling edge of the clock signal, and thus affecting the transmission delay of the clock signal. With the changes in the operating voltage, temperature, and process, the step change of this digital delay line is very large, and the linearity is also relatively poor. Especially in some larger-sized processes, it becomes very difficult to adjust the training or duty cycle through the digital delay line method. Summary of the Invention

[0004] The present invention provides a duty cycle adjustment circuit, a chip, and a duty cycle adjustment method for a clock signal. The duty cycle adjustment circuit of the present application has good linearity of steps and is suitable for large chips.

[0005] To solve the above technical problems, the first technical solution provided by the present invention is: to provide a duty cycle adjustment circuit for a clock signal, including: a decoding module, which receives a configuration signal and generates a control signal based on the configuration signal; a duty cycle adjustment module, which is connected to the decoding module and receives the clock signal. The duty cycle adjustment module delays at least one step value for the rising edge or the falling edge of the received clock signal based on the control signal to generate an adjusted clock signal.

[0006] Among them, the clock signal includes a complementary first clock signal and a second clock signal; the control signal includes a first control signal group and a second control signal group; the duty cycle adjustment module generates a first adjusted clock signal complementary to the first clock signal based on the first clock signal, and delays the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group; and the duty cycle adjustment module generates a second adjusted clock signal complementary to the second clock signal based on the second clock signal, and delays the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group; wherein, the adjusted clock signal output is determined by the first adjusted clock signal and the second adjusted clock signal, and the rising edge of the adjusted clock signal output is determined by the rising edge of the first adjusted clock signal, and the falling edge of the adjusted clock signal output is determined by the rising edge of the second adjusted clock signal.

[0007] Among them, the duty cycle adjustment module includes: a first duty cycle adjustment unit, connected to the decoding module to receive the first control signal group, and receiving the first clock signal, to generate a first adjusted clock signal based on the first clock signal, and delay the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group; a second duty cycle adjustment unit, connected to the decoding module to receive the second control signal group, and receiving the second clock signal, to generate a second adjusted clock signal based on the second clock signal, and delay the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group.

[0008] Among them, the first duty cycle adjustment unit includes: a first switch group, including M first switches, to respectively receive the control signals in the first control signal group; a second switch group, including M second switches and a third switch, wherein each second switch and the third switch respectively receive the first clock signal, and each first switch is connected in series with a corresponding second switch to form an adjustment branch; the M adjustment branches are respectively connected in parallel and are connected in parallel with the third switch; wherein, the third switch and the second switches are used to generate a first adjusted clock signal complementary to the first clock signal based on the first clock signal; the first switches cooperate with the second switches to delay the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group.

[0009] Among them, the second duty cycle adjustment unit includes: a third switch group including N fourth switches to respectively receive control signals in the second control signal group; a fourth switch group including N fifth switches and a sixth switch, where each fifth switch and the sixth switch respectively receive a second clock signal, and each fourth switch is connected in series with a corresponding fifth switch to form an adjustment branch; the N adjustment branches are respectively connected in parallel and are also connected in parallel with the sixth switch; where the fifth switch and the sixth switch are used to generate a second adjustment clock signal complementary to the second clock signal based on the second clock signal; the fourth switch cooperates with the fifth switch to delay the rising edge of the second adjustment clock signal by at least one step value based on the second control signal group.

[0010] Among them, the number M of the first switches is equal to the number N of the fourth switches.

[0011] Among them, the second switch, the third switch, the fifth switch, and the sixth switch have the same specifications.

[0012] Among them, the duty cycle adjustment module further includes: a tail current adjustment unit connected to the first duty cycle adjustment unit and the second duty cycle adjustment unit to adjust the tail current of the duty cycle adjustment circuit.

[0013] Among them, the tail current adjustment unit includes: a fifth switch group including a plurality of seventh switches, where each seventh switch receives a control signal in the tail current adjustment control signal group; a sixth switch group including a plurality of eighth switches, where each eighth switch respectively receives a bias voltage, each seventh switch is connected in series with a corresponding eighth switch to form a tail current adjustment branch, and the plurality of tail current adjustment branches are respectively connected in parallel to determine the turned-on tail current adjustment branches based on the control signals in the tail current adjustment control signal group, thereby adjusting the tail current of the duty cycle adjustment circuit.

[0014] To solve the above technical problems, the second technical solution provided by the present invention is: to provide a chip including: the duty cycle adjustment circuit of the clock signal in any one of the above.

[0015] To solve the above technical problems, the third technical solution provided by the present invention is: to provide a method for adjusting the duty cycle of a clock signal, including: receiving a configuration signal and generating a control signal based on the configuration signal; receiving a clock signal and delaying the rising edge or falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal.

[0016] Among them, the control signal includes a first control signal group and a second control signal group; the step of receiving a clock signal and delaying at least one step value for the rising edge or falling edge of the received clock signal based on the control signal to generate an adjusted clock signal includes: receiving a first clock signal, generating a first adjusted clock signal complementary to the first clock signal based on the first clock signal, and delaying at least one step value for the rising edge of the first adjusted clock signal based on the first control signal group; receiving a second clock signal, generating a second adjusted clock signal complementary to the second clock signal based on the second clock signal, and delaying at least one step value for the rising edge of the second adjusted clock signal based on the second control signal group; wherein, the first clock signal is complementary to the second clock signal, the output adjusted clock signal is determined by the first adjusted clock signal and the second adjusted clock signal, and the rising edge of the output adjusted clock signal is determined by the rising edge of the first adjusted clock signal, and the falling edge of the output adjusted clock signal is determined by the rising edge of the second adjusted clock signal.

[0017] The beneficial effects of the present invention, different from the prior art, the duty cycle adjustment circuit of the clock signal of the present invention includes a decoding module and a duty cycle adjustment module. Among them, the decoding module receives a configuration signal and generates a control signal based on the configuration signal; the duty cycle adjustment module is connected to the decoding module and receives a clock signal. Among them, the duty cycle adjustment module delays at least one step value for the rising edge or falling edge of the received clock signal based on the control signal to generate an adjusted clock signal. In the duty cycle adjustment circuit of the present application, since both the input and output of the duty cycle adjustment circuit are analog signals, the step of it can be made relatively small, thereby making the linearity of the step of the duty cycle adjustment circuit relatively good; the step of the duty cycle adjustment circuit changes very little with the working voltage, temperature, and process corner. Especially when it is desired to adjust the duty cycle of a high-speed clock path in a large-size process, the duty cycle adjustment circuit of the present application is a very good choice. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings, where:

[0019] Figure 1 It is a schematic diagram of the functional modules of the first embodiment of the duty cycle adjustment circuit of the clock signal of the present invention;

[0020] Figure 2 It is a schematic diagram of the functional modules of the second embodiment of the duty cycle adjustment circuit of the clock signal of the present invention;

[0021] Figure 3 Schematic diagram of the functional modules of the third embodiment of the duty cycle adjustment circuit for the clock signal of the present invention;

[0022] Figure 4 Schematic diagram of the structure of an embodiment of the duty cycle adjustment module;

[0023] Figure 5 Timing diagram of the first embodiment of the clock signal;

[0024] Figure 6 Timing diagram of the second embodiment of the clock signal;

[0025] Figure 7 Timing diagram of the third embodiment of the clock signal;

[0026] Figure 8 Schematic diagram of the linearity of the steps of the digital duty cycle adjustment circuit of the prior art;

[0027] Figure 9 Schematic diagram of the linearity of the steps of the analog duty cycle adjustment circuit of the present application;

[0028] Figure 10 Schematic diagram of the structure of an embodiment of the chip of the present invention;

[0029] Figure 11 Schematic diagram of the flow of an embodiment of the duty cycle adjustment method of the present invention. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0031] Please refer to Figure 1 , which is a schematic diagram of the functional modules of the first embodiment of the duty cycle adjustment circuit for the clock signal of the present invention, specifically including: a decoding module 11 and a duty cycle adjustment module 12.

[0032] Among them, the decoding module 11 receives the configuration signal mrtrm<3:0> and generates a control signal SEL based on the configuration signal mrtrm<3:0>. Among them, the configuration signal mrtrm<3:0> is a four-bit configuration bit used to adjust the size of the clock delay, thereby affecting the size of the clock duty cycle.

[0033] The duty cycle adjustment module 12 is connected to the decoding module 11 and receives a clock signal. Among them, the duty cycle adjustment module 12 delays the rising edge or falling edge of the received clock signal by at least one step value based on the control signal SEL to generate an adjusted clock signal.

[0034] Specifically, the clock signal includes a complementary first clock signal inn and a second clock signal inp; the control signal includes a first control signal group and a second control signal group.

[0035] The duty cycle adjustment module 12 generates a first adjusted clock signal inp_dca complementary to the first clock signal inn based on the first clock signal inn, and delays the rising edge of the first adjusted clock signal inp_dca by at least one step value based on the first control signal group. The duty cycle adjustment module generates a second adjusted clock signal inn_dca complementary to the second clock signal inp based on the second clock signal inp, and delays the rising edge of the second adjusted clock signal inn_dca by at least one step value based on the second control signal group. Among them, the output adjusted clock signal is determined by the first adjusted clock signal inp_dca and the second adjusted clock signal inn_dca, and the rising edge of the output adjusted clock signal is determined by the rising edge of the first adjusted clock signal inp_dca, and the falling edge of the output adjusted clock signal is determined by the rising edge of the second adjusted clock signal inn_dca.

[0036] Specifically, as Figure 2 shown, the duty cycle adjustment module 12 includes a first duty cycle adjustment unit 121 and a second duty cycle adjustment unit 122. Among them, the first duty cycle adjustment unit 121 is connected to the decoding module 11 to receive the first control signal group, and receives the first clock signal inn to generate a first adjusted clock signal inp_dca based on the first clock signal inn, and delays the rising edge of the first adjusted clock signal inp_dca by at least one step value based on the first control signal group. The second duty cycle adjustment unit 122 is connected to the decoding module 11 to receive the second control signal group, and receives the second clock signal inp to generate a second adjusted clock signal inn_dca based on the second clock signal inp, and delays the rising edge of the second adjusted clock signal inn_dca by at least one step value based on the second control signal group.

[0037] Please refer to Figure 3 , the duty cycle adjustment module 12 further includes: a tail current adjustment unit 123. The tail current adjustment unit 123 is connected to the first duty cycle adjustment unit 121 and the second duty cycle adjustment unit 122 to adjust the tail current of the duty cycle adjustment module 12. Specifically, the tail current adjustment unit 123 adjusts the tail currents of the first duty cycle adjustment unit 121 and the second duty cycle adjustment unit 122.

[0038] Specifically, please combine with Figure 4 , Figure 4 is Figure 3 A schematic structural diagram of a specific embodiment of the duty cycle adjustment circuit shown. Among them, the decoding module 11 receives the configuration signal mrtrm<3:0> and generates a first control signal group and a second control signal group based on the configuration signal mrtrm<3:0>. The first control signal group includes control signals sel1, sel2... seln; the second control signal group includes control signals sel1_n, sel2_n... seln_n.

[0039] The configuration signal mrtrm<3:0> is a four-bit configuration bit used to adjust the size of the clock delay, thereby affecting the size of the clock duty cycle. In a specific embodiment, assume that the first control signal group includes control signals sel1, sel2... sel7, and the second control signal group includes sel1_n, sel2_n... sel7_n. When mrtrm<3:0> is 0000, sel1, sel2... sel7 are all low levels, and no duty cycle adjustment is performed. When mrtrm<3:0> is 0001, only sel1 is high level, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 1 step value, and the duty cycle of the output adjusted clock signal is reduced by 1 step value; when mrtrm<3:0> is 0010, only sel1 and sel2 are high levels, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 2 step values, and the duty cycle of the output adjusted clock signal is reduced by 2 step values; when mrtrm<3:0> is 0011, sel1, sel2, and sel3 are high levels, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 3 step values, and the duty cycle of the output adjusted clock signal is reduced by 3 step values; when mrtrm<3:0> is 0100, sel1, sel2, sel3, and sel4 are high levels, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 4 step values, and the duty cycle of the output adjusted clock signal is reduced by 4 step values; when mrtrm<3:0> is 0101, sel1, sel2, sel3, sel4, and sel5 are high levels, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 5 step values, and the duty cycle of the output adjusted clock signal is reduced by 5 step values; when mrtrm<3:0> is 0110, sel1, sel2, sel3, sel4, sel5, and sel6 are high levels, and the rest are low levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 6 step values, and the duty cycle of the output adjusted clock signal is reduced by 6 step values; when mrtrm<3:0> is 0111, sel1, sel2, sel3, sel4, sel5, sel6, and sel7 are all high levels. At this time, the rising edge of the first adjusted clock signal inp_dca is delayed by 7 step values, and the duty cycle of the output adjusted clock signal is reduced by 7 step values.

[0040] When mrtrm<3:0> is 1000, sel1_n, sel2_n... sel7_n are all at low level, and no duty cycle adjustment is performed. When mrtrm<3:0> is 1001, only sel1_n is at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 1 step value, and the duty cycle of the output adjusted clock signal increases by one step value; when mrtrm<3:0> is 1010, only sel1_n and sel2_n are at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 2 step values, and the duty cycle of the output adjusted clock signal increases by two step values; when mrtrm<3:0> is 1011, sel1_n, sel2_n, and sel3_n are at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 3 step values, and the duty cycle of the output adjusted clock signal increases by three step values; when mrtrm<3:0> is 1100, sel1_n, sel2_n, sel3_n, and sel4_n are at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 4 step values, and the duty cycle of the output adjusted clock signal increases by four step values; when mrtrm<3:0> is 1101, sel1_n, sel2_n, sel3_n, sel4_n, and sel5_n are at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 5 step values, and the duty cycle of the output adjusted clock signal increases by five step values; when mrtrm<3:0> is 1110, sel1_n, sel2_n, sel3_n, sel4_n, sel5_n, and sel6_n are at high level and the rest are at low level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 6 step values, and the duty cycle of the output adjusted clock signal increases by six step values; when mrtrm<3:0> is 1111, sel1_n, sel2_n, sel3_n, sel4_n, sel5_n, sel6_n, and sel7_n are all at high level. At this time, the rising edge of the second adjustment clock signal inn_dca is delayed by 7 step values, and the duty cycle of the output adjusted clock signal increases by seven step values.

[0041] The first duty cycle adjustment unit 121 includes a first switch group. The first switch group includes M first switches, which respectively receive the control signals sel1, sel2... seln in the first control signal group. Specifically, each of the M first switches corresponds to a control signal. For example Figure 4As shown, the first switch group includes first switches Q1, Q2... Qn. Among them, the control signal sel1 controls the conduction and cutoff of the first switch Q1; the control signal sel2 controls the conduction and cutoff of the first switch Q2; the control signal seln controls the conduction and cutoff of the first switch Qn.

[0042] The first duty cycle adjustment unit 121 further includes a second switch group, and the second switch group includes M second switches and a third switch M0. Among them, each second switch and the third switch respectively receive the first clock signal inn, and each first switch is connected in series with a corresponding second switch to form an adjustment branch; the M adjustment branches are respectively connected in parallel and are connected in parallel with the third switch. As Figure 4 shown, the M second switches are respectively M1, M2... Mn. Among them, the control terminals of the second switches M1, M2... Mn and the control terminal of the third switch M0 all receive the first clock signal inn. The first switch Q1 is connected in series with the second switch M1 to form an adjustment branch, the first switch Q1 is connected in series with the second switch M1 to form an adjustment branch, the first switch Q2 is connected in series with the second switch M2 to form an adjustment branch, and the first switch Qn is connected in series with the second switch Mn to form an adjustment branch. And the adjustment branches formed by the first switch Q1 and the second switch M1, the adjustment branches formed by the first switch Q2 and the second switch M2... the adjustment branches formed by the first switch Qn and the second switch Mn are respectively connected in parallel, and are also connected in parallel with the third switch M0.

[0043] Among them, the third switch M0 and the second switches M1, M2... Mn are used to generate a first adjustment clock signal inp_dca complementary to the first clock signal inn based on the first clock signal inn. The first switch cooperates with the second switch to delay the rising edge of the first adjustment clock signal inp_dca by at least one step value based on the first control signal group. Specifically, when the control signal sel1 in the first control signal group controls the first switch Q1 to conduct, the rising edge of the first adjustment clock signal inp_dca is delayed by one step value; when the control signal sel1 in the first control signal group controls the first switch Q1 to conduct, and the control signal sel2 in the first control signal group controls the first switch Q2 to conduct, the rising edge of the first adjustment clock signal inp_dca is delayed by two step values; when the control signal sel1 in the first control signal group controls the first switch Q1 to conduct, and the control signal sel2 in the first control signal group controls the first switch Q2 to conduct, and the control signal seln in the first control signal group controls the first switch Qn to conduct, the rising edge of the first adjustment clock signal inp_dca is delayed by n step values.

[0044] The second duty cycle adjustment unit 122 includes: a third switch group, the third switch group includes N fourth switches, which respectively receive the control signals sel1_n, sel2_n... seln_n in the second control signal group. Specifically, each of the N fourth switches corresponds to a control signal. As Figure 4 shown, the third switch group includes fourth switches Q1_n, Q2_n... Qn_n. Among them, the control signal sel1_n controls the on and off of the fourth switch Q1_n; the control signal sel2_n controls the on and off of the fourth switch Q2_n; the control signal seln_n controls the on and off of the fourth switch Qn_n.

[0045] The second duty cycle adjustment unit 122 further includes: a fourth switch group, the fourth switch group includes N fifth switches and a sixth switch M0_n. Among them, each of the fifth switches and the sixth switch M0_n receives the second clock signal inp, and each fourth switch is connected in series with a corresponding fifth switch to form an adjustment branch; the N adjustment branches are respectively connected in parallel and are also connected in parallel with the sixth switch M0_n. As Figure 4 shown, the N fifth switches are respectively M1_n, M2_n... Mn_n. Among them, the control terminals of the fifth switches M1_n, M2_n... Mn_n and the control terminal of the sixth switch M0_n all receive the second clock signal inp. The fourth switch Q1_n is connected in series with the fifth switch M1_n to form an adjustment branch, the fourth switch Q1_n is connected in series with the fifth switch M1_n to form an adjustment branch, the fourth switch Q2_n is connected in series with the fifth switch M2_n to form an adjustment branch, and the fourth switch Qn_n is connected in series with the fifth switch Mn_n to form an adjustment branch. And the adjustment branches formed by the fourth switch Q1_n and the fifth switch M1_n, the adjustment branches formed by the fourth switch Q2_n and the fifth switch M2_n... the adjustment branches formed by the fourth switch Qn_n and the fifth switch Mn_n are respectively connected in parallel, and are also connected in parallel with the sixth switch M0_n.

[0046] Among them, the fifth switches M1_n, M2_n... Mn_n and the sixth switch M0_n are used to generate a second adjusted clock signal inn_dca complementary to the second clock signal based on the second clock signal inp. The fourth switch cooperates with the fifth switch to delay the rising edge of the second adjusted clock signal inn_dca by at least one step value based on the second control signal group. Specifically, when the control signal sel1_n in the second control signal group controls the fourth switch Q1_n to conduct, the rising edge of the second adjusted clock signal inn_dca is delayed by one step value; when the control signal sel1_n in the second control signal group controls the fourth switch Q1_n to conduct, and the control signal sel2_n in the second control signal group controls the fourth switch Q2_n to conduct, the rising edge of the second adjusted clock signal inn_dca is delayed by two step values; when the control signal sel1_n in the second control signal group controls the fourth switch Q1_n to conduct, the control signal sel2_n in the second control signal group controls the fourth switch Q2_n to conduct, and the control signal seln_n in the second control signal group controls the fourth switch Qn_n to conduct, the rising edge of the second adjusted clock signal inn_dca is delayed by n step values.

[0047] In a specific embodiment, the number M of the first switches is equal to the number N of the fourth switches. And, in an embodiment, the second switches, the third switches, the fifth switches, and the sixth switches have the same specifications.

[0048] Please continue to refer to Figure 4 , the tail current adjustment unit 123 includes: a fifth switch group and a sixth switch group.

[0049] The fifth switch group includes a plurality of seventh switches T0, T1, T2. Among them, each of the seventh switches T0, T1, T2 receives a control signal in the tail current adjustment control signal group. As Figure 4 shown, the seventh switch T0 receives the control signal trm<0> in the tail current adjustment control signal group, the seventh switch T1 receives the control signal trm<1> in the tail current adjustment control signal group, and the seventh switch T2 receives the control signal trm<2> in the tail current adjustment control signal group.

[0050] The sixth switch group includes a plurality of eighth switches T. Among them, each of the eighth switches T receives the bias voltage Vbias respectively. Each seventh switch is connected in series with a corresponding eighth switch to form a tail current adjustment branch. The plurality of tail current adjustment branches are connected in parallel to determine the turned-on tail current adjustment branches based on the control signals in the tail current adjustment control signal group, so as to adjust the tail current of the duty cycle adjustment circuit.

[0051] Please combine with Figure 5 , Figure 5It is a timing diagram of the first embodiment of the duty cycle adjustment circuit. Specifically, when the configuration signal mrtrm<3:0> is 0000 or 1000, the control signals sel1, sel2... seln in the first control signal group are all at low level, and the control signals sel1_n, sel2_n... seln_n in the second control signal group are also at low level; at this time, only the third switch M0 acts on the first clock signal inn and generates the first adjusted clock signal inp_dca; the sixth switch M0_n acts on the second clock signal inp and generates the second adjusted clock signal inn_dca. At this time, the delay times of the first adjusted clock signal inp_dca and the second adjusted clock signal inn_dca are the same. Specifically, at this time, the rising edge and falling edge propagation delays of the output adjusted clock signal CLOCK1 are the same, and the clock duty cycle does not change and is the same as that of the input clock signal.

[0052] Please refer to Figure 6 , Figure 6 It is a timing diagram of the second embodiment of the duty cycle adjustment circuit. Specifically, when the configuration signal mrtrm<3:0> is 0001, the control signal sel1 in the first control signal group is at high level, the first switch Q1 is turned on, the current value increases, which in turn causes the low level output by the first duty cycle adjustment unit 121 to decrease, resulting in an increase in the rising edge delay time of the output first adjusted clock signal inp_dca by one step value, which also means that the duty cycle of the input clock signal decreases by one step value. Specifically, the high level duration of the original input clock signal is A1, and the high level duration of the adjusted clock signal is A2. Compared with the original clock signal, the high level duration decreases by one step value, so that the duty cycle of the output adjusted clock signal CLOCK2 decreases by one step value.

[0053] It can be understood that when mrtrm<3:0> is 0010, the control signal sel2 in the first control signal group is at high level, the first switch Q2 is turned on, resulting in an increase in the rising edge delay time of the output first adjusted clock signal inp_dca by two step values, which also means that the duty cycle of the input clock signal decreases by two step values. Thus, the duty cycle of the output adjusted clock signal CLOCK2 decreases by two step values. And so on, the more the number of turned-on first switches, the greater the rising edge delay time of the first adjusted clock signal inp_dca, and the smaller the duty cycle of the output adjusted clock signal CLOCK2.

[0054] Please refer to Figure 7 , Figure 7It is a timing diagram of the third embodiment of the duty cycle adjustment circuit. Specifically, when the configuration signal mrtrm<3:0> is 1001, the control signal sel1_n in the first control signal group is at a high level, the fourth switch Q1_n is turned on, the current value increases, which in turn causes the low level output by the second duty cycle adjustment unit 122 to decrease, thereby causing the rising edge delay time of the output second adjustment clock signal inn_dca to increase by one step value, which also means that the duty cycle of the input clock signal increases by one step value. Specifically, the high-level duration of the original input clock signal is A1, and the high-level duration of the adjusted clock signal is A3. Compared with the original clock signal, the high-level duration increases by one step value, so that the duty cycle of the output adjusted clock signal CLOCK3 increases by one step value.

[0055] It can be understood that when mrtrm<3:0> is 1010, the control signal sel2_n in the second control signal group is at a high level, the fourth switch Q2_n is turned on, which causes the rising edge delay time of the output second adjustment clock signal inn_dca to increase by two step values, which also means that the duty cycle of the input clock signal increases by two step values. Thus, the duty cycle of the output adjusted clock signal CLOCK3 increases by two step values. And so on, the more the number of the fourth switches turned on, the greater the rising edge delay time of the second adjustment clock signal inn_dca, and the greater the duty cycle of the output adjusted clock signal CLOCK3.

[0056] In the duty cycle adjustment circuit of the present application, since both the input and output of the duty cycle adjustment circuit are analog signals, its step can be made relatively small, and thus the linearity of the step of the duty cycle adjustment circuit is relatively good; the step of the duty cycle adjustment circuit changes very little with the working voltage, temperature, and process corner. Especially when it is desired to adjust the duty cycle of a high-speed clock path in a large-size process, the duty cycle adjustment circuit of the present application is a very good choice.

[0057] For specific reference Figure 8 and Figure 9 , Figure 8 is a schematic diagram of the linearity of the step of the digital duty cycle adjustment circuit in the prior art, Figure 9 is a schematic diagram of the linearity of the step of the analog duty cycle adjustment circuit of the present application. Obviously, as shown in the figure, the linearity of the duty cycle adjustment circuit of the present application is much better than that of the step of the duty cycle adjustment circuit in the prior art.

[0058] Please refer to Figure 10 , which is a schematic structural diagram of an embodiment of the chip of the present application. Specifically, the chip 100 shown in the present application includes a duty cycle adjustment circuit 110. The duty cycle adjustment circuit 110 is the above-mentionedFigures 1 to 4 The duty cycle adjustment circuit of any embodiment.

[0059] In the duty cycle adjustment circuit of the present application, since both the input and output of the duty cycle adjustment circuit are analog signals, its step can be made relatively small, thereby making the linearity of the step of the duty cycle adjustment circuit relatively good; the step of the duty cycle adjustment circuit changes very little with the operating voltage, temperature, and process corner. Especially when it is desired to adjust the duty cycle of a high-speed clock path in a large-size process, the duty cycle adjustment circuit of the present application is a very good choice.

[0060] Please refer to Figure 11 , which is a schematic flowchart of an embodiment of the duty cycle adjustment method of the present application, specifically including:

[0061] Step S11: Receive a configuration signal and generate a control signal based on the configuration signal.

[0062] Specifically, in the present application, the configuration signal is a four-bit configuration bit used to adjust the size of the clock delay, thereby affecting the size of the clock duty cycle.

[0063] In one embodiment, a decoding module can be used to generate a control signal based on the configuration signal.

[0064] Step S12: Receive a clock signal and delay the rising edge or falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal.

[0065] In one embodiment, the clock signal includes complementary first clock signal inn and second clock signal inp; the control signal includes a first control signal group and a second control signal group. Receive the first clock signal, generate a first adjusted clock signal complementary to the first clock signal based on the first clock signal, and delay the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group. Receive the second clock signal, generate a second adjusted clock signal complementary to the second clock signal based on the second clock signal, and delay the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group. Among them, the first clock signal is complementary to the second clock signal, the output adjusted clock signal is determined by the first adjusted clock signal and the second adjusted clock signal, and the rising edge of the output adjusted clock signal is determined by the rising edge of the first adjusted clock signal, and the falling edge of the output adjusted clock signal is determined by the rising edge of the second adjusted clock signal.

[0066] In a specific embodiment, it can be based on the above Figures 1 to 4The duty cycle adjustment module 12 shown generates a first adjusted clock signal inp_dca complementary to the first clock signal inn based on the first clock signal inn, and delays the rising edge of the first adjusted clock signal inp_dca by at least one step value based on the first control signal group. The duty cycle adjustment module generates a second adjusted clock signal inn_dca complementary to the second clock signal inp based on the second clock signal inp, and delays the rising edge of the second adjusted clock signal inn_dca by at least one step value based on the second control signal group.

[0067] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A duty cycle adjustment circuit for a clock signal, characterized in that, Including: A decoding module, which receives a configuration signal and generates a control signal based on the configuration signal; A duty cycle adjustment module, connected to the decoding module and receiving a clock signal, wherein the duty cycle adjustment module delays the rising edge or the falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal; Wherein the clock signal includes a complementary first clock signal and a second clock signal; The control signal includes a first control signal group and a second control signal group; The duty cycle adjustment module generates a first adjusted clock signal complementary to the first clock signal based on the first clock signal, and delays the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group; And the duty cycle adjustment module generates a second adjusted clock signal complementary to the second clock signal based on the second clock signal, and delays the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group; Wherein, the output adjusted clock signal is determined by the first adjusted clock signal and the second adjusted clock signal, and the rising edge of the output adjusted clock signal is determined by the rising edge of the first adjusted clock signal, and the falling edge of the output adjusted clock signal is determined by the rising edge of the second adjusted clock signal; Wherein, the duty cycle adjustment module includes: A first duty cycle adjustment unit, connected to the decoding module to receive the first control signal group and receive the first clock signal, to generate the first adjusted clock signal based on the first clock signal, and delay the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group; A second duty cycle adjustment unit, connected to the decoding module to receive the second control signal group and receive the second clock signal, to generate the second adjusted clock signal based on the second clock signal, and delay the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group; A tail current adjustment unit, connected to the first duty cycle adjustment unit and the second duty cycle adjustment unit to adjust the tail current of the duty cycle adjustment circuit.

2. The duty cycle adjustment circuit according to claim 1, wherein The first duty cycle adjustment unit includes: A first switch group, including M first switches to respectively receive control signals in the first control signal group; A second switch group, including M second switches and a third switch, wherein each of the second switches and the third switch respectively receives the first clock signal, and each of the first switches is connected in series with a corresponding second switch to form an adjustment branch; the M adjustment branches are respectively connected in parallel and are connected in parallel with the third switch; Wherein, the third switch and the second switch are used to generate the first adjusted clock signal complementary to the first clock signal based on the first clock signal; the first switch cooperates with the second switch to delay the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group.

3. The duty cycle adjustment circuit according to claim 2, wherein the second duty cycle adjustment unit includes: a third switch group including N fourth switches to respectively receive control signals in the second control signal group; a fourth switch group including N fifth switches and a sixth switch, wherein each of the fifth switches and the sixth switch respectively receives the second clock signal, and each of the fourth switches is connected in series with a corresponding fifth switch to form an adjustment branch; the N adjustment branches are respectively connected in parallel and are connected in parallel with the sixth switch; wherein, the fifth switch and the sixth switch are used to generate a second adjusted clock signal complementary to the second clock signal based on the second clock signal; the fourth switch cooperates with the fifth switch to delay the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group.

4. The duty cycle adjustment circuit according to claim 3, characterized in that The number M of the first switches is equal to the number N of the fourth switches.

5. The duty cycle adjustment circuit according to claim 3, wherein The second switch, the third switch, the fifth switch and the sixth switch have the same specifications.

6. The duty cycle adjustment circuit according to claim 1, wherein The tail current adjustment unit includes: a fifth switch group including a plurality of seventh switches, wherein each of the seventh switches receives a control signal in the tail current adjustment control signal group; a sixth switch group including a plurality of eighth switches, wherein each eighth switch respectively receives a bias voltage, each of the seventh switches is connected in series with a corresponding eighth switch to form a tail current adjustment branch, and the plurality of tail current adjustment branches are respectively connected in parallel to determine the turned-on tail current adjustment branches based on the control signals in the tail current adjustment control signal group, thereby adjusting the tail current of the duty cycle adjustment circuit.

7. A chip, characterized in that, including: the duty cycle adjustment circuit of the clock signal according to any one of claims 1-6.

8. A method for adjusting the duty cycle of a clock signal, characterized in that, The duty cycle adjustment method is applied to the duty cycle adjustment circuit of the clock signal according to any one of claims 1-6, and the duty cycle adjustment method includes: receiving a configuration signal and generating a control signal based on the configuration signal; receiving a clock signal, delaying the rising edge or the falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal; wherein, the control signal includes a first control signal group and a second control signal group; the step of receiving a clock signal, delaying the rising edge or the falling edge of the received clock signal by at least one step value based on the control signal to generate an adjusted clock signal includes: receiving a first clock signal, generating a first adjusted clock signal complementary to the first clock signal based on the first clock signal, and delaying the rising edge of the first adjusted clock signal by at least one step value based on the first control signal group; Receive a second clock signal, generate a second adjusted clock signal complementary to the second clock signal based on the second clock signal, and delay the rising edge of the second adjusted clock signal by at least one step value based on the second control signal group; Wherein, the first clock signal is complementary to the second clock signal, the output adjusted clock signal is determined by the first adjusted clock signal and the second adjusted clock signal, and the rising edge of the output adjusted clock signal is determined by the rising edge of the first adjusted clock signal, and the falling edge of the output adjusted clock signal is determined by the rising edge of the second adjusted clock signal.

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