Semiconductor packaging device and manufacturing method thereof

Abstract

This disclosure relates to a semiconductor packaging apparatus and a method for manufacturing the same. The semiconductor packaging apparatus includes: a first redistribution layer; a first structure disposed below the first redistribution layer, wherein the first structure has an opening to expose a portion of the first redistribution layer; a first conductive pad disposed on a lower surface of the first redistribution layer; a second conductive pad disposed on a lower surface of the first structure; and a first wire bonding electrically connecting the first conductive pad and the second conductive pad.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Traditional FOSUB (Fan-Out Substrate) typically attaches a redistribution layer to the substrate via an adhesive layer. Electrical connections between the redistribution layer and the substrate are achieved through vias passing through the adhesive layer. In the via formation process, laser drilling is first performed on the redistribution layer surface facing the substrate to create vias that pass through the dielectric layer. Next, a seed layer is created, followed by filling with conductive metal.

[0003] Reliability testing revealed fractures and delamination between the seed layer and the dielectric layer, leading to electrical failure of the vias. The causes may include: poor adhesion between the seed layer and the dielectric layer; the via's aspect ratio (AR ratio) resulting in a very small aperture near the substrate, causing plating problems; and complex via fabrication processes. Summary of the Invention

[0004] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising: a first redistribution layer; a first structure disposed below the first redistribution layer, wherein the first structure has an opening to expose a portion of the first redistribution layer; a first conductive pad disposed on a lower surface of the first redistribution layer; a second conductive pad disposed on a lower surface of the first structure; and a first wire bonding electrically connecting the first conductive pad and the second conductive pad.

[0006] In some alternative implementations, the first structure is a substrate.

[0007] In some alternative embodiments, the substrate contains glass fibers.

[0008] In some alternative implementations, the first structure is a second wiring layer.

[0009] In some alternative embodiments, the semiconductor packaging device further includes an adhesive layer disposed between the first redistribution layer and the first structure.

[0010] In some alternative embodiments, the adhesive layer is recessed within the first structure.

[0011] In some alternative implementations, the semiconductor packaging device further includes a protective layer covering the first structure, the opening, and the first wire bonding beneath the first structure.

[0012] In some alternative embodiments, the semiconductor packaging apparatus further includes: a third conductive pad disposed on the lower surface of the protective layer; a second wire electrically connecting the first conductive pad and the third conductive pad; and a third wire electrically connecting the second conductive pad and the third conductive pad.

[0013] In some alternative embodiments, the semiconductor packaging device further includes solder balls disposed on the lower surface of the third conductive pad.

[0014] In some alternative embodiments, the semiconductor packaging device further includes: a second structure disposed above the first redistribution layer, wherein the second structure has at least one opening to expose a portion of the first redistribution layer; a fourth conductive pad disposed on the upper surface of the first redistribution layer; a fifth conductive pad disposed on the upper surface of the second structure; and a fourth wire bonding electrically connecting the fourth conductive pad and the fifth conductive pad.

[0015] To address the issues of via electrical failure caused by breakage and delamination between the seed layer and dielectric layer, this disclosure provides a semiconductor packaging device and its manufacturing method. This method utilizes wire bonding to electrically connect the redistribution layer and the protective layer, and then covers the wire bonding with the protective layer. This results in a more reliable electrical connection between the two structures, eliminating the need to consider the surface condition of the wire bonding. Furthermore, due to the smaller diameter of the wire bonding, higher I / O density can be provided. Additionally, because the substrate has openings and the protective layer material is filled within these openings, the overall coefficient of thermal expansion (CTE) of the semiconductor packaging device varies less, leading to a more stable structure. Moreover, the semiconductor packaging device manufacturing process is simpler, less expensive, and has a higher yield. Attached Figure Description

[0016] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0017] Figure 1 This is a longitudinal cross-sectional structural schematic diagram of a first embodiment of a semiconductor packaging apparatus according to the present disclosure;

[0018] Figure 2 This is a longitudinal cross-sectional structural schematic diagram of a second embodiment of the semiconductor packaging apparatus according to the present disclosure;

[0019] Figure 3This is a longitudinal cross-sectional structural schematic diagram of a third embodiment of a semiconductor packaging apparatus according to the present disclosure;

[0020] Figure 4 This is a longitudinal cross-sectional structural schematic diagram of a fourth embodiment of a semiconductor packaging apparatus according to the present disclosure;

[0021] Figure 5A , 5B 5C, 5D, 5E, 5F and 5G are schematic diagrams of longitudinal cross-sectional structures at various manufacturing stages of a second embodiment of the semiconductor packaging apparatus according to the present disclosure.

[0022] Figure label:

[0023] 101: First redistribution layer; 102: First substrate; 103: First conductive pad; 104: Second conductive pad; 105: First wire bonding; 106: First adhesive layer; 107: Glass fiber; 108: Seed layer; 109: First protective layer; 110: Third conductive pad; 111: Second wire bonding; 112: Third wire bonding; 113: Solder ball; 114: Second redistribution layer; 102': Second substrate; 103': Fourth conductive pad; 104': Fifth conductive pad; 105': Fourth wire bonding; 106': Second adhesive layer; 109': Second protective layer; 110': Sixth conductive pad; 201: Carrier board; 202: Seed layer. Detailed Implementation

[0024] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0025] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0026] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0027] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] refer to Figure 1 , Figure 1 This is a longitudinal cross-sectional structural schematic diagram of a first embodiment of the semiconductor packaging apparatus according to the present disclosure. Figure 1 As shown, the semiconductor packaging device includes a first redistribution layer 101, a first adhesive layer 106, a first substrate 102, and a first wire bonding 105. The first redistribution layer 101 and the first substrate 102 are bonded together by the first adhesive layer 106. Although Figure 1 The semiconductor packaging device shown has a first adhesive layer 106, but in some alternative embodiments, the first substrate 102 can be directly bonded to the first redistribution layer 101 without the first adhesive layer 106. Furthermore, according to... Figure 1 As shown in the cross-sectional view, the first substrate 102 is located below the first redistribution layer 101. However, as is well known to those skilled in the art, this orientation is not absolute and can be reversed so that the first substrate 102 is located above the first redistribution layer 101.

[0029] The first adhesive layer 106 and the first substrate 102 have openings to expose portions of the first redistribution layer 101. The number of openings is at least one, for example, one, two, or more. A first conductive pad 103 is disposed on the lower surface of the first redistribution layer 101. A second conductive pad 104 is disposed on the lower surface of the first substrate 102. Note that in... Figure 1 In the figure, although reference numeral 103 is only indicated at a portion of the first conductive pad, all conductive pads provided on the lower surface of the first redistribution layer 101 are first conductive pads 103; although reference numeral 104 is only indicated at a portion of the second conductive pad, all conductive pads provided on the lower surface of the first substrate 102 are second conductive pads 104.

[0030] The first conductive pad 103 and the second conductive pad 104 can be, for example, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), palladium (Pd), solder, and / or graphene, etc.

[0031] The first substrate 102 can be of various types of substrates, and this disclosure does not specifically limit it.

[0032] The first substrate 102 may include organic and / or inorganic materials, wherein the organic materials may be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0033] The first substrate 102 can also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0034] The first redistribution layer 101 can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, it can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramics, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys.

[0035] Both the first substrate 102 and the first redistribution layer 101 can be single-layer or multi-layer structures.

[0036] The first bonding wire 105 can be made of conductive materials such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), palladium (Pd), platinum (Pt) and their alloys.

[0037] The above Figure 1 In the illustrated semiconductor packaging device embodiment, the electrical connection between the first substrate 102 and the first redistribution layer 101 is not achieved through vias, but rather by electrically connecting a portion of the first conductive pad 103 and a portion of the second conductive pad 104 using conductive first bonding wires 105. This avoids the electrical failure problem associated with vias.

[0038] In some alternative implementations, such as Figure 1 As shown, the adhesive layer 106 is recessed within the first substrate 102. That is, the horizontal length of the adhesive layer 106 in the cross-sectional view shown is shorter than that of the first substrate 102. In this way, in addition to achieving the purpose of bonding the first redistribution layer 101 and the first substrate 102, the adhesive layer 106 can also achieve the following: when the openings in the first adhesive layer 106 and the first substrate 102 are filled with a protective layer, more protective layer material can be filled at the opening locations of the adhesive layer. This results in higher overall strength of the semiconductor packaging device, smaller differences in the coefficient of thermal expansion (CTE) of the semiconductor packaging device, and a more stable structure.

[0039] In some alternative implementations, such as Figure 1 As shown, the first substrate 102 may contain glass fibers to enhance the rigidity of the first substrate 102 and prevent warping.

[0040] In some alternative implementations, such as Figure 1 As shown, seed layers 108 may be provided between the first conductive pad 103 and the first redistribution layer 101, and between the second conductive pad 104 and the first substrate 102, to facilitate the formation of conductive pads on the redistribution layer and the substrate during the manufacturing process. The seed layer 108 may be, for example, titanium (Ti), tungsten (W), nickel (Ni), and their alloys.

[0041] Further reference Figure 2 , Figure 2 This is a longitudinal cross-sectional structural schematic diagram of a second embodiment of the semiconductor packaging apparatus according to the present disclosure. Figure 1 Based on the semiconductor packaging device shown, Figure 2 The semiconductor packaging device shown also includes: a first protective layer 109, a third conductive pad 110, a second wire bonding 111, a third wire bonding 112, and solder balls 113.

[0042] The first protective layer 109 covers the first substrate 102, the first adhesive layer 106, the openings in the first substrate 102, and the first wire bonding 105 beneath the first substrate 102. The first protective layer 109 can be, for example, an underfill or a molding compound. The first protective layer 109 can fix the first wire bonding 105, the second wire bonding 111, and the third wire bonding 112, and can provide a substantially flat surface.

[0043] Since the openings in the first adhesive layer 106 and the first substrate 102 are filled with the first protective layer 109, that is, part of the substrate is replaced by the protective layer, the stress brought by the protective layer during thermal expansion is smaller than that of the substrate, and the openings make the stress of the substrate discontinuous, thereby reducing the occurrence of warping.

[0044] The third conductive pad 110 is disposed on the lower surface of the first protective layer 109. Note that... Figure 2 Although reference numeral 110 only indicates a portion of the third conductive pad, all conductive pads disposed on the lower surface of the first protective layer 109 are third conductive pads 110.

[0045] The materials of the second bonding wire 111 and the third bonding wire 112 can be the same as those of the first bonding wire 105. The material of the third conductive pad 110 can be the same as that of the first conductive pad 103 and the second conductive pad 104.

[0046] The second wire 111 electrically connects a portion of the first conductive pad 103 and a portion of the third conductive pad 110, thereby achieving an electrical connection between the first redistribution layer 101 and the device disposed at the third conductive pad 110. The third wire 112 electrically connects a portion of the second conductive pad 104 and a portion of the third conductive pad 110, thereby achieving an electrical connection between the first substrate 102 and the device disposed at the third conductive pad 110.

[0047] Therefore, by using wire bonding, the I / O interfaces of the redistribution layer and the substrate can be brought out to the lower surface of the protective layer. Since the diameter of wire bonding is smaller than that of micro bumps as external electrical connections of semiconductor packaging devices, wire bonding can provide higher I / O density on the lower surface of the protective layer.

[0048] As an example, the dimensions of the above components can be set as follows: the diameters of the first bonding wire 105, the second bonding wire 111, and the third bonding wire 112 are 10um to 50um; the thickness of the first redistribution layer 101 is 3um to 50um; the thickness of the first adhesive layer 106 is 50um to 200um; the thickness of the first substrate 102 is 20um to 200um; the thickness of the first protective layer 109 under the first substrate 102 is 10um to 100um; the width of the opening in the first adhesive layer 106 is between several hundredum and several millimeters; the linewidth / spacing (L / S) of the upper surface of the first redistribution layer 101 is less than 2um / 2um; the linewidth / spacing (L / S) of the lower surface of the first substrate 102 is greater than 20um / 20um; and the linewidth / spacing (L / S) of the lower surface of the first redistribution layer 101 is greater than 5um / 5um.

[0049] Solder balls 113 are disposed on the lower surface of the third conductive pad 110. Electrical connection between the semiconductor enclosure and external devices can be achieved through solder balls 113.

[0050] Further reference Figure 3 , Figure 3 This is a longitudinal cross-sectional structural schematic diagram of a third embodiment of a semiconductor packaging apparatus according to the present disclosure. Figure 3 The semiconductor packaging device shown is Figure 2 The semiconductor packaging devices shown are largely the same, except that... Figure 2 The first substrate 102 in the semiconductor packaging device shown is in Figure 3 In the semiconductor packaging device shown, a second wiring layer 114 is used instead. That is, the first bonding wire 105 not only electrically connects the first substrate 102 and the first wiring layer 101, but in different embodiments, the first bonding wire 105 can also electrically connect the first wiring layer 101 and the second wiring layer 114 to transmit electrical signals between them. Please note that... Figure 1 and Figure 2 The first substrate 102 and the semiconductor packaging device shown Figure 3 The semiconductor packaging device shown, which is covered by the second wiring layer 114, can be collectively referred to as the first structure.

[0051] Further reference Figure 4 , Figure 4 This is a longitudinal cross-sectional structural schematic diagram of a fourth embodiment of a semiconductor packaging apparatus according to the present disclosure. Figure 4 The semiconductor packaging device shown is Figure 2The semiconductor packaging device shown differs in that, in addition to the first adhesive layer 106, the first substrate 102, and the first protective layer 109 being disposed below the first redistribution layer 101, a second adhesive layer 106', a second substrate 102', and a second protective layer 109' are also disposed above the first redistribution layer 101. Similarly, the second adhesive layer 106' and the second substrate 102' have at least one opening to expose a portion of the first redistribution layer 101. A fourth conductive pad 103' is disposed on the upper surface of the first redistribution layer 101, a fifth conductive pad 104' is disposed on the upper surface of the second substrate 102', and a sixth conductive pad 110' is disposed on the upper surface of the second protective layer 109'. A fourth wire bonding 105' electrically connects a portion of the fourth conductive pad 103' and a portion of the fifth conductive pad 104'.

[0052] The technical effects achievable by the semiconductor packaging apparatus provided in the above embodiments of this disclosure include, but are not limited to: by using wire bonding to electrically connect the redistribution layer and the protective layer, and by covering the wires with the protective layer, the electrical connection between the two structures is more reliable, and the surface condition of the wires does not need to be considered. Furthermore, since the wire diameter is small, higher I / O density can be provided using wire bonding. Additionally, because the substrate has openings and the openings are filled with protective layer material, the difference in the overall coefficient of thermal expansion (CTE) of the semiconductor packaging apparatus is smaller, resulting in a more stable structure. Moreover, the semiconductor packaging apparatus has a simpler manufacturing process, lower cost, and higher yield.

[0053] The following is for reference. Figure 5A-5G , Figure 5A , 5B Figures 5C, 5D, 5E, 5F, and 5G are longitudinal cross-sectional structural diagrams of the semiconductor packaging apparatus according to the present disclosure at various manufacturing stages, thereby schematically illustrating the flow of the method for manufacturing the semiconductor packaging apparatus of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0054] refer to Figure 5A A carrier board 201 is provided, on which a seed layer 202 and a first redistribution layer 101 are sequentially formed, and a first conductive pad 103 is formed on the first redistribution layer 101.

[0055] refer to Figure 5B The pre-made first substrate 102 with openings is bonded to the first redistribution layer 101 through the first adhesive layer 106. The openings on the first substrate 102 expose a portion of the first redistribution layer 101. A second conductive pad 104 is provided on the first substrate 102.

[0056] In some alternative implementations, the first adhesive layer 106 may be omitted, and the first substrate 102 may be directly bonded to the first redistribution layer 101.

[0057] refer to Figure 5C A first bonding wire 105 is formed to electrically connect the first conductive pad 103 and the second conductive pad 104, thereby realizing the transmission of electrical signals between the first substrate 102 and the first redistribution layer 101.

[0058] refer to Figure 5D A first protective layer 109 is formed to cover the first substrate 102, the opening of the first substrate 102 and the first adhesive layer 106, and the first wire bonding 105.

[0059] refer to Figure 5E The first protective layer 109 is ground to expose the first bonding wire 105 and a portion of the first bonding wire 105 is ground off.

[0060] refer to Figure 5F A third conductive pad 110 is formed at the break point of the first bonding wire 105. Thus, a portion of the broken first bonding wire 105 electrically connects the first conductive pad 103 and the third conductive pad 110, and another portion electrically connects the second conductive pad 104 and the third conductive pad 110. The unbroken first bonding wire 105 continues to electrically connect the first conductive pad 103 and the second conductive pad 104.

[0061] refer to Figure 5G Remove carrier plate 201 and seed layer 202.

[0062] The manufacturing method of the semiconductor packaging device provided in this embodiment can achieve the corresponding technical effects of the semiconductor packaging device described above, and will not be repeated here.

[0063] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package device, comprising: a first redistribution layer; a first structure disposed below the first redistribution layer, wherein the first structure has an opening to expose a portion of the first redistribution layer; a first conductive pad disposed on a lower surface of the first redistribution layer; a second conductive pad disposed on a lower surface of the first structure; and a first wire electrically connecting the first conductive pad and the second conductive pad; an adhesive layer disposed between the first redistribution layer and the first structure, the adhesive layer being recessed within the first structure; a protective layer covering the first structure, the opening, and the first wire below the first structure; a third conductive pad disposed on a lower surface of the protective layer, a second wire electrically connecting the first conductive pad and the third conductive pad; and a third wire electrically connecting the second conductive pad and the third conductive pad; a solder ball disposed on a lower surface of the third conductive pad.

2. The semiconductor package device of claim 1, wherein, The first structure is a substrate.

3. The semiconductor package device of claim 2, wherein, The substrate contains glass fibers.

4. The semiconductor package device of claim 1, wherein, The first structure is a second redistribution layer.

5. The semiconductor package device of claim 1, further comprising: a second structure disposed above the first redistribution layer, wherein the second structure has an opening to expose a portion of the first redistribution layer; a fourth conductive pad disposed on an upper surface of the first redistribution layer; a fifth conductive pad disposed on an upper surface of the second structure; and a fourth wire electrically connecting the fourth conductive pad and the fifth conductive pad.

6. A method of manufacturing a semiconductor package device, comprising: providing a carrier, on which a seed layer and a first redistribution layer are sequentially formed, and a first conductive pad is formed on the first redistribution layer; adhering a first substrate having an opening to the first redistribution layer through a first adhesive layer, the opening of the first substrate exposing a portion of the first redistribution layer, the first substrate having a second conductive pad disposed thereon; forming a first wire to electrically connect the first conductive pad and the second conductive pad; forming a first protective layer to cover the first substrate, the opening of the first substrate and the first adhesive layer, and the first wire; polishing the first protective layer to expose the first wire and to break a portion of the first wire; forming a third conductive pad at a break point of the first wire, such that a portion of the first wire that is broken electrically connects the first conductive pad and the third conductive pad, another portion of the first wire that is broken electrically connects the second conductive pad and the third conductive pad, and the first wire that is not broken continues to electrically connect the first conductive pad and the second conductive pad; removing the carrier and the seed layer.

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