Method for manufacturing a semiconductor device and semiconductor device

Abstract

This application provides a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: providing a memory array structure; forming an amorphous silicon thin film on the surface of the memory array structure; forming a capping layer on the surface of the amorphous silicon thin film away from the memory array structure; and annealing the memory array structure with the capping layer to convert the amorphous silicon thin film into a polycrystalline silicon thin film. This method ensures that the obtained polycrystalline silicon thin film has good uniformity and flatness.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and a 3D NAND memory. Background Technology

[0002] In existing technologies, during the manufacturing process of 3D NAND, a laser annealing process is introduced to transform the surface A-Si (amorphous silicon) into polycrystalline silicon and generate GIDL (Gate-Induced Drain Leakage). However, the non-uniformity of laser energy and the crystallization characteristics of polycrystalline silicon in the laser annealing process result in poor surface uniformity and a rough texture in the obtained polycrystalline silicon.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a semiconductor device, a semiconductor device, and a 3D NAND memory, in order to solve the problem that the uniformity and roughness of the polycrystalline silicon layer obtained by converting an amorphous silicon layer into a polycrystalline silicon layer using laser annealing in the prior art are poor.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: providing a memory array structure; forming an amorphous silicon thin film on the surface of the memory array structure; forming a capping layer on the surface of the amorphous silicon thin film away from the memory array structure; and annealing the memory array structure on which the capping layer is formed, thereby converting the amorphous silicon thin film into a polycrystalline silicon thin film.

[0006] Optionally, annealing the memory array structure on which the capping layer is formed to convert the amorphous silicon thin film into a polycrystalline silicon thin film includes: annealing the amorphous silicon thin film by using a laser through the capping layer to convert the amorphous silicon thin film into the polycrystalline silicon thin film.

[0007] Optionally, the wavelength range of the laser is 300nm to 600nm.

[0008] Optionally, the thickness of the covering layer is greater than 40 nm and less than 50 nm.

[0009] Optionally, after annealing the memory array structure with the capping layer to convert the amorphous silicon thin film into a polycrystalline silicon thin film, the method further includes removing the capping layer.

[0010] Optionally, a memory array structure is provided, comprising: providing a substrate; forming a stacked structure on an exposed surface of the substrate, the stacked structure including a body structure and a channel via located in the body structure, the bottom of the channel via extending into the substrate, the body structure including alternating layers of insulating dielectric and sacrificial layers; and at least removing the substrate to expose the bottom of the channel via.

[0011] Optionally, forming an amorphous silicon thin film on the surface of the memory array structure includes: forming the amorphous silicon thin film on the surface of the memory array structure to cover the bottom of the exposed channel holes.

[0012] Optionally, the material of the coating layer includes oxides or nitrides.

[0013] According to another aspect of this application, a semiconductor device is also provided, said semiconductor device being manufactured using any of the methods described.

[0014] According to another aspect of this application, a 3D NAND memory is also provided, the 3D NAND memory including the aforementioned semiconductor device.

[0015] According to the technical solution of this application, the method for fabricating a semiconductor device first forms an amorphous silicon thin film on the surface of a memory array structure; then, a capping layer is formed on the surface of the amorphous silicon thin film away from the memory array structure, and annealing is performed to convert the amorphous silicon thin film into a polycrystalline silicon thin film. In the method of this application, before annealing the amorphous silicon thin film, a capping layer is formed on the surface of the amorphous silicon thin film. This capping layer can prevent the energy injected into the amorphous silicon thin film during annealing from diffusing into the air, thereby allowing energy to be uniformly conducted in the amorphous silicon thin film in a direction away from the capping layer (i.e., from top to bottom). Furthermore, the capping layer can promote heat exchange between different locations on the surface of the amorphous silicon thin film, resulting in a more uniform temperature distribution on the amorphous silicon surface, allowing the amorphous silicon thin film to crystallize uniformly into the polycrystalline silicon thin film, thus ensuring that the obtained polycrystalline silicon thin film is relatively uniform. Meanwhile, during the crystallization process of the amorphous silicon thin film, the formed grains will gradually increase in size. As two adjacent grains grow, a protrusion will form at the junction on the surface of the amorphous silicon thin film. This application forms a capping layer on the surface of the amorphous silicon thin film. The capping layer can form pressure on the surface of the amorphous silicon layer to effectively avoid the formation of protrusions, thereby avoiding the problem of a relatively rough surface of the obtained polycrystalline silicon layer. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown.

[0018] Figures 2 to 6 The diagrams show the structural schematics obtained after each process step of the semiconductor device fabrication method according to embodiments of this application.

[0019] The above figures include the following reference numerals:

[0020] 10. Memory array structure; 20. Amorphous silicon thin film; 30. Capping layer; 40. Polycrystalline silicon thin film; 100. Insulating dielectric layer; 101. Sacrificial layer; 102. Charge blocking layer; 103. Electron trapping layer; 104. Tunneling layer; 105. Channel layer; 106. Filling material; 107. Dielectric layer. Detailed Implementation

[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0022] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0026] As described in the background section, the existing technology uses laser annealing to convert amorphous silicon layers into polycrystalline silicon layers, resulting in polycrystalline silicon layers with poor uniformity and roughness. In order to solve the above problems, this application proposes a method for fabricating a semiconductor device, a semiconductor device, and a 3D NAND memory.

[0027] According to a typical embodiment of this application, a method for fabricating a semiconductor device is provided, such as... Figure 1 As shown, the above method includes the following steps:

[0028] Step S101, provide as follows Figure 2 The storage array structure 10 shown is shown.

[0029] Step S102: An amorphous silicon thin film 20 is formed on the surface of the above-mentioned memory array structure 10 to obtain... Figure 3 The structure shown;

[0030] Step S103, as follows Figure 4 As shown, a capping layer 30 is formed on the surface of the amorphous silicon thin film 20 that is away from the memory array structure 10.

[0031] Step S104: The memory array structure 10 with the aforementioned capping layer 30 is annealed to convert the amorphous silicon thin film 20 into a polycrystalline silicon thin film 40, resulting in... Figure 5 The structure shown.

[0032] The aforementioned semiconductor device fabrication method first forms an amorphous silicon thin film on the surface of a memory array structure; then, a capping layer is formed on the surface of the amorphous silicon thin film away from the memory array structure, and annealing is performed to convert the amorphous silicon thin film into a polycrystalline silicon thin film. In the method of this application, a capping layer is formed on the surface of the amorphous silicon thin film before annealing. This capping layer prevents energy injected into the amorphous silicon thin film during annealing from diffusing into the air, allowing energy to be uniformly conducted in the amorphous silicon thin film in a direction away from the capping layer (i.e., from top to bottom). Furthermore, the capping layer promotes heat exchange between different locations on the surface of the amorphous silicon thin film, resulting in a more uniform temperature distribution on the amorphous silicon surface. This allows the amorphous silicon thin film to crystallize uniformly into the polycrystalline silicon thin film, ensuring a more uniform polycrystalline silicon thin film. Meanwhile, during the crystallization process of the aforementioned amorphous silicon thin film, the formed grains gradually increase in size. As two adjacent grains grow, a protrusion will form at the junction on the surface of the amorphous silicon thin film. This application forms a capping layer on the surface of the aforementioned amorphous silicon thin film. The capping layer can form pressure on the surface of the amorphous silicon layer to effectively prevent the formation of protrusions, thereby avoiding the problem of a relatively rough surface of the obtained polycrystalline silicon layer.

[0033] Specifically, in the process of converting the aforementioned amorphous silicon thin film into a polycrystalline silicon thin film, the amorphous silicon thin film first absorbs heat to transform into liquid silicon, and then the liquid silicon solidifies into solid silicon. The density of the liquid silicon is 2.42 g / cm³. 3 The density of the aforementioned solid silicon is 2.33 g / cm³. 3 During the solidification process, the volume expands, pushing the liquid to expand between the two grains, resulting in a relatively rough surface of the polycrystalline silicon film after crystallization. By forming the covering layer on the surface of the amorphous silicon film, the expansion can be suppressed, ensuring that the surface of the formed polycrystalline silicon film is relatively smooth, thereby ensuring that the quality of the polycrystalline silicon film is good.

[0034] Furthermore, in the above-described method of this application, the covering layer can reduce the heat generated during the annealing process from dissipating into the air, thus playing a role in heat insulation and slowing down the temperature drop rate of the amorphous silicon film, thereby ensuring a faster growth rate of the polycrystalline silicon and a higher efficiency in converting the amorphous silicon film into the polycrystalline silicon film.

[0035] According to a specific embodiment of this application, the memory array structure with the aforementioned capping layer is annealed to convert the amorphous silicon thin film into a polycrystalline silicon thin film. This includes annealing the amorphous silicon thin film by using a laser to penetrate the capping layer, thereby converting the amorphous silicon thin film into a polycrystalline silicon thin film. In the prior art, when a laser is directly injected onto the surface of an amorphous silicon thin film, the temperature at different locations on the amorphous silicon surface is uneven due to the non-uniformity of the laser. When a capping layer is present, the laser penetrates the capping layer to anneal the amorphous silicon thin film, thus further ensuring heat exchange between different locations on the surface of the amorphous silicon thin film, further ensuring a relatively uniform temperature distribution within the amorphous silicon thin film, thereby further ensuring better uniformity of the resulting polycrystalline silicon thin film, and further avoiding surface protrusion problems caused by grain expansion during the crystallization process of the amorphous silicon thin film, further ensuring better surface quality of the polycrystalline silicon thin film.

[0036] In practical applications, those skilled in the art can use any feasible laser annealing process in the prior art to perform laser annealing on the above intermediate structure, such as excimer laser annealing or solid-state laser annealing.

[0037] To further ensure conversion efficiency and quality, in one specific embodiment, the wavelength range of the laser is 300nm to 600nm. Preferably, the wavelength of the laser is 527nm.

[0038] In practical applications, if the thickness of the aforementioned cover layer is too thick, voids will form at the contact surface between the cover layer and the amorphous silicon thin film, resulting in defects. If the thickness of the aforementioned cover layer is too thin, most of the laser energy will not reach the aforementioned amorphous silicon thin film and will be absorbed by the aforementioned amorphous silicon thin film. Instead, it will enter the memory array structure through the aforementioned amorphous silicon thin film, resulting in defects. In order to avoid the occurrence of the aforementioned defects, according to another specific embodiment of this application, the thickness of the aforementioned cover layer is greater than 40 nm and less than 50 nm.

[0039] In another specific embodiment of this application, after annealing the memory array structure with the aforementioned capping layer to convert the amorphous silicon thin film into a polycrystalline silicon thin film, the method further includes: removing the capping layer 30 to obtain... Figure 6 The structure is shown. Specifically, those skilled in the art can choose any feasible removal process from the prior art to remove the aforementioned covering layer.

[0040] According to another specific embodiment of this application, a memory array structure is provided, comprising: providing a substrate; forming a stacked structure on an exposed surface of the substrate, the stacked structure including a body structure and a channel via located in the body structure, the bottom of the channel via penetrating into the substrate, the body structure including alternating layers of insulating dielectric and sacrificial layers; at least removing the substrate to expose the bottom of the channel via. Forming an amorphous silicon thin film on the surface of the memory array structure includes: forming the amorphous silicon thin film on the surface of the memory array structure to cover the exposed bottom of the channel via.

[0041] In practical applications, the above-mentioned memory array structure also includes a dielectric layer. After providing the substrate, before forming a stacked structure on the exposed surface of the substrate, the method further includes: forming the dielectric layer on the exposed surface of the substrate, and forming a stacked structure on the exposed surface of the substrate, including: forming the stacked structure on the surface of the dielectric layer away from the substrate, and the channel hole penetrates the dielectric layer into the substrate.

[0042] Specifically, such as Figure 2 As shown, a stacked structure is formed on the exposed surface of the substrate, including: alternately stacking an insulating dielectric layer 100 and a sacrificial layer 101 on the surface of the dielectric layer 107 away from the substrate to obtain a body structure; etching the body structure to form a pre-existing channel hole penetrating into the substrate; sequentially disposing a pre-existing charge blocking layer, a pre-existing electron trapping layer, a pre-existing tunneling layer, and a channel layer 105 in the pre-existing channel hole, wherein the pre-existing charge blocking layer is an oxide layer, the pre-existing electron trapping layer is a nitride layer, the pre-existing tunneling layer is an oxide layer, and the channel layer is an amorphous silicon layer; depositing a filling material 106 in the remaining pre-existing channel holes to obtain the channel holes, wherein the filling material includes silicon oxide.

[0043] At least the substrate is removed to expose the bottom of the channel via, including: removing the substrate to expose the dielectric layer 107 and a portion of the pre-charge blocking layer; removing the exposed pre-charge blocking layer to expose a portion of the electron trapping layer, with the remaining pre-charge blocking layer forming a charge blocking layer 102; removing the exposed pre-electron trapping layer to expose a portion of the pre-tunneling layer, with the remaining pre-electron trapping layer forming an electron trapping layer 103; and removing the exposed pre-tunneling layer to expose a portion of the channel layer 105, with the remaining pre-tunneling layer forming a tunneling layer 104.

[0044] An amorphous silicon thin film is formed on the surface of the above-mentioned memory array structure, including: such as Figure 3As shown, the amorphous silicon thin film 20 is formed on the exposed surfaces of the dielectric layer 107 and the channel layer 105.

[0045] The presence of the aforementioned capping layer in this application enables the energy of the laser to be conducted downwards along the amorphous silicon thin film, with some energy being conducted to the channel hole. This allows the doped amorphous silicon channel layer formed in the channel hole due to ion implantation disrupting the crystal lattice to be converted into a doped polycrystalline silicon channel layer, thereby effectively promoting the activation of GIDL (gate-induced drain leakage).

[0046] In practical applications, those skilled in the art can use any suitable method in the prior art to grow the dielectric layer on the surface of the substrate, such as plasma glow discharge, photoinduced chemical vapor deposition, hot filament catalytic chemical vapor deposition, or physical vapor deposition.

[0047] Those skilled in the art can choose any suitable material from the prior art as the material for the aforementioned capping layer. In one specific embodiment, the material of the capping layer includes oxides or nitrides. In a more specific embodiment, the capping layer is an oxide layer or a nitride layer. The oxide layer or the nitride layer further avoids the problems of poor uniformity and rough surface of the obtained polycrystalline silicon film, further ensuring the better quality of the polycrystalline silicon film.

[0048] In practical applications, those skilled in the art can choose any suitable material as the oxide layer. In one specific embodiment of this application, the material of the oxide layer includes silicon oxide. In a more specific embodiment of this application, the material of the oxide layer is silicon oxide.

[0049] In practical applications, those skilled in the art can choose any suitable material as the aforementioned nitriding layer. In one specific embodiment of this application, the material of the aforementioned nitriding layer includes silicon nitride. In a more specific embodiment of this application, the material of the aforementioned nitriding layer is silicon nitride.

[0050] According to another typical embodiment of this application, a semiconductor device is also provided, which is manufactured using any of the methods described above.

[0051] The aforementioned semiconductor device is a semiconductor device fabricated using any of the methods described above. In the aforementioned methods, before annealing the amorphous silicon thin film, a capping layer is first formed on the surface of the amorphous silicon thin film. The capping layer can prevent the energy injected into the amorphous silicon thin film during the annealing process from diffusing into the air, thereby allowing the energy to be uniformly conducted in the amorphous silicon thin film in a direction away from the capping layer (i.e., from top to bottom). Furthermore, the capping layer can promote heat exchange between different locations on the surface of the amorphous silicon thin film, thereby making the temperature distribution on the amorphous silicon surface more uniform, and allowing the amorphous silicon thin film to crystallize uniformly into the polycrystalline silicon thin film, thereby ensuring that the obtained polycrystalline silicon thin film is more uniform. Meanwhile, during the crystallization process of the aforementioned amorphous silicon thin film, the formed grains gradually increase in size. As two adjacent grains grow, a protrusion will form at the junction on the surface of the amorphous silicon thin film. This application forms a capping layer on the surface of the aforementioned amorphous silicon thin film. The capping layer can form pressure on the surface of the amorphous silicon layer to effectively prevent the formation of protrusions, thereby avoiding the problem of a relatively rough surface of the obtained polycrystalline silicon layer, thus ensuring that the polycrystalline silicon thin film in the aforementioned semiconductor device has good quality.

[0052] According to another typical embodiment of this application, a 3D NAND memory is also provided, which includes the semiconductor device described above.

[0053] The aforementioned 3D NAND memory includes the aforementioned semiconductor device, which is manufactured using the aforementioned method. The aforementioned method ensures good uniformity of the polycrystalline silicon thin film in the aforementioned semiconductor device and alleviates the problem of relatively rough polycrystalline silicon thin film, thereby ensuring good quality of the aforementioned 3D NAND memory.

[0054] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0055] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0056] In the description of this invention, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this invention; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0057] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0058] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0059] 1) The method for fabricating the semiconductor device described in this application first forms an amorphous silicon thin film on the surface of a memory array structure; then, a capping layer is formed on the surface of the amorphous silicon thin film away from the memory array structure, and annealing is performed to convert the amorphous silicon thin film into a polycrystalline silicon thin film. In the method described in this application, a capping layer is formed on the surface of the amorphous silicon thin film before annealing. This capping layer prevents energy injected into the amorphous silicon thin film during annealing from diffusing into the air, thereby allowing energy to be uniformly conducted in the amorphous silicon thin film in a direction away from the capping layer (i.e., from top to bottom). Furthermore, the capping layer promotes heat exchange between different locations on the surface of the amorphous silicon thin film, resulting in a more uniform temperature distribution on the amorphous silicon surface. This allows the amorphous silicon thin film to crystallize uniformly into the polycrystalline silicon thin film, ensuring a more uniform polycrystalline silicon thin film. Meanwhile, during the crystallization process of the aforementioned amorphous silicon thin film, the formed grains gradually increase in size. As two adjacent grains grow, a protrusion will form at the junction on the surface of the amorphous silicon thin film. This application forms a capping layer on the surface of the aforementioned amorphous silicon thin film. The capping layer can form pressure on the surface of the amorphous silicon layer to effectively prevent the formation of protrusions, thereby avoiding the problem of a relatively rough surface of the obtained polycrystalline silicon layer.

[0060] 2) The semiconductor device described in this application is a semiconductor device manufactured using any of the methods described above. In the above methods, before annealing the amorphous silicon thin film, a capping layer is first formed on the surface of the amorphous silicon thin film. The capping layer can prevent the energy injected into the amorphous silicon thin film during the annealing process from diffusing into the air, thereby allowing the energy to be uniformly conducted in the amorphous silicon thin film in a direction away from the capping layer (i.e., from top to bottom). Furthermore, the capping layer can promote heat exchange between different locations on the surface of the amorphous silicon thin film, thereby making the temperature distribution on the surface of the amorphous silicon more uniform, and making the amorphous silicon thin film uniformly crystallize into the polycrystalline silicon thin film, thereby ensuring that the obtained polycrystalline silicon thin film is more uniform. Meanwhile, during the crystallization process of the aforementioned amorphous silicon thin film, the formed grains gradually increase in size. As two adjacent grains grow, a protrusion will form at the junction on the surface of the amorphous silicon thin film. This application forms a capping layer on the surface of the aforementioned amorphous silicon thin film. The capping layer can form pressure on the surface of the amorphous silicon layer to effectively prevent the formation of protrusions, thereby avoiding the problem of a relatively rough surface of the obtained polycrystalline silicon layer, thus ensuring that the polycrystalline silicon thin film in the aforementioned semiconductor device has good quality.

[0061] 3) The 3D NAND memory described in this application includes the semiconductor device described above. The semiconductor device is formed by the method described above. The method ensures that the polysilicon thin film in the semiconductor device has good uniformity and alleviates the problem of the polysilicon thin film being relatively rough, thus ensuring that the 3D NAND memory has good quality.

[0062] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provides storage array architecture; An amorphous silicon thin film is formed on the surface of the memory array structure; A capping layer is formed on the surface of the amorphous silicon thin film away from the memory array structure. The material of the capping layer includes oxides or nitrides, and the thickness of the capping layer is greater than 40 nm and less than 50 nm. The memory array structure with the covering layer is subjected to laser annealing to convert the amorphous silicon thin film into a polycrystalline silicon thin film.

2. The method according to claim 1, characterized in that, Annealing the memory array structure with the capping layer formed thereon to convert the amorphous silicon thin film into a polycrystalline silicon thin film includes: The amorphous silicon film is annealed by using a laser through the capping layer, so that the amorphous silicon film is converted into the polycrystalline silicon film.

3. The method according to claim 2, characterized in that, The wavelength range of the laser is 300nm~600nm.

4. The method according to claim 1, characterized in that, After annealing the memory array structure with the capping layer to convert the amorphous silicon thin film into a polycrystalline silicon thin film, the method further includes: Remove the overlay.

5. The method according to claim 1, characterized in that, Provides storage array architecture, including: Provide substrate; A stacked structure is formed on the exposed surface of the substrate. The stacked structure includes a body structure and a channel hole located in the body structure. The bottom of the channel hole extends into the substrate. The body structure includes alternating layers of insulating dielectric and sacrificial layers. At least the substrate is removed so that the bottom of the channel hole is exposed.

6. The method according to claim 5, characterized in that, Forming an amorphous silicon thin film on the surface of the memory array structure includes: The amorphous silicon thin film is formed on the surface of the memory array structure to cover the bottom of the exposed channel holes.

7. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 6.

8. A 3D NAND memory, characterized in that, The 3D NAND memory includes the semiconductor device as described in claim 7.

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