Neural network memory

Abstract

In an example, a device may include: an array of variable resistance memory cells; and a neural memory controller coupled to the array of variable resistance memory cells and configured to: apply a subthreshold voltage pulse to a variable resistance memory cell of the array to cause a threshold voltage of the variable resistance memory cell to change in an analog manner from a voltage associated with a reset state to achieve a first synaptic weight change; and apply additional subthreshold voltage pulses to the variable resistance memory cell to achieve each subsequent synaptic weight change.

Description

Technical Field

[0001] The present disclosure generally relates to operating devices such as memories, and more particularly, the present disclosure relates to neural network memories. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are various types of memories including volatile and non-volatile memories.

[0003] Various memory arrays can be organized in a cross-point architecture where memory cells (e.g., two-terminal cells) are located at the intersection of a first signal line and a second signal line for accessing the cell (e.g., at the intersection of a word line and a sense line). For example, some memory cells can be resistive variable memory cells whose logical state (e.g., storing a data value) depends on the programmed resistance of the memory cell. Some variable resistance memory cells (which can be referred to as self-selecting memory cells) include a single material that can serve as both a selection element and a storage element of the memory cell. Brief Description of the Drawings

[0004] Figure 1 Illustrate examples of devices in the form of a memory array of a memory device according to various embodiments of the present disclosure.

[0005] Figure 2 Illustrate examples of a memory array supporting a neural network memory according to an embodiment of the present disclosure.

[0006] Figure 3 Illustrate examples of a memory array supporting a neural network memory according to an embodiment of the present disclosure.

[0007] Figure 4 Illustrate an example graph of the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure.

[0008] Figure 5 Illustrate an example graph of the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure.

[0009] Figure 6 Illustrate an example method for using a neural network memory of a memory device according to an embodiment of the present disclosure.

[0010] Figure 7 Illustrate an example method for using a neural network memory of a memory device according to an embodiment of the present disclosure. Detailed Description

[0011] In a neural network, synaptic weights can refer to the strength or amplitude of the connection between two nodes (such as neurons). The nature and content of the information transmitted through the neural network can be partially based on the nature of the synapses (such as synaptic weights) formed between the nodes. A memory array can be operated as a neural network memory (such as a neuromorphic system and device) and can be designed to achieve results that cannot be achieved by traditional computer architectures. For example, a neuromorphic system can be used to achieve more results associated with biological systems such as learning, vision or visual processing, auditory processing, advanced computing, or other processes or combinations thereof.

[0012] This disclosure describes systems, devices, apparatuses, and methods configured to simulate neurobiological architectures and / or store synaptic weights that may exist in a nervous system. In an example, a device can include an array of variable resistance memory cells and a neural memory cell controller coupled to the array of variable resistance memory cells. The neural memory cell controller can be configured to: apply a subthreshold voltage pulse to the variable resistance memory cells of the array to cause the threshold voltage of the variable resistance memory cells to change in an analog manner from a voltage associated with a reset state to achieve a first synaptic weight change; and apply additional subthreshold voltage pulses to the variable resistance memory cells to achieve each subsequent synaptic weight change.

[0013] As used herein, "a" or "one or more" can mean one or more of something, and "a plurality" can mean two or more of such things. For example, a memory device can mean one or more memory devices, and a plurality of memory devices can mean two or more memory devices. Additionally, as used herein, the identifiers "M", "P", "R", "B", "S", and "N" (especially in relation to reference element symbols in the figures) indicate that the number of the particular feature so labeled can be included in several embodiments of the present disclosure. The numbers between the labels can be the same or different.

[0014] The figures herein follow a numbering convention in which the first or first few digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, 101 can refer to Figure 1 element "01" in Figure 2 and a similar element can be referred to as

[0015] Figure 1 An example of a device in the form of a memory array of a memory device according to various embodiments of the present disclosure is illustrated. As used herein, "device" can mean (but is not limited to) any one of various structures or combinations of structures, such as (for example) a circuit or circuitry, one or more die, one or more modules, one or more apparatuses, or one or more systems. Figure 1It is an explanatory diagram of various components and features of the memory device 100. Thus, it should be understood that the components and features of the memory device 100 are shown to illustrate the functional interrelationships, rather than their actual physical locations within the memory device 100.

[0016] Although Figure 1 some of the elements included in

[0017] are marked with numerical indicators, other corresponding elements are not marked, but they are the same or should be understood as similar, for the purpose of enhancing the visibility and clarity of the depicted features. Figure 1 In an illustrative example of

[0018] the memory device 100 includes a memory array 101. The memory array 101 includes memory cells 105 that can be programmed to different logic states. In some embodiments, each memory cell 105 can be programmed to two states represented as logic 0 and logic 1. In some embodiments, the memory cells 105 can be programmed to more than two logic states. In some embodiments, the memory cells 105 can include variable resistance memory cells, such as self-selecting memory cells. A self-selecting memory cell is a memory cell that includes a single chalcogenide material that operates as both a selection component and a storage component.

[0019] As will be further described herein, the variable resistance memory cells can be self-selecting memory cells and can be arranged in an array (such as a neural memory cell) to emulate neurobiological functions, such as learning. The self-selecting memory cell includes a chalcogenide material that can change the logic state (such as set or reset) of the chalcogenide material in an amorphous state in response to a voltage magnitude. The set state can be conductive (such as a low current resistance) and the reset state can be non-conductive (such as a higher current resistance). The state change of the chalcogenide between the set state and the reset state can analogously change the threshold voltage value of the self-selecting memory cell. The analog threshold voltage change of the chalcogenide material of the self-selecting memory cell can represent synaptic weights in a neuromorphic memory system. The change of synaptic weights can represent and / or be interpreted as representing learning and other biological functions. Figure 1not described in order not to obscure the examples of the present disclosure, but the memory array 101 may include a substrate (as described herein in connection with Figure 2 further description).

[0020] Generally, a memory cell 105 may be located at the intersection of two signal lines (e.g., access line 110 and sense line 115). For example, memory cell 105 is located at the intersection of access line 110-1 and sense line 115-S. This intersection may be referred to as the address of memory cell 105. The target memory cell 105 may be a memory cell 105 located at the intersection of an energized (e.g., activated) access line 110 and an energized (e.g., activated) sense line 115; that is, both the access line 110 and the sense line 115 may be energized to read from or write to the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication (e.g., connected to the same access line 110 or sense line 115) with the same access line 110 or sense line 115 may be referred to as non-target memory cells 105.

[0021] In some cases, an electrode may couple the memory cell 105 to the access line 110 or the sense line 115. As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may be used as an electrical contact to other components of the memory cell or memory array. The electrode may include a trace, wire, conductive wire, conductive layer, or the like that provides a conductive path between elements or components of the memory array 101 of the memory device 100. Thus, the term "electrode" may, in some cases, refer to an access line (e.g., access line 110) or a sense line (e.g., sense line 115), and in some cases, refers to an additional conductive element that serves as an electrical contact between the access line and the memory cell 105.

[0022] In some embodiments, the memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. The first electrode may couple the chalcogenide material to the access line 110, and the second electrode may couple the chalcogenide material to the sense line 115. The first electrode and the second electrode may be the same material (e.g., carbon) or different materials. In other embodiments, the memory cell 105 may be directly coupled to one or more access lines, and electrodes other than the access lines may be omitted.

[0023] The chalcogenide material can be a material or alloy containing at least one of the elements S, Se, and Te. The chalcogenide material can include alloys of each of the following: S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Examples of chalcogenide materials and alloys can include (but are not limited to) Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. As used herein, chemical composition symbols connected by hyphens indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometries involving the indicated elements. For example, Ge-Te can include Ge x Te y , where x and y can be any positive integers. Other examples of variable resistance materials can include binary metal oxide materials or mixed valence oxides containing two or more metals (such as transition metals, alkaline earth metals) and / or rare earth metals. The examples are not limited to one or several specific variable resistance materials associated with the memory elements of the memory unit. For example, other examples of variable resistance materials can be used to form memory elements and can include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, and so on.

[0024] Operations such as reading and writing can be performed on the memory unit 105 by activating or selecting the access line 110 and the sense line 115. Activating or selecting the access line 110 or the sense line 115 can include applying a voltage to the corresponding line. The access line 110 and the sense line 115 can be made of a conductive material such as each of the following: metal (such as copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloy, carbon, conductive doped semiconductor, or other conductive materials, alloys, compounds, or the like.

[0025] In some architectures, the logical storage devices of the cells (e.g., the resistive components in CBRAM cells, the capacitive components in FeRAM cells) can be electrically isolated from the sense lines by select components. The access line 110 can be connected to and can control the select components. For example, the select component can be a transistor and the access line 110 can be connected to the gate of the transistor.

[0026] As mentioned, the select component can be the variable resistive component of a variable resistive memory cell, which can include a chalcogenide material. Specifically, the variable resistive memory cell can be a self-selecting memory cell, which includes a single material (e.g., a chalcogenide material) that can serve as both the select element and the storage element of the memory cell. Activating the access line 110 can cause an electrical connection or a closed circuit between the logical storage device of the memory cell 105 and its corresponding sense line 115. Then, the sense line can be accessed to read or write to the memory cell 105. After selecting the memory cell 105, the resulting signal can be used to determine the stored logical state. In some cases, the first logical state can correspond to no current or a negligibly small current passing through the memory cell 105, while the second logical state can correspond to a finite current. In some cases, the memory cell 105 can include a two-terminal self-selecting memory cell, and a separate select component can be omitted. Thus, one terminal of the self-selecting memory cell can be electrically connected to the access line 110 and the other terminal of the self-selecting memory cell can be electrically connected to the sense line 115.

[0027] Access to the memory cell 105 can be controlled by the row decoder 120 and the column decoder 130. For example, the row decoder 120 can receive a row address from the memory controller 140 and activate the appropriate access line 110 based on the received row address. Similarly, the column decoder 130 can receive a column address from the memory controller 140 and activate the appropriate sense line 115. For example, the memory array 101 can include multiple access lines 110-1, 110-2, and 110-N and multiple sense lines 115-1, 115-2, and 115-S, where S and N depend on the array size. Thus, the memory cell 105 at the intersection can be accessed by activating the access line 110 and the sense line 115 (e.g., 110-1 and sense line 115-S).

[0028] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the programming state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding access line 110 and sense line 115), and the presence of the resulting current through the memory cell 105 can depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not result in a current, other voltages can be applied until a current is detected by the sensing component 125. The logical state of the memory cell 105 can be determined by evaluating the voltage that results in a current. In some cases, the magnitude of the voltage can be ramped up until a current is detected. In other cases, a predetermined voltage can be applied sequentially until a current is detected. Similarly, a current can be applied to the memory cell 105, and the magnitude of the voltage used to generate the current can depend on the resistance or threshold voltage of the memory cell 105.

[0029] The memory cell 105 (such as a variable resistance memory cell and / or a self-selective memory cell) can include a chalcogenide material. The chalcogenide material of the memory cell can remain amorphous during an access operation. In some cases, operating the memory cell can include applying programming pulses of various shapes to the memory cell to determine a specific threshold voltage of the memory cell, i.e., the threshold voltage of the memory cell can be modified by changing the shape of the programming pulse.

[0030] The specific threshold voltage of the memory cell 105 (such as a variable resistance memory cell and / or a self-selective memory cell) can be determined by applying reading pulses of various shapes to the memory cell. For example, when the applied voltage of the reading pulse exceeds the specific threshold voltage of the memory cell, a limited amount of current can flow through the memory cell. Similarly, when the applied voltage of the reading pulse is less than the specific threshold voltage of the memory cell, no appreciable amount of current can flow through the memory cell.

[0031] In some of the examples described herein where the memory cell is a variable resistance memory cell (such as a self-selective memory cell), applying a reading pulse (such as a sub-threshold voltage) that is less than the threshold voltage of the memory cell can change the threshold voltage of the memory cell 105 in an analog manner. In other words, the initial threshold voltage of the variable resistance memory cell can change incrementally (e.g., in an analog manner) in response to having been pulsed below the initial threshold voltage (pulsed with a sub-threshold voltage). This change in the threshold voltage can be in response to the chalcogenide material of the variable resistance memory cell being altered.

[0032] In some embodiments, the sensing component 125 can read the information stored in the memory cell 105 by detecting the presence or absence of current flowing through a selected memory cell 105. In this way, the memory cell 105 (such as a variable resistance memory cell and / or a self-selecting memory cell) can store one data bit based on a threshold voltage level (such as two threshold voltage levels) associated with a chalcogenide material, where the threshold voltage level that allows current to flow through the memory cell 105 indicates the logic state stored by the memory cell 105. In some cases, the memory cell 105 can exhibit a specific number of different threshold voltage levels (such as three or more threshold voltage levels) to thereby store more than one data bit.

[0033] The sensing component 125 can include various transistors or amplifiers to detect and amplify the difference in the signal associated with the sensed memory cell 105, which can be referred to as latching. Then, the detected logic state of the memory cell 105 can be output as an output 135 by the column decoder 130. In some cases, the sensing component 125 can be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 can be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Those of ordinary skill in the art will understand that the sensing component 125 can be associated with a column decoder or a row decoder without losing its functional use.

[0034] One or more of the transistors discussed herein can represent a field effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by a conductive material (such as metal). The source and the drain can be conductive and can include heavily doped (such as degenerate) semiconductor regions. The source and the drain can be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET can be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be called a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET respectively can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0035] The memory cell 105 can be set or written by similarly activating the associated access line 110 and sensing line 115, and at least one logic value can be stored in the memory cell 105. The column decoder 130 or the row decoder 120 can accept the data written to the memory cell 105, such as the input / output 135.

[0036] In some memory architectures, accessing a memory cell 105 can degrade or corrupt the logic state, or a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105. For example, in DRAM, the capacitor can partially or fully discharge during a sense operation to corrupt the logic state, so the logic state can be rewritten after the sense operation. Additionally, in some memory architectures, activating an access line 110 can cause all the memory cells in a row (e.g., coupled to the access line 110) to discharge; thus, it is necessary to rewrite some or all of the memory cells 105 in the row. However, in non-volatile memories such as resistive random access memory (RRAM) cells, self-selecting memory cells, and / or phase change memory (PCM) memories, accessing the memory cell 105 does not corrupt the logic state, and thus, the memory cell 105 does not need to be rewritten after access.

[0037] A memory controller 140 (e.g., a neuromorphic memory cell controller) can control the operations (e.g., read, write, rewrite, refresh, discharge) of the memory cells 105 through various components (e.g., a row decoder 120, a column decoder 130, and a sense component 125). In some cases, one or more of the row decoder 120, the column decoder 130, and the sense component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals to activate the desired access lines 110 and sense lines 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100. Generally, the amplitude, shape, polarity, and / or duration of the applied voltage or current discussed herein can be adjusted or varied and can be different for the various operations discussed in operating the memory device 100. Additionally, one, multiple, or all of the memory cells 105 within the memory array 101 can be accessed simultaneously; for example, multiple or all of the cells of the memory array 101 can be accessed simultaneously during a reset operation, in which all of the memory cells 105 or groups of memory cells 105 are set to a single logic state.

[0038] The various memory cells 105 of the memory device 100 may be grouped into memory cells configured to store analog values (e.g., neural memory cells). The memory controller 140 may be coupled to the neural memory cells and is referred to as a neural memory cell controller. The neural memory cells may be configured to emulate a neural biological architecture. The neural memory cells may utilize the properties of a chalcogenide material within the memory cell to change the properties of the chalcogenide material. The changed properties of the chalcogenide material may change the threshold voltage of the memory cell, and this operation may be referred to as the memory cell "storing" an analog value, as an example value. The analog value of the neural memory cell and / or multiple analog values of the memory cells of the neural memory cell may be interpreted as the learning result in the neural memory cell. An external host and / or a part or the whole of the memory device 100 may generate and / or receive a learning algorithm. The learning algorithm is an algorithm that can be used in machine learning to help the neural memory cells emulate (e.g., simulate, imitate, etc.) a neural biological architecture.

[0039] The learning algorithm may include variables of learning events. The learning event may be a certain number of pulses of a voltage value, the magnitude of a voltage value (e.g., supra-threshold or sub-threshold voltage), and / or the duration of applying a pulse to the memory cells of the neural memory cell (e.g., variable resistance memory cells). The neural memory cell controller (e.g., the memory controller 140) may apply the learning algorithm to the array to attempt to detect learning events from the variable resistance memory cells of the neural memory cell.

[0040] As mentioned, the neural memory cell controller (e.g., the memory controller 140) may be configured to apply a learning algorithm that includes learning events. For example, the neural memory cell controller may apply a certain number of sub-threshold voltage pulses to change a single chalcogenide material of a self-selecting memory cell (e.g., the memory cell 105) in an amorphous condition associated with a reset state to a condition associated with a set state. In other words, the chalcogenide material of the self-selecting memory cell may move between two electrical states in response to the sub-threshold voltage pulses.

[0041] A neural memory cell controller, such as memory controller 140, may apply iterations of a learning algorithm by applying sub-threshold voltage pulses to a resistive memory cell. The threshold voltage of the cell may change in an analog manner in response to the sub-threshold voltage pulses applied to the resistive memory cell. Each threshold voltage pulse may change the synaptic weight of the resistive memory cell (e.g., increase or decrease). The increase and / or decrease of the synaptic weight may indicate whether learning has occurred in the neural memory cell. The neural memory cell controller may monitor the neural memory cell to determine when additional sub-threshold pulses may be applied based on the synaptic weight. For example, the neural memory cell controller may refrain from applying additional sub-threshold voltage pulses in response to the learning algorithm indicating that no additional learning has occurred (e.g., the threshold voltage has not changed or increased).

[0042] In some embodiments, the neural memory cell controller may vary the sub-threshold voltage pulses in response to the degree of learning. For example, the neural memory cell controller may apply additional sub-threshold voltage pulses as relatively long pulses to the resistive memory cell when an indication of relatively strong learning occurs (e.g., the threshold voltage of the resistive memory cells of the array decreases). Individually or in combination, the neural memory cell controller may increase (or decrease) the number of sub-threshold voltage pulses in response to the degree to which learning has occurred. The neural memory cell may be configured to monitor the degree of learning (e.g., the changing synaptic weights of the resistive memory cells of the array) and adjust variables of the learning algorithm (e.g., learning events).

[0043] Figure 2 An example of a memory array 201 that supports a neural network memory in accordance with embodiments of the present disclosure is illustrated. The memory array 201 may be an example of a portion of the memory array 101 described in reference Figure 1 The memory array 201 may include memory cells 205 positioned above a substrate 204. The memory array 201 may also include access lines 210-1 and 210-2 and sense lines 215-1 and 215-2, which may be examples of the access lines 110 and sense lines 115 described in reference Figure 1 As in the illustrative example depicted in Figure 2 The memory cells 205 may be self-selecting memory cells. Although some of the elements included in Figure 2 are marked with numerical designators, other corresponding elements are not marked, but are the same or should be understood to be similar, for the purpose of enhancing the visibility and clarity of the depicted features.

[0044] In some instances, the memory cells 205 may be self-selecting memory cells and may include a first electrode 211, a chalcogenide material 213, and a second electrode 217. In some embodiments, signal lines (e.g., Figure 1The access lines 110 and sense lines 115) may include an electrode layer (e.g., a conformal layer) instead of electrodes 211 or 217 and may thus include multiple layers of access lines. In such embodiments, the electrode layer of the signal line may interface with a memory material (e.g., a chalcogenide material 213). In some embodiments, the signal lines (e.g., access lines 110, sense lines 115) may interface directly with the memory material (e.g., a chalcogenide material 213) without an intervening electrode layer or electrode.

[0045] In some cases, the architecture of the memory array 201 may be referred to as an instance of a cross-point architecture because the memory cells 205 may be formed at the topological cross-points between the access lines 210 and the sense lines 215, as Figure 2 illustrated. This cross-point architecture may provide relatively higher density data storage and lower production costs compared to some other memory architectures. For example, a memory array with a cross-point architecture may include memory cells with a reduced area and may thus support a higher memory cell density than some other architectures.

[0046] For example, compared to other architectures (e.g., architectures with three-terminal select components) with a 6F 2 memory cell area, the cross-point architecture may have a 4F 2 memory cell area, where F is the minimum feature size (e.g., the lowest feature size). For example, a DRAM memory array may use transistors (which are three-terminal devices) as the select component for each memory cell. Thus, a DRAM memory array including a given number of memory cells may have a larger memory cell area than a memory array with a cross-point architecture including the same number of memory cells. Although Figure 2 the example shows one level (e.g., a memory lamella) of the memory array, other configurations may include any number of lamellas. In some embodiments, one or more memory lamellas may include self-selecting memory cells that include a chalcogenide material 213.

[0047] A memory cell (e.g., memory cell 205) can be incorporated as part of a memory cell that can be configured to store a value, which in some cases can be or include an analog value. In some memory devices, applying an electronic pulse to a chalcogenide material 213 can cause the chalcogenide material 213 to be affected, which in some cases can include changing its physical form. The physical forms of some chalcogenide materials 213 include amorphous and crystalline states. The resistances of these physical forms are different, thereby allowing the chalcogenide material 213 to maintain a physical state, which can be referred to as stored logic (e.g., sense logic and / or analog values). In some embodiments of the memory device, applying an electronic pulse to the chalcogenide material 213 does not change the phase of the chalcogenide material 213, and the chalcogenide material 213 can remain amorphous. For example, set and reset states can be obtained by applying pulses of different (e.g., opposite) polarities. Additionally, in some embodiments, the threshold voltage can be modified or tuned by applying a voltage pulse of an appropriate amplitude and / or polarity.

[0048] Figure 3 An example of a memory array 301 that supports a neural network memory according to an embodiment of the present disclosure is illustrated. The memory array 301 can be similar to Figure 1 and 2 the example memory arrays 101 and 201. The memory array 301 can include neural memory cells 323, which can include some or all of the variable resistance memory cells 305 in the array 301. The memory array 301 can include a plurality of variable resistance memory cells 305-1, 305-2, 305-3, 305-4, 305-5, 305-6, 305-7, 305-8, 305-9, 305-10, 305-11, and 305-P (collectively referred to as variable resistance memory cells 305). The memory array 301 can include neural memory cells 323, which can include some or all of the variable resistance memory cells 305 in the array 301. The variable resistance memory cells 305 of the neural memory cells 323 can be coupled to a plurality of sense lines 315-1, 315-2, 315-S (collectively referred to as sense lines 315) and a plurality of access lines 310-1, 310-2, 310-3, 310-N (collectively referred to as access lines 310).

[0049] In some instances, some of the resistive memory cells of the memory array 301 may not be included in the neural memory cell 323. In the example array 301, the neural memory cell 323 includes resistive memory cells 305-1, 305-2, 305-3, 305-4, 305-5, 305-6, 305-7, 305-8, and 305-9, and the resistive memory cells 305-10, 305-11, and 305-P may be excluded from the neural memory cell 323. Thus, the resistive memory cells 305 coupled to the access line 310-N may be included in the memory array 301, but need not be part of the neural memory cell 323. In such instances, the resistive memory cells may be excluded from the total analog value stored by the neural memory cell 323.

[0050] A neural memory cell controller (such as Figure 1 memory controller 140) may select the neural memory cell 323 for a read operation. In some cases, the neural memory cell controller may select one or more of the resistive memory cells 305 of the neural memory cell 323 for a read operation. The neural memory cell controller may identify and / or select one or more sense lines 315 and / or access lines 310 associated with the neural memory cell 323.

[0051] The neural memory cell controller may provide an input 341 to the resistive memory cells 305 of the neural memory cell 323. The input 341 may include a plurality of voltage values (such as sub-threshold voltage values) (such as V1, V2, V3) applied to a plurality of access lines 310. The neural memory cell controller may bias the access lines 310 to one or more of the voltage values (such as read voltage values) included in the input 341. In some cases, all of the access lines 310 are biased to the same read voltage. In some cases, the neural memory cell controller may bias one or more of the access lines to a voltage different from the other access lines.

[0052] The neural memory cell controller may also bias the unselected access lines 310-N (such as access lines not included in the neural memory cell 323) to a read voltage value. In some cases, the read voltage value applied to one or more of the unselected access lines 310-N is the same as the voltage value applied to the selected access lines 310-1, 310-2, 310-3. In some cases, the read voltage value applied to the unselected access lines 310-N is different from the voltage value applied to one of the selected access lines 310-1, 310-2, 310-3.

[0053] A neural memory cell controller can detect an output 343 that includes one or more signals generated on one or more sense lines 315 coupled to a neural memory cell 323. The output 343 on the sense lines 315 can be generated based on applying an input 341 to an access line 310 coupled to the neural memory cell 323. The signals of the output 343 can include current signals (such as I1, I2, I3).

[0054] An individual signal or an individual threshold voltage (such as a threshold weight and / or a synaptic weight) can be detected on each sense line 315 coupled to the neural memory cell 323. Each signal or weight can have different variable resistance memory cells that contribute to the signal. For example, the variable resistance memory cells 305-1, 305-4, and 305-7 can contribute to the signal on the first sense line 315-1. The variable resistance memory cells 305-2, 305-5, and 305-8 can contribute to the signal on the second sense line 315-2. The variable resistance memory cells 305-3, 305-6, and 305-9 can contribute to the signal on the third sense line 315-S.

[0055] The neural memory cell controller can determine an analog value stored in the neural memory cell 323 based on detecting the signals generated on the sense lines 315 coupled to the neural memory cell 323. The neural memory cell controller can combine the signals and / or threshold voltages (such as synaptic weights) on each sense line 315 to generate a total weight (which can be referred to as a total analog value). The analog value can be proportional to and / or based on the total weight. The neural memory cell controller can sum the signals of the sense lines 315 to generate the total weight. In some cases, the neural memory cell controller can generate a product by applying a weight matrix to an input vector of voltages (such as V1, V2, V3) representing one or more voltages on one or more access lines. For example, the neural memory cell controller can apply the vector through a matrix multiplication operation, where the vector is the input 341 (V1, V2, and V3), and the matrix is the threshold voltages of the corresponding variable resistance memory cells 305 included in the neural memory cell 323.

[0056] For example, a neural memory cell controller can be configured to apply a respective sub-threshold voltage pulse via each access line 310 to cause the threshold voltage of a respective variable resistance memory cell 305 coupled to each access line 310 and a particular sense line 315-1 to change in an analog manner toward a voltage associated with a set state to effect a synaptic weight change. In this example, each of the variable resistance memory cells 305-1, 305-4, and 305-7 can receive a sub-threshold voltage. The neural memory cell controller can be further configured to apply another respective sub-threshold voltage pulse via each of the plurality of access lines 310 to cause the threshold voltage of a respective variable resistance memory cell 305 coupled to each access line 310 and a different sense line 315-2 to change in an analog manner toward a voltage associated with a set state to effect a synaptic weight change. In this example, each of the variable resistance memory cells 305-2, 305-5, and 305-8 can receive a sub-threshold voltage. This example method can continue for any number of sense lines 315 to effect synaptic weight changes of the variable resistance memory cells 305. The neural memory cell controller can be configured to read voltages from each of the sense lines 315-1 and 315-2 to determine a total analog value of the memory array 301 (e.g., a total analog value of the neural memory cell 323), which can be an output 343.

[0057] The neural memory cell controller can be configured to apply subsequent voltage pulses as an input 341 based on the detected total analog values of the sense lines 315-1 and 315-2. In some embodiments, the neural memory cell controller can be configured to apply vectors (e.g., inputs 341-V1, V2, and V3) in response to a learning algorithm. The learning algorithm and / or the neural memory cell controller can be configured to perform matrix multiplication of vectors (e.g., input 341) each composed of respective threshold voltages of each variable resistance memory cell in each of the plurality of sense lines 315-1 and 315-2 and / or 315-S.

[0058] Figure 4 An example graph illustrating the threshold voltage distribution of a neural network memory according to an embodiment of the present disclosure. Example graph 484 illustrates the x-axis of the threshold voltage (Vth) 469 of a variable resistance memory cell (e.g., a self-selective memory cell), where Vth increases from the left side of the page to the right side of the page. Graph 484 illustrates the y-axis 467 representing the statistical normal quantile of bits (e.g., the standard deviation of a Gaussian distribution). Graphical 484 illustrates an array of variable resistance memory cells during different programming and read combinations. The legend below the x-axis contains the polarities of the programming pulses and the respective line symbols for different combinations of read values, such as symbol 461 for negative programming and negative read, symbol 462 for negative programming and positive read, symbol 464 for positive programming and negative read, and symbol 466 for positive programming and positive read.

[0059] Each variable resistance memory cell of a memory array (such as a neural memory cell) can be programmed to include a threshold voltage Vth 469. When the voltage is pulse-modulated below the threshold voltage Vth 469, each variable resistance memory cell can expand the Vth value within a range between a high Vth state (such as a reset pulse) and a low Vth state (such as a set pulse). The programming pulse and / or other voltage pulses applied across the variable resistance memory cell (such as a self-selecting memory cell) can be referred to as having a polarity herein. Polarity refers to the bias of the voltage for write and read operations. The sense line and the access line (such as Figure 3 the sense line 315 and the access line 310) can have different voltage biases for write and read operations. For example, the programming pulse can have a positive or negative polarity and can depend on the read polarity. The behavior of the variable resistance memory cell can determine whether the read pulse determined in response to the programming pulse has a positive or negative voltage value.

[0060] As described herein, a self-selecting memory cell (such as a variable resistance memory cell in an array) can be configured by a neural memory cell controller to change the logic state by manipulating its corresponding chalcogenide material in the amorphous state. This state change can increase or decrease the resistance value of the self-selecting memory cell, which can be represented as a synaptic weight. Such variable resistance memory cells can include memory cells configured to store multiple levels and / or can have a wide sensing window. This type of memory can be configured to perform training operations through pulse (such as spike) control. Such training operations can include spike-timing-dependent plasticity (STDP). STDP can be a form of Hebbian learning induced by the correlation between spikes transmitted between nodes (such as neurons). STDP can be an example of a process for adjusting the connection strength between nodes (such as neurons). Figure 4 Illustrate a large analog value expansion (such as a wide sensing window / digital state of inter-bit variability) of the Vth value in examples where the read value is negative (such as negative-negative 461 and positive-negative 464), which can have a narrower sensing window and a smaller Vth expansion compared to examples where the read value is positive (such as negative-positive 462 and positive-positive 466).

[0061] Variable resistance memory cells can be used in neuromorphic applications, where an array of variable resistance memory cells can be trained by external pulses to obtain specific analog Vth values. The current along the signal line (such as Figure 3 the sense line 315 and the access line 310) can represent the final output (such as output 343, Figure 3 the total analog value of the neural memory cell 323) depending on the input voltage (such as Figure 3 the input 341). This can be obtained by multiplying the analog voltage input in the matrix by a vector multiplication function.

[0062] Figure 5 An example graph illustrating the threshold voltage distribution of a neural network memory according to an embodiment of the present disclosure. Example graph 578 illustrates the x-axis of the threshold voltage (Vth) 569 of a variable resistance memory cell (e.g., a self-selective memory cell), where Vth increases from the left side of the page (set state 581) to the right side of the page (reset state 582). Graph 578 illustrates the y-axis 567 representing the statistical normal quantile of the bit (e.g., the standard deviation of a Gaussian distribution).

[0063] The legend of graph 578 illustrates a solid line 579 representing a memory array of variable resistance memory cells read 10,000 times with sub-threshold voltage pulses. The legend of graph 578 illustrates a dashed line 580 representing variable resistance memory cells read 65,000 times with sub-threshold voltage pulses. Although the number of pulses is listed here as an example, any number of pulses can be used.

[0064] Graph 578 illustrates the threshold voltage (Vth) 569, which can be a range of analog values representing incremental changes in the logical state of a chalcogenide material of a variable resistance memory cell (e.g., a self-selective memory cell). As the variable resistance memory cell is pulse modulated (e.g., read 10,000 times or 65,000 times), the chalcogenide material of the variable resistance memory cell can change from a reset state 582 corresponding to a higher Vth (e.g., low conductivity, high current resistance) towards a set state 581 corresponding to a lower Vth (e.g., high conductivity, low current resistance). At least in part based on the number of sub-threshold pulses, the magnitude of the sub-threshold pulses, and / or the duration of the sub-threshold pulses, the chalcogenide material of the self-selective memory cell can be amorphous and have different threshold voltage values while remaining amorphous.

[0065] The variable resistance memory cells of 579 and / or 580 can cause the threshold voltage to change in an analog manner from the reset state 582 towards the set state 581. In other words, the threshold voltage 569 within the analog value range between the voltage associated with the reset state 582 and the voltage associated with the set state 581 can change in response to sub-threshold voltage pulses, where each of the analog value ranges corresponds to a synaptic weight.

[0066] The number of pulses and / or the magnitude of sub-threshold voltage pulses may be associated with strong learning events and / or weak learning events. In some embodiments, the learning events (e.g., the number of pulses and / or the magnitude of voltage pulses) may be set by a learning algorithm, where a weak learning event may be a relatively low number of pulses (e.g., less than 1000) and / or pulses that are not much lower than the Vth of the variable resistance memory cell. A strong learning event may be a relatively high number of pulses (e.g., greater than 1000) and / or pulses with a magnitude much lower than the Vth of the variable resistance memory cell. A stronger learning event may correspond to a larger change in the threshold voltage of the variable resistance memory cell.

[0067] Figure 6 Illustrate an example method 660 for a neural network memory according to an embodiment of the present disclosure. The operations of method 660 may be implemented by the neural memory cell controller described herein (e.g., Figure 1 controller 140) or its components. For example, the operations of method 660 may be performed within the neural memory cell described in reference to Figures 1 to 5 In some embodiments, the neural memory cell controller may execute a set of program codes to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, the neural memory cell controller may use dedicated hardware to perform each aspect of the functions described below.

[0068] In block 692, method 660 includes applying weak sub-threshold voltage pulses to the variable resistance memory cells of an array (e.g., Figure 1 array 301) of variable resistance memory cells (e.g., Figure 3 variable resistance memory cell 105) coupled to the neural memory cell controller in response to a first weak learning event.

[0069] The weak sub-threshold voltage pulses cause the threshold voltage of the variable resistance memory cell (e.g., Figure 5 Vth 569) to change weakly in an analog manner towards the voltage associated with the set state (e.g., Figure 5 set state 581) to achieve a weak synaptic weight change. In this example, the weak sub-threshold voltage may be a voltage lower than the threshold voltage Vth of the variable resistance memory cell, but the magnitude difference between the sub-voltage pulse and the Vth of the variable resistance memory cell is not sufficient to change the Vth to the extent that represents learning.

[0070] In block 694, method 660 includes applying, by a neural memory cell controller coupled to an array of variable resistance memory cells, a strong subthreshold voltage pulse to the variable resistance memory cells of the array. The strong subthreshold voltage pulse may have a relatively large magnitude difference between the voltage of the subthreshold voltage pulse and the Vth of the variable resistance memory cell, wherein the strong subthreshold voltage pulse causes the threshold voltage of the variable resistance memory cell to strongly vary in an analog manner toward the voltage associated with the set state to achieve a strong synaptic weight change. In other words, the application of the strong subthreshold voltage pulse may include a second pulse having a larger magnitude difference than the first pulse. In other embodiments, as an alternative or addition to the strong subthreshold pulse, the duration of the subthreshold pulse may be manipulated to probe the change in the Vth of the variable resistance memory cell. For example, the application of the strong subthreshold voltage pulse may include a second pulse having a longer duration difference than the first pulse.

[0071] Figure 7 Illustrate an example method 777 for a neural network memory according to an embodiment of the present disclosure. Operations of method 777 may be implemented by the neural memory cell controller described herein (e.g., Figure 1 controller 140) or components thereof. For example, operations of method 777 may be performed within the neural memory cells described in reference to Figures 1 to 6 In some instances, the neural memory cell controller may execute a set of program code to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, the neural memory cell controller may use dedicated hardware to perform aspects of the functions described below.

[0072] In 791, method 777 includes applying, by a neural memory cell controller coupled to an array of variable resistance memory cells (e.g., Figure 1 variable resistance memory cell 105), a first number of subthreshold voltage pulses to the variable resistance memory cells of the array in response to a weak learning event. The first number of subthreshold voltage pulses may cause the threshold voltage Vth of the variable resistance memory cell (e.g., Figure 5 Vth 569) to weakly vary in an analog manner toward the voltage associated with the set state (e.g., Figure 5 set state 581) to achieve a weak synaptic weight change.

[0073] The weak synaptic weight change may be an ineffective change in the voltage threshold Vth of the variable resistance memory cell. In this example, the learning algorithm may increase the number of pulses applied to the variable number of resistance cells (e.g., the learning event may be changed).

[0074] In 793, method 777 includes a neural memory cell controller coupled to an array of variable resistance memory cells applying a second number of sub-threshold voltage pulses to the variable resistance memory cells of the array in response to a strong learning event, where the second number is greater than the first number. For example, the neural network cell controller may increase the number of pulses from 1000 to 65000 to effect a change in Vth towards the set state. In this way, the second number of sub-threshold voltage pulses may cause a strong change in the threshold voltage of the variable resistance memory cells in an analog manner towards the voltage associated with the set state to effect a strong synaptic weight change.

[0075] Using example method 777, the neural memory cell controller may apply subsequent sub-threshold voltage pulses to the variable resistance memory cells in response to subsequent learning events until the sub-threshold voltage pulses cause the variable resistance memory cells to reach the set state (e.g., a crystalline, highly conductive, low current resistance state).

[0076] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description is by way of illustration and not limitation. Those of ordinary skill in the art will recognize combinations of the above-described embodiments and other embodiments not specifically described herein after reviewing the above description. The scope of several embodiments of this disclosure includes other applications using the above-described structures and methods. Accordingly, the scope of several embodiments of this disclosure should be determined with reference to the appended claims and the full scope of equivalents to which the claims are entitled.

[0077] In the detailed description, for the sake of simplicity of the disclosure, some features are grouped together in a single embodiment. The methods of this disclosure should not be construed as reflecting an intention that the disclosed embodiments of this disclosure must use more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive subject matter presents non-all features of a single disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment.

Claims

1. A device, comprising: An array (101, 201, 301) of variable resistance memory cells (105, 205, 305); And A neural memory cell controller (140) coupled to the array of variable resistance memory cells and configured to: Apply a sub-threshold voltage pulse to the variable resistance memory cells of the array to cause the threshold voltages (469, 569) of the variable resistance memory cells to change in an analog manner from the voltage associated with the reset state (582) to achieve a first synaptic weight change; Wherein the sub-threshold voltage pulse includes a voltage pulse having a polarity opposite to the write polarity; and Apply additional sub-threshold voltage pulses to the variable resistance memory cells to achieve each subsequent synaptic weight change.

2. The device according to claim 1, wherein the variable resistance memory cell is a self-selecting memory cell including a single chalcogenide material (213) for operation as a selection component and a storage component.

3. The device according to claim 2, wherein the neural memory cell controller is configured to apply the sub-threshold voltage pulse and the additional sub-threshold voltage pulses includes the neural memory cell controller being configured to determine that the single chalcogenide material is in an amorphous condition associated with the reset state.

4. The device according to claim 2, wherein the neural memory cell controller is configured to apply the sub-threshold voltage pulse and the additional sub-threshold voltage pulses includes the neural memory cell controller being configured to change the single chalcogenide material towards a condition associated with the set state (581).

5. The device according to claim 1, wherein the neural memory cell controller is further configured to operate the array of variable resistance memory cells as a neural network, wherein the threshold voltage of the variable resistance memory cell represents a synaptic weight; and Wherein each of the additional sub-threshold voltage pulses reduces the resistance of the variable resistance memory cell to represent a change in the synaptic weight.

6. The device according to claim 1, wherein the neural memory cell controller is configured to apply one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to an indication of an iteration of a learning algorithm that indicates that learning has occurred.

7. The device according to claim 6, wherein the neural memory cell controller is further configured not to apply one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to the indication of the iteration of the learning algorithm that indicates that no additional learning has occurred.

8. The device according to claim 6, wherein the neural memory cell controller is configured to apply the one of the additional sub-threshold voltage pulses as a relatively long pulse to the variable resistance memory cell in response to an indication of an iteration of a learning algorithm that indicates that relatively strong additional learning has occurred.

9. The apparatus according to claim 6, wherein the neural memory cell controller is configured to apply more than one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to an iteration of a learning algorithm indicating that relatively strong incremental learning has occurred.

10. The apparatus according to claim 1, wherein the neural memory cell controller being configured to apply an additional sub-threshold voltage pulse to the variable resistance memory cell includes the neural memory cell controller being configured to change the threshold voltage of the variable resistance memory cell within an analog voltage value range.

11. An apparatus comprising: a plurality of first signal lines (110, 210, 310); a plurality of second signal lines (115, 215, 315); an array (101, 201, 301) of variable resistance memory cells (105, 205, 305); and a neural memory cell controller (140) coupled to the plurality of first signal lines and the plurality of second signal lines, the neural memory cell controller being configured to: apply a respective sub-threshold voltage pulse via each of the plurality of first signal lines to cause the threshold voltage (469, 569) of the respective variable resistance memory cell coupled to each of the plurality of first signal lines and a particular second signal line to change in an analog manner toward a voltage associated with a set state (581) to effect a synaptic weight change; wherein the respective sub-threshold voltage pulse includes a voltage pulse having a polarity opposite to a write polarity; apply a respective sub-threshold voltage pulse via each of the plurality of first signal lines to cause the threshold voltage of the respective variable resistance memory cell coupled to each of the plurality of first signal lines and a different second signal line to change in an analog manner toward a voltage associated with a set state (581) to effect a synaptic weight change; and read a voltage or current from each of the plurality of second signal lines to determine a total analog value of the array.

12. The apparatus according to claim 11, wherein the neural memory cell controller is further configured to apply subsequent respective sub-threshold voltage pulses via each of the plurality of first signal lines to cause the threshold voltage of the respective variable resistance memory cell coupled to each of the plurality of first signal lines and the particular second signal line to change in an analog manner to effect a subsequent synaptic weight change, based in part on the total analog value of the array.

13. The apparatus according to claim 11, wherein the neural memory cell controller being configured to apply the respective sub-threshold voltage pulse via each of the first plurality of signal lines includes the neural memory cell controller being configured to input a data vector from a learning algorithm (341).

14. The apparatus according to claim 13, wherein the neural memory cell controller is configured to read the voltage or the current from each of the plurality of second signal lines includes the neural memory cell controller being configured to perform a matrix multiplication of vectors each consisting of a respective threshold voltage of each variable resistance memory cell in each of the plurality of second signal lines.

15. A method, comprising: applying, by a neural memory cell controller (140) coupled to an array (101, 201, 301) of variable resistance memory cells (105, 205, 305), a weak subthreshold voltage pulse (692) to the variable resistance memory cells of the array in response to a first weak learning event; wherein the weak subthreshold voltage pulse causes a weak change in an analog manner of a threshold voltage (469, 569) of the variable resistance memory cell toward a voltage associated with a set state (581) to effect a weak synaptic weight change; applying, by the neural memory cell controller coupled to the array of variable resistance memory cells, a strong subthreshold voltage pulse (694) to the variable resistance memory cells of the array; and wherein the strong subthreshold voltage pulse causes a strong change in an analog manner of the threshold voltage of the variable resistance memory cell toward the voltage associated with the set state to effect a strong synaptic weight change; and wherein applying the weak subthreshold voltage pulse and wherein applying the strong subthreshold voltage pulse includes applying respective voltages having polarities opposite to a write polarity.

16. The method according to claim 15, wherein applying the weak subthreshold voltage pulse includes applying a first voltage pulse having a first magnitude; and wherein applying the strong subthreshold voltage pulse includes applying a second voltage pulse having a second magnitude greater than the first magnitude.

17. The method according to claim 15, wherein applying the weak subthreshold voltage pulse includes applying a third voltage pulse having a first duration; and wherein applying the strong subthreshold voltage pulse includes applying a fourth voltage pulse having a second duration longer than the first duration.

18. The method according to claim 15, further comprising determining a total analog value of the array of variable resistance memory cells, wherein the total analog value represents a set of synaptic weights of each of the variable resistance memory cells of the array.

19. The method according to claim 15, wherein applying the weak subthreshold voltage pulse and applying the strong subthreshold voltage pulse includes reducing a resistance of a chalcogenide material (213) of the variable resistance memory cell.

20. The method according to claim 15, wherein the array of variable resistance memory cells includes self-selecting memory cells, each of the self-selecting memory cells including a single chalcogenide material (213) operative as a selection component and a storage component.

21. A method, comprising: A neural memory cell controller (140) coupled to an array (101, 201, 301) of variable resistance memory cells (105, 205, 305) applies a first number of sub-threshold voltage pulses to (791) the variable resistance memory cells of the array in response to a weak learning event; wherein the first number of sub-threshold voltage pulses causes a weak change in the threshold voltage of the variable resistance memory cell in an analog manner toward the voltage associated with the set state (581) to effect a weak synaptic weight change; wherein the first number of sub-threshold voltage pulses includes voltage pulses having a polarity opposite to the write polarity; the neural memory cell controller coupled to the array of variable resistance memory cells applies a second number of sub-threshold voltage pulses to (793) the variable resistance memory cells of the array in response to a strong learning event; and wherein the second number of sub-threshold voltage pulses causes a strong change in the threshold voltage of the variable resistance memory cell in an analog manner toward the voltage associated with the set state to effect a strong synaptic weight change.

22. The method according to claim 21, wherein the second number is greater than the first number.

23. The method according to claim 21, further comprising applying subsequent sub-threshold voltage pulses to the variable resistance memory cells in response to subsequent learning events until the sub-threshold voltage pulses cause the variable resistance memory cells to reach the set state.

24. The method according to claim 23, wherein the method comprises changing the threshold voltage within an analog value range between the voltage associated with the reset state (582) and the voltage associated with the set state, each of the analog value ranges corresponding to a synaptic weight.

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