Method for manufacturing mask and method for manufacturing semiconductor device

Abstract

The disclosure provides a method of manufacturing a mask and a method of manufacturing a semiconductor device. A method of manufacturing a mask can include identifying an error pattern in a final pattern formed on a substrate, correcting a first target pattern based on the error pattern, dividing a first mask layout into a plurality of first segments based on the corrected first target pattern, and correcting the first mask layout by shifting a plurality of first target segments corresponding to first final targets among the plurality of segments. The first mask layout can include a first extension pattern, final targets disposed in a zigzag shape, and first final targets corresponding to the error pattern, and each of the plurality of first segments can correspond to one of the final targets.

Description

TECHNICAL FIELD

[0001] Some example embodiments relate to a method of designing a mask layout and / or a method of manufacturing a mask by using the same. BACKGROUND

[0002] In a semiconductor process, a lithography process can be performed to form a pattern on a semiconductor substrate such as a wafer. By using two line patterns extending in different directions, a final pattern having a contact shape and / or a dot shape can be implemented on the semiconductor substrate. SUMMARY

[0003] Some example embodiments provide a method of manufacturing a mask, the method including a process of correcting a target pattern and a mask layout based on an error pattern.

[0004] A method of manufacturing a mask according to some example embodiments can include identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern; segmenting a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (a) a first extension pattern extending in a first horizontal direction, (b) a final target corresponding to the final pattern and arranged in a zigzag form, and (c) a first final target corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; and correcting the first mask layout by shifting a plurality of first target segments corresponding to the first final target among the plurality of first segments.

[0005] A method of manufacturing a mask according to some example embodiments can include identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern; segmenting a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (a) a first extension pattern extending in a first horizontal direction, (b) a final target corresponding to the final pattern and arranged in a zigzag form, and (c) a first final target corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; and correcting the first mask layout by shifting a plurality of first target segments corresponding to the first final target among the plurality of first segments.

[0006] A method for manufacturing a semiconductor device according to some example embodiments may include: identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern; dividing a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (A) a first extended pattern extending in a first horizontal direction, (B) a final target corresponding to the final pattern and arranged in a zigzag shape, and (C) a first final target corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; correcting the first mask layout by offsetting a plurality of first target segments corresponding to the first final target among the plurality of first segments; forming a photomask based on the corrected first mask layout; forming a photoresist pattern by using the photomask; and forming a semiconductor pattern on the substrate by using the photoresist pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a conceptual diagram illustrating a photolithography system according to some example embodiments of the inventive concept.

[0008] Figure 2 is a flowchart illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0009] Figure 3 is a flowchart illustrating processes included in a method of correcting a first target pattern according to some example embodiments of the inventive concepts.

[0010] Figure 4 and Figure 5 is a conceptual diagram of a method of correcting a first target pattern according to some example embodiments of the inventive concept.

[0011] Figures 6 to 9 is a conceptual diagram of a method of correcting a first mask layout according to some example embodiments of the inventive concepts.

[0012] Figures 10 to 13 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0013] Figures 14 to 16 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0014] Figure 17 is a flowchart illustrating processes included in a method of correcting a second target pattern according to some example embodiments of the inventive concepts.

[0015] Figures 18 to 21 is a conceptual diagram of a method of correcting a second target pattern according to some example embodiments of the inventive concept.

[0016] Figures 22 to 25 is a conceptual diagram of a method of correcting a second mask layout according to some example embodiments of the inventive concepts.

[0017] Figures 26 to 30 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0018] Figures 31 to 34 is a conceptual diagram of a method of correcting a second target pattern and a second mask layout according to some example embodiments of the inventive concepts.

[0019] Figures 35 to 37 are cross-sectional views for describing a method of manufacturing a photomask according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Figure 1 is a conceptual diagram illustrating a photolithography system 10 according to some example embodiments of the inventive concepts.

[0021] Reference Figure 1 The photolithography system 10 may include a light source 20, a photomask 30, a photoresist 40, a hard mask 50, a target layer 60, and a substrate 70. In some example embodiments, the photolithography system 10 may further include a reduced projection device, which may be disposed between the light source 20 and the photomask 30 and / or between the photomask 30 and the photoresist 40.

[0022] The light source 20 may emit radiation such as light. The light emitted from the light source 20 may be irradiated onto the photomask 30. For example, to adjust the light focus, a lens and / or a reflector may be provided between the light source 20 and the photomask 30. The light source 20 may include an ultraviolet (UV) source. The light source 20 may include one point light source PS, but example embodiments are not limited thereto. In some example embodiments, the light source 20 may include a plurality of point light sources PS.

[0023] In order to print (realize) the layout of the photomask 30, the photomask 30 may include a plurality of image patterns. The plurality of image patterns may be formed based on a plurality of layout patterns, wherein the plurality of layout patterns are obtained based on layout design / optical proximity correction (OPC). The image pattern may be defined based on transparent regions and opaque regions. The transparent regions may be formed by etching a metal layer of the photomask 30. The transparent regions may transmit light emitted from the light source 20, for example, allowing transmission of light emitted from the light source 20. On the other hand, the opaque regions may not transmit the emitted light and may block the light.

[0024] The layout of the photomask 30 may include multiple layers. For example, OPC may be performed to adjust the layout of a single layer. For example, OPC may be performed independently for each of the multiple layers. The multiple layers may be sequentially implemented on the substrate 70 using a semiconductor process, thereby forming a semiconductor device. For example, the semiconductor device may include multiple metal layers for implementing a specific circuit, such as a runner and / or a via.

[0025] The layout of the photomask 30 may be implemented on or transferred to the photoresist 40. For example, the layout of the photomask 30 may be transferred to the photoresist 40 through a photolithography process. In some example embodiments, the target pattern may include two layers. For example, a first target pattern TP1 and a second target pattern TP2 may be used, and the first target pattern TP1 and the second target pattern TP2 may be implemented using two types of photoresists. The first target pattern TP1 may intersect the second target pattern TP2 in a direction, such as a diagonal direction, but example embodiments are not limited thereto. For example, in some example embodiments, the first target pattern TP1 may be perpendicular to the second target pattern TP2.

[0026] Here, the mask layout may refer to the layout of a pattern formed on the photomask 30. The target pattern may refer to a shape to be formed on the photoresist 40 based on the mask layout. For example, the target pattern may refer to an image formed on the photoresist 40 after a photolithography process and a development process based on the photomask 30. In terms of the characteristics of the photolithography process, for example, due to a diffraction effect, the shape of the mask layout may partially differ from the shape of the target pattern.

[0027] The pattern of the photoresist 40 can be realized as a final pattern FP on the patterned hard mask 55. For example, the final pattern FP can be realized by etching the hard mask 50 using each of the photoresist 40 having the first target pattern TP1 realized therein and the photoresist 40 having the second target pattern TP2 realized therein as an etching mask. The etching process can be a dry etching process and / or a wet etching process. The final pattern FP can have a hole shape and / or a column shape. The hole shape can be circular and / or oval / elliptical. Here, the final pattern FP can represent the image after the etching process and the cleaning process. Based on the process conditions including the etching material and the relative position on the wafer, the final pattern FP can be different from the target pattern on the photoresist 40.

[0028] A target layer 60 may be disposed on a substrate 70, and a pattern of the hard mask 50 may be formed on the target layer 60 through an etching process. The etching process performed on the target layer 60 may be performed separately and / or separately from the etching process of the hard mask 50, for example, after the etching process of the hard mask 50; however, example embodiments are not limited thereto. Furthermore, the etching process of the target layer 60 may be performed using a dry etching process and / or a wet etching process. For example, a semiconductor pattern may be formed by etching the target layer 60 using the pattern of the hard mask 50 as an etching mask.

[0029] Figure 2 is a flowchart illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0030] Reference Figure 2 According to some example embodiments, a method of manufacturing / fabricating a semiconductor device may include: a process of identifying an error pattern in a final pattern formed / to be formed on a substrate (S110), a process of correcting a first target pattern based on the error pattern (S120a), a process of segmenting and / or dividing a first mask layout into a plurality of segments based on the corrected first target pattern (S130a), a process of correcting the first mask layout (S140a), a process of correcting a second target pattern based on the error pattern (S120b), a process of segmenting and / or dividing a second mask layout into a plurality of segments based on the corrected second target pattern (S130b), a process of correcting the second mask layout (S140b), a process of forming a mask (S150), and a process of forming a semiconductor device (S160).

[0031] Regarding the process of identifying an error pattern in a final pattern (S110), each final pattern formed on the substrate may be or correspond to a contact pattern, a via pattern, and / or a dot pattern. The contact pattern and / or the via pattern may have, for example, a hole shape, and the dot pattern may have a pillar shape.

[0032] The process of identifying an error pattern in the final pattern may include a simulation process (such as process simulation) and / or a process of measuring a scanning electron microscope (SEM) image (such as a critical dimension SEM (CD-SEM) image). For example, when viewed in a plan view, the final pattern may be circular. However, example embodiments are not limited thereto. Here, the error pattern may refer to a pattern having a size (e.g., a critical dimension) larger or smaller than that of the final pattern to be formed, and / or may refer to a pattern that is misaligned with other final patterns.

[0033] After the process of identifying the error pattern (S110), a process of correcting the first target pattern (S120a) may be performed based on the error pattern, and a process of correcting the second target pattern (S120b) may be performed based on the error pattern. In some example embodiments, the process (S120a) and the process (S120b) may be performed in parallel, partially in parallel, or selectively. For example, only the processes (S120a, S130a, and S140a) may be performed, and the processes (S120b, S130b, and S140b) may not be performed. Alternatively, the opposite may be performed, or all the processes (S120a, S130a, S140a, S120b, S130b, and S140b) may be performed. In some example embodiments, the processes (S120a, S130a, S140a, S120b, S130b, and S140b) may be performed sequentially.

[0034] Figure 3 is a flowchart illustrating processes included in a method of correcting a first target pattern according to some example embodiments of the inventive concept. For example, Figure 3 is a flowchart illustrating a method of performing the process ( S120 a ) of correcting the first target pattern based on the error pattern. Figure 4 and Figure 5 is a conceptual diagram of a method of correcting a first target pattern according to some example embodiments of the inventive concept.

[0035] Reference Figure 3 , the process (S120a) may include a process (S121a) of forming a mark layer overlapping with the first final target, a process (S122a) of selecting a first error region from the mark layer, a process (S123a) of correcting the first error region based on a skew value of the first target pattern and the error pattern, and a process (S124a) of reflecting the corrected first error region in the first target pattern.

[0036] Figure 4 The process of forming the mark layer MRK (S121a) and the process of selecting the first error region ER1 (S122a) are shown. Figure 4 The first target pattern TP1 may include a plurality of first extension patterns EP1. In some example embodiments, the plurality of first extension patterns EP1 may extend in a first horizontal direction D1 and may be spaced apart from each other in a second horizontal direction D2. In some example embodiments, each of the plurality of first extension patterns EP1 may be a line pattern, but example embodiments are not limited thereto. For example, each of the plurality of first extension patterns EP1 may be or correspond to a line pattern including one or more protruding patterns and / or recessed patterns.

[0037] The final target FT may represent the position of the final pattern to be formed on the substrate after the etching process and the cleaning process. Figure 4 In the figure, each of the plurality of final target FTs is shown as a quadrilateral / square, but example embodiments are not limited thereto. In some example embodiments, the final target FTs may have a shape such as a circle, an ellipse, a hexagon, or an octagon. For example, the final pattern achieved on the substrate may be circular. The final target FTs may be arranged in a plurality of rows at regular intervals, and adjacent rows may be arranged in a zigzag pattern. For example, the final target FTs may be arranged in a honeycomb structure or another lattice structure.

[0038] In some example embodiments, some final target FTs may not overlap with the first extension pattern EP1. When using a double patterning technique, the final pattern after etching may have a finer pitch than the pitch of a pattern on a photoresist formed by a photolithography process. For example, the pitch of the final target FT may be smaller than the pitch of the first extension pattern EP1, and some final target FTs may not overlap with the first extension pattern EP1.

[0039] The first final target FT1 may represent a final target corresponding to the identified error pattern among the final targets FT. In some example embodiments, the first final target FT1 may overlap with the first extended pattern EP1.

[0040] Regarding the process of forming the marking layer MRK (S121a), the marking layer MRK may be formed to overlap with the first final target FT1 corresponding to the error pattern. For example, the marking layer MRK may extend across the first extension pattern EP1 in the second horizontal direction D2 and may be formed to partially overlap with the first final target FT1. The marking layer MRK may be or correspond to a layer different from the first target pattern TP1.

[0041] Regarding the process of selecting the first error region ER1 ( S122 a ), a portion of the marking layer MRK overlapping the first extension pattern EP1 may be selected. For example, the first error region ER1 may be selected by using a Boolean operation, such as a Boolean operation on polygons (eg, an AND operation corresponding to the intersection of polygons).

[0042] Figure 5 is a conceptual diagram illustrating a process ( S123 a ) of correcting the first error region ER1 and a process ( S124 a ) of reflecting the corrected first error region ER1 in the first target pattern TP1 .

[0043] In some example embodiments, the error pattern can be or correspond to a pattern formed smaller than the final target FT. In this case, the process of correcting the first error region ER1 (S123a) can be a process of increasing the size of the first error region ER1. For example, in the case of correcting the first extended pattern EP1 extending in the first horizontal direction D1, the first error region ER1 can extend in a second horizontal direction D2 perpendicular to the first horizontal direction D1.

[0044] The correction can be based on a difference between the error pattern and the final target FT. For example, a skew value of a critical dimension (CD) of the error pattern and a CD of the final target FT can be considered. The length in which the first error region ER1 extends can be the same as or different from the difference between the CD of the error pattern and the CD of the final target FT.

[0045] Regarding the process of reflecting the corrected first error region ER1 in the first target pattern TP1 (S124a), the corrected first error region ER1 can be reflected in / correspond to the first target pattern TP1 by using a Boolean operation (e.g., OR operation). Figure 5 The corrected first target pattern TP1' is illustrated. The portion of the corrected first target pattern TP1' corresponding to the first final target FT1 can be corrected. For example, the corrected first target pattern TP1' can include a serif / protrusion pattern 210 on the first final target FT1 and a serif / protrusion pattern 212 under the first final target FT1.

[0046] Figures 6 to 9 is a conceptual diagram of a method of correcting a first mask layout according to some example embodiments.

[0047] Figure 6 is a conceptual diagram illustrating a method of splitting and / or dividing a first mask layout L1 based on the corrected first target pattern TP1'. The first mask layout L1 can represent a layout of the first target pattern TP1 to be implemented on a photoresist. Figure 7 and Figure 8 is a conceptual diagram illustrating a process (S140a) of correcting a first mask layout L1. As described above, in terms of characteristics of a lithography process, a target pattern to be implemented on a photoresist can be different from a layout of a photomask, and when the first target pattern TP1 is corrected to the corrected first target pattern TP1', the first mask layout L1 will be corrected.

[0048] Referring to Figure 6Regarding the process of dividing and / or splitting the first mask layout L1 into a plurality of segments based on the corrected first target pattern TP1' (S130a), the first extended pattern EP1 of the first mask layout L1 may be divided and / or split into a plurality of segments SG. Each of the plurality of segments SG may have the same length. Figure 7 , each segment SG can be set based on the position of the final target FT, and can be set to correspond to only one final target FT. For example, the center point of the segment SG corresponding to the first final target FT1 among the multiple segments SG can be aligned with the center point of the first final target FT1 in the second horizontal direction D2. Additionally or optionally, each of the multiple final target FTs can correspond to two segments SG. The final target FTs can be arranged in a zigzag manner such as a hexagonal lattice, so that in the event that the segment SG corresponding to the first final target FT1 is offset, the adjacent final target FT may be affected thereby. Therefore, the endpoint of each segment SG can be set / extended between the edge of the first final target FT1 and the edge of the final target FT adjacent to the first final target FT1 in the second horizontal direction D2. For example, the first final target FT1 can overlap the adjacent final target FT by a specific width W1 in the second horizontal direction D2, and the endpoint of each segment SG can be set at the center point of the overlapping portion. Additionally or optionally, each segment SG can correspond to Figure 5 The protrusion patterns 210 and 212 are shown. Here, the segment SG corresponding to the first final target FT1 may be referred to as a target segment.

[0049] The first mask layout L1 can be segmented and / or divided so that the segments SG are set as described above, thereby more accurately adjusting the error pattern. Alternatively or additionally, each segment SG can correspond to only one final target FT, thereby independently correcting the layout for each final target FT.

[0050] The process of correcting the first mask layout L1 (S140a) may include a process of generating a target point P and a process of shifting the segment SG. Referring again to Figure 7 , a target point P (eg, evaluation point) may be generated on each segment SG along the first target pattern TP1 .

[0051] Reference Figure 8, a corrected first mask layout L1' can be generated by offsetting the segment SG. For example, a simulation (such as an optical simulation) based on the offset segment SG can be performed, and the first mask layout L1 can be corrected so that the simulated contour SC matches / intersects the target point P. For example, the segment SG can be offset so that the distance between the simulated contour SC and the target point P is equal to or less than a specific value. In some example embodiments, multiple segments SG can be offset in the positive direction. Here, the offset performed in the positive direction may indicate that the segment SG moves in the direction for increasing the width of the first extension pattern EP1 (or the second extension pattern EP2). Alternatively, the offset performed in the negative direction may indicate that the segment SG moves in the direction for reducing the width of the first extension pattern EP1 (or the second extension pattern EP2).

[0052] Figure 9 A corrected first mask layout L1' is shown. The corrected first mask layout L1' may include a plurality of first extension patterns EP1'. The corrected first extension pattern EP1' may include a protrusion pattern 220 on the first final target FT1 and a protrusion pattern 222 below the first final target FT1. In some example embodiments, the first extension pattern EP1' opposite the protrusion patterns 220 and 222 may include a plurality of concave patterns 224 and 226, respectively. The concave patterns 224 and 226 may prevent or reduce the amount and / or possibility of deformation of the first extension pattern EP1' adjacent to the protrusion patterns 220 and 222. In some example embodiments, the concave patterns may not be formed in the corrected first mask layout L1'.

[0053] Figures 10 to 13 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0054] Figure 10 and Figure 11 The process of correcting the first target pattern TP1a is shown. The process of correcting the first target pattern TP1a may include the above reference Figure 3 and Figure 4 The process of forming the marking layer MRK (S121a), the process of selecting the first error region ER1 (S122a), and the process of correcting the first error region ER1 (S123a) are described. In some example embodiments, the error pattern may be or correspond to a pattern in which a pattern shift has occurred relative to the final target FT. For example, the error pattern may be misaligned with other final patterns. In this case, the process of correcting the first error region ER1 (S123a) may be or correspond to a process of shifting the first error region ER1 in a direction opposite to the direction in which the error pattern is misaligned.

[0055] Figure 11The corrected first target pattern TP1'a is shown. A portion of the first target pattern TP1a corresponding to the first final target FT1 may be corrected. When the error pattern is positioned downward from the other final targets FT1, the portion of the first target pattern TP1a corresponding to the first final target FT1 may be corrected upward in the second horizontal direction D2. For example, the first target pattern TP1'a may include a serif / protrusion pattern on the first final target FT1 and a recessed pattern below the first final target FT1.

[0056] Figure 12 1 is a conceptual diagram illustrating a method of segmenting and / or dividing the first mask layout L1a based on the corrected first target pattern TP1a. The first mask layout L1a can be segmented and / or divided based on the error pattern, and the segmentation and / or division method can be the same as that described above with reference to FIG. Figure 6 and Figure 7 For example, each of the plurality of segments SG may have the same length, and a segment SG between two final target FTs adjacent to each other in the second horizontal direction D2 may be arranged so that an end point of the segment SG is arranged between edges of the two final target FTs.

[0057] Figure 13 A corrected first mask layout L1'a is shown. The corrected first mask layout L1'a may include a plurality of first extension patterns EP1'. The segments SG may be offset in a direction opposite to the direction in which the error patterns are misaligned. For example, the corrected first extension pattern EP1' may include a protruding pattern 220a on the first final target FT1 and a recessed pattern 222a below the first final target FT1.

[0058] Figures 14 to 16 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0059] Figure 14 The first target pattern TP1'b after correction is shown. In some example embodiments, the error pattern may not overlap with the first extended pattern EP1 and may be a pattern formed to be smaller than the final target FT. For example, the first final target FT1 may not overlap with the first extended pattern EP1. The process of correcting the first target pattern TP1'b may be similar to that described above with reference to FIG. Figure 4 The corrected first target pattern TP1 ′ b may include a concave pattern 210 b on the first final target FT1 and a concave pattern 212 b below the first final target FT1 .

[0060] Figure 15 and Figure 16 is a conceptual diagram of a method for correcting the first mask layout.

[0061] Reference Figure 15 , the first mask layout L1b can be divided and / or partitioned by a plurality of segments SG, and a target point P can be generated on each segment SG along the first target pattern TP1. The method of dividing and / or partitioning the first extended pattern EP1 of the first mask layout L1b can be as described above with reference to Figure 6 and Figure 7 In some example embodiments, the segment SG corresponding to the first final target FT1 may be offset in a negative direction.

[0062] Figure 16 The corrected first mask layout L1'b is shown. The corrected first mask layout L1'b may include a plurality of first extended patterns EP1'. The corrected first extended pattern EP1' may include a protruding pattern 220b on the first final target FT1 and a recessed pattern 222b below the first final target FT1.

[0063] Figure 17 is a flow chart illustrating processes included in a method of correcting a second target pattern according to some example embodiments. For example, Figure 17 is a flowchart illustrating a method of performing the process ( S120 b ) of correcting the second target pattern based on the error pattern. Figures 18 to 20 is a conceptual diagram of a method of correcting a second target pattern according to some example embodiments.

[0064] Reference Figure 17 , the process (S120b) may include a process (S121b) of forming a mark layer overlapping with the first final target, a process (S122b) of selecting a second error region from the mark layer, a process (S123b) of correcting the second error region based on a skew value of a second target pattern and an error pattern, and a process (S124b) of reflecting the corrected second error region in a second target pattern.

[0065] Figures 18 to 21 is a conceptual diagram of a method of correcting a second target pattern according to some example embodiments of the inventive concept.

[0066] Figure 18A second target pattern TP2 is shown. The second target pattern TP2 may be or correspond to a different layer than the first target pattern TP1 and may have a shape different from that of the first target pattern TP1. For example, the second target pattern TP2 may include a plurality of second extension patterns EP2 extending in a direction intersecting the first horizontal direction D1. In some example embodiments, the second extension pattern EP2 may be a line pattern extending in a diagonal direction. For example, the second extension pattern EP2 may extend in a direction oblique to the first extension pattern EP1 at an angle, such as an angle between 45 degrees and 80 degrees (inclusive), relative to the first horizontal direction D1.

[0067] Reference Figure 19 , the second target pattern TP2 may be rotated. The rotated second target pattern TP2-R may include a rotated second extended pattern EP2-R, a rotated final target FT-R, and a rotated first final target FT1-R. For example, the plurality of second extended patterns EP2 may be rotated to be aligned in the first horizontal direction D1 (or parallel to the first horizontal direction D1). For example, the plurality of final targets FT may be rotated so that the edges of the quadrilaterals / squares are parallel to the first horizontal direction D1.

[0068] Figure 20 is a conceptual diagram illustrating a process of forming a mark layer MRK ( S121 b ) and a process of selecting a second error region ER2 ( S122 b ).

[0069] Regarding the process of forming the marking layer MRK (S121b), the marking layer MRK may be formed to overlap the first final target FT1-R corresponding to the error pattern. For example, the marking layer MRK may extend across the second extension pattern EP2-R in the second horizontal direction D2 and may be formed to partially overlap the first final target FT1-R. Regarding the process of selecting the second error region ER2 (S122b), the second error region ER2 in which the marking layer MRK overlaps the second extension pattern EP2-R may be selected.

[0070] Subsequently, a process of correcting the second error region ER2 (S123b) and a process of reflecting the corrected second error region ER2 in the second target pattern TP2-R (S124b) may be performed. In some example embodiments, the error pattern may be a pattern formed to be smaller than the final target pattern FT-R. Therefore, the process of correcting the second error region ER2 (S123b) may be a process of increasing the size of the second error region ER2.

[0071] Figure 21The corrected second target pattern TP2'-R is shown. The portion of the second target pattern TP2'-R corresponding to the first final target FT1-R can be corrected by reflecting the corrected second error region ER2. For example, the second target pattern TP2'-R can include a protrusion pattern 310 on the first final target FT1-R and a protrusion pattern 312 below the first final target FT1-R.

[0072] Figures 22 to 25 is a conceptual diagram of a method of correcting the second mask layout L2 according to some example embodiments of the inventive concepts.

[0073] Figure 22 is a conceptual diagram illustrating a method of dividing and / or partitioning the second mask layout L2 -R based on the corrected second target pattern TP2 ′-R. Figure 23 is a conceptual diagram illustrating a process of correcting the second mask layout L2-R (S140b). The second mask layout L2-R may represent a layout of a second target pattern TP2-R to be implemented on a photoresist.

[0074] Reference Figure 22 and Figure 23 , the second extended pattern EP2-R of the second mask layout L2-R may be segmented and / or divided into a plurality of segments SG, and a target point P may be generated on each of the plurality of segments SG along the second target pattern TP2'-R. The method of segmenting and / or dividing the second extended pattern EP2-R may be as described above with reference to Figure 6 and Figure 7 As described above, the endpoints of each segment SG may be positioned between an edge of the first final target FT1-R and an edge of a final target FT-R adjacent to the first final target FT1-R in the second horizontal direction D2. For example, the first final target FT1-R may overlap with an adjacent final target FT-R by a specific width W1 in the second horizontal direction D2, and the endpoints of each segment SG may be positioned at the center point of the overlapping portion. The plurality of segments SG may be offset in the positive direction.

[0075] Figure 24 The corrected second mask layout L2'-R is shown. The corrected second mask layout L2'-R may include a plurality of second extension patterns EP2-R. The corrected second extension pattern EP2-R may include a protrusion pattern 320 on the first final target FT1-R and a protrusion pattern 322 below the first final target FT1-R.

[0076] Figure 25 The second mask layout L2' after rotation is shown. Correction of the second mask layout L2 can be accomplished by rotating the second mask layout L2'-R again.

[0077] As mentioned above Figures 18 to 25 As described above, when the second extended pattern EP2 extends in a diagonal direction that is not parallel to the first horizontal direction D1 and the second horizontal direction D2, correction can be performed by rotating the second target pattern TP2 and the second mask layout L2. However, the inventive concept is not limited thereto, and in some example embodiments, the second target pattern TP2 and the second mask layout L2 may not be rotated. In some example embodiments, the edges of the plurality of second extended patterns EP2 and the edge of the final target pattern FT may be rotated to be parallel to each other in the second horizontal direction D2.

[0078] Figures 26 to 30 is a conceptual diagram of a method of correcting a first target pattern and a first mask layout according to some example embodiments of the inventive concepts.

[0079] In some example embodiments, the final target FTs of the first target pattern TP1c may be arranged in a lattice structure. For example, the final target FTs may be spaced apart from each other by a specific interval in the first horizontal direction D1 and the second horizontal direction D2. Figure 31 As described, when the second extending pattern EP2 is perpendicular to the first extending pattern EP1 , the final target FT may be arranged in a lattice structure.

[0080] Figure 26 2 is a conceptual diagram illustrating a process (S121a) of forming a mark layer MRK and a process (S122a) of selecting a first error region ER1. The process (S121a) of forming a mark layer MRK and the process (S122a) of selecting a first error region ER1 may be similar to Figure 4 Description to execute.

[0081] Subsequently, a process of correcting the first error region ER1 (S123a) and a process of reflecting the corrected first error region ER1 in the first target pattern TP1 (S124a) may be performed. In some example embodiments, the error pattern may be a pattern formed to be smaller than the final target FT. In this case, the process of correcting the first error region ER1 (S123a) may be a process of increasing the size of the first error region ER1.

[0082] Figure 27 The corrected first target pattern TP1'c is shown. The portion of the first target pattern TP1 corresponding to the first final target FT1 may be corrected. For example, the corrected first target pattern TP1'c may include a protrusion pattern 210c on the first final target FT1 and a protrusion pattern 212c below the first final target FT1.

[0083] Figure 28 is a conceptual diagram illustrating a method of dividing and / or partitioning the first mask layout L1c based on the corrected first target pattern TP1. Figure 29 is a conceptual diagram illustrating a process ( S140 a ) of correcting the first mask layout L1 c .

[0084] Reference Figure 28 and Figure 29 , the first extended pattern EP1 of the first mask layout L1c can be segmented and / or divided into a plurality of segments SG, and a target point P can be generated on each of the plurality of segments SG along the first target pattern TP1'c. Each segment SG can be set based on the position of the final target FT. For example, the center point of the segment SG corresponding to the first final target FT1 among the plurality of segments SG can be aligned with the center point of the first final target FT1 in the second horizontal direction D2. In some example embodiments, the endpoint of each segment SG can be set at the center point between the edge of the first final target FT1 and the edge of the final target FT adjacent to the first final target FT1 in the first horizontal direction D1. For example, the first final target FT1 can be spaced apart from the final target FT adjacent to it in the first horizontal direction D1 by a specific width W2, and the endpoint of each segment SG can be set to divide the width W2 into two. Additionally or optionally, each segment SG can correspond to Figure 27 The plurality of segments SG may be offset in the positive direction.

[0085] Figure 30 The corrected first mask layout L1'c is shown. The corrected first mask layout L1'c may include a plurality of first extended patterns EP1'. The corrected first extended pattern EP1' may include a protrusion pattern 220c on the first final target FT1 and a protrusion pattern 222c below the first final target FT1.

[0086] Figures 31 to 34 is a conceptual diagram of a method of correcting a second target pattern and a second mask layout according to some example embodiments of the inventive concepts.

[0087] Figure 31 A corrected second target pattern TP2'c is shown. The corrected second target pattern TP2'c may include a plurality of second extended patterns EP2. In some example embodiments, the plurality of second extended patterns EP2 may extend in the second horizontal direction D2 and may be spaced apart from each other in the first horizontal direction D1. In some example embodiments, the error pattern corresponding to the first final pattern may be a pattern formed to be smaller than the final target FT. The portion of the second target pattern TP2 corresponding to the first final target FT1 may be corrected. For example, the corrected second target pattern TP2'c may include a protruding pattern 310c on the left side of the first final target FT1 and a protruding pattern 312c on the right side of the first final target FT1.

[0088] Figure 32 is a conceptual diagram illustrating a method of segmenting and / or dividing the second mask layout L2c based on the corrected second target pattern TP2'c. Figure 33 is a conceptual diagram illustrating a process ( S140 b ) of correcting the second mask layout L2 c .

[0089] Reference Figure 32 and Figure 33 , the second extension pattern EP2 of the second mask layout L2c can be divided and / or split into a plurality of segments SG, and a target point P can be generated on each of the plurality of segments SG along the second target pattern TP2'c. Each segment SG can be set based on the position of the final target FT. For example, the center point of the segment SG corresponding to the first final target FT1 among the plurality of segments SG can be aligned with the center point of the first final target FT1 in the first horizontal direction D1. In some example embodiments, the endpoint of each segment SG can be set at the center point between the edge of the first final target FT1 and the edge of the final target FT adjacent to the first final target FT1 in the second horizontal direction D2. For example, the first final target FT1 can be spaced apart from the final target FT adjacent thereto by a specific width W2 in the second horizontal direction D2, and the endpoint of each segment SG can be set to divide the width W2 into two. Additionally or optionally, each segment SG can correspond to Figure 31 The plurality of segments SG may be offset in the positive direction.

[0090] Figure 34 The corrected second mask layout L2'c is shown. The corrected second mask layout L2'c may include a plurality of second extended patterns EP2'. The corrected second extended pattern EP2' may include a protrusion pattern 320c on the left side of the first final target FT1 and a protrusion pattern 322c on the right side of the first final target FT1.

[0091] Through Figure 29 and Figure 33 Segmenting and / or dividing the first and second mask layouts L1c and L2c as shown may adjust the error pattern more accurately. Additionally or alternatively, each segment SG may correspond to only one final target FT, and thus the layout may be corrected independently for each final target FT.

[0092] Refer again Figure 1 and Figure 2, with respect to the process of forming a mask (S150), a mask can be formed based on the designed mask layout. For example, a first photomask and a second photomask can be formed based on the first mask layout L1 and the second mask layout L2 that have been corrected in processes (S140a) and (S140b). The first photomask may correspond to a layer different from the second photomask. With respect to the process of forming a semiconductor device (S160), a first photoresist pattern and a second photoresist pattern can be formed by using the first photomask and the second photomask. For example, after forming the first photoresist pattern, a second photoresist covering the first photoresist pattern and the hard mask can be formed, and the second photoresist pattern can be formed by using the second photomask. By etching the hard mask using each of the first photoresist pattern and the second photoresist pattern as an etching mask, a plurality of final patterns can be achieved. The plurality of final patterns can be implemented as semiconductor patterns in the target layer by an etching process such as a dry etching and / or wet etching process.

[0093] Figures 35 to 37 are cross-sectional views for describing a method of manufacturing a photomask according to some example embodiments.

[0094] Reference Figure 35 The method of manufacturing a photomask according to some example embodiments of the inventive concepts may include processes of forming a plurality of reflective layers 420 and 430 on a mask substrate 410 and forming a capping layer 440 on the plurality of reflective layers 420 and 430 .

[0095] In some example embodiments, the photomask may be or correspond to an extreme ultraviolet (EUV) lithography mask. The mask substrate 410 may include a silicon layer, such as an amorphous silicon, polycrystalline silicon, and / or a single crystal silicon layer. The multiple reflective layers 420 and 430 may be or correspond to a layer in which multiple first material layers 420 and multiple second material layers 430 are alternately and repeatedly stacked. The multiple reflective layers 420 and 430 may be stacked by alternating the multiple first material layers 420 and the multiple second material layers 430. The multiple second material layers 430 may include a material different from / not included in the materials of the multiple first material layers 420. Each of the multiple first material layers 420 may include a silicon layer and may not include molybdenum. Each of the multiple second material layers 430 may include a molybdenum layer and may not include silicon. The capping layer 440 may include a ruthenium (Ru) layer.

[0096] Reference Figure 36 , a mask pattern 450 may be formed on the cover layer 440. The photomask 400 may include a mask pattern 450, a cover layer 440, the plurality of reflective layers 420 and 430, and a mask substrate 410. The mask pattern 450 may be based on the above reference Figures 1 to 34 The first mask layout and the second mask layout are described to form.

[0097] The process of forming the mask pattern 450 on the capping layer 440 may include a process of forming a thin layer using a process such as a chemical vapor deposition (CVD) process and a patterning process. The mask pattern 450 may include an absorber 460, an anti-reflection layer 470, and an opening portion 460T. The absorber 460 may directly contact the capping layer 440. The absorber 460 may include tantalum boron nitride (TaBN). The anti-reflection layer 470 may cover the absorber 460. The anti-reflection layer 470 may include lawrencium (Lr). The opening portion 460T may pass through the anti-reflection layer 470 and the absorber 460 to expose the top surface of the capping layer 440.

[0098] Reference Figure 37 , the photomask 400 may be or correspond to an EUV lithography mask.

[0099] In some example embodiments, in an EUV lithography system, light 480 (e.g., an EUV radiation beam generated by a light source device) may be projected toward a photomask 400 at an inclined incident angle. Light 480 may be projected toward the photomask 400 in an inclined manner to form an incident angle 490 relative to a vertical axis 500 perpendicular to the surface of the photomask 400. In some example embodiments, when the incident angle 490 is in a range of about 5 degrees to about 7 degrees, reflected light 510 may be projected toward a projection optical system (not shown) for performing an EUV lithography process. Due to the height of the mask pattern 450, a shadow region 520 may appear in the surface of the photomask 400. The shadow region 520 may be projected toward the photomask 400 in the above referenced manner. Figures 1 to 34 The described processes ( S140 a ) and ( S140 b ) of correcting the first mask layout and the second mask layout are reflected.

[0100] In some example embodiments, the mask may be a light-transmitting mask. The mask substrate 410 may include a light-transmitting substrate such as quartz. The plurality of reflective layers 420 and 430 and the cover layer 440 may be omitted. The mask pattern 450 may include a light-blocking layer such as a chromium (Cr) layer.

[0101] According to some example embodiments of the inventive concepts, since a target pattern and a mask layout are corrected based on an error pattern, the CD of a final target may be precisely or more precisely adjusted, and the layout may be independently improved and corrected for each final target.

[0102] In the above, some example embodiments have been described with reference to the accompanying drawings, but it is understood that those skilled in the art can implement the embodiments in another specific form without changing the inventive concept or essential features. It should be understood that the above embodiments are only examples in all aspects and are not restrictive.

[0103] This application claims the benefit of Korean Patent Application No. 10-2020-0098633 filed on August 6, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a mask, the method comprising: identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern, the first target pattern being a pattern implemented on a photoresist; dividing a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (a) a first extended pattern extending in a first horizontal direction, (b) final targets corresponding to the final pattern and arranged in a zigzag form, and (c) first final targets corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; as well as The first mask layout is corrected by shifting a plurality of first target segments corresponding to the first final target among the plurality of first segments.

2. The method according to claim 1, wherein an endpoint of each of the plurality of first target segments is between an edge of the first final target and an edge of a second final target, the second final target being adjacent to the first final target in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction. 3 . The method of claim 2 , wherein an endpoint of each of the plurality of first target segments is at a center point of a portion of the first final target, the portion overlapping with the adjacent second final target in the second horizontal direction. The method according to claim 1 , wherein each of the final goals corresponds to two first segments.

5. The method according to claim 1, wherein In response to the first final target overlapping the first extended pattern and a critical dimension of the error pattern being smaller than a critical dimension of the first final target, the correcting of the first mask layout includes shifting the plurality of first target segments in a positive direction.

6. The method of claim 1 , wherein in response to the first final target overlapping the first extended pattern and the error pattern being misaligned with other final patterns, the correcting of the first mask layout comprises shifting the plurality of first target segments in a direction opposite to a misalignment direction.

7. The method of claim 1 , wherein in response to the first final target not overlapping the first extended pattern and a critical dimension of the error pattern being relatively smaller than a critical dimension of the first final target, the correcting of the first mask layout comprises shifting the plurality of first target segments in a negative direction.

8. The method of claim 1 , wherein the correction of the first target pattern comprises: forming a marking layer overlapping the first final target; selecting a first error region from the marking layer; correcting the first error region from the marking layer; as well as The corrected first error region is reflected in the first target pattern.

9. The method of claim 1 , wherein correcting the first mask layout comprises: generating target points along the first target pattern; as well as The first target segment is offset so that a simulated contour of the first mask layout matches the target point.

10. The method according to claim 1, wherein each of the final targets has one of a quadrilateral shape, a circular shape, and an oval shape.

11. The method according to claim 1 , further comprising: correcting a second target pattern based on the error pattern, the second target pattern being a pattern implemented on a photoresist; dividing a second mask layout into a plurality of second segments based on the corrected second target pattern, the second mask layout including (a) a second extended pattern extending in a direction intersecting the first horizontal direction, (b) a final target corresponding to the final pattern, and (c) a first final target corresponding to the error pattern, each of the plurality of second segments corresponding to one of the final targets; as well as The second mask layout is corrected by shifting a plurality of second target segments corresponding to the first final target among the plurality of second segments. 12 . The method according to claim 11 , wherein the second extension patterns are arranged in a diagonal direction with respect to the first horizontal direction.

13. The method according to claim 12, further comprising: Prior to said correction of said second target pattern, rotating the second target pattern so that an edge of the final target and an edge of the second extended pattern are parallel to the first horizontal direction, Wherein the correction of the second mask layout comprises shifting the plurality of second target segments in the first horizontal direction.

14. A method for manufacturing a mask, the method comprising: identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern, the first target pattern being a pattern implemented on a photoresist; dividing a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (A) a first extended pattern extending in a first horizontal direction, (B) final targets corresponding to the final pattern and arranged in a lattice structure, and (C) first final targets corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; as well as The first mask layout is corrected by shifting a plurality of first target segments of the plurality of first segments corresponding to the first final target. 15 . The method of claim 14 , wherein an endpoint of each of the plurality of first target segments is between an edge of the first final target and an edge of a final target adjacent to the first final target in the first horizontal direction. 16 . The method of claim 15 , wherein an endpoint of each of the plurality of first target segments is at a center point between an edge of the first final target and an edge of an adjacent final target.

17. The method according to claim 14, further comprising: correcting a second target pattern based on the error pattern, the second target pattern being a pattern implemented on a photoresist; dividing a second mask layout into a plurality of second segments based on the corrected second target pattern, the second mask layout including (A) a second extended pattern extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, (B) a final target corresponding to the final pattern, and (C) a first final target corresponding to the error pattern, each of the plurality of second segments corresponding to one of the final targets; as well as The second mask layout is corrected by shifting a plurality of second target segments corresponding to the first final target among the plurality of second segments.

18. A method for manufacturing a semiconductor device, the method comprising: identifying an error pattern in a final pattern corresponding to a pattern on a substrate; correcting a first target pattern based on the error pattern, the first target pattern being a pattern implemented on a photoresist; dividing a first mask layout into a plurality of first segments based on the corrected first target pattern, the first mask layout including (A) a first extended pattern extending in a first horizontal direction, (B) a final target corresponding to the final pattern and arranged in a zigzag shape, and (C) a first final target corresponding to the error pattern, each of the plurality of first segments corresponding to one of the final targets; correcting the first mask layout by shifting a plurality of first target segments corresponding to the first final target among the plurality of first segments; forming a photomask based on the corrected first mask layout; forming a photoresist pattern by using the photomask; as well as A semiconductor pattern is formed on the substrate by using the photoresist pattern.

19. The method according to claim 18, wherein The forming of the photoresist pattern includes performing a photolithography process, and The photolithography process includes an extreme ultraviolet (EUV) photolithography process.

20. The method according to claim 19, wherein The forming of the photomask includes sequentially forming a mask substrate, a reflective layer, and a cover layer. The reflective layer includes a plurality of first material layers and a plurality of second material layers stacked alternately. The mask substrate comprises quartz, Each of the plurality of first material layers comprises a silicon layer, Each of the plurality of second material layers includes a molybdenum layer, and The capping layer includes a ruthenium layer.

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