Data storage device and data processing method

Abstract

The present invention relates to a memory controller for accessing a flash memory device, comprising a buffer memory and a microprocessor. The buffer memory comprises at least a first cache memory and a second cache memory. The microprocessor is used to control access to the flash memory device. The microprocessor obtains the number of empty blocks corresponding to the flash memory device in a first operation cycle, determines a write speed compensation amount according to the number of empty blocks, determines a target write speed according to the write speed compensation amount and a balance speed, and determines a target garbage collection speed according to the target write speed. The microprocessor further processes one or more write instructions received from a host device according to the target write speed in the first operation cycle, and performs at least one garbage collection operation according to the target garbage collection speed in the first operation cycle.

Description

Technical Field

[0001] The present invention relates to a data processing method, and more particularly to a data processing method that can effectively control the writing speed of a memory device to avoid significant writing delay. Background Art

[0002] As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as memory cards, solid state drives, embedded Multi Media Cards (eMMC) and Universal Flash Storage (UFS) that comply with Secure Digital (SD) / Multi Media Card (MMC) specifications, Compact Flash (CF) specifications, Memory Stick (MS) specifications and Extreme Digital (XD) specifications, have been widely used in a variety of applications. Therefore, efficient access control has become an important issue for these data storage devices.

[0003] In order to improve the access performance of a data storage device and avoid significant write delays that would cause a poor user experience, the present invention proposes a novel data processing method that can effectively control the write speed of a memory device so that the write speed can remain stable and will not be significantly reduced due to the execution of a garbage collection (GC) operation, thereby avoiding significant write delays. Summary of the invention

[0004] One purpose of the present invention is to provide a novel data processing method, which controls the number of empty blocks by controlling the ratio of the write speed to the garbage collection speed, thereby achieving the effect of stabilizing the number of empty blocks. When the number of empty blocks remains stable, the write speed can be correspondingly kept stable and will not drop significantly due to the execution of the garbage collection operation, thereby avoiding the generation of significant write delays.

[0005] According to one embodiment of the present invention, a memory controller is coupled to a host device and a flash memory device for accessing the flash memory device, and includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is used to control access to the flash memory device. The microprocessor obtains the number of empty blocks corresponding to the flash memory device in a first operation cycle, determines a write speed compensation amount according to the number of empty blocks, determines a target write speed according to the write speed compensation amount and a balance speed, and determines a target garbage collection speed according to the target write speed. The microprocessor further processes one or more write instructions received from the host device according to the target write speed in the first operation cycle, and performs at least one garbage collection operation according to the target garbage collection speed in the first operation cycle.

[0006] According to another embodiment of the present invention, a data processing method is applicable to a data storage device including a memory device and a memory controller, the memory device including multiple memory blocks, the method including: obtaining the number of empty blocks corresponding to a first operation cycle; determining a write speed compensation amount based on the number of empty blocks; determining a target write speed based on the write speed compensation amount and a balance speed; determining a target garbage collection speed based on the target write speed; processing one or more write instructions received from a host device according to the target write speed in the first operation cycle; and performing at least one garbage collection operation according to the target garbage collection speed in the first operation cycle.

[0007] According to another embodiment of the present invention, a data storage device is coupled to a host device, including a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks. The memory blocks include a plurality of empty blocks. The memory controller is coupled to the flash memory device for accessing the flash memory device. The memory controller obtains the number of empty blocks corresponding to an operation cycle, determines a write speed compensation amount according to the number of empty blocks, determines a target write speed according to the write speed compensation amount and a balance speed, and determines a target garbage collection speed according to the target write speed. The memory controller further processes one or more write instructions received from the host device according to the target write speed during the operation cycle, and performs at least one garbage collection operation according to the target garbage collection speed during the operation cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram showing a data storage device according to an embodiment of the present invention.

[0009] Figure 2 is a flow chart showing an exemplary data processing method according to an embodiment of the present invention.

[0010] Figure 3 is a flow chart showing another exemplary data processing method according to an embodiment of the present invention.

[0011] Figure 4 is a detailed flow chart showing a data processing method according to an embodiment of the present invention.

[0012] Figure 5 FIG. 1 is a diagram showing a feedback control system according to an embodiment of the present invention.

[0013] Figure 6 is another detailed flow chart showing a data processing method according to an embodiment of the present invention.

[0014] Explanation of symbols

[0015] 100: Data storage device

[0016] 110: memory controller

[0017] 112: Microprocessor

[0018] 112C: Program code

[0019] 112M: Read-only memory

[0020] 114: Control Logic

[0021] 116: Buffer memory

[0022] 118: Interface Logic

[0023] 120: memory device

[0024] 130: Host device

[0025] 132: Encoder

[0026] 134:Decoder

[0027] 501: Feedback Path DETAILED DESCRIPTION

[0028] In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention in the absence of one or more specific details or relying on other methods, elements or materials. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main concepts of the present invention.

[0029] References throughout this specification to "one embodiment," "an embodiment," "an example," or "an example" mean that the particular features, structures, or characteristics described in conjunction with the embodiment or example are included in at least one of the multiple embodiments of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," "in an example," or "in an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples.

[0030] In addition, in order to make the purpose, features and advantages of the present invention more clearly understood, the following specific embodiments of the present invention are specifically cited and described in detail with the accompanying drawings. The purpose is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented via software, hardware, firmware, or any combination thereof.

[0031] Figure 1 1 is a schematic diagram showing a data storage device 100 according to an embodiment of the present invention. The data storage device 100 includes a memory device 120, such as a flash memory module, and a memory controller 110. The memory controller 110 is used to access the memory device 120. According to an embodiment of the present invention, the memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the memory device 120. The control logic 114 includes an encoder 132 and a decoder 134. The encoder 132 is used to encode the data written into the memory device 120 to generate a corresponding check code (or error correction code, ECC). The decoder 134 is used to decode the data read from the memory device 120 .

[0032] In a typical case, the memory device 120 includes a plurality of flash memory chips or dies, and each flash memory chip or dies includes a plurality of memory blocks, and the controller (e.g., the memory controller 110 executing the program code 112C through the microprocessor 112) performs the operation of erasing data on the memory device 120 in units of blocks. In addition, a memory block may record (include) a specific number of data pages, i.e., physical data pages, wherein the controller (e.g., the memory controller 110 executing the program code 112C through the microprocessor 112) performs the operation of writing data on the memory device 120 in units of data pages.

[0033] In practice, the memory controller 110, which executes the program code 112C through the microprocessor 112, can use its own internal components to perform a variety of control operations, such as using the control logic 114 to control the access operation of the memory device 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130. The interface logic 118 can also be regarded as a front-end controller engine, which is used to transmit communication signals between the memory controller 110 and the host device 130, transmit data written / read by the host device 130, and control the work schedule of reading / writing data. The control logic 114 can also be regarded as a back-end controller engine, which is used to transmit communication signals between the memory controller 110 and the memory device 120, transmit data to be written / read from the memory device 120, perform corresponding encoding operations through the encoder 132 before writing the data into the memory device 120, and perform corresponding decoding operations on the data through the decoder 134 after reading the data from the memory device 120.

[0034] In one embodiment, the memory controller 110 communicates with the host device 130 via the interface logic 118 using a standard communication protocol. For example, the above-mentioned standard communication protocols include (but are not limited to): Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Compact flash (CF) interface standard, Multimedia Card (MMC) interface standard, Embedded Multimedia Card (eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard.

[0035] In one embodiment, the buffer memory 116 is implemented as a random access memory (RAM). For example, the buffer memory 116 may be a static random access memory (SRAM), but the present invention is not limited thereto.

[0036] In one embodiment, the data storage device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the data storage device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the data storage device 100 may be a solid state drive or an embedded storage device that complies with the Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0037] The host device 130 may issue commands, such as read commands or write commands, to the data storage device 100 to access data stored in the memory device 120 , or to further control and manage the data storage device 100 .

[0038] According to one embodiment of the present invention, the multiple memory blocks included in the memory device 120 may include a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and / or a triple-level cell (TLC) memory block. Each memory cell of the SLC memory block stores one bit of data, each memory cell of the MLC memory block stores two bits of data, and each memory cell of the TLC memory block stores three bits of data. According to one embodiment of the present invention, the memory device 120 is a 3D NAND-type flash memory.

[0039] Generally speaking, the memory device 120 can be logically divided into three areas, including a system area, a data area, and a spare area. Each area may include one or more memory blocks. The memory blocks belonging to the system area are used to store system data required for managing the memory device 120. The memory blocks belonging to the spare area are spare blocks (spare blocks) that do not store valid data, or empty blocks. The memory blocks belonging to the data area are used to store data received from the host device 130 (for example, user data). The memory controller 110 can select one or more memory blocks from the spare area as active memory blocks, or buffers, to receive and temporarily store data. When the active memory blocks are full, the memory controller 110 will update the active memory blocks to data blocks in the data area.

[0040] Since the user or the host device 130 may update the data content at any time, the data stored in the memory block may change from valid data to invalid data due to the subsequent write operation of the host device 130. For example, each memory block may include multiple storage units, wherein the size of a storage unit may correspond to, for example but not limited to, the size of a logical data page, or 4K bytes. Assuming that two storage units (for example, a first storage unit and a second storage unit) both point to the same logical data page, and this logical data page first points to the first storage unit in response to the first write operation, and then points to the second storage unit in response to the second write operation, it means that the data content corresponding to this logical data page has been updated from the content stored in the first storage unit to the content stored in the second storage unit. Therefore, the data stored in the second storage unit is valid data, and the data stored in the first storage unit becomes invalid data. Here, the aforementioned "pointing" means the mapping relationship between the logical address and the physical address. For example, the physical-to-logical mapping relationship of a physical storage unit UA pointing to a logical data page PB means that the data content stored in this physical storage unit UA is the data corresponding to this logical data page PB. Similarly, the logical-to-physical mapping relationship of a logical data page PB pointing to a physical storage unit UA means that the data corresponding to this logical data page PB is actually stored in the physical storage unit UA. When the physical-to-logical mapping relationship of a physical storage unit matches the logical-to-physical mapping relationship of the logical data page it points to, the data stored in this physical storage unit is valid data. The mapping relationship between the aforementioned logical address and the physical address can be recorded by the memory controller 110 in one or more mapping tables. The mapping table can be stored in the buffer memory 116 or the memory device 120, and the memory controller 110 can update the content of the mapping table according to the write operation of the host device 130, so that the mapping table can reflect the latest mapping relationship.

[0041] The memory controller 110 can trigger garbage collection (GC) according to some conditions. In the operation of garbage collection, the memory controller 110 can concentrate valid data scattered in different memory blocks (source memory blocks) in the same memory block (destination memory block) through data migration operations, and release the memory blocks that do not store valid data after the data migration as spare blocks, or empty blocks. For example, when the data stored in a memory block are all invalid data, the memory controller 110 can perform an erase operation on this memory block and update it as an empty block in the spare area, or mark it as a memory block belonging to the spare area. Thereafter, when the memory controller 110 needs a new memory block to store data, the memory controller 110 can directly select an empty block from the spare area.

[0042] In the prior art, the data storage device determines whether to trigger garbage collection based on the number of empty blocks. However, actual application results show that such control will cause a huge change in the write speed, thereby generating significant write delays. This is because the garbage collection operation includes read and write operations, which will occupy a lot of system resources of the data storage device. Therefore, when garbage collection is triggered, the write speed will decrease accordingly. When the execution volume of garbage collection is not properly planned and the data storage device needs to perform a large amount of garbage collection, the write speed will decrease significantly.

[0043] To solve the aforementioned problem, the present invention proposes a novel data processing method, which can effectively achieve the effect of stably controlling the number of empty blocks by adaptively controlling the write speed and garbage collection speed of the memory device. In this way, the write speed can be kept stable and will not be significantly reduced due to the execution of garbage collection operations, thereby avoiding the occurrence of significant write delays.

[0044] Figure 2 1 is a flow chart showing an exemplary data processing method according to one embodiment of the present invention. The data processing method may be executed by the memory controller 110 (eg, the memory controller 110 executing corresponding program codes via the microprocessor 112), and includes the following steps:

[0045] Step S202: Obtain the current number C of empty blocks.

[0046] Step S204: Determine the write speed compensation amount ω' according to the current number of empty blocks.

[0047] Step S206: Determine a target writing speed ω according to the writing speed compensation amount ω′ and a balance speed ω_B.

[0048] Step S208: Determine the target garbage collection rate g according to the target write rate ω.

[0049] Step S210: Process one or more write commands received from the host device according to the target write speed ω, and execute one or more corresponding write operations in response to the write commands, and execute garbage collection operations according to the target garbage collection speed g.

[0050] According to one embodiment of the present invention, the memory controller 110 can determine the time length T of an operation cycle based on the system clock and the work planning design within an operation cycle, wherein the work planning design of the operation cycle can be the content actually edited into the program code 112C during the product planning stage. For example, assuming that the content of the program code 112C is set to execute N lines of machine code in one operation cycle, the length T of the operation cycle can be equal to N times the system clock cycle.

[0051] According to one embodiment of the present invention, the memory controller 110 may repeatedly re-execute the Figure 2 Therefore, the current number of empty blocks C obtained in step S202 may be the result obtained corresponding to the current operation cycle (i.e., the number of empty blocks C obtained in different operation cycles may be the same value or different values), and after determining the target write speed ω and the target garbage collection speed g, the memory controller 110 may complete the write operation of writing the data from the host device (i.e., write data, or host data) into the memory device 120 and a predetermined number of garbage collection operations in the current operation cycle according to the target write speed ω and the target garbage collection speed g in step S210. After the current operation cycle ends, the memory controller 110 may re-obtain the number of empty blocks C corresponding to the next operation cycle, and re-determine the parameters such as the write speed compensation amount ω', the target write speed ω and the target garbage collection speed g corresponding to the next operation cycle, and process one or more write commands received from the host device according to the re-determined target write speed ω in the next operation cycle, and execute one or more corresponding write operations in response to the write command, and execute garbage collection operations according to the re-determined target garbage collection speed g.

[0052] It should be noted that the memory controller 110 may also be designed to obtain the current number of empty blocks C after executing the write operation and the garbage collection operation, and the number of empty blocks C obtained at this time will be provided for the next operation cycle. Figure 2 For example, if substantially the same result can be obtained, the execution order of step S202 can be arranged after step S210.

[0053] According to one embodiment of the present invention, the microprocessor 112 may be a dual-core microprocessor. The first core may be configured to execute steps S202 to S208. That is, the target write speed ω and the target garbage collection speed g associated with the current operation cycle are determined, and the size of the cache memory used in this operation cycle is configured according to these speeds. The second core may be configured to execute step S210. That is, after the cache memory is configured, the host write operation is started, the cache memory is used to temporarily store the write data received from the host device, and the data temporarily stored in the cache memory is written to the memory device 120, and the cache memory is used to perform a garbage collection operation to release the newly generated empty blocks while the write operation consumes the empty blocks.

[0054] More specifically, since the target write speed ω and the target garbage collection speed g can be defined by the amount of data processed per unit time, for example, how much host data is expected to be written within the time length of an operation cycle, and how many new empty blocks are expected to be generated within the time length of an operation cycle, the target write speed ω and the target garbage collection speed g are actually related to the amount of host data and the amount of garbage collection data that the microprocessor 112 is specified to process within an operation cycle, respectively. Therefore, after determining the target write speed ω and the target garbage collection speed g associated with the current operation cycle, the first core can configure the size of the cache memory used in this operation cycle according to these speeds.

[0055] For example, the memory controller 110 (or the first core of the microprocessor 112) may configure the size of a first cache memory used in the current operation cycle according to the target write speed ω. The first cache memory is used to temporarily store write data (i.e., host data) from the host device 130 to assist the memory controller 110 in executing one or more write instructions, and configure the size of a second cache memory used in the current operation cycle according to the target garbage collection speed g. The second cache memory is used to assist the memory controller 110 in performing garbage collection operations, for example, to temporarily store valid data collected from multiple memory blocks.

[0056] According to one embodiment of the present invention, the memory controller 110 may configure two predetermined storage spaces in the buffer memory 116 or an external random access memory (included in the data processing device 100 but configured outside the memory controller 110, not shown) to serve as the aforementioned first cache memory and second cache memory, and dynamically configure the usage range (usable memory space size) of the first cache memory and the second cache memory according to the currently determined target write speed ω and target garbage collection speed g in each operation cycle. By dynamically limiting the usage range of the cache memory according to the latest determined speed in each operation cycle, the result of controlling the write speed and the garbage collection speed is achieved.

[0057] According to an embodiment of the present invention, since the memory controller 110 dynamically re-determines the target write speed ω and the target garbage collection speed g in each operation cycle, the target write speed ω determined in two operation cycles can be the same value or different values. Similarly, the target garbage collection speeds determined in two operation cycles can be the same value or different values.

[0058] In addition, in the embodiment of the present invention, the equilibrium speed ω_B may be related to the read speed and / or write speed of the memory device 120. The following will introduce the determination method of each parameter in more detail.

[0059] Figure 3 It is a flow chart showing another exemplary data processing method according to one embodiment of the present invention, and is used to illustrate the start and end conditions of executing the data processing method proposed by the present invention.

[0060] Step S302: Execute general garbage collection operations.

[0061] Step S304: Determine whether the current number of empty blocks C is less than a critical value Cth, wherein the critical value Cth can be designed according to system requirements. In one embodiment of the present invention, the memory controller 110 can perform the determination of step S304 after the garbage collection operation is completed. If yes, then execute step S306. If no, then execute step S302.

[0062] Step S306: Apply the data processing method proposed by the present invention, for example, execute the following Figure 2 The process shown.

[0063] Step S308: Determine whether the target write speed ω is greater than the data write speed ω required by the host device 130. host The host device 130 may inform the memory controller 110 of the data writing speed it requires through a command or a signal. host , data writing speed ω hostIt can be defined by the amount of data required to be written by the host device 130 per unit time. Therefore, the data writing speed ω host In fact, it is related to the amount of write data required by the host device 130 or the write command issued. If yes, it means that after applying the data processing method proposed by the present invention, the target write speed ω set by the memory controller 110 is greater than the data write speed ω required by the host device 130. host Since the writing speed ω has been adjusted to be sufficient to cope with the data writing speed ω required by the host device 130 host , so the data processing method proposed by the present invention can be terminated. If not, the data processing method proposed by the present invention needs to be continued to be applied so that the writing speed ω can be properly controlled and kept stable.

[0064] Figure 4 1 is a detailed flow chart showing a data processing method according to an embodiment of the present invention, for illustrating detailed operations of the data processing method. The data processing method may be implemented by the memory controller 110 or the dual-core

[0065] The process is executed by the microprocessor 112 of the core and includes the following steps:

[0066] Step S402: Obtain the current number C of empty blocks.

[0067] Step S404: Calculate the difference between the number of empty blocks C and the threshold value Cth.

[0068] Step S406: Multiply the difference by a proportional control parameter K to determine the write speed compensation amount ω'. According to one embodiment of the present invention, the proportional control parameter K is used to amplify the aforementioned difference. When the proportional control parameter K is larger, the response speed of the proportional controller is faster. In the embodiment of the present invention, as long as the selected proportional control parameter K can satisfy the condition K*(C-Cth)≤ω max , then the proportional control parameter K can be selected arbitrarily, where ω max It is the maximum writing speed supported by the data processing device 100 .

[0069] Step S408: Calculate target writing speed in To balance the speed ω_B, β is a value related to the ratio of the time required for write operations and garbage collection operations, which will be introduced in the following paragraphs.

[0070] Step S410: configuring the size of the cache memory used to perform the write operation in the current operation cycle according to the target write speed ω.

[0071] Step S412: Calculate the target garbage collection rate g = β (ω max -ω).

[0072] Step S414: Allocate a cache size for performing garbage collection operations in the current operation cycle according to the target garbage collection speed g.

[0073] According to one embodiment of the present invention, assuming that T SR is the time required to read the data of one storage unit in the SLC memory block, T SP is the time required to write data to one storage unit of the SLC memory block, T TR is the time required to read the data of one storage unit in a TLC memory block, T TP is the time required to write data of a storage unit of a TLC memory block, and T is the time of an operation cycle. Then β can be calculated according to the content shown in the following Table 1:

[0074]

[0075] Table 1: Calculation method of β

[0076] The SLC on the left side of the table represents that the active memory block used for receiving host data is an SLC memory block, TLC represents that the active memory block used for receiving host data is a TLC memory block, scenario 1 represents that the source memory block in the garbage collection operation is an SLC memory block and the destination memory block is an SLC memory block, scenario 2 represents that the source memory block in the garbage collection operation is an SLC memory block and the destination memory block is a TLC memory block, scenario 3 represents that the source memory block in the garbage collection operation is a TLC memory block and the destination memory block is an SLC memory block, and scenario 4 represents that the source memory block in the garbage collection operation is a TLC memory block and the destination memory block is a TLC memory block. According to the active memory block type, source memory block type and destination memory block type configured in the current data storage device, the corresponding ratio β can be calculated.

[0077] Maximum write speed max It can be calculated according to the following Table 2:

[0078]

[0079] Table 2:ω max Calculation method

[0080] Similarly, the SLC on the left side of the table indicates that the active memory block used to receive the host data is an SLC memory block, and the TLC indicates that the active memory block used to receive the host data is a TLC memory block. According to the active memory block type currently configured in the data storage device, the corresponding maximum write speed ω can be calculated. max .

[0081] Figure 5 It shows a feedback control system according to an embodiment of the present invention, and this feedback control system can be completed by a proportional controller. As shown in the figure, the current number of empty blocks C is fed back to the proportional controller through the feedback path 501. The proportional controller multiplies the difference obtained by subtracting the current number of empty blocks C from the critical value Cth by -K to obtain the write speed compensation amount ω', and then adds the write speed compensation amount ω' to the balance speed ω_B to obtain the target write speed ω. The proportional controller also derives the target garbage collection speed g according to the target write speed ω as shown in step S412, and finally performs speed configuration (equivalent to the configuration of the cache memory) according to the obtained target write speed ω and target garbage collection speed g. After an operation cycle is completed, the current number of empty blocks C will be updated due to the results of the executed write operation and row garbage collection operation, and then fed back to the proportional controller through the feedback path 501.

[0082] One of the spirits of the present invention is that by controlling the ratio of the write speed (equivalent to the amount of host data written to the memory device 120) and the garbage collection speed (equivalent to the amount of data processed in the garbage collection operation), the number of empty blocks can be stably controlled. When the number of empty blocks is stably controlled, for example, the number of empty blocks is controlled to a certain value after one or more operation cycles, the write speed can be kept stable and will not be significantly reduced due to the execution of the garbage collection operation as in the prior art, thereby avoiding the generation of significant write delays and effectively solving the problems of the prior art.

[0083] Figure 6 is another detailed flow chart showing a data processing method according to an embodiment of the present invention. Figure 6 The process steps shown are similar to Figure 4 Similarly, steps S602 to S614 are the same as steps S402 to S414. Figure 4 The description paragraph will not be repeated here.

[0084] In this embodiment, whether the target writing speed ω is greater than the data writing speed ω required by the host device 130 is added. host As shown in the figure, after the target write speed ω is calculated in step S608, the memory controller 110 or the microprocessor 112 may further perform the following steps:

[0085] Step S616: Obtain the data writing speed currently required by the host device 130 host (As shown in the figure, the current host data writing speed ω host , which can be defined by the amount of write data required by the host device 130 per unit time).

[0086] Step S618: Determine whether the target write speed ω is greater than the data write speed ω required by the host device 130. host If yes, the process ends. If no, step S610 is executed to further configure the size of the cache memory used for performing the write operation in the current operation cycle according to the target write speed ω.

[0087] In summary, the data processing method proposed in the present invention can effectively achieve the effect of stably controlling the number of empty blocks by adaptively controlling the write speed and garbage collection speed of the memory device according to information such as the current number of empty blocks and the currently configured active memory block type, the source memory block type, and the destination memory block type. In this way, the write speed can be kept stable and will not be significantly reduced due to the execution of the garbage collection operation, thereby avoiding the occurrence of significant write delays.

[0088] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller, coupled to a host device and a flash memory device, for accessing the flash memory device, comprising: a buffer memory, comprising at least a first cache memory and a second cache memory; as well as a microprocessor for controlling access to the flash memory device, The microprocessor obtains a number of empty blocks corresponding to a first operation cycle of the flash memory device, determines a write speed compensation amount according to the number of empty blocks, determines a target write speed according to the write speed compensation amount and a balance speed, and determines a target garbage collection speed according to the target write speed. wherein the microprocessor further processes one or more write commands received from the host device according to the target write speed during the first operation cycle, and performs at least one garbage collection operation according to the target garbage collection speed during the first operation cycle, and The microprocessor further determines whether the target write speed is greater than a data write speed required by the host device, and when the target write speed is not greater than the data write speed required by the host device, the microprocessor re-determines the target write speed and the target garbage collection speed corresponding to a second operation cycle.

2. The memory controller according to claim 1, wherein: The microprocessor further configures the size of the first cache memory and the size of the second cache memory used in the first operation cycle according to the target write speed and the target garbage collection speed, the first cache memory is used to temporarily store write data from the host device to assist the microprocessor in executing the one or more write instructions, and the second cache memory is used to assist the microprocessor in executing the at least one garbage collection operation.

3. The memory controller according to claim 1, wherein: The microprocessor further obtains the number of empty blocks corresponding to the second operation cycle, redetermines the write speed compensation amount according to the number of empty blocks, redetermines the target write speed according to the redetermined write speed compensation amount and the balance speed, and redetermines the target garbage collection speed according to the redetermined target write speed, and wherein the microprocessor further processes one or more write instructions received from the host device according to the redetermined target write speed in the second operation cycle, and performs the at least one garbage collection operation according to the redetermined target garbage collection speed in the second operation cycle.

4. The memory controller according to claim 3, wherein: The target writing speed determined in the first operation cycle is different from the target writing speed re-determined in the second operation cycle.

5. The memory controller according to claim 3, wherein: The target garbage collection rate determined in the first operation cycle is different from the target garbage collection rate re-determined in the second operation cycle.

6. The memory controller according to claim 1, wherein: The equilibrium speed is related to a read speed of the flash memory device.

7. The memory controller according to claim 1, wherein: The equilibrium speed is related to a write speed of the flash memory device.

8. A data processing method, applicable to a data storage device, the data storage device comprising a memory device and a memory controller, the memory device comprising a plurality of memory blocks, the plurality of memory blocks comprising multiple empty blocks, the method comprising: Obtaining a number of empty blocks corresponding to a first operation cycle; Determine a write speed compensation amount according to the number of empty blocks; Determine a target writing speed according to the writing speed compensation amount and a balance speed; Determine a target garbage collection rate according to the target write rate; processing one or more write commands received from a host device according to the target write speed during the first operation cycle; Performing at least one garbage collection operation according to the target garbage collection rate in the first operation cycle; Determining whether the target write speed is greater than a data write speed required by the host device; as well as When it is determined that the target write speed is not greater than the data write speed required by the host device, the target write speed and the target garbage collection speed corresponding to a second operation cycle are re-determined.

9. The data processing method according to claim 8, characterized in that: Also includes: Allocating a size of a first cache memory used in the first operation cycle according to the target write speed, wherein the first cache memory is used to temporarily store write data from the host device to assist the memory controller in executing the one or more write commands; as well as A size of a second cache memory used in the first operation cycle is configured according to the target garbage collection speed, wherein the second cache memory is used to assist the memory controller in performing the at least one garbage collection operation.

10. The data processing method according to claim 8, characterized in that: Also includes: Obtaining the number of empty blocks corresponding to the second operation cycle; Re-determine the write speed compensation amount according to the number of empty blocks; Re-determine the target writing speed according to the re-determined writing speed compensation amount and the balance speed; Re-determining the target garbage collection rate according to the re-determined target write rate; and One or more write commands received from the host device are processed according to the re-determined target write speed in the second operation cycle, and at least one garbage collection operation is performed according to the re-determined target garbage collection speed in the second operation cycle.

11. The data processing method according to claim 10, characterized in that: The target writing speed determined in the first operation cycle is different from the target writing speed re-determined in the second operation cycle.

12. The data processing method according to claim 10, characterized in that: The target garbage collection rate determined in the first operation cycle is different from the target garbage collection rate re-determined in the second operation cycle.

13. The data processing method according to claim 8, characterized in that: The equilibrium speed is related to a read speed of the memory device.

14. The data processing method according to claim 8, characterized in that: The equilibrium speed is related to a write speed of the memory device.

15. A data storage device coupled to a host device, comprising: A flash memory device includes a plurality of memory blocks, wherein the plurality of memory blocks include multiple empty blocks; as well as a memory controller coupled to the flash memory device for accessing the flash memory device, wherein the memory controller obtains a number of empty blocks corresponding to an operation cycle, determines a write speed compensation amount according to the number of empty blocks, determines a target write speed according to the write speed compensation amount and a balance speed, and determines a target garbage collection speed according to the target write speed, wherein the memory controller further processes one or more write commands received from the host device according to the target write speed during the operation cycle, and performs at least one garbage collection operation according to the target garbage collection speed during the operation cycle, and The memory controller further determines whether the target write speed is greater than a data write speed required by the host device, and when the target write speed is not greater than the data write speed required by the host device, the memory controller re-determines the target write speed and the target garbage collection speed corresponding to the next operation cycle.

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