Method and apparatus for generating pseudo-random sequence, electronic device, storage medium
By employing AND and XOR operations in pseudo-random sequence generation, the problem of wasted device resources is solved, resulting in faster processing speed and higher device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANECHIPS TECH CO LTD
- Filing Date
- 2020-07-31
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies for generating pseudo-random sequences suffer from limitations in device performance due to memory usage and execution time. In particular, as the sequence length increases, this leads to wasted device resources and performance degradation.
A method for generating pseudo-random sequences is adopted by performing simple AND and XOR operations on M bit values. The (A+m)th bit value of the first sequence is obtained by performing AND and XOR operations on M bit values, and then the mth bit value of the pseudo-random sequence is obtained.
It improves computing speed, saves storage space and processor resources, thereby enhancing device performance.
Smart Images
Figure CN114063980B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communications, and in particular to methods and apparatus for generating pseudo-random sequences, electronic devices, and computer-readable storage media. Background Technology
[0002] Pseudo-random sequences are widely used in communication systems for channel estimation, signal scrambling, and frequency switching because they have good randomness and correlation properties close to white noise, and can be predetermined and are repeatable.
[0003] The Third Generation Partnership Project (3GPP) rd The Generation Partnership Project (GPP) Long Term Evolution (LTE) or New Radio (NR) standards use Gold sequences as pseudo-random sequences. Currently, the memory usage or execution time for generating Gold sequences increases with the sequence length, thus affecting device performance. Summary of the Invention
[0004] This application provides a method and apparatus for generating pseudo-random sequences, an electronic device, and a computer-readable storage medium.
[0005] In a first aspect, embodiments of this application provide a method for generating pseudo-random sequences, including:
[0006] Perform AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0;
[0007] The m-th bit value of the pseudo-random sequence is determined based on the (A+m)-th bit value of the first sequence.
[0008] Secondly, embodiments of this application provide an electronic device, including:
[0009] At least one processor;
[0010] A memory, on which at least one program is stored, which, when executed by the at least one processor, causes the at least one processor to implement any of the methods described above for generating pseudo-random sequences.
[0011] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the methods described above for generating pseudo-random sequences.
[0012] The method for generating a pseudo-random sequence provided in this application first performs simple AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, and then obtains the mth bit value of the pseudo-random sequence. Since the AND and XOR operations are simple logical operations, the operation speed is improved while saving storage space and processor resources, thereby improving the performance of the device. Attached Figure Description
[0013] Figure 1 A flowchart illustrating a method for generating pseudo-random sequences according to one embodiment of this application;
[0014] Figure 2 This is a schematic diagram illustrating AND and XOR operations performed in embodiments of this application;
[0015] Figure 3 A block diagram of an apparatus for generating pseudo-random sequences provided in another embodiment of this application. Detailed Implementation
[0016] To enable those skilled in the art to better understand the technical solutions of this application, the method and apparatus for generating pseudo-random sequences, electronic devices, and computer-readable storage media provided in this application will be described in detail below with reference to the accompanying drawings.
[0017] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.
[0018] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.
[0019] As used herein, the term “and / or” includes any and all combinations of at least one related enumerated entry.
[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.
[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.
[0022] The pseudo-random sequence used in 3GPP LTE or New Radio (NR) is a 31-bit Gold sequence. The polynomials used to generate the 31-bit Gold sequence are shown in equations (1) to (3):
[0023] c(n) = [x1(n+N)] C )+x2(n+N C )]mod2 (1)
[0024] x1(n+31)=[x1(n+3)+x1(n)]mod2 (2)
[0025] x2(n+31)=[x2(n+3)+x2(n+2)+x2(n+1)+x2(n)]mod2 (3)
[0026] Where, N C =1600.
[0027] According to the polynomial iteration relations (1) to (3), the sequence c(n) is based on x1(n+N). C ) and x2(n+N C The calculated values are used to initialize x1 as follows: x1(0) = 1, x1(n) = 0; n = 1, 2, 3... 30; the initial values of x2 are determined according to c. init Calculated, i.e. Then we can obtain x1(n+N) C ) sequence and x2(n+N C The sequence is obtained by processing the sequence c(n) to obtain the final c(n) sequence.
[0028] Currently, there are two methods for generating pseudo-random sequences:
[0029] The first method involves inputting the initial values of x1 and x2, and iterating through all sequences according to the polynomial iteration relationship (1) to (3). This method can be implemented using software or hardware, and it consumes less device resources (including memory and processor resources), but the calculation speed is low, which is not conducive to real-time calculation of generated scenarios.
[0030] The second method involves obtaining the initial state sequence V0 based on the initial values of x1 and x2, and deriving the one-step state transition matrix M from the current state sequence to the next state sequence using the iterative formula. The next state sequence can be obtained by multiplying the current state sequence by M. This process is repeated to generate all sequences, as shown below:
[0031] V1 = V0M;
[0032] V2 = V1M = V0M 2 ;
[0033] ...
[0034]
[0035] The advantage of the second method is that it utilizes the parallel processing capabilities of multiple computing units, enabling simultaneous calculation of 32-bit data. However, its disadvantage is that it requires calculations of M raised to the power of k, involving a large amount of accumulation and multiplication, which wastes significant storage space and processor resources, thus impacting device performance.
[0036] Figure 1 This is a flowchart illustrating a method for generating pseudo-random sequences according to an embodiment of this application.
[0037] Firstly, referring to Figure 1 One embodiment of this application provides a method for generating pseudo-random sequences, comprising:
[0038] Step 100: Perform AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence; where M is an integer greater than or equal to 1 and A is an integer greater than or equal to 0.
[0039] In some exemplary embodiments, M is less than or equal to the processor's bit width. Optimal performance is achieved when M equals the processor's bit width. For example, when the processor's bit width is 32, M can be any of 4, 8, 16, or 32, but performance is optimal when M is 32. Other cases follow the same principle.
[0040] In some exemplary embodiments, the M bit values include: the j-th bit value to the (j+M-1)-th bit value; where j is an integer greater than or equal to 0. For example, the M bit values include the 0-th bit value to the (M-1)-th bit value, or the 1-th bit value to the M-th bit value. This application does not limit which M bit values specifically refer to the M bit values.
[0041] In some exemplary embodiments, if the pseudo-random sequence to be generated is a Gold sequence, then the first sequence can be an x2 sequence. If the pseudo-random sequence to be generated is another sequence, the first sequence can also be another sequence. This application does not limit the specific form of the first sequence.
[0042] In some exemplary embodiments, performing AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence includes:
[0043] Combine the i-th bit value from the M bit values with k (m.i) Perform a bitwise AND operation to obtain the corresponding i-th intermediate bit value; where i is an integer greater than or equal to 1 and less than or equal to M, and k (m.i) Let m be the scaling factor corresponding to the i-th bit value and m; m is an integer greater than or equal to 0; XOR the M intermediate bit values to obtain the (A+m)-th bit value of the first sequence.
[0044] In some exemplary embodiments, k (m.i) The value of k is determined based on the original scaling factor of x2(i) obtained by splitting x2(A+m). When the original scaling factor of x2(i) obtained by splitting x2(A+m) is even, k (m.i) The value is 0; when the original scaling factor of x2(i) obtained by splitting x2(A+m) is odd, k (m.i) The value is 1.
[0045] Figure 2 The diagrams for AND and XOR operations are given using M=32 as an example. Figure 2 As shown, input 32 bit values, perform a bitwise AND operation between the 32 bit values and 32 k values to obtain 32 intermediate bit values, and perform an XOR operation between the 32 intermediate bit values to obtain the (A+m)th bit value.
[0046] In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, then A can take the value Nc, i.e., 1600. If the pseudo-random sequence is another sequence, A can also take other values, the specific value being determined according to the actual situation, as long as the value of A satisfies the calculation of the first bit value of the pseudo-random sequence. For the Gold sequence, since the first bit value of the Gold sequence is calculated based on x2(Nc), taking the value of A as Nc is the most efficient calculation method. Of course, A can also be different from Nc, but further iterative calculations are required to obtain the first bit value of the Gold sequence.
[0047] In some exemplary embodiments, the i-th bit value and k from the M bit values are... (m.i)Before performing the AND operation to obtain the corresponding i-th intermediate bit value, the method further includes: based on i, m, and k (m.i) The first correspondence between them determines k. (m.i) .
[0048] In some exemplary embodiments, the first correspondence can be implemented in various forms, such as a two-dimensional table, a two-dimensional array, or a two-dimensional matrix. If a two-dimensional table is used, the number of rows can be i, and the number of columns can be m; or, the number of rows can be m, and the number of columns can be i; each cell is k. (m.i) The corresponding values. Other cases follow the same logic and will not be elaborated here.
[0049] In some exemplary embodiments, AND and XOR operations can be performed serially or in parallel. The parallel approach fully utilizes the processor's arithmetic units, achieving rapid real-time generation of pseudo-random sequences, saving storage space, and improving the generation efficiency. For example, with four arithmetic units, through timing analysis and optimal segmentation (4 segments), a result of 4 bits can be calculated in one clock cycle. This means that for the first sequence, the AND operation of the 4 M bits can be performed simultaneously, thereby increasing the computation speed.
[0050] In some exemplary embodiments, performing AND and XOR operations in parallel may specifically include: performing AND and XOR operations on m corresponding to the same segment in parallel; wherein each segment includes N bit values, where N is an integer greater than or equal to 2; and the segment is a segment obtained by dividing the pseudo-random sequence.
[0051] In other words, the pseudo-random sequence is divided into at least one segment, and each segment includes N bit values of the pseudo-random sequence. The calculation process of the N bit values belonging to the same segment is performed in parallel. The calculation process of each bit value includes AND operation, XOR operation, and step 102.
[0052] In some exemplary embodiments, N is less than or equal to the maximum number of parallelisms supported by the processor.
[0053] The following uses the Gold sequence as an example to explain why performing AND and XOR operations on M features yields the (A+m)th bit value of the first sequence. Although the Gold sequence is used as an example here, it is not excluded that the generation process of other pseudo-random sequences can also adopt the method of the embodiments of this application.
[0054] According to the recursive formula for the x2 sequence, x2(n+31) = [x2(n+3) + x2(n+2) + x2(n+1) + x2(n)] mod 2, we can calculate x2(1570+31), that is:
[0055]
[0056] Since the mod2 operation reflects the parity of the result, we can add all the bits together and then perform the mod2 operation again, resulting in:
[0057]
[0058] The above formula can also be equivalent to k i The expression ×x2(i) is first modulo 2, then added together, and finally modulo 2 is performed again. Therefore, the above expression can be rewritten as:
[0059]
[0060] For [k] i [×x2(n)]mod2, since [k] i [×x2(n)]mod2=(k i mod2)×[x2(n)mod2], if k i If (i.e., the original proportionality coefficient) is even, then [k] i [×x2(n)]mod2=0; if k i If it is an odd number, then [k] i [×x²(n)]mod²=x²(n)mod²; Therefore, the above formula can be simplified to:
[0061] x2(1601)={[x2(1545)]mod2+[x2(1543)]mod2+[x2(1541)]mod2+[x2(1539)]mod2}mod2;
[0062] Then, x2(1545), x2(1543), x2(1541), and x2(1539) can be further split, and finally x2(1601) can be split into combinations of x2(n), where n∈[0,M-1], thus obtaining:
[0063]
[0064] Where, N C =1600, k (m.i) x2(i)∈[0,1].
[0065] Among them, y (m，i) =k (m，i)*x2(i) can be implemented using a bitwise AND operation on (M-1) bits, i.e., y (m，i) =k (m，i) *x2(i) is equivalent to y (m，i) =k (m，i) &x2(i), denoted as y(mi), since [x2(i)+x2(i+1)]mod2 is equivalent to x2(i)^x2(i+1), therefore x2(N C +m) can also be achieved through the XOR operation, that is:
[0066]
[0067] Here, ^ represents the XOR operation. That is, to obtain the (A+m)th bit value of the first sequence, we need to first perform a bitwise AND operation on the M bits, and then perform an M-bit XOR operation on the result of the M-bit AND operation to obtain the (A+m)th bit value of the first sequence, and then obtain the output of 1 bit value of the pseudo-random sequence.
[0068] Step 101: Determine the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence.
[0069] In some exemplary embodiments, the determination of N bit values belonging to the same segment in a pseudo-random sequence is performed in parallel.
[0070] In some exemplary embodiments, before performing AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further includes:
[0071] Calculate the M bit values of the first sequence based on the initial values of the first sequence.
[0072] The following example, using the pseudo-random sequence Gold, illustrates the calculation process for M bit values.
[0073] First, based on the initial value c init Calculate the values from the 0th bit to the 30th bit, which are the initial values of the first sequence. Specifically, according to the formula... Perform calculations;
[0074] Secondly, if there is a bit value in the first sequence that is greater than 30 among the M bit values, then calculate the bit value in the first sequence that is greater than 30 according to the recursive formula x2(n+31)=[x2(n+3)+x2(n+2)+x2(n+1)+x2(n)]mod2.
[0075] In some exemplary embodiments, before determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence, the method further includes: obtaining the (A+m)-th bit value of the second sequence according to a pre-set second correspondence between i and the i-th bit value of the second sequence; wherein i is an integer greater than or equal to 1 and less than or equal to M;
[0076] Accordingly, determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence includes: determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence and the (A+m)-th bit value of the second sequence.
[0077] In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, then the second sequence can be an x1 sequence. Each bit value of the x1 sequence can be calculated in advance according to the recursive formula x1(n+31)=[x1(n+3)+x1(n)]mod2 and stored. When a certain bit value of the second sequence is needed, it can be directly called.
[0078] In some exemplary embodiments, the second correspondence can be implemented in various forms, such as a one-dimensional table, a one-dimensional array, or a one-dimensional matrix. If a one-dimensional table is used, the row or column of the table can be i; the cell corresponding to each row or column is the i-th bit value of the second sequence. Other cases follow the same principle and will not be elaborated here.
[0079] In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, then the m-th bit value of the pseudo-random sequence is determined according to the recursive formula c(n) = [x1(n+N)]. C )+x2(n+N C The result is obtained by calculating mod2.
[0080] The method for generating a pseudo-random sequence provided in this application first calculates the M bit values of the first sequence, and then performs simple AND and XOR operations on the M bit values to obtain the (A+m)th bit value of the first sequence, thereby obtaining the mth bit value of the pseudo-random sequence. Since the AND and XOR operations are simple logical operations, they improve the calculation speed while saving storage space and processor resources, thereby improving the performance of the device.
[0081] It should be noted that the method for generating pseudo-random sequences provided in this application embodiment can be implemented in software or in hardware, for example, by using AND gates and XOR gates.
[0082] Secondly, embodiments of this application provide an electronic device, including:
[0083] At least one processor;
[0084] A memory, on which at least one program is stored, which, when executed by at least one processor, causes the at least one processor to implement any of the methods described above for generating pseudo-random sequences.
[0085] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH).
[0086] In some embodiments, the processor and memory are interconnected via a bus, and thus connected to other components of the computing device.
[0087] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the methods described above for generating pseudo-random sequences.
[0088] Figure 3 A block diagram of an apparatus for generating pseudo-random sequences provided in another embodiment of this application.
[0089] Fourthly, refer to Figure 3 Another embodiment of this application provides an apparatus for generating pseudo-random sequences, comprising:
[0090] The calculation module 301 is used to calculate the M bit values of the first sequence based on the initial value of the first sequence; where M is an integer greater than or equal to 1;
[0091] The logic operation module 302 is used to perform AND and XOR operations on M bit values to obtain the (A+m)th bit value of the first sequence; where A is an integer greater than or equal to 0;
[0092] The determination module 303 is used to determine the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence.
[0093] In some exemplary embodiments, the logic operation module 302 is specifically used for:
[0094] Combine the i-th bit value from the M bit values with k (m.i) Perform a bitwise AND operation to obtain the corresponding i-th intermediate bit value; where i is an integer greater than or equal to 1 and less than or equal to M, and k (m.i)Let m be the scaling factor corresponding to the i-th bit value and m; m is an integer greater than or equal to 0; XOR the M intermediate bit values to obtain the (A+m)-th bit value of the first sequence.
[0095] In some exemplary embodiments, the logic operation module 302 is further configured to:
[0096] Based on i, m and k (m.i) The first correspondence between them determines k. (m.i) .
[0097] In some exemplary embodiments, the AND and XOR operations corresponding to m of the same segment are performed in parallel, and the determination of bit values belonging to the same segment in the pseudo-random sequence is performed in parallel; wherein, each segment includes N bit values, where N is an integer greater than or equal to 2; the segment is a segment obtained by dividing the pseudo-random sequence.
[0098] In some exemplary embodiments, N is less than or equal to the maximum number of parallelisms supported by the processor.
[0099] In some exemplary embodiments, M is less than or equal to the bit width of the processor.
[0100] In some exemplary embodiments, the M bit values include: the j-th bit value to the (j+M-1)-th bit value; where j is an integer greater than or equal to 0.
[0101] In some exemplary embodiments, the method further includes: an acquisition module 304, configured to acquire the (A+m)th bit value of the second sequence according to a pre-set second correspondence between i and the i-th bit value of the second sequence; wherein i is an integer greater than or equal to 1 and less than or equal to M;
[0102] Accordingly, the determining module 303 is specifically used to: determine the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence and the (A+m)-th bit value of the second sequence.
[0103] The specific implementation process of the above-described device for generating pseudo-random sequences is the same as that of the method for generating pseudo-random sequences in the foregoing embodiments, and will not be repeated here.
[0104] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0105] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.
Claims
1. A method for generating pseudo-random sequences, comprising: Perform AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; The m-th bit value of the pseudo-random sequence is determined based on the (A+m)-th bit value of the first sequence; The step of performing AND and XOR operations on the M bits of the first sequence to obtain the (A+m)th bit value of the first sequence includes: Combine the i-th bit value from the M bit values with k (m.i) Perform a bitwise AND operation to obtain the corresponding i-th intermediate bit value; where i is an integer greater than or equal to 1 and less than or equal to M, and k (m.i) Let m be the scaling factor corresponding to the i-th bit value and m; where m is an integer greater than or equal to 0. The (A+m)th bit value of the first sequence is obtained by performing an XOR operation on the M intermediate bit values; The M is less than or equal to the bit width of the processor; The AND and XOR operations corresponding to m in the same segment are performed in parallel by multiple operation units, and the determination of bit values belonging to the same segment in the pseudo-random sequence is performed in parallel by multiple operation units; wherein, each segment includes N bit values of the pseudo-random sequence, where N is an integer greater than or equal to 2; the segment is a segment obtained by dividing the pseudo-random sequence; and N is less than or equal to the maximum number of parallel operations supported by the processor.
2. The method according to claim 1, wherein the i-th bit value and k of the M bit values are... (m.i) Before performing the AND operation to obtain the corresponding i-th intermediate bit value, the method further includes: Based on i, m and k (m.i) The first correspondence between them determines k. (m.i) .
3. The method according to claim 1, wherein, The M bit values include: the j-th bit value to the (j+M-1)-th bit value; where j is an integer greater than or equal to 0.
4. The method according to any one of claims 1-3, wherein before performing AND and XOR operations on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further comprises: Calculate the M bit values of the first sequence based on the initial value of the first sequence.
5. The method according to any one of claims 1-3, wherein before determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence, the method further comprises: According to the second correspondence between i and the i-th bit value of the second sequence, the (A+m)-th bit value of the second sequence is obtained; wherein i is an integer greater than or equal to 1 and less than or equal to M; Accordingly, determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence includes: determining the m-th bit value of the pseudo-random sequence based on the (A+m)-th bit value of the first sequence and the (A+m)-th bit value of the second sequence.
6. An electronic device, comprising: At least one processor; A memory storing at least one program that, when executed by the at least one processor, causes the at least one processor to implement the method for generating a pseudo-random sequence according to any one of claims 1-5.
7. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method for generating a pseudo-random sequence according to any one of claims 1-5.