Testing Method, System, Device and Storage Medium for Decoding Unit

Abstract

The present disclosure provides a test method, system, device, and storage medium for a decoding unit. The method includes: obtaining a target instruction; obtaining a set of approximate instruction codes according to the target instruction, where the set of approximate instruction codes includes multiple approximate instruction codes corresponding to the target instruction; obtaining multiple approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes; and testing the multiple approximate instructions to be tested using the decoding unit. The test method of the present disclosure can more comprehensively complete the verification of the target instruction and the approximate instructions of the target instruction, and verify whether the decoding unit can support the newly added instruction and work properly in the case of adding a new target instruction.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a test method, system, device, and storage medium for a decoding unit. Background Art

[0002] As a specialized unit for operation and logical control, a processor will refine and package common calculations or logical controls into a single instruction. When a user develops a program based on a specific processor platform, these instructions can be directly used to achieve specific goals without the need to concern about the hardware implementation. The combination composed of these instructions is called an instruction set. For the sake of hardware simplification, the instructions in the instruction set are relatively concise, and users need to perform secondary packaging at the software level to complete the final algorithm.

[0003] With the development of technology, the software's computing requirements for the processor are getting higher and higher. The implementation of some common algorithms at the software level can no longer meet the speed requirements and need to be converted into hardware implementation to speed up. Therefore, refining these algorithms into instructions and adding them to the instruction set is one direction of processor evolution. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a test method for a decoding unit, including: obtaining a target instruction; obtaining a set of approximate instruction codes according to the target instruction, where the set of approximate instruction codes includes a plurality of approximate instruction codes corresponding to the target instruction; obtaining a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes; and testing the plurality of approximate instructions to be tested using the decoding unit.

[0005] For example, in a test method provided by at least one embodiment of the present disclosure, obtaining a set of approximate instruction codes according to the target instruction includes: obtaining at least one legal instruction code of the target instruction; obtaining an instruction constraint table corresponding to the at least one legal instruction code; and obtaining the plurality of approximate instruction codes according to the instruction constraint table.

[0006] For example, in a test method provided by at least one embodiment of the present disclosure, obtaining the plurality of approximate instruction codes according to the instruction constraint table includes: randomly changing at least one in at least one constituent region of each of the at least one legal instruction code according to the instruction constraint table to form a plurality of approximate instruction code sequences, performing a legality mark on each of the plurality of approximate instruction code sequences, and marking at least one constituent region that has been randomly changed in each approximate instruction code sequence of the plurality of approximate instruction code sequences to form the plurality of approximate instruction codes.

[0007] For example, in a testing method provided by at least one embodiment of the present disclosure, the at least one constituent region is multiple constituent regions, and the multiple constituent regions include an opcode region, and one or more of the following regions: an instruction prefix region, an instruction map region, and an instruction operand region.

[0008] For example, in a testing method provided by at least one embodiment of the present disclosure, at least one of the at least one constituent region of each of the at least one legal opcode is randomly changed to form a plurality of approximate opcode sequences, including one or more of the following operations: performing a constrained random operation of selecting a random value within a preset range on the instruction prefix region; performing a constrained random operation of selecting a random value within a preset range on the instruction map region; performing a cross random operation on the opcode region to select a random value; performing a constrained random operation of differentiating validity on the instruction operand region to select a random value.

[0009] For example, in a testing method provided by at least one embodiment of the present disclosure, according to the instruction constraint table, obtaining the plurality of approximate opcodes further includes: checking the uniqueness of each of the plurality of approximate opcode sequences by determining the consistency of at least one constituent region of each of the plurality of approximate opcodes.

[0010] For example, in a testing method provided by at least one embodiment of the present disclosure, according to at least one legal format of the target instruction and the set of approximate opcodes, obtaining a plurality of approximate instructions to be tested corresponding to the target instruction includes: randomly mixing each of the plurality of approximate opcodes in the set of approximate opcodes with each of the at least one legal format of the target instruction to obtain the plurality of approximate instructions to be tested.

[0011] For example, in a testing method provided by at least one embodiment of the present disclosure, using the decoding unit to test the plurality of approximate instructions to be tested includes: obtaining a plurality of instruction groups to be tested according to the plurality of approximate instructions to be tested; obtaining a plurality of test cases, where each of the instruction groups to be tested has a corresponding test case selected from the plurality of test cases; and using the plurality of test cases to test each of the plurality of instruction groups to be tested in parallel.

[0012] For example, in a testing method provided by at least one embodiment of the present disclosure, obtaining a plurality of instruction groups to be tested according to the plurality of approximate instructions to be tested includes: dividing the plurality of approximate instructions to be tested into the plurality of instruction groups to be tested; or obtaining at least one legal instruction of the target instruction, mixing the plurality of approximate instructions to be tested and the at least one legal instruction to obtain an instruction mixture set, and dividing all the instructions to be tested included in the instruction mixture set into the plurality of instruction groups to be tested.

[0013] For example, in a test method provided by at least one embodiment of the present disclosure, each of the plurality of instruction groups under test is tested in parallel using the plurality of test cases, including: for the decoding test of the current instruction under test corresponding to each of the instruction groups under test, in response to the current instruction under test being an illegal instruction, performing a jump operation so that after the current instruction under test is decoded, the test jumps to the next instruction under test.

[0014] For example, in a test method provided by at least one embodiment of the present disclosure, performing a jump operation so that after the current instruction under test is decoded, the test jumps to the next instruction under test includes: reloading an exception response function; decoding the current instruction under test; in response to an exception being triggered, executing the exception response function, setting the return address to the initial address of the next instruction under test to jump to the test of the next instruction under test, and in response to no exception being triggered, reporting a test error.

[0015] For example, in a test method provided by at least one embodiment of the present disclosure, each of the plurality of instruction groups under test is tested in parallel using the plurality of test cases, including: for the decoding test of the current instruction under test corresponding to each of the instruction groups under test, in response to the current instruction under test being a legal instruction: in response to no exception being triggered and the decoding execution result of the current instruction under test not being consistent with the expected result, reporting a test error; in response to no exception being triggered and the decoding execution result of the current instruction under test being consistent with the expected result, directly jumping to the decoding test of the next instruction under test; in response to an exception being triggered, reporting a test error.

[0016] At least one embodiment of the present disclosure provides a test system for a decoding unit, including: an instruction acquisition module configured to acquire a target instruction; an approximate instruction code acquisition module configured to acquire a set of approximate instruction codes according to the target instruction, the set of approximate instruction codes including a plurality of approximate instruction codes corresponding to the target instruction; and a to-be-tested instruction acquisition module configured to acquire a plurality of to-be-tested approximate instructions corresponding to the target instruction according to the legal format of the target instruction and the set of approximate instruction codes, wherein the plurality of to-be-tested approximate instructions are configured to be tested by the decoding unit.

[0017] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the test method described in any one of the above is implemented.

[0018] At least one embodiment of the present disclosure provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the testing method described in any of the above examples is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the composition of an instruction code;

[0021] Figure 2 Schematic diagram of the principle of decoding;

[0022] Figure 3 Schematic diagram of the comparison of some instructions;

[0023] Figure 4 Partial schematic diagram of an instruction map;

[0024] Figure 5 Flowchart of the testing method for the decoding unit provided by some embodiments of the present disclosure;

[0025] Figure 6 Provided by some embodiments of the present disclosure Figure 5 Flowchart of step S2 in;

[0026] Figure 7 Provided by some embodiments of the present disclosure Figure 5 Flowchart of step S4 in;

[0027] Figure 8 Flowchart of the decoding test of the corresponding currently tested instruction in each tested instruction group provided by some embodiments of the present disclosure;

[0028] Figure 9 Block diagram of a testing system provided by some embodiments of the present disclosure; and

[0029] Figure 10 Block diagram of an electronic device provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the embodiments of the present disclosure.

[0032] The "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Terms such as "a", "an" or "the" do not denote a quantity limitation either, but mean that there is at least one. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the steps before or after do not necessarily have to be carried out precisely in order. On the contrary, they can be carried out in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0033] Currently, for the instruction codes of some complex instruction sets, they generally consist of four regions: instruction prefix (Prefix), instruction map (Map), opcode (Opcode) and instruction operand (Operand). For example, the decoding order is carried out in the order of Prefix -> Map -> Opcode -> Operand, as Figure 1 shown. When the instruction does not meet the above instruction format, it is considered an illegal instruction code.

[0034] As Figure 1As shown, instruction prefixes are used to distinguish certain specific instruction sets (e.g., to mark newly added instruction sets) or to override the behavior of existing instruction sets. Instruction maps are used to mark instruction maps (e.g., to refer to a specific instruction table). The opcode is used to mark a unique position in a specific instruction map, thereby specifying the decoding entry and core behavior of the instruction. That is, the opcode represents a unique encoding position in the specified instruction map and characterizes the basic behavior of the instruction. Instruction operands represent the original operands required by the instruction and can carry operands or be extended using a predefined format.

[0035] As Figure 2 As shown, the inventors of the present disclosure found that the decoding process includes: first, determining whether the instruction needs to be overridden and whether it belongs to a certain specific instruction set based on the instruction prefix, then finding the corresponding instruction map entry according to the instruction map, finding the unique encoding position according to the opcode in the specified instruction map, and finally parsing the instruction operands to complete the decoding.

[0036] As Figure 3 As shown, the opcode encodings of instruction a and instruction b are the same, but instruction a and instruction b belong to different instruction maps. Therefore, instruction a and instruction b are not the same instruction. For example, the instruction maps and opcode encodings of instruction b and instruction c are the same, but when instruction prefix A is an instruction set marker, instruction b and instruction c are not the same instruction. For example, when both instruction prefix B and instruction prefix C are simple instruction override symbols, instruction d and instruction e are different forms of the same instruction.

[0037] In this regard, the inventors of the present disclosure found that in addition to being characterized by a unique opcode, a single instruction also has some format constraints, such as not allowing certain specific instruction prefixes to be carried. For example, if it is agreed that instruction c does not support instruction prefix B, but the encoding of instruction c is added with instruction prefix B when input to the decoding unit, then the instruction code of the current instruction is considered an illegal instruction code. Thus, instruction codes that do not meet the instruction constraints are illegal instruction codes.

[0038] As Figure 4As shown, the horizontal direction is the low 4-bit hexadecimal encoding of the opcode, and the vertical direction is the high 4-bit hexadecimal encoding of the opcode. For example, there are only four defined instructions A / B / C / D in the instruction map, and the opcode encodings are 0x22 / 0x21 / 0x42 / 0x44 respectively. Then for instruction A, the encodings of instruction B and instruction C are only 4 bits different from instruction A, and can be called approximate instructions of instruction A. The encoding of instruction D is completely different from instruction A and does not belong to the approximate instruction of instruction A. Undefined encodings are called instruction holes, that is, blank positions in the instruction map where valid instruction codes are not marked. For example, 0x33 or 0x23, which do not have agreed instructions represented by the encoding in the instruction map, belong to instruction holes. The instruction set generally does not fill the entire instruction map. When the opcode part of the instruction code falls on the instruction hole, the instruction code is considered to be an illegal instruction code.

[0039] Therefore, the inventors of the present disclosure have found that generally, only when the instruction structure and instruction constraints are met and there is a defined operation code in the unique instruction map, can it be identified as a legal instruction code, otherwise, it is an illegal instruction code. In other words, only when there is a defined instruction code in the decoding table of the decoding unit can it be considered as a legal instruction code, otherwise it is an illegal instruction code, that is, except for all defined legal instruction codes, the remaining ones are illegal instruction codes.

[0040] The inventors of the present disclosure further discovered that current applications have higher requirements for computing accuracy. For example, it may be necessary to expand the basic functions of the original instructions, or to expand the operand precision, but there is no need to replace the instruction code. At this time, some instruction prefixes will be added to overload the instructions, which requires support from a decoding unit.

[0041] The inventors of the present disclosure also discovered that the expansion of the instruction set and instruction overloading have put forward new requirements for the verification of the decoding unit. For example, while ensuring that the newly added instructions are decoded normally, it is also necessary to ensure that approximate inputs are not incorrectly translated into existing or newly added correct instructions, and the amount of test traversal is relatively large.

[0042] In this regard, at least one embodiment of the present disclosure provides a testing method for a decoding unit, comprising: obtaining a target instruction; obtaining a set of approximate instruction codes based on the target instruction, wherein the set of approximate instruction codes includes multiple approximate instruction codes corresponding to the target instruction; obtaining multiple approximate instructions to be tested corresponding to the target instruction based on at least one legal format of the target instruction and the set of approximate instruction codes; and using a decoding unit to test the multiple approximate instructions to be tested.

[0043] The test method of the above-mentioned embodiment of the present disclosure can more comprehensively complete the verification of the target instruction (such as the newly added instruction) and the instructions similar to the target instruction, and verify whether the decoding unit can support the newly added instruction and work normally when the target instruction is newly added.

[0044] Figure 5 Flowchart of a test method for a decoding unit provided by some embodiments of the present disclosure.

[0045] For example, as Figure 5 shown, the test method for a decoding unit provided by at least one embodiment of the present disclosure includes steps S1 to S4.

[0046] Step S1: Obtain a target instruction.

[0047] Step S2: According to the target instruction, obtain a set of approximate instruction codes, where the set of approximate instruction codes includes multiple approximate instruction codes corresponding to the target instruction.

[0048] Step S3: According to at least one legal format of the target instruction and the set of approximate instruction codes, obtain multiple to-be-tested approximate instructions corresponding to the target instruction.

[0049] Step S4: Use the decoding unit to test multiple to-be-tested approximate instructions.

[0050] Thus, the test method of the above embodiments of the present disclosure can more comprehensively complete the verification of the target instruction (such as a newly added instruction) and the approximate instructions of the target instruction, verifying whether the decoding unit can support the newly added instruction and whether the decoding unit can work properly when a new target instruction is added.

[0051] For example, in step S1, the target instruction refers to an instruction that needs to be newly added to the original instruction set. It should be noted that the following mainly takes the target instruction as a newly added instruction as an example for illustration, but the embodiments of the present disclosure are not limited thereto.

[0052] In some examples, the obtained target instruction can be one or more, and for each target instruction, the tests can be performed according to steps S1 to S4. For example, the embodiments of the present disclosure can simultaneously perform the tests according to the above steps S1 to S4 for multiple different target instructions respectively.

[0053] In some examples, the instruction code is the hexadecimal encoding corresponding to the instruction. This is only exemplary and not a limitation of the present disclosure. For example, it can also be other radix encodings, which will not be elaborated here.

[0054] Figure 6 For some embodiments of the present disclosure Figure 5 Flowchart of step S2 in

[0055] For example, as Figure 6 shown, for step S2, obtaining the set of approximate instruction codes according to the target instruction includes steps S21 to S23.

[0056] Step S21: Obtain at least one legal instruction code of the target instruction.

[0057] Step S22: Obtain an instruction constraint table corresponding to the at least one legal instruction code.

[0058] Step S23: Obtain a plurality of approximate instruction codes according to the instruction constraint table.

[0059] Thus, the embodiments of the present disclosure generate a plurality of approximate instruction codes corresponding to the target instruction based on the legal instruction codes in the instruction constraint table, which can reduce the workload. For example, each time a new target instruction is added, only the instruction constraint table needs to be maintained, and other parts can be basically reused, so the efficiency is high and the operation is convenient.

[0060] In some examples, the instruction code includes at least one constituent region. For example, the at least one constituent region includes an operation code region. For another example, the at least one constituent region is a plurality of constituent regions, and the plurality of constituent regions may include not only the operation code region, but also one or more of an instruction prefix region, an instruction map region, and an instruction operand region. In this way, it is beneficial for the test method to cover a sufficient number of test scenarios. This is only exemplary and not a limitation of the present disclosure. For example, the instruction code of the present disclosure may also be in other constituent forms, which will not be elaborated here. It should be noted that the embodiments of the present disclosure do not limit the bit width of each constituent region of the instruction code. For example, the bit width of the operation code region may be 1 bit or 2 bits, which will not be limited and elaborated here.

[0061] In some examples, when defining an instruction, at least one of the instruction prefix, the instruction map, and the instruction operand may not be carried. For example, an instruction may carry multiple instruction prefixes, and may not carry them when using the basic instruction set and no overloading is required. For example, the instruction map may not be carried when using the basic instruction set. For example, the instruction operand may not be carried when the instruction does not require the original operand.

[0062] For example, the test method of the embodiments of the present disclosure is applicable to any instruction by means of table lookup and decoding, that is, the specific form of the table is not limited, which will not be elaborated here.

[0063] The inventors of the present disclosure have found that for the verification in the case of adding a new target instruction, it is not only necessary to ensure the decoding correctness of the agreed legal instruction code format, but also necessary to ensure that it does not affect the decoding correctness of the approximate instruction positions of the same instruction map or different instruction maps, and to be able to correctly identify an illegal instruction when the operation code is unique but the instruction prefix, the instruction map, and the instruction operand do not meet the constraints.

[0064] In some examples, a target instruction has multiple legal instruction codes. For example, it has three legal instruction codes, namely A, B, and C. In this case, the instruction code scenarios that can be covered by the approximate instruction code of the target instruction include at least one of the following situations:

[0065] The first situation: Only change the operation code area of the legal instruction code, that is, the obtained instruction code is an approximate instruction encoding located in the same instruction map as the target instruction. If the obtained instruction code is a defined or agreed legal instruction code, it is normally decoded into the corresponding instruction instead of adding a new instruction; if it falls into an instruction hole, it is reported as illegal.

[0066] The second situation: Only change the instruction map area of the legal instruction code, that is, the obtained instruction code is the same encoding as the target instruction but located in a different instruction map. If the obtained instruction code is a defined or agreed legal instruction code, it is normally decoded into the corresponding instruction instead of adding a new instruction. If it falls into an instruction hole, it is reported as illegal.

[0067] The third situation: Only change the instruction prefix area of the legal instruction code. If the decoding table supports it, it is normally decoded; if it violates the constraints, it is reported as illegal.

[0068] The fourth situation: Only change the instruction operand area of the legal instruction code. If the decoding table supports it, it is normally decoded; if it violates the constraints, it is reported as illegal.

[0069] The fifth situation: Any two or more of the instruction prefix area, instruction map area, operation code area, and instruction operand area are changed. If the obtained instruction code has a legal instruction code, it is normally decoded into the corresponding instruction; otherwise, it is reported as illegal.

[0070] In some examples, the changes in the above embodiments may include the behavior of replacing values or the behavior of deleting values. It should be noted that the scenarios that can be covered by the approximate instruction code of the target instruction illustrated in the above embodiments are only exemplary and are not limitations on the embodiments of the present disclosure.

[0071] Thus, the embodiments of the present disclosure can generate approximate instruction codes that cover a sufficient number of scenarios.

[0072] For example, for step S21, in some examples, at least one legal instruction code corresponding to the target instruction can be multiple legal instruction codes, and the multiple legal instruction codes corresponding to the target instruction are generally defined or agreed by the specifications of a specific project.

[0073] For example, for step S22, in some examples, by adding the values of the respective block formation regions (such as Prefix, Map, Opcode, Operand) of all legal instruction codes of the target instruction to the instruction constraint table, that is, adding all the legal instruction codes corresponding to the target instruction to the instruction constraint table, an instruction constraint table corresponding to the at least one legal instruction code can be obtained, which can be used to generate approximate instruction codes and identify whether the generated approximate instruction codes are legal. For example, all the legal instruction codes corresponding to the target instruction can be manually added to the instruction constraint table, and the instruction constraint table only constrains correct legal instruction codes.

[0074] In some examples, based on the instruction constraint table corresponding to the previous project, if a new project is updated on this basis and the multiple original legal instruction codes in the original instruction constraint table do not need to be concerned about or do not affect the new project, etc., only new legal instruction codes need to be added to the original instruction constraint table. This is only exemplary and not a limitation of the embodiments of the present disclosure.

[0075] For example, for step S23, in some examples, obtaining multiple approximate instruction codes according to the instruction constraint table includes the following steps or processes: according to the instruction constraint table, randomly change at least one in at least one block formation region of each legal instruction code in the at least one legal instruction code to form multiple approximate instruction code sequences, and perform a legality mark on each of the multiple approximate instruction code sequences and mark at least one block formation region that has been randomly changed in each approximate instruction code sequence in the multiple approximate instruction code sequences to form multiple approximate instruction codes. In this way, the test method of the embodiments of the present disclosure is not only efficient but also can generate a sufficiently comprehensive set of approximate instruction codes, which can cover most of the test scenarios that need to be verified, such as the instruction code scenarios involved in the above embodiments.

[0076] In some examples, randomly changing at least one in at least one block formation region of each of the at least one legal instruction code to form multiple approximate instruction code sequences includes one or more of the following operations: (a) performing a constrained random operation of selecting a random value within a preset range on the instruction prefix region; (b) performing a constrained random operation of selecting a random value within a preset range on the instruction map region; (c) performing a cross random operation on the opcode region to select a random value; (d) performing a constrained random operation with validity discrimination on the instruction operand region to select a random value. In this way, randomness under the above constraints can effectively reduce the number of approximate instruction codes, and a relatively reasonable set of approximate instruction codes for testing can be obtained, which can avoid unnecessary invalid tests and also avoid the problem that the test convergence speed is seriously affected due to the excessive number of approximate instruction codes obtained.

[0077] In some examples, for operations (a) and (b), regarding the instruction prefix and the instruction map, there are fewer valid values, and random values can be selected from the legal range, so as to avoid the problem of too many invalid tests caused by using all random values.

[0078] In some examples, for operation (c), generally for extensibility considerations, the bit width of the opcode is at least 1 byte, that is, at least 256 opcodes can be accommodated in one instruction table. Thus, by using the cross-random method, that is, fixing the upper half and the lower half of the opcode respectively and randomizing the remaining part, the problem that the number of approximate instruction codes obtained by using all random values is too large in magnitude and seriously affects the test convergence speed can be avoided.

[0079] In some examples, for operation (d), due to the precision requirements of the instruction operands, there are generally too many valid values. The randomization of the instruction operand area can be simply distinguished between valid and invalid, that is, perform constraint randomization on the instruction operand area to distinguish validity to select random values.

[0080] In some examples, for the validity and invalidity of the instruction operands, they can be determined according to the original definition of the instruction, that is, the defined ones are valid and the undefined ones are invalid. For example, if the instruction is agreed to support 16 logical registers, then these 16 registers are all considered valid operands. If the instruction is agreed to support 32-bit wide memory, then the addresses from 0x0 to 0xFFFFFFFF are all considered valid operands.

[0081] In some examples, for operation (c), it includes: selecting random values for the opcode area of the legal instruction codes in the instruction constraint table and keeping the values of other areas of the legal instruction codes unchanged, thereby obtaining the corresponding approximate instruction codes. Similarly, for operations (a), (b), and (d), random values can be similarly selected for at least one constituent area of the legal instruction codes in the instruction constraint table and keeping the values of other constituent areas unchanged to obtain the corresponding approximate instruction codes, which will not be elaborated here.

[0082] For marking the constituent areas that have been randomly changed for each approximate instruction code sequence, in some examples, it can be marked by adding comments. For example, append a specific character sequence after the approximate instruction code sequence and the character sequence can be customized as long as it will not be mistaken for an instruction code. The embodiments of the present disclosure do not limit this.

[0083] Similarly, the method for performing a legality mark on each approximate instruction code sequence is similar to the method for marking the randomly modified constituent regions of each approximate instruction code sequence, and can be referred to the description above, which will not be elaborated here. Before performing the legality mark, it is also necessary to judge the legality of the approximate instruction code sequence according to the instruction constraint table, which is not the focus of the present disclosure and will not be elaborated here.

[0084] For example, for step S23, in some examples, obtaining multiple approximate instruction codes according to the instruction constraint table further includes the following steps or processes: by judging the consistency of at least one constituent region of each approximate instruction code among the multiple approximate instruction codes, checking the uniqueness of each approximate instruction code sequence among the multiple approximate instruction code sequences. In this way, unnecessary repeated tests are avoided due to the non-uniqueness of the approximate instruction codes, and the simulation time is not prolonged due to repeated tests. For example, when the four constituent regions (such as Prefix, Map, Opcode, Operand) of the randomly generated approximate instruction code are exactly the same as those of the previously generated approximate instruction code, it indicates that the currently generated approximate instruction code is not unique.

[0085] For example, for step S3, in some examples, obtaining multiple approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes includes the following processes or steps: randomly mixing each approximate instruction code among the multiple approximate instruction codes in the set of approximate instruction codes with each of at least one legal format of the target instruction to obtain multiple approximate instructions to be tested. In this way, the embodiments of the present disclosure can obtain multiple approximate instructions to be tested that are relatively reasonable and can cover a sufficient number of test scenarios.

[0086] The inventors of the present disclosure also found that generally, for processors with complex instruction sets, multiple instruction maps and multiple instruction prefixes are supported, and the random range is relatively large. As a result, the number of tested instructions included in the finally generated set of tested instructions is generally in the tens of thousands or hundreds of thousands. If a single simulation task is used to serially complete the test of all tested instructions, although the hardware resources are not overly occupied, the single simulation convergence time is very long. For example, it may last for several days or more than ten days, and such a long duration is basically unacceptable.

[0087] Figure 7 For some embodiments of the present disclosure Figure 5 The flowchart of step S4.

[0088] For example, as Figure 7 shown, for step S4, using the decoding unit to test multiple approximate instructions to be tested includes steps S41 to S43.

[0089] Step S41, obtaining multiple groups of tested instructions according to multiple approximate instructions to be tested.

[0090] Step S42: Acquire multiple test cases, wherein each instruction group under test has a corresponding test case selected from the multiple test cases.

[0091] Step S43: Use multiple test cases to test each of the multiple tested instruction groups in parallel.

[0092] Therefore, the embodiments of the present disclosure use multiple test cases to implement traversal testing of multiple instruction groups under test in parallel, which can reduce the simulation time to complete the testing of all instruction groups under test, and can use limited hardware resources to complete the verification work as quickly as possible, thereby reducing the total simulation time.

[0093] In some examples, the above-mentioned parallel testing is implemented by LSF clustering. In this way, parallel testing is easier to implement, easier to manage, and has good scalability. This is only exemplary and is not a limitation of the present disclosure. As long as the parallel testing of all the approximate instructions to be tested can be implemented, it will not be repeated here.

[0094] For example, for step S41, in some examples, obtaining multiple instruction groups to be tested according to multiple approximate instructions to be tested includes the following process or steps: dividing the multiple approximate instructions to be tested into multiple instruction groups to be tested. In this way, the embodiments of the present disclosure can implement mixed testing of legal instructions and illegal instructions, and the test method covers more test scenarios.

[0095] For another example, for step S41, in other examples, obtaining multiple instruction groups to be tested according to multiple approximate instructions to be tested includes the following processes or steps: obtaining at least one legal instruction of the target instruction, mixing multiple approximate instructions to be tested and at least one legal instruction to obtain an instruction mixed set, and dividing all the instructions to be tested included in the instruction mixed set into multiple instruction groups to be tested. In this way, the test method of the embodiment of the present disclosure covers more scenarios and the simulation time is longer.

[0096] It should be noted that the embodiments of the present disclosure can also remove legal instructions from the generated multiple approximate instructions to be tested, and only test the illegal instructions from the multiple approximate instructions to be tested separately, which makes the test simpler and shortens the simulation time. Since this is not the focus of the present disclosure, it will not be described in detail.

[0097] For example, for step S43, in some examples, testing each of the multiple instruction groups under test in parallel using multiple test cases includes the following processes or steps: For the decoding test of the current instruction under test corresponding to each instruction group under test, in response to the current instruction under test being an illegal instruction, a jump operation is performed so that after the current instruction under test is decoded, the test jumps to the next instruction under test. In this way, the embodiments of the present disclosure can selectively insert reload operations according to the legal expectation of the instruction under test, so that after an exception is triggered, the test of the next instruction under test can still continue as soon as possible, avoiding the simulation from not proceeding in sequence due to a jump error caused by a failure in decoding an illegal instruction. That is, the embodiments of the present disclosure can successfully complete the traversal test of all instructions under test. Compared with the method of using one test case for each instruction under test to avoid exceptions, the embodiments of the present disclosure will not cause problems such as simulation difficulties due to a large number of parallel simulation tasks occupying a large amount of hardware resources.

[0098] In some examples, multiple generated approximate instructions to be tested are read by an automatic tool, and multiple test cases are adopted by comprehensively considering the execution time of a single instruction under test and the hardware resources available for the project, so as to use multiple simulation tasks to perform parallel simulation. In this way, the simulation time for completing the tests of all instructions under test can be reduced, and the number of parallel simulation tasks that can be performed simultaneously is limited by the hardware resources of the specific project.

[0099] In some examples, performing a jump operation so that after the current instruction under test is decoded, the test jumps to the next instruction under test includes the following processes or steps: (1) Reloading the exception response function; (2) Decoding the current instruction under test; (3) In response to an exception being triggered, executing the exception response function, and pointing the return address to the initial address of the next instruction under test to jump to the test of the next instruction under test, and in response to no exception being triggered, reporting a test error. In this way, by directly reloading the response function, the jump position can be pointed to the beginning of the next instruction under test, which can reduce the execution of some instructions that are not concerned, thereby reducing the simulation time.

[0100] For example, for step S43, in some examples, testing each of the multiple instruction groups under test in parallel using multiple test cases includes the following processes or steps:

[0101] For the decoding test of the current tested instruction corresponding to each tested instruction group, in response to the current tested instruction being a legal instruction: if no exception is triggered and the decoding execution result of the current tested instruction is inconsistent with the expected result, the test reports an error; if no exception is triggered and the decoding execution result of the current tested instruction is consistent with the expected result, directly jump to the decoding test of the next tested instruction; if an exception is triggered in response, the test reports an error. In this way, the embodiments of the present disclosure can test the decoding of legal tested instructions by the decoding unit.

[0102] Figure 8 It is a flowchart of the decoding test of the current tested instruction corresponding to each tested instruction group provided by some embodiments of the present disclosure.

[0103] For example, as Figure 8 shown, the decoding test of the current tested instruction corresponding to each tested instruction group includes steps T41 to T49.

[0104] Step T41, start the decoding test of the current tested instruction.

[0105] Step T42, determine whether the current tested instruction is illegal: if so, continue to execute step T43; if not, go to step T47.

[0106] Step T43, reload the exception response function and point the return address to the initial address of the next tested instruction.

[0107] Step T44, perform decoding on the current tested instruction.

[0108] Step T45, determine whether the current tested instruction triggers an exception: if so, continue to execute step T46; if not, go to step T49.

[0109] Step T46, execute the exception response function, jump to the test of the next tested instruction, and regard the next tested instruction as the current tested instruction for the next test, then go to step T41 to loop until all the tested instructions in the tested instruction group are tested.

[0110] Step T47, determine whether the current tested instruction triggers an exception: if so, go to step T49; if not, go to step T48.

[0111] Step T48, determine whether the decoding execution result of the current tested instruction is inconsistent with the expected result: if so, go to step T49; if not, go to step T46.

[0112] Step T49, the test reports an error.

[0113] In some examples, in the case of a test error where it is determined in step T45 that the current instruction under test does not trigger an exception and the process proceeds to step T49, it indicates that the decoding unit fails to decode the illegal instruction under test.

[0114] In some examples, in the case of a test error where it is determined in step T47 that the current instruction under test does not trigger an exception and the process proceeds to step T49, it indicates that the decoding unit fails to decode the legal instruction under test.

[0115] In some examples, in the case where it is determined in step T48 that the decoding execution result of the current instruction under test is inconsistent with the expected result, it indicates that the decoding unit fails to decode the legal instruction under test. For example, it is possible that the generated operation code after decoding is incorrect.

[0116] In some examples, in the case where it is determined in step T48 that the decoding execution result of the current instruction under test is consistent with the expected result, that is, no exception is triggered and the execution result is correct, it indicates successful decoding and the normal operation of the decoding unit.

[0117] Thus, each individual test case in the multiple test cases adopted in the embodiments of the present disclosure can complete the testing of multiple instructions under test, enabling the overall traversal testing of all instructions under test to be quickly completed using relatively reasonable resources, thereby accelerating verification convergence.

[0118] Figure 9 It is a block diagram of a test system for a decoding unit provided by some embodiments of the present disclosure.

[0119] For example, as Figure 9 shown, a test system 100 for a decoding unit provided by at least one embodiment of the present disclosure includes an instruction acquisition module 101, an approximate instruction code acquisition module 102, and a to-be-tested instruction acquisition module 103. The instruction acquisition module 101 is configured to acquire a target instruction. The approximate instruction code acquisition module 102 is configured to acquire a set of approximate instruction codes according to the target instruction, and the set of approximate instruction codes includes multiple approximate instruction codes corresponding to the target instruction. The to-be-tested instruction acquisition module 103 is configured to acquire multiple to-be-tested approximate instructions corresponding to the target instruction according to the legal format of the target instruction and the set of approximate instruction codes, where the multiple to-be-tested approximate instructions are configured to be tested by the decoding unit 301.

[0120] It should be noted that in the embodiments of the present disclosure, the test system 100 for the decoding unit may include more or fewer modules, and the connection relationship between the various modules is not limited and can be determined according to actual needs. The specific composition manner of each module is not limited. For the technical effects of the test system 100 for the decoding unit, reference can be made to the technical effects of the test method for the decoding unit provided in the above embodiments of the present disclosure, which will not be elaborated here.

[0121] Each module in the above embodiments can be separately configured as software, hardware, firmware, or any combination of the above for performing specific functions. For example, these modules can correspond to dedicated integrated circuits, or pure software code, or modules combining software and hardware.

[0122] It should be noted that although the test system for the decoding unit is divided into modules for separately performing corresponding processes as described above, however, those skilled in the art are aware that the processes performed by each module can also be executed when the test system does not perform any specific module division or there is no clear demarcation between the modules.

[0123] Figure 10 The structural schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 10 The illustrated electronic device is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0124] For example, as Figure 10 shown, in some examples, the electronic device 200 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 201, which can execute the above-described test method according to a program stored in the read-only memory (ROM) 202 or a program loaded from the storage device 208 into the random access memory (RAM) 203. In the RAM 203, various programs and data required for the operation of the computer system are also stored. The processing device 201, the ROM 202, and the RAM 203 are connected to each other through a bus 204. The input / output (I / O) interface 205 is also connected to the bus 204.

[0125] For example, the following components can be connected to the I / O interface 205: an input device 206 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 207 including, such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 208 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, a modem, etc. The communication device 209 can allow the electronic device 200 to communicate with other devices wirelessly or wiredly to exchange data and perform communication processing via a network such as the Internet. The driver 310 is also connected to the I / O interface 205 as needed. A removable medium 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver 310 as needed so that a computer program read from it can be installed into the storage device 208 as needed. Although Figure 10 the electronic device 200 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. More or fewer devices can be alternatively implemented or included.

[0126] For example, the electronic device 200 can further include a peripheral interface (not shown in the figure), etc. The peripheral interface can be various types of interfaces, for example, a USB interface, a Lightning interface, etc. The communication device 209 can communicate with a network and other devices through wireless communication. The network can be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0127] For example, the electronic device can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or can be any combination of an electronic device and hardware. The embodiments of the present disclosure are not limited thereto.

[0128] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 209, or installed from the storage device 208, or installed from the ROM 202. When the computer program is executed by the processing device 201, the above-described test function for the decoding unit defined in the method of the embodiment of the present disclosure is executed.

[0129] It should be noted that the above-mentioned computer-readable medium in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device. In an embodiment of the present disclosure, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0130] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0131] The above computer-readable medium can be included in the above electronic device; it can also exist separately and not be assembled into the electronic device.

[0132] It should be noted that in the embodiments of the present disclosure, for the specific functions and technical effects of the electronic device 200, reference can be made to the description of the test method for the decoding unit in the above text, and details will not be elaborated here.

[0133] The following points need to be noted:

[0134] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0135] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0136] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A test method for a decoding unit, comprising: Obtaining a target instruction; According to the target instruction, obtaining a set of approximate instruction codes, wherein the set of approximate instruction codes includes a plurality of approximate instruction codes corresponding to the target instruction; According to at least one legal format of the target instruction and the set of approximate instruction codes, obtaining a plurality of approximate instructions to be tested corresponding to the target instruction; Testing the plurality of approximate instructions to be tested by using the decoding unit; Wherein, obtaining the set of approximate instruction codes according to the target instruction includes: Obtaining at least one legal instruction code of the target instruction; Obtaining an instruction constraint table corresponding to the at least one legal instruction code; According to the instruction constraint table, obtaining the plurality of approximate instruction codes; Wherein, obtaining the plurality of approximate instruction codes according to the instruction constraint table includes: According to the instruction constraint table, randomly changing at least one in at least one constituent region of each of the at least one legal instruction code to form a plurality of approximate instruction code sequences, and performing a legality mark on each of the plurality of approximate instruction code sequences and marking at least one constituent region that has been randomly changed in each approximate instruction code sequence of the plurality of approximate instruction code sequences, to form the plurality of approximate instruction codes.

2. The test method according to claim 1, wherein, The at least one constituent region is a plurality of constituent regions, and the plurality of constituent regions include an opcode region, and one or more of the following regions: an instruction prefix region, an instruction map region, and an instruction operand region.

3. The test method according to claim 2, wherein Randomly changing at least one in at least one constituent region of each of the at least one legal instruction code to form a plurality of approximate instruction code sequences includes one or more of the following operations: Performing a constrained random operation of selecting a random value within a preset range on the instruction prefix region; Performing a constrained random operation of selecting a random value within a preset range on the instruction map region; Performing a cross random operation on the opcode region to select a random value; Performing a constrained random operation of differentiating validity on the instruction operand region to select a random value.

4. The test method according to claim 2, wherein, According to the instruction constraint table, obtaining the plurality of approximate instruction codes further includes: Checking the uniqueness of each of the plurality of approximate instruction code sequences by judging the consistency of at least one constituent region of each of the plurality of approximate instruction codes.

5. The testing method according to any one of claims 1 to 4, wherein, According to at least one legal format of the target instruction and the set of approximate instruction codes, obtaining a plurality of approximate instructions to be tested corresponding to the target instruction includes: Randomly mixing each of the plurality of approximate instruction codes in the set of approximate instruction codes with each of the at least one legal format of the target instruction to obtain the plurality of approximate instructions to be tested.

6. The testing method according to any one of claims 1 to 4, wherein, Testing the plurality of approximate instructions to be tested by using the decoding unit includes: Obtaining a plurality of groups of instructions to be tested according to the plurality of approximate instructions to be tested; Obtaining a plurality of test cases, wherein each group of instructions to be tested has a corresponding test case selected from the plurality of test cases; Using the plurality of test cases to test each group of instructions to be tested in the plurality of groups of instructions to be tested in parallel.

7. The test method according to claim 6, wherein, Obtain a plurality of instruction groups to be tested according to the plurality of approximate instructions to be tested, including: Dividing the plurality of approximate instructions to be tested into the plurality of instruction groups to be tested; or, Obtain at least one legal instruction of the target instruction, mix the plurality of approximate instructions to be tested and the at least one legal instruction to obtain an instruction mixing set, and divide all the instructions to be tested included in the instruction mixing set into the plurality of instruction groups to be tested.

8. The testing method according to claim 7, wherein, Use the plurality of test cases to test each of the plurality of instruction groups to be tested in parallel, including: For the decoding test of the current instruction to be tested corresponding to each of the instruction groups to be tested, in response to the current instruction to be tested being an illegal instruction, perform a jump operation so that after the current instruction to be tested is decoded, jump to the test of the next instruction to be tested.

9. The testing method according to claim 8, wherein, Performing a jump operation so that after the current instruction to be tested is decoded, jump to the test of the next instruction to be tested, including: Overload the exception response function; Decode the current instruction to be tested; In response to an exception being triggered, execute the exception response function, point the return address to the initial address of the next instruction to be tested to jump to the test of the next instruction to be tested, and in response to no exception being triggered, report a test error.

10. The test method according to claim 7, wherein, Use the plurality of test cases to test each of the plurality of instruction groups to be tested in parallel, including: For the decoding test of the current instruction to be tested corresponding to each of the instruction groups to be tested, in response to the current instruction to be tested being a legal instruction, In response to no exception being triggered and the decoding execution result of the current instruction to be tested not being consistent with the expected result, report a test error; In response to no exception being triggered and the decoding execution result of the current instruction to be tested being consistent with the expected result, directly jump to the decoding test of the next instruction to be tested; In response to an exception being triggered, report a test error.

11. A test system for a decoding unit, including: An instruction acquisition module configured to acquire a target instruction; An approximate instruction code acquisition module configured to acquire a set of approximate instruction codes according to the target instruction, the set of approximate instruction codes including a plurality of approximate instruction codes corresponding to the target instruction; An instruction to be tested acquisition module configured to acquire a plurality of approximate instructions to be tested corresponding to the target instruction according to the legal format of the target instruction and the set of approximate instruction codes, wherein the plurality of approximate instructions to be tested are configured to be tested by the decoding unit; Wherein, acquiring a set of approximate instruction codes according to the target instruction includes: Acquire at least one legal instruction code of the target instruction; Obtain an instruction constraint table corresponding to the at least one legal instruction code; Obtain the plurality of approximate instruction codes according to the instruction constraint table; Wherein, obtaining the plurality of approximate instruction codes according to the instruction constraint table includes: According to the instruction constraint table, at least one in at least one constituent area of each of the at least one legal instruction code is randomly changed to form a plurality of approximate instruction code sequences, and each of the plurality of approximate instruction code sequences is marked for legality and at least one constituent area that has been randomly changed in each approximate instruction code sequence of the plurality of approximate instruction code sequences is marked to form the plurality of approximate instruction codes.

12. An electronic device, comprising: a processor and a memory, wherein, a computer program is stored on the memory, and when the computer program is executed by the processor, the testing method according to any one of claims 1 to 10 is implemented.

13. A computer-readable storage medium, wherein, A computer program is stored in the storage medium, and when the computer program is executed by a processor, the testing method according to any one of claims 1 to 10 is implemented.

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