Chip encapsulation post-adaptive communication interface architecture and chip communication system based on same

Abstract

The application discloses a chip sealing post-adaptive communication method and a chip communication system based on the same. The chip sealing post-adaptive communication method comprises the following steps: S1, powering on two chips for communication; S2, resetting and driving the two chips for communication; S3, dividing the two chips for communication into a chip a and a second chip b through serial numbers; and S4, respectively executing the work of the chip a and the chip b. The chip sealing post-adaptive communication method and the chip communication system based on the same solve the problem that the chip a and the chip b cannot be connected for communication when the chip distribution position is limited in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multi-chip integrated packaging, and particularly relates to a chip interface architecture adaptive communication method for physical connection under different packaging modes and a chip communication system based on the method. BACKGROUND

[0002] In a multi-chip integrated packaging system, a plurality of small chips need to be integrated in an integrated chip, and the multi-chip integrated system mainly involves two technologies: first, a physical position relationship of an interface circuit adapted to different packaging stacking relationships (that is, a physical position relationship between small chips and small chips); and second, an adaptive information communication technology of the interface circuit (that is, communication between chips and chips). Through the two technologies, the same architecture of the interface circuit design can be used in the small chip stacking structure under different packaging, and the communication system between chips can be quickly detected and established. Thus, the multi-chip system can be flexibly used in different packaging systems to achieve high integration, small size, and few interfaces of the modern chip system production requirements. The two technologies will be further described below.

[0003] The communication interface system between chips: each chip includes a bus control layer, a digital physical layer, and an analog interface layer, and the analog interface layer undertakes an important task when two chips communicate with each other. The analog interface layer is provided with TX pins and RX pins, and the TX pins and the RX pins achieve tasks such as data signal and clock signal transmission. Figure 1 As shown in Figures 1 to 5 , the circles on the chip represent the starting point of the chip. It is worth noting that: first, only when the TX pin and the RX pin are connected, the mutual communication between the chips can be achieved; second, when the chips are connected in communication, there can be multiple pairs of TX pins and RX pins; and third, the TX pin and the RX pin have polarity, that is, divided into positive P and negative N.

[0004] The physical position relationship between chips: the physical position relationship between chips has multiple types, which can be "horizontal parallel type" (as shown in Figure 2 ), "overlapping type" (as shown in Figure 4 ), and the like. The physical position relationship between chips directly affects the size of the whole chip, the processing difficulty, the wiring inside the chip, and the like. Figure 3 This "overlapping type" is not allowed in the chip manufacturing process, because the wiring needs to pass through the gap between the two chips.

[0005] In order to achieve mass production, it is necessary to produce Figure 5Multiple chips (e.g., chip a and chip b) are shown. During the manufacturing process, chip a and chip b need to be arranged together in an "overlapping" manner. Chip a and chip b are connected to form a chip communication system. The TX pin of chip a is directly opposite the TX pin of chip b, and the RX pin of chip a is directly opposite the RX pin of chip b. Other pins are also directly opposite. For the convenience of wiring, it is necessary to connect the TX pin of chip a to the TX pin of chip b, and the RX pin of chip a to the RX pin of chip b. However, if the custom programs inside chip a and chip b are fixed, that is, the TX pin and RX pin of chip a are fixed, then the above connection cannot realize the communication connection between chip a and chip b.

[0006] In summary, in order to meet the needs, when mass production of chips is achieved, it is not possible to meet the chip connection and communication requirements under different packaging and stacking methods (that is, when different packaging and stacking methods meet the physical positional relationship, chip communication may not be possible). Summary of the Invention

[0007] This invention provides an adaptive communication method after chip packaging and a chip communication system based thereon, which solves the problem that the existing technology cannot meet the chip connection and communication requirements under different packaging and stacking methods.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] This invention first discloses an adaptive communication method after chip packaging, based on the premise that the RESET pin of each chip is located in the middle of the chip, and that the RX pin and TX pin of each chip are symmetrically distributed on both sides of the RESET pin, including the following steps:

[0010] S1. Power on the two communicating chips;

[0011] S2. Reset and drive the two communicating chips;

[0012] S3. The two communicating chips are divided into chip a and chip b by serial number;

[0013] S4. Chips a and b perform their respective tasks in the handshake communication between the TX and RX pins:

[0014] The tasks performed by chip a include: sending a specified signal to chip b through chip a's TX pin and determining whether the specified signal has been received by chip b through chip RX pin;

[0015] Meanwhile, the work performed by the chip b includes: judging whether the TX pin and the RX pin are reversed by judging whether the specified signal is in the TCKP / TCKN differential signal of the TX pin or in the RCKP / RCKN differential signal of the RX pin, and if reversed, then performing the TX pin and RX pin exchange;

[0016] Step S2 includes: S21, the chip a and the chip b drive the RESET pin to high level; S22, in the two chips communicating with each other, each chip waits for the reference reset signal input on the INPUT signal line to be high level, and stops driving the RESET pin;

[0017] Step S3 includes: S31, in the two chips communicating with each other, each chip judges whether to wait for the pad_reset signal of the RESET pin to be equal to 0, and if yes, then proceeds to step S32; S32, then drives the chip serial number of each chip to the RESET pin; S33, in the two chips communicating with each other, each chip judges whether to satisfy the condition that whether the serial number of itself is less than the received serial number; if yes, then judges that itself is the chip a; if not, then judges that itself is the chip b.

[0018] Preferably, after the step S4 is performed, the step S5 is further performed, and the work performed in the step S5 includes: judging whether the positive P and the negative N are reversed by judging whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or in the RCKN signal of the RCKP / RCKN differential signal, and if reversed, then performing the positive P and negative N switching; if not reversed, then no operation is performed.

[0019] Preferably, the work performed by the chip a in the step S4 includes the following steps:

[0020] S411, driving the TX pin to send the specified signal to the chip b;

[0021] S412, waiting for the RCKP / RCKN differential signal received on the RX pin of itself to be the received specified signal;

[0022] S413, detecting whether the RCKP / RCKN differential signal is the specified signal from the chip b, and if yes, then proceeds to the step S5; if not, then outputs a detection failure fail.

[0023] Preferably, the work performed by the chip b in the step S4 includes the following steps:

[0024] S421, the signal on the RX pin of the chip is a differential signal of RCKP / RCKN, the signal on the TX pin is a differential signal of TCKP / TCKN, and the specified signal sent by the chip a is expected to enter the differential signal of RCKP / RCKN or the differential signal of TCKP / TCKN of the chip b;

[0025] S422, it is judged whether the specified signal sent by the chip a is in the differential signal of RCKP / RCKN or the differential signal of TCKN of the chip b; if yes, step S423 is performed; if no, a detection failure fail is outputted;

[0026] S423, it is continuously judged whether the specified signal sent by the chip a is in the differential signal of RCKP / RCKN of the chip b; if no, step S424 is performed; if yes, it is judged that the RX pin of the chip b is connected to the TX pin of the chip a;

[0027] S424, the RX pin and the TX pin of the chip b are exchanged.

[0028] The application further discloses a chip communication system based on the chip sealing and adaptive communication method, characterized by comprising the chip a and the chip b, the RESET pin of each chip is in the middle of the chip, the RX pin and the TX pin of each chip are symmetrically distributed on both sides of the RESET pin, and the chip a and the chip b communicate with each other.

[0029] The chip a comprises:

[0030] A first power-on module for powering on the chip a;

[0031] A first reset driving module for resetting and driving the chip a;

[0032] A first classification module for classifying the chip a;

[0033] A first communication task execution module for sending the specified signal to the chip b through the TX pin of the chip a, and judging whether the specified signal of the chip b is received through the RX pin;

[0034] The chip b comprises:

[0035] A second power-on module for powering on the chip b;

[0036] A second reset driving module for resetting and driving the chip b;

[0037] A second classification module for classifying the chip b;

[0038] The second communication task execution module is used for judging whether the TX pin and the RX pin are reversed by judging whether the specified signal is on the TCKP / TCKN differential signal of the TX pin or on the RCKP / RCKN differential signal of the RX pin, and if reversed, the TX pin and the RX pin are exchanged.

[0039] Preferably, the chip a further comprises a first polarity determination module, and the chip b further comprises a second polarity determination module.

[0040] The first polarity determination module and the second polarity determination module are both used for judging whether the positive pole P and the negative pole N are reversed by judging whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or in the RCKN signal of the RCKP / RCKN differential signal, and if reversed, the positive pole P and the negative pole N are switched; if not reversed, no operation is performed.

[0041] Compared with the prior art, the present application has the following beneficial effects:

[0042] 1) The chip distribution position limited demand can be met first in production, the original TX pin of the chip a is connected with the original TX pin of the chip b, and the original RX pin of the chip a is connected with the original RX pin of the chip b, so that the production operation is avoided due to the connection of the TX pin and the RX pin in production, the production is facilitated, and the production efficiency is improved.

[0043] 2) The internal wiring of the integrated chip is also simplified, the connection of the TX pin and the RX pin in error position is avoided, the wiring is also simplified, and the production difficulty due to the complex wiring is avoided.

[0044] 3) The connection of the original TX pin with the original TX pin and the connection of the original RX pin with the original RX pin are realized, the TX pin and the RX pin of the chip b are exchanged through the method and the system, and the communication between the chip a and the chip b is realized.

[0045] Other advantages, objects and features of the present application will be partly embodied in the following description, and will be partly understood by those skilled in the art through the study and practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 It is an interface connection diagram for the communication connection between chips;

[0047] Figure 2 It is a physical position relationship layout diagram for horizontally parallel chips;

[0048] Figure 3 It is a physical position relationship layout diagram for overlapping chips;

[0049] Figure 4 A layout diagram showing the physical positional relationships between overlapping chips;

[0050] Figure 5 A layout diagram showing the physical positional relationships between overlapping chips;

[0051] Figure 6 This is a flowchart of the adaptive communication method after chip sealing in Example 1;

[0052] Figure 7 Diagram showing the internal module setup of a chip communication system. Detailed Implementation

[0053] To make the technical means, creative features, objectives and effects of this invention clearer and easier to understand, the invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0054] Example 1

[0055] like Figure 1 as well as Figure 6 As shown, this invention discloses an adaptive communication method after chip packaging, based on the premise that the RESET pin of each chip is in the middle of the chip, and that the RX pin and TX pin of each chip are symmetrically distributed on both sides of the RESET pin (e.g., Figures 2 to 5 As shown, the RESET pins of all chips are located in the middle of the chip, thus, the following steps are included:

[0056] S1. Power on the two communicating chips; (This step is to power on the two communicating chips)

[0057] S2. Reset and drive the two communicating chips; (This step initializes and resets the two communicating chips and notifies them to start working)

[0058] S3. Divide the two communicating chips into chip a and chip b using their serial numbers; (This step classifies the two chips because the serial number is a unique code for the chip, just like a person's ID card. Each chip has the same serial number. Classifying the two communicating chips makes it easier to perform different tasks later. Only one chip keeps its TX and RX pins unchanged, while the other chip checks whether it should be paired and then adjusts its TX and RX pins. This avoids the situation where the TX and RX pins are already matched even if they have been successfully paired, which would prevent communication from being interrupted.)

[0059] S4. Chip a and chip b each perform their own tasks:

[0060] The work performed by the chip a includes: sending a specified signal to the chip b through the TX pin of the chip a and judging whether the RX pin receives the specified signal of the chip b;

[0061] Meanwhile, the work performed by the chip b includes: judging whether the TX pin and the RX pin are connected reversely through the TCKP / TCKN differential signal of the TX pin and the RCKP / RCKN differential signal of the RX pin, and if connected reversely, interchanging the TX pin and the RX pin.

[0062] In this step S4, it can be seen that the chip a performs the work of starting to send the specified signal, and also ensures that the opposite chip b also starts to work, which is to detect whether the RCKP / RCKN differential signal on the RX pin contains the specified signal, thereby ensuring that the entire chip communication system runs normally, and if it does not run normally, it outputs fai, and the chip a ensures that the RX pin and the TX pin do not change. The chip b also works corresponding to the chip a, and the TX pin of the chip a sends the specified signal to the chip b (the specified signal can be a CLK clock signal, which will be generated when the chip is reset and driven, and the clock signal is positive, of course, it is worth noting that the specified signal can also be other signals), the chip a has sent the specified signal and has started to work, so the chip b needs to wait for the arrival of the specified signal. Since the chip b can be connected to the TX pin or the RX pin of the chip a, the RX pin corresponds to the RCKP signal or the RCKN signal to form the RCKP / RCKN differential signal, and the TX pin corresponds to the TCKP signal or the TCKN signal to form the TCKP / TCKN differential signal, so they are all waiting for whether there is a specified signal on the RCKP signal (R represents the receiving pin, CK represents the clock, P represents the positive, N represents the negative, and T represents the sending pin), the RCKN signal, the TCKP signal or the TCKN signal. When the specified signal is in the RCKP signal, the RCKN signal, the TCKP signal or the TCKN signal, it is necessary to determine which signal the specified signal is in. If it is determined to be in the RCKP signal, the RCKN signal, it proves that the RX pin of the chip b receives the specified signal sent by the TX pin of the chip a, so the TX pin of the chip a is connected to the RX pin of the chip b, and the connection is correct. If it is determined not to be in the RCKP signal, the RCKN signal, it is in the TCKP signal or the TCKN signal, so the chip b needs to interchange its own TX pin and RX pin, which ensures that the subsequent connection can realize communication, that is, data transmission.

[0063] In order to ensure that the reset drive can be completely implemented, step S2 comprises: S21, driving the RESET pin to high level; S22, in the two chips communicating with each other, each chip waits for the reference reset signal input from the INPUT signal line to be high level, and stops driving the RESET pin.

[0064] Explanation of the above design of step S2: in the chip communication system, the RESET pins of chip a and chip b are connected with each other, and the connection is bidirectional, that is, as long as the RESET pin of one of the chips a and chip b is high level, the RESET pin of the other chip is pulled to low level, but the RESET line still maintains high level. One of the RESET pins is the INPUT signal line, and the other is the INOUT signal line. The INPUT signal line corresponds to the reference reset signal, and the INOUT signal line corresponds to the pad_reset signal. The following is an example of step S22: waiting for chip a to detect that the reference reset signal is high level, which indicates that the system informs the module to release the reset, and at the same time, the module stops driving the PAD RESET to high level, that is, the pad_reset signal starts to be 0, low level.

[0065] In order to ensure that the reset drive can be completely implemented, step S2 comprises: S21, driving the RESET pin to high level; S22, in the two chips communicating with each other, each chip waits for the reference reset signal input from the INPUT signal line to be high level, and stops driving the RESET pin.

[0066] Explanation of step S3: In S31, the pad_reset signal is equal to 0, which means that no reset driving is performed on the RESET pin, and the reset driving function of step S2 has been completed, so step S32 can be performed; in step S32, chip a and chip b inform each other of their serial numbers; in step S33, chip a and chip b compare their serial numbers with each other, and in the specific operation, the chip with the smaller serial number is chip a, and the chip with the larger serial number is chip b, so the chip with the smaller serial number will never switch the TX pin and the RX pin, and only the chip with the larger serial number can switch the TX pin and the RX pin. When a plurality of chips are connected together, the TX pin and the RX pin will not be confused, and the chip that has determined the TX pin and the RX pin will not determine the TX pin and the RX pin again, so that the determination work can be started from the beginning.

[0067] In order to ensure that the TX pin (such as Figure 1 as shown, the TX pin includes: TX pin C+ and TX pin C-, and the TX pin C+ corresponds to the TCKP signal, and the TX pin C- corresponds to the TCKN signal) and the RX pin (such as Figure 1 as shown, the RX pin includes: RX pin C+ and RX pin C-, and the RX pin C+ corresponds to the RCKP signal, and the RX pin C- corresponds to the RCKN signal) are correctly connected to the positive and negative terminals, and after step S4 is executed, step S5 is continued to be executed, and the work of step S5 is to determine whether the positive terminal P (i.e., whether the TX pin C+ is connected to the RX pin C+) and the negative terminal N (i.e., whether the TX pin C- is connected to the RX pin C-) are reversed by judging whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or the RCKN signal of the RCKP / RCKN differential signal, and if they are reversed, the positive terminal P and the negative terminal N are switched; if they are not reversed, no operation is performed. (If: the TX pin C+ is connected to the RX pin C-, which is a wrong connection, and this operation is to avoid similar situations)

[0068] The work of step S5 is to determine whether the polarity of the specified signal CLK channel is correct by judging whether the specified signal CLK is in the TCKN signal of the TCKP / TCKN differential signal or the RCKN signal of the RCKP / RCKN differential signal, and if it is, it means that the polarity of the specified signal CLK channel is wrong, and the polarity of the channel needs to be reversed, TCK+ is switched to TCK-, TCK- is switched to TCK+, RCK+ is switched to RCK-, and RCK- is switched to RCK+; if not, it means that the polarity of the specified signal CLK channel is correct, and no conversion is needed.

[0069] The work performed by chip a in step S4 includes the following steps:

[0070] S411, driving the TX pin of the chip a to send a designated signal to the chip b; (initiating the sending of the designated signal to start the whole chip communication system to run)

[0071] S412, the chip a waits for the RCKP / RCKN differential signal received on its RX pin to be the designated signal of the chip b;

[0072] S413, the chip a detects whether the RCKP / RCKN differential signal has the designated signal from the chip b, if yes, step S5 is performed; if no, a detection failure fail is outputted. (The CLK signal returned by the opposite party is received to judge whether the whole chip communication system has run)

[0073] The work performed by the chip b in step S4 includes the following steps:

[0074] S421, the RX pin of the chip b has the RCKP / RCKN differential signal and the TX pin has the TCKP / TCKN differential signal, and waits for the designated signal sent by the chip a to the RCKP / RCKN differential signal or the TCKP / TCKN differential signal of the chip b;

[0075] S422, judging whether the designated signal sent by the chip a is in the RCKP / RCKN differential signal and the TCKP / TCKN differential signal of the chip b; if yes, step S423 is performed; if no, a detection failure fail is outputted;

[0076] S423, continuing to judge whether the designated signal sent by the chip a is in the RCKP / RCKN differential signal, if no, step S424 is performed; if yes, judging that the RX pin of the chip b is connected to the TX pin of the chip a; (realizing the judgment of whether the RX pin is correctly connected to the TX pin, if correctly connected, the pins are not exchanged, if incorrectly connected, the pins are exchanged, that is, step S425 is performed)

[0077] S424, the RX pin of the chip b is exchanged with the TX pin.

[0078] Embodiment 2

[0079] The embodiment also discloses a chip communication system based on the chip self-adaptive communication method after sealing in embodiment 1, which comprises a chip a and a chip b, the RESET pin of each chip is in the middle of the chip, the RX pin and the TX pin of each chip are symmetrically distributed on both sides of the RESET pin, and the chip a and the chip b communicate with each other.

[0080] The chip a comprises:

[0081] a first power-on module for powering on itself;

[0082] The first reset driving module is used for resetting and driving itself;

[0083] The first classification module is used for classifying itself and identifying itself as the chip a;

[0084] The first communication task execution module is used for sending a specified signal to the chip b through the TX pin of the chip a, and judging whether the RX pin receives the specified signal of the chip b;

[0085] The chip b comprises:

[0086] The second power-on module is used for powering on itself;

[0087] The second reset driving module is used for resetting and driving itself;

[0088] The second classification module is used for classifying itself and identifying itself as the chip b;

[0089] The second communication task execution module is used for judging whether the TX pin and the RX pin are reversed by judging whether the specified signal is on the TCKP / TCKN differential signal of the TX pin or in the RCKP / RCKN differential signal of the RX pin, and if reversed, performing the TX pin and RX pin exchange.

[0090] The chip a further comprises a first polarity determining module, and the chip b further comprises a second polarity determining module; the first polarity determining module and the second polarity determining module are both used for judging whether the positive pole P and the negative pole N are reversed by judging whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or in the RCKN signal of the RCKP / RCKN differential signal, and if reversed, performing the positive pole P and negative pole N switching; and if not reversed, not performing the operation.

[0091] Finally, it is to be explained that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application, and although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the purpose and scope of the present application, and all should be covered in the scope of the claims of the present application.

Claims

1. An adaptive communication method after chip encapsulation, characterized in that, Given that the RESET pin of each chip is located in the middle of the chip, and that the RX pin and TX pin of each chip are symmetrically distributed on both sides of the RESET pin, the following steps are included: S1. Power on the two communicating chips; S2. Reset and drive the two communicating chips; S3. The two communicating chips are divided into chip a and chip b by serial number; S4. Chips a and b perform their respective tasks in the handshake communication between the TX and RX pins: The tasks performed by chip a include: sending a specified signal to chip b through chip a's TX pin and determining whether the specified signal has been received by chip b through chip RX pin; Meanwhile, the work performed by chip b includes: determining whether the TX pin and RX pin are reversed by judging whether the specified signal is in the TCKP / TCKN differential signal of the TX pin or in the RCKP / RCKN differential signal of the RX pin; if they are reversed, the TX pin and RX pin are swapped. Step S2 includes: S21, chip a and chip b drive the RESET pin to a high level; S22, in the two communicating chips, each chip waits until the reference reset signal input to the INPUT signal line is high level, and then stops driving the RESET pin. Step S3 includes: S31, in the two communicating chips, each chip determines whether it has received the pad_reset signal of the RESET pin equal to 0. If so, proceed to step S32; S32, drive its own chip serial number to the RESET pin; S33, in the two communicating chips, each chip determines whether the following condition is met: whether its own serial number is less than the received serial number. If so, it determines that it is chip a; if not, it determines that it is chip b.

2. The adaptive communication method after chip encapsulation according to claim 1, characterized in that, After step S4 is completed, step S5 is executed. Step S5 is performed as follows: by determining whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or the RCKN signal of the RCKP / RCKN differential signal, it is determined whether the positive P and negative N are opposite. If they are opposite, the positive P and negative N are switched. If they are not opposite, no operation is performed.

3. The adaptive communication method after chip encapsulation according to claim 2, characterized in that, The work performed by chip a in step S4 includes the following steps: S411, drive the TX pin to send a specified signal to chip b; S412, wait for the RCKP / RCKN differential signal received on its own RX pin to be the specified received signal; S413. Detect whether the RCKP / RCKN differential signal is the specified signal from chip b. If yes, proceed to step S5; otherwise, output "detection failed".

4. The adaptive communication method after chip encapsulation according to claim 3, characterized in that, The work performed by chip b in step S4 includes the following steps: S421: The signal on its own RX pin is an RCKP / RCKN differential signal, and the signal on its TX pin is a TCKP / TCKN differential signal. It waits for the specified signal sent by chip a to enter the RCKP / RCKN differential signal or TCKP / TCKN differential signal of chip b. S422. Determine whether the RCKP / RCKN differential signal and TCKP / TCKN differential signal of chip b contain the specified signal sent by chip a; if yes, proceed to step S423; if no, output detection failure. S423. Continue to determine whether the specified signal sent by chip a is within the RCKP / RCKN differential signal of chip b. If not, proceed to step S424; if yes, determine whether the RX pin of chip b is connected to the TX pin of chip a. S424, chip b swaps its RX pin with its TX pin.

5. A chip communication system based on the chip-to-chip adaptive communication method as described in any one of claims 1 to 4, characterized in that, Includes: chip a and chip b. The RESET pin of each chip is located in the middle of the chip. The RX pin and TX pin of each chip are symmetrically distributed on both sides of the RESET pin. Chip a and chip b communicate with each other. Chip A includes: The first power-on module is used to power itself; The first reset driver module is used to reset and drive itself. The first classification module is used to identify itself as chip a by classifying itself. The first communication task execution module is used to send a specified signal to chip b through the TX pin of chip a, and to determine whether the RX pin has received the specified signal from chip b. Chip b includes: The second power-on module is used to power itself. The second reset driver module is used to reset and drive itself. The second classification module is used to identify itself as chip b by classifying itself. The second communication task execution module is used to determine whether the TX pin and RX pin are reversed by judging whether the specified signal is on the TCKP / TCKN differential signal of the TX pin or on the RCKP / RCKN differential signal of the RX pin. If they are reversed, the TX pin and RX pin are swapped.

6. A chip communication system according to claim 5, characterized in that, Chip a further includes: a first polarity determination module; chip b further includes: a second polarity determination module. Both the first polarity determination module and the second polarity determination module are used to determine whether the positive pole P and the negative pole N are opposite by judging whether the specified signal is in the TCKN signal of the TCKP / TCKN differential signal or the RCKN signal of the RCKP / RCKN differential signal. If they are opposite, the step of switching the positive pole P and the negative pole N is performed; if they are not opposite, no operation is performed.

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