A centralized control method and system for interconnecting multiple FPGA chips

Abstract

The present invention proposes a centralized control method for interconnecting multiple FPGA chips, which relates to the field of communication technology. It includes a main processor and multiple slave processors that are centrally controlled by the main processor; initialization operations are performed on the control system of the main processor and the control systems of the multiple slave processors; the control system of the main processor sends management and configuration commands to the programmable logic device of the main processor through the AXI bus; after receiving the management and configuration commands, the programmable logic device of the main processor converts the management and configuration commands into port physical layer data through the chip2chip protocol, and interacts with the programmable logic devices of the multiple slave processors respectively. It can thereby improve the transmission line speed and meet the complex control and management of large-scale antenna technology systems.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a centralized control method and system for interconnecting multiple FPGA chips. Background Art

[0002] 5G NR (New Radio) is a global 5G standard based on a new air interface design of OFDM (Orthogonal Frequency Division Multiplexing). It is also an important next-generation cellular mobile technology. A key technology of 5G is massive antenna technology, namely Massive MIMO. The number of antennas in traditional TDD (Time Division Duplexing) networks is usually 2, 4 or 8, while the number of channels of Massive MIMO can reach 64. With the increase in the number of antennas, the system capacity will increase exponentially, but correspondingly, the complexity of system implementation will also increase exponentially. Therefore, the logical implementation of the Massive MIMO system usually requires multiple FPGAs to complete. In order to realize the configuration, monitoring and management of multiple FPGAs, it is necessary to design a reasonable FPGA inter-chip interconnection control method. Usually, the control mainly includes centralized control and distributed control. Distributed control means that each FPGA is controlled separately. The disadvantage of this is that it is difficult to meet the control timing requirements for the control with timing requirements between multiple FPGAs. Therefore, centralized control is the preferred control method, and centralized control usually uses switch (Ethernet switching chip) chips, such as Figure 3 As shown, the PS (control system / processing system) controls the PS of other FPAGs through the switch chip. This method has a low rate and is difficult to meet the control requirements of complex systems. Summary of the invention

[0003] The object of the present invention is to provide a centralized control method for interconnecting multiple FPGA chips, which can thereby increase the line speed of transmission and meet the complex control and management of large-scale antenna technology systems.

[0004] The embodiment of the present invention is achieved as follows:

[0005] In the first aspect, an embodiment of the present application provides a centralized control method for interconnecting multiple FPGA chips, including a main processor and multiple slave processors centrally controlled by the main processor; initialization operations are performed on the control system of the main processor and the control systems of the multiple slave processors; the control system of the main processor sends management and configuration commands to the programmable logic device of the main processor through an AXI bus; after receiving the management and configuration commands, the programmable logic device of the main processor converts the management and configuration commands into port physical layer data through the chip2chip protocol, and interacts with the multiple slave processors respectively.

[0006] In some embodiments of the present invention, the steps of initializing the control system of the master processor and the control systems of multiple slave processors include: placing the chip2chip protocol of the slave processor in a reset state; resetting the orthogonal phase-locked loop of the high-speed serial deserializer, checking whether the phase-locked loop is locked, and canceling the chip2chip protocol reset operation of the slave processor; resetting the chip2chip protocol of the master processor and checking whether the link establishment is successful.

[0007] In some embodiments of the present invention, the step of resetting the high-speed serial deserializer includes: resetting the orthogonal phase-locked loop, the transmission data link and the reception data link of the high-speed serial deserializer in sequence, and sending interactive data to the main processor.

[0008] In some embodiments of the present invention, the interactive data includes orthogonal phase-locked loop reset data and transceiver channel reset data.

[0009] In some embodiments of the present invention, the step of placing the chip2chip protocol of the slave processor in a reset state includes placing the chip2chip protocol of the slave processor in a reset state via a port expander.

[0010] In some embodiments of the present invention, the step of resetting the chip2chip protocol of the main processor includes: directly configuring through the AXI bus to reset the chip2chip protocol of the main processor.

[0011] In some embodiments of the present invention, the port physical layer data adopts the port physical layer under the Aurora 64B / 66B high-speed serial communication extensible link layer protocol.

[0012] In the second aspect, an embodiment of the present application provides a centralized control system in which multiple FPGA chips are interconnected, wherein the processor module is used for a main processor and multiple slave processors centrally controlled by the main processor; an initialization module is used to perform initialization operations on the control system of the main processor and the control systems of multiple slave processors; a configuration module is used for the control system of the main processor to send management and configuration commands to the programmable logic device of the main processor through an AXI bus; and an inter-chip interaction module is used for the programmable logic device of the main processor to convert the management and configuration commands into port physical layer data through the chip2chip protocol after receiving the management and configuration commands, and to interact with multiple slave processors respectively.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, which includes a main processor, multiple slave processors connected to the processor, at least one memory and a data bus; wherein: the main processor, multiple slave processors, and the memory communicate with each other through the data bus; the memory stores program instructions that can be executed by the processor, and the main processor and multiple slave processors call the program instructions to execute the above method.

[0014] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the above method when executed by a processor.

[0015] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects:

[0016] A high-speed centralized control method based on the interconnection between programmable logic devices in a processor. The principle is to use the programmable logic device (hereinafter referred to as PL) of the main processor to uniformly configure the programmable logic device of the slave processor, while the original control system of the slave processor (hereinafter referred to as PS) is only used for some initialization configurations during system initialization, thereby improving the line speed and meeting the complex control and management of the system of Massive MIMO technology. The line speed can reach 4GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flowchart of a centralized control method for interconnecting multiple FPGA chips in the present invention;

[0019] Figure 2 A schematic diagram of the structure of a centralized control method for interconnecting multiple FPGA chips in the present invention;

[0020] Figure 3 It is a structural schematic diagram of the prior art in the present invention;

[0021] Figure 4 A schematic diagram of the structure of the centralized control of interconnection between multiple FPGA chips of the present invention;

[0022] Figure 5 The present invention is a flowchart of a centralized control system for interconnecting multiple FPGA chips.

[0023] Icons: 1. Main processor; 2. Slave processor; 3. Processor module; 4. Initialization module; 5. Configuration module; 6. Inter-chip interaction module. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0026] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0027] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0028] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0029] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0030] Example 1

[0031] See also Figure 1 , Figure 2 and Figure 4 , a centralized control method for interconnecting multiple FPGA chips provided in the embodiment of the present application, the present invention proposes a high-speed centralized control method based on the interconnection between programmable logic devices in the processor, the principle of which is to use the programmable logic device (hereinafter referred to as PL) of the main processor 1 to uniformly configure the programmable logic device of the slave processor 2, and the original control system of the slave processor 2 (hereinafter referred to as PS) is only used for some initialization configurations during system initialization, thereby improving the line speed and meeting the complex control and management of the system of massive antenna technology (Massive MIMO system), and its line rate can reach 4GHz. The specific implementation method is as follows:

[0032] The hardware of the present invention is based on the Xilinx ZYNQ SOC architecture, and is provided with a main processor 1 and multiple slave processors 2 that are centrally controlled by the main processor 1; the programmable logic array (FPGA) therein is composed of two parts: a control system (the control system is hereinafter referred to as PS) and a programmable logic device (hereinafter referred to as PL). The PS mainly realizes the management, configuration and monitoring of the entire system; the PL mainly realizes various functional modules. Taking five FPGAs as an example, one of them is used as the main processor 1, and the other four are used as slave processors 2. The PS of the main processor 1 centrally controls all the other FPGAs.

[0033] S101: Initializing the control system of the master processor 1 and the control systems of the plurality of slave processors 2;

[0034] The PS of the master processor 1 and the slave processor 2 can also communicate with each other, but due to the low communication interface rate, only some simple initialization and other controls are performed. Therefore, at the beginning of data processing, the control system of the master processor 1 and the control systems of multiple slave processors 2 are initialized to avoid the influence of the previous data processing.

[0035] S102: The control system of the main processor 1 sends management and configuration commands to the programmable logic device of the main processor 1 through the AXI bus;

[0036] The main management and configuration data are exchanged between the PS of the main processor 1 and the PL of the main processor 1 through the AXI bus.

[0037] S103: After receiving the management and configuration commands, the programmable logic device of the main processor 1 converts the management and configuration commands into port physical layer data through the chip2chip protocol, and exchanges data with the multiple slave processors 2 respectively.

[0038] After the management and configuration commands reach the PL of the main processor 1 through the AXI bus, the lightweight IP core of Xilinx is used on the PL of the main processor 1 to convert the AXI commands into port physical layer (PHY) data based on the chip2chip protocol, and interact with the PLs of several slave processors 2 respectively. This improves the operating rate and meets the control requirements of complex systems. The chip2chip protocol is an IP core proposed by Xilinx. Its core function is like a bridge, seamlessly connecting two processors through the AXI interface and using the AXI protocol specification. The bridging function allows all AXI channels to operate independently by forwarding the data and control information of each channel.

[0039] In some embodiments of the present invention, the steps of initializing the control system of the master processor 1 and the control systems of the plurality of slave processors 2 include:

[0040] Put the chip2chip protocol of slave processor 2 into reset state; reset the orthogonal phase-locked loop of the high-speed serial deserializer, check whether the phase-locked loop is locked, and cancel the chip2chip protocol reset operation of slave processor 2; reset the chip2chip protocol of master processor 1 and check whether the link establishment is successful.

[0041] In some embodiments of the present invention, for high-speed interfaces, the reset process is very critical. Insufficient reset or unreasonable reset process will cause abnormalities in the interface. In the embodiment, two reset operations are very important, and the correct reset timing must be guaranteed, otherwise the PS will be hung. One is to reset the chip2chip protocol; the other is to reset the high-speed serial transceiver (serdes). When resetting the chip2chip protocol of the main processor 1, it can be directly configured through the AXI bus, and when resetting the chip2chip protocol on the slave processor 2, it is performed through the port expander (GPIO), so that only 4 GPIOs are needed to achieve the reset of the chip2chip protocol of the entire system. According to the reset requirements of serdes, the QPLL (Quadrature phased lockedloop, orthogonal phase-locked loop), TX DATAPATH (transmit data link), and RXDATAPATH (receive data link) of serdes (high-speed serial deserializer) are reset in turn, and interactive data is provided to the PS so that the corresponding parts of the high-speed port can be reset in time when needed.

[0042] In some embodiments of the present invention, the step of resetting the high-speed serial deserializer includes:

[0043] The orthogonal phase-locked loop, the transmitting data link and the receiving data link of the high-speed serial deserializer are reset in sequence, and the interactive data is sent to the main processor 1.

[0044] In some embodiments of the present invention, in addition to ensuring the respective reset processes of the chip2chip protocol and serdes, it is also necessary to ensure that a specific reset timing is met between the chip2chip protocol and serdes.

[0045] In some embodiments of the present invention, the interactive data includes orthogonal phase-locked loop reset data and transceiver channel reset data.

[0046] The specific data provided to PS include QPLL reset (which can reset the QPLL of serdes), GTRESET (which can reset the TX and RX datapath of serdes), and GTTXRESET or GTRXREST (which can reset the TX and RX datapaths respectively). TX and RX correspond to the transmit and receive channels respectively.

[0047] In some embodiments of the present invention, the step of placing the chip2chip protocol of the slave processor 2 in a reset state comprises: placing the chip2chip protocol of the slave processor 2 in a reset state via a port expander.

[0048] In some embodiments of the present invention, the step of resetting the chip2chip protocol of the main processor 1 includes:

[0049] The chip2chip protocol of the main processor 1 is reset by directly configuring it via the AXI bus.

[0050] In some embodiments of the present invention, the port physical layer data adopts the port physical layer under the Aurora 64B / 66B high-speed serial communication extensible link layer protocol.

[0051] In some embodiments of the present invention, Aurora 64B / 66B is selected as the PHY of chip2chip. For the selection of the port physical layer (PHY), SelectIO can be directly used, but doing so will greatly increase the hardware pins. Since the hardware platform of this design has rich Serdes resources, Xilinx's Aurora64B / 66B IP is selected in the selection of PHY to realize the conversion between chip2chip data and Xilinx serial transceiver (GTH / GTY) data. Through chip2chip+Aurora 64B / 66B+GTY / GTH, the control data line rate can reach 4Gsps.

[0052] Example 2

[0053] See also Figure 5 , a centralized control system with multiple FPGA chips interconnected, including:

[0054] A processor module 3 is used for a main processor 1 and a plurality of slave processors 2 centrally controlled by the main processor 1; an initialization module 4 is used to perform initialization operations on the control system of the main processor 1 and the control systems of the plurality of slave processors 2; a configuration module 5 is used for the control system of the main processor 1 to send management and configuration commands to the programmable logic device of the main processor 1 through the AXI bus; an inter-chip interaction module 6 is used for the programmable logic device of the main processor 1 to convert the management and configuration commands into port physical layer data through the chip2chip protocol after receiving the management and configuration commands, and to interact with the plurality of slave processors 2 respectively.

[0055] Example 3

[0056] See also Figure 4, an electronic device, comprising a main processor 1, multiple slave processors 2 connected to the main processor 1, at least one memory and a data bus; wherein: the main processor 1, multiple slave processors 2, and the memory communicate with each other through the data bus; the memory stores program instructions that can be executed by the processor, and the main processor 1 and multiple slave processors 2 call the program instructions to execute a centralized control method for interconnecting multiple FPGA chips. For example, the following is realized:

[0057] A main processor 1 and multiple slave processors 2 centrally controlled by the main processor 1; initialization operations are performed on the control system of the main processor 1 and the control systems of the multiple slave processors 2; the control system of the main processor 1 sends management and configuration commands to the programmable logic device of the main processor 1 through the AXI bus; after receiving the management and configuration commands, the programmable logic device of the main processor 1 converts the management and configuration commands into port physical layer data through the chip2chip protocol, and interacts with the multiple slave processors 2 respectively.

[0058] Example 4

[0059] In some embodiments of the present invention, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements a centralized control method for interconnecting multiple FPGA chips. For example, it implements:

[0060] A main processor 1 and multiple slave processors 2 centrally controlled by the main processor 1; initialization operations are performed on the control system of the main processor 1 and the control systems of the multiple slave processors 2; the control system of the main processor 1 sends management and configuration commands to the programmable logic device of the main processor 1 through the AXI bus; after receiving the management and configuration commands, the programmable logic device of the main processor 1 converts the management and configuration commands into port physical layer data through the chip2chip protocol, and interacts with the multiple slave processors 2 respectively.

[0061] Among them, the memory can be, but is not limited to, random access memory (RAM), read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), etc.

[0062] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0063] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0064] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0065] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0066] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A centralized control method for interconnecting multiple FPGA chips, wherein the multiple FPGA chips include a main processor and a processor, characterized in that: The method comprises: Initializing the control system of the master processor and the control systems of the plurality of slave processors; The control system of the main processor sends management and configuration commands to the programmable logic device of the main processor via the AXI bus; After receiving the management and configuration commands, the programmable logic device of the master processor converts the management and configuration commands into port physical layer data through the chip2chip protocol, and interacts with the programmable logic devices of the multiple slave processors respectively for data; The steps of initializing the control system of the master processor and the control systems of the plurality of slave processors include: Put the chip2chip protocol of the slave processor into reset state; Reset the quadrature phase-locked loop of the high-speed serial transceiver, check whether the phase-locked loop is locked, and cancel the chip2chip protocol reset operation of the slave processor; Reset the chip2chip protocol of the main processor and check whether the link is established successfully.

2. A centralized control method for interconnecting multiple FPGA chips as described in claim 1, characterized in that: After resetting the quadrature phase-locked loop of the high-speed serial transceiver, the following steps are also included: The transmitting data link and receiving data link of the high-speed serial transceiver are reset in sequence, and the interactive data is sent to the main processor.

3. A centralized control method for interconnecting multiple FPGA chips as described in claim 2, characterized in that: The interactive data includes orthogonal phase-locked loop reset data and transceiver channel reset data.

4. A centralized control method for interconnecting multiple FPGA chips as described in claim 1, characterized in that: The step of placing the chip2chip protocol of the slave processor in a reset state comprises: placing the chip2chip protocol of the slave processor in a reset state through a port expander.

5. A centralized control method for interconnecting multiple FPGA chips as described in claim 1, characterized in that: The steps to reset the chip2chip protocol of the main processor include: Configuration is performed directly via the AXI bus, resetting the chip2chip protocol of the main processor.

6. A centralized control method for interconnecting multiple FPGA chips as claimed in claim 1, characterized in that: The port physical layer data adopts the port physical layer under the Aurora 64B / 66B high-speed serial communication extensible link layer protocol.

7. A centralized control system in which multiple FPGA chips are interconnected, wherein the multiple FPGA chips include a main processor and a processor, characterized in that: The system comprises: A processor module, for a master processor and a plurality of slave processors centrally controlled by the master processor; An initialization module, used to perform initialization operations on the control system of the master processor and the control systems of the plurality of slave processors; A configuration module, used for the control system of the main processor to send management and configuration commands to the programmable logic device of the main processor through the AXI bus; An inter-chip interaction module, which is used for the programmable logic device of the master processor to convert the management and configuration commands into port physical layer data through the chip2chip protocol after receiving the management and configuration commands, and to interact with multiple slave processors respectively for data; The steps of initializing the control system of the master processor and the control systems of the plurality of slave processors include: placing the chip2chip protocol of the slave processor in a reset state; resetting the orthogonal phase-locked loop of the high-speed serial transceiver, checking whether the phase-locked loop is locked, and canceling the chip2chip protocol reset operation of the slave processor; resetting the chip2chip protocol of the master processor and checking whether the link establishment is successful.

8. An electronic device, characterized in that: It includes a main processor, multiple slave processors connected to the main processor, at least one memory and a data bus; wherein: the main processor, the multiple slave processors, and the memory communicate with each other through the data bus; the memory stores program instructions that can be executed by the processor, and the main processor and the multiple slave processors call the program instructions to execute any method as claimed in claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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