Method for convolution computation in memory and corresponding integrated circuit

Abstract

Embodiments of the present disclosure relate to methods and corresponding integrated circuits for in-memory convolutional computation. In one embodiment, a method for performing a convolutional computation (CNVL) on an input value with a weight factor includes converting the input value to a voltage signal, and successively applying the voltage signal on selected bit lines in a non-volatile memory dot array over respective time slots, each memory dot including a phase change resistive memory cell coupled to the bit line and having a resistive state corresponding to the weight factor, and a bipolar selection transistor coupled in series with the phase change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signal biases the respective phase change memory cell, integrating a read current generated by the voltage signal biasing the respective phase change resistive memory cell and flowing through the selected word line over the successive time slots, and converting the integrated read current to an output value.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of French patent application No. 2008327, filed on August 6, 2020, which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to convolution computation, particularly in-memory computation, such as convolution computation between layers of a neural network. Background Technology

[0004] In the field of neural network technology, the term "convolution computation" refers to computation between an input space of a finite number of input values ​​and an output space of a finite number of output values, where the computation of each output value uses all input values. The most convenient mathematical expression for this computation is the matrix multiplication of the convolution matrix operator with the vector of input values, resulting in a vector of output values. Therefore, each output value is obtained through multiplication and accumulation operations.

[0005] The term "in-memory computation" refers to computation performed in real time within circuitry (called memory) that stores computational parameters. This differs fundamentally from classical computation because it does not require transferring values ​​and parameters from memory to a processing unit, which performs the computation itself. Furthermore, processing units are typically limited in the number of basic operations they can perform simultaneously, while in-memory computation is generally independent of the number of computational elements, calculating and providing all results at once, based on the limited capacity of the computer's memory.

[0006] In classic memory systems, computation is performed using resistive memory arrays, where each memory point has a resistance value programmed according to computational parameters. Digital input values ​​are converted into voltage signals applied to the row lines of the memory points, with currents of sufficient strength to obey Ohm's law flowing through each point. The currents flowing through the column lines are summed using Kirchhoff's laws and converted into digital output values; thus, each output value is derived from the multiplication and accumulation of the input values.

[0007] The classic technique for selecting resistive memory points in an array uses MOS (Metal-Oxide-Semiconductor, an acronym well-known to those skilled in the art) access transistors, also known as selectors. MOS transistors are specifically used for their ability to flow current in both directions, which is mandatory in some resistive memory technologies, such as MRAM (Magnetic Random Access Memory) used to program cells.

[0008] However, MOS transistors typically need to be large enough to drive high-intensity write currents, and scaling down MOS selectors introduces reliability issues, given the typically elevated voltage applied to the gate oxide of the MOS. Summary of the Invention

[0009] The embodiments provide in-memory computing methods and apparatuses that can be scaled down while remaining reliable and flexible under usage conditions.

[0010] Another embodiment uses an array of multiple phase-change memory cells and multiple bipolar transistors (BJTs) used as cell selectors to perform convolution calculations.

[0011] According to one embodiment, a method for performing convolution calculation on an input value using a weighting factor includes: converting the input value into a voltage signal and continuously applying the voltage signal over selected bit lines in a non-volatile memory point array over corresponding time slots, each memory point including a phase-change resistor memory cell and a bipolar selection transistor, the phase-change resistor memory cell being coupled to the bit line and having a resistance state corresponding to the weighting factor, the bipolar selection transistor being coupled in series with the cell and having a base terminal coupled to a word line, the voltage signal thus biasing the corresponding phase-change resistor memory cell; integrating a read current generated by the voltage signal biasing the corresponding phase-change resistor memory cell and flowing through the selected word line over consecutive time slots; and converting the integrated read current into an output value.

[0012] The memory points used in this method can therefore be very compact because they incorporate bipolar transistors as selectors. Bipolar transistors can indeed be reduced to a very compact footprint while exhibiting high current drive capability and maintaining high reliability.

[0013] Phase-change resistor memory allows for the advantageous use of bipolar transistors because the phase-change resistor memory cells can be written to (i.e., set or reset) according to the shape of a signal with unidirectional current flow.

[0014] In contrast to the classical technique of summing currents flowing simultaneously on a single line using Kirchhoff's laws, this approach applies a voltage signal across the corresponding time slot, limiting the voltage drop in the word line to the current of a single phase-change memory cell at a time, and thus without negatively impacting the overall architecture's performance. Integrating the resulting read current allows for efficient summation of the currents. Alternatively, if the voltage drop of a cell is sufficiently low, more than one memory cell can be activated simultaneously, or time slots can overlap.

[0015] According to one embodiment, the method includes performing a decoding operation to select a selected bit line for each input value and select a selected word line for each output value.

[0016] In other words, since each memory point is located at the intersection of a bit line and a word line, each memory point can be accessed. For example, selecting a bit line can be achieved by biasing the bit line to a voltage signal, while selecting a word line can be achieved by grounding the selected word line and biasing the unselected word line to a suppression potential configured not to drive current through the line.

[0017] According to one embodiment, the selected bipolar transistor is provided with a β gain of less than 1.

[0018] "β gain" (beta gain) is a known ratio of DC collector current to DC base current in the forward active region, and is also known as "common emitter current gain" or "h parameter hFE".

[0019] Therefore, in the selection of bipolar transistors, the base current flowing to the word line is improved and the collector current loss is limited.

[0020] According to one embodiment, the selected bipolar transistor is provided in the form of a multi-emitter bipolar element group, each multi-emitter bipolar element including a corresponding number of emitter regions, a shared base region having two symmetrical base terminals coupled to the same word line, and a shared ground collector region, each phase-change resistor memory cell being coupled to a corresponding emitter region.

[0021] This embodiment provides a very compact structure for the selected bipolar transistor. For example, in a multi-emitter bipolar device, the selected bipolar transistor can be grouped into four groups, including, for example, four aligned emitter regions and base regions located at both ends of the line.

[0022] According to one embodiment, convolution computation includes performing multiplication and accumulation operations on input values ​​and weight factors, each operation producing an output value, and the method includes programming phase-change resistor memory cells to resistor states corresponding to the respective weight factors.

[0023] The phase-change resistor memory cells are programmed before the convolution calculation, i.e. before receiving the input values.

[0024] According to one embodiment, programming a phase-change resistor memory cell includes making the write current flow in only one direction for each possible resistance state, such as from the memory cell to the select bipolar transistor.

[0025] According to one embodiment, the read current is integrated over consecutive time slots using an integrator circuit, which includes an amplifier coupled to a feedback loop, the feedback loop including a capacitive element and a switching circuit capable of reversing the polarity of the capacitive element in the feedback loop in response to a sign control signal.

[0026] Therefore, the integral can be made by reversing the polarity of the capacitor element to integrate the negative value, and allows for the calculation of, for example, positive and / or negative weighting factors.

[0027] According to one embodiment, converting an input value into a voltage signal includes generating, in addition to the net converted voltage for each input value, an offset voltage that compensates for the threshold voltage of the selected bipolar transistor.

[0028] According to one embodiment, converting an input value into a voltage signal includes simulating the selection of a bipolar transistor under bias conditions by simulating the current readout to generate an offset voltage under in-situ conditions.

[0029] Therefore, in these embodiments, process variations and temperature variations in the threshold voltage of the bipolar transistor are compensated for, while the conversion of the input value into a voltage signal is unaffected by this compensation and can therefore be optimized, for example, in terms of accuracy and dynamic range.

[0030] According to one embodiment, the time slot calibration operation includes adjusting the duration of the time slot associated with the reference phase-change resistor memory cell and the reference output value to compensate for possible temperature and process variations in the conductance of the phase-change resistor memory cell and the selection of the β gain of the bipolar transistor.

[0031] According to one embodiment, adjusting the time slot duration includes: simulating an output value generated by integrating a read current, the read current being generated by a reference voltage signal biasing a reference phase-change resistor memory cell during the adjustable time slot; and comparing the simulated output value with a reference output value to adjust the time slot duration.

[0032] Therefore, in these embodiments, process variations and temperature variations in the conductance of the phase-change resistor memory cell and the β gain of the selected bipolar transistor are compensated in situ, which allows for the provision of undamaged output values.

[0033] According to another aspect, an integrated circuit for performing convolution calculations on input values ​​using weighting factors includes: a non-volatile memory dot array, each non-volatile memory including a phase-change resistor memory cell and a select bipolar transistor cell, the phase-change resistor memory cell being coupled to a bit line and configured to have a resistance state corresponding to the weighting factor, the select bipolar transistor cell being coupled in series with the cell and having a base terminal coupled to a word line; an input converter circuit configured to receive an input value and convert the input value into a voltage signal and continuously apply the voltage signal on a selected bit line over a corresponding time slot; and an output converter circuit configured to: integrate a read current generated by the voltage signal biasing the corresponding phase-change resistor memory cell and flowing through the selected word line over consecutive time slots, and convert the integrated read current into an output value.

[0034] According to one embodiment, the integrated circuit includes a decoder circuit configured to select a selected bit line for each input value and a selected word line for each output value.

[0035] According to one embodiment, the selected bipolar transistor is configured to have a β gain of less than 1.

[0036] According to one embodiment, selected bipolar transistors are grouped into multi-emitter bipolar elements, each multi-emitter bipolar element including a corresponding number of emitter regions, a shared base region having two symmetrical base terminals coupled to the same word line, and a shared ground collector region, each phase-change resistor memory cell being coupled to a corresponding emitter region.

[0037] According to one embodiment, the convolution calculation includes multiplication and accumulation operations of input values ​​and weight factors, each operation producing an output value, and the phase-change resistor memory cell is configured to be programmed to a resistance state corresponding to the respective weight coefficient.

[0038] According to one embodiment, for each possible resistance state, the phase-change resistor memory cell can be programmed by making the write current flow in only one direction.

[0039] According to one embodiment, for each selected word line, the output converter circuit includes an integrator circuit, which includes an amplifier coupled to a feedback loop, the feedback loop including a capacitive element and a switching circuit capable of reversing the polarity of the capacitive element in the feedback loop in response to a symbol control signal.

[0040] According to one embodiment, the input converter circuit is configured to generate, in addition to the net conversion voltage for each input value, an offset voltage that compensates for the threshold voltage of the selected bipolar transistor.

[0041] According to one embodiment, the input converter circuit includes a memory point analog circuit configured to simulate the selection of a bipolar transistor under bias conditions by simulating a read current in order to generate an offset voltage under in-situ conditions.

[0042] According to one embodiment, the time slot calibration circuit is configured to adjust the time slot duration associated with a reference phase-change resistor memory cell and with a reference output value to compensate for possible temperature and process variations in the conductance of the resistor phase-change memory cell and the β gain of the selected bipolar transistor.

[0043] According to one embodiment, the time slot calibration circuit includes: a memory point analog circuit and an output converter circuit analog circuit configured to simulate an output value generated by integrating a read current, the read current being generated by a reference voltage signal biasing a reference phase-change resistor memory cell during an adjustable time slot; and a comparator configured to compare the analog output value with a reference output value to control the calibration feedback circuit for adjusting the time slot duration. Attached Figure Description

[0044] Other advantages and features of the invention will become apparent from a review of the detailed description of non-limiting embodiments of the invention and the accompanying drawings, in which:

[0045] Figure 1 An example of an artificial neural network and its mathematical representation are shown;

[0046] Figure 2 A non-volatile memory point according to an embodiment is shown;

[0047] Figure 3 The write mechanism of a phase-change resistor memory cell (PCM) is shown.

[0048] Figure 4 A portion of a non-volatile memory dot array according to an embodiment is shown, as per [reference to...] Figure 2 Described;

[0049] Figure 5 A cross-sectional view of the semiconductor stage of an array of selected bipolar transistors is shown;

[0050] Figure 6 An embodiment of an input converter circuit configured to compensate for process and temperature variations in the threshold voltage of a bipolar transistor is shown; and

[0051] Figure 7 An embodiment of an input converter circuit configured to compensate for process and temperature variations that affect convolution calculations is shown. Detailed Implementation

[0052] Figure 1 An example of an artificial neural network is shown, including "neuron" layers A1-A. 2- A3, B1-B2-B3, where each neuron is connected to all neurons in the previous layer via a corresponding number of "synapses." This biomimetic terminology describes the computational mechanism involved in this field, where all values ​​in the input space (e.g., neurons A1-A3 in the first layer) are weighted by a factor W. i1 W i2 W i3 (That is, synapses) are weighted and weighted for each value B in the output space. i(For example, neurons B1-B3 in the second layer) are accumulated. This computation is called convolution computation CNVL. The input and output spaces consist of a finite number of values ​​(neurons), and the dimensions of these spaces can vary from the input space to the output space and can be greater than (or less than) 3 (in the illustrated example, the dimensions of the two spaces are 3).

[0053] The right side shows a convenient mathematical expression for this convolutional computation CNVL applicable to artificial neural networks, where the input space has a dimension of n and the output space has a dimension of m.

[0054] This expression is essentially a convolution matrix operator MTXOP applied to the input vector VECTIN and producing the output vector VECTOUT. The matrix operator MTXOP has coefficients W11-Wmn set according to the weight values ​​(i.e., synapses), while the input vector VECTIN has input values ​​A1-An, and the output vector VECTOUT has values ​​B1-Bm.

[0055] Each output value Bi is thus obtained according to a dedicated coefficient Wij through a corresponding multiplication and accumulation sequence MACi of the input value Aj. Therefore, each weighting factor Wij is dedicated to a unique pair of one input value Aj and one output value Bi.

[0056] Figure 2 The non-volatile memory point MPT is shown. ij One embodiment is isolated from the array designed to perform in-memory convolution computations. For example... Figure 4 As shown, the array includes multiple such memory points (MPTs). ij Memory points can be organized into rows by corresponding word lines and into columns by corresponding bit lines.

[0057] The memory point MPTij includes a phase-change resistor memory cell PCMij, which includes a first terminal T1 and a second terminal T2. The first terminal T1 is coupled to the bit line BLj, and the second terminal T2 is coupled to the emitter terminal E of the select bipolar transistor BJTij. The base terminal B of the select bipolar transistor BJTij is coupled to the word line WLi. The collector terminal C of the select bipolar transistor BJTij is coupled to the reference ground potential GND.

[0058] In this way, by selecting the word line WLi and the bit line BLj coupled to the memory point MPTij respectively, the rows and columns of the memory point MPTij can be selectively accessed in the array to access the cell PCMij for write and read operations.

[0059] The phase-change resistor memory cell PCMij presents a programmable resistor (and a programmable conductance Gij, which is the reciprocal of the resistor) between its terminals T1 and T2. The programmable resistor / conductance Gij can be set via a write operation.

[0060] Therefore, under a given bias between bit line BLj and word line WLi, the current flowing from bit line BLj to word line WLi is proportional to the conductance Gij, and allows the information stored by cell PCMij to be read.

[0061] More precisely, in the example read operation, the base terminal B of the selected bipolar transistor BJTij is biased to ground voltage VB = 0V, while the first terminal T1 of cell PCMij is biased to the bit line voltage VBL. Therefore, the read voltage VSE across terminals T1 and T2 of the cell is equal to the bit line voltage VBL minus the emitter-base voltage VEB. Thus, in order to use a given read voltage VSE, the bit line voltage is set to VBL = VSE + VEB.

[0062] The current IE flowing from unit PCMij to emitter terminal E has the strength of the product of conductance Gij and read voltage VSE, i.e., IE = Gij * VSE.

[0063] Figure 3 The write mechanism of a favorable example of a phase-change resistor memory cell (PCM) is shown. The same reference numerals are used to indicate... Figure 2 The same components.

[0064] Phase change materials (GSTs) possess the ability to change their phase (the physical solid state of the material). For example, GST (related to the chemical symbols of the elements germanium (G), antimony (S), and tellurium (T)) thus provides the stoichiometric composition “GexSbyTez,” the classic Ge₂Sb₂Te₅, whose natural state is crystalline or polycrystalline PC. The heating element HTR is in contact with one side of the GST.

[0065] The first terminal T1 corresponds to the top electrode that contacts one side (free side) of the phase change material PCM. The second terminal T2 corresponds to the bottom electrode that contacts the opposite (free) side of the heating element HTR.

[0066] When a sufficiently high current flows between the first terminal T1 and the second terminal T1 and through the heating element HTR, the Joule effect produces controllable temperature conditions, allowing the phase of the phase change material GST to be controlled in a reversible manner.

[0067] Therefore, it is possible to exceed the melting temperature of material GST to produce an amorphous phase, or to keep it between the crystallization temperature and melting temperature of material GST to produce a crystalline or polycrystalline phase.

[0068] Therefore, resetting the write operation IRST can change the local volume of the phase change material GST to the amorphous phase AM, and setting the write operation IST can change the amorphous local volume back to the crystalline or polycrystalline phase PC.

[0069] In the reset state RST, such as Figure 3 As shown on the left, the unit PCM comprises a local volume of amorphous phase change material GST, which exhibits high resistance (which can be assimilated to an infinite resistance value).

[0070] In setting the status ST, such as Figure 3 As shown on the right, the unit PCM includes GST, a phase change material that is fully crystallized, resulting in a normal (i.e., low) resistance value.

[0071] The reset write operation can be performed by injecting a high rectangular current pulse for a short IRST, such as 240 μA (microamp) for 100 ns (nanoseconds), and / or 270 μA for 100 ns, and / or 300 μA for 100 ns.

[0072] A setup write operation can be performed by injecting a trapezoidal current pulse with a slowly decreasing current slope IST, such as 160 μA decreasing to zero at 0.045 μA / ns, and / or 230 μA decreasing to zero at 0.045 μA / ns, and / or 260 μA decreasing to zero at 0.045 μA / ns.

[0073] refer to Figure 2 During the reset and set write operation, the base terminal B of the select bipolar transistor BJTij is biased to approximately 0V, i.e., the ground reference voltage, and the write current pulse is dissipated through the base terminal B and the collector terminal C.

[0074] Figure 4 An embodiment is shown that incorporates a portion of an array ARR of non-volatile memory points MPTij into an integrated circuit IC designed to perform memory convolution computations, as per [reference to...]. Figure 2 Described.

[0075] Therefore, each non-volatile memory point is coupled to bit lines BL1, BL2, BL3, BL4 and word lines WL1, WLi.

[0076] The memory point MPTij is selected and activated to perform convolution calculations via the input converter circuit INCVRT and the output converter circuit OUTCVRT.

[0077] The input converter circuit INCVRT includes a digital-to-analog converter (DAC) configured to receive input values ​​A1-A4, such as digital binary data, and convert the input values ​​A1-A4 into voltage signals V1-V4.

[0078] The input converter circuit INCVRT also includes a decoder circuit DEC, which is configured to select a bit line BLj for each input value Aj and continuously apply voltage signals V1-V4 on the selected bit lines BL1-BL4 over the corresponding time slots t1-t4.

[0079] Time slots t1-t4 can be spaced out sequentially and can be non-overlapping, or, if the resistance drop along the word line (as will be explained later) is low enough, the time slots can overlap or be simultaneous.

[0080] The digital-to-analog converter (DAC) and decoder circuit (DEC) are exemplary devices constituting the input converter circuit INCVRT (which may additionally include classical means for driving input values), and do not limit the implementation of the operation of the input converter circuit INCVRT.

[0081] The decoder circuit DEC is configured to select one word line WLi for each output value Bi. (As previously mentioned...) Figure 2 As described above, word line WL1 is selected by applying ground potential GND while other word lines WLi are biased to the suppression potential VWL. This mechanism of the decoder circuit DEC can be considered to be included in the output converter circuit OUTCVRT, or in different word line decoder circuits.

[0082] Therefore, the selected unit PCMij is biased by voltage signals V1-V4 on one hand and by the 0V word line voltage WL1 on the other.

[0083] refer to Figure 2 The read voltage VSE across the selected cell PCMij, generated by this bias condition, produces a cell current IE flowing to the emitter terminal E of the selected bipolar transistor BJTij.

[0084] A suppression potential VWL is applied to the word line WLi that was not selected for convolution calculation, and is set according to the conversion range of voltage signals V1-V4 to apply a read voltage VSE across the unselected word line, which does not cause destructive current to flow through the unselected cell. For example, the suppression potential can be set near the maximum level generated by the converter DAC.

[0085] Furthermore, other bit lines coupled to unselected cells can be biased to approximately 0V or kept floating so that no destructive current is generated in the selected word line WL1 and the unselected word line WLi.

[0086] In the selected cell, the cell current IE = Gij * VSE flowing at the emitter terminal E is divided into the base current IB through the base terminal B and the collector current IC through the collector terminal C in proportion to the β gain of the bipolar transistor BJTij, i.e., 1 / (1+β)IE = IB and β / (1+β)IE = IC.

[0087] Therefore, in order to draw more than half of the emitter current IE to the base terminal B, the β gain must be less than 1. For example, if β is set to 0.5, then two-thirds (2 / 3) of the cell current IE will be drawn through the base B.

[0088] Therefore, the bipolar transistor BJTij is advantageously configured to have a β gain of less than 1 in order to reduce current loss through the grounded collector terminal C.

[0089] The current drawn from the base region is called the read current IB and flows through the corresponding word line WL1.

[0090] The output converter circuit OUTCVRT includes an integrator circuit INTG for each selected word line, and this integrator circuit is coupled to the corresponding word line WL1. The integrator circuit INTG is configured to integrate the read current IB over consecutive time slots t1-t4.

[0091] Each integrator circuit INTG includes an amplifier circuit, such as an operational amplifier, which has a grounded positive input and a negative input coupled to the word line WLi.

[0092] The capacitor feedback loop FL is coupled from the output to the negative input so that charge from the current flowing through the word line WLi can accumulate on the capacitor element CAP.

[0093] The capacitor feedback loop advantageously includes switching circuits SWN and SWP, which are configured to reverse the polarity PPol and NPol of the capacitor element CAP in the feedback loop in response to a symbol control signal SGN.

[0094] Therefore, according to the symbol control signal SGN, the read current IB flowing through word line WL1 during each time slot t1-t4 can be added to charge accumulation PPol or subtracted from charge accumulation NPol on capacitor element CAP.

[0095] Each analog-to-digital converter (ADC) is configured to convert the charge accumulated from the read current IB into an output value Bi, such as a digital output value.

[0096] In other words, the convolution calculation first involves converting the input values ​​A1-A4 into voltage signals V1-V4, and then sequentially applying these voltage signals to the selected bit lines BL1-BL4 over the corresponding time slots t1-t4. Secondly, a memory point is selected because of the word line bias voltage WL1 = 0V applied to the base region of the selected bipolar transistor BJTij. The voltage signals V1-V4 bias the corresponding phase-change resistor memory cell PCMij, which generates a cell current IE, defined by the product of the cell's conductance value Gij and the corresponding voltage signals V1-V4. Thirdly, the cell current ICELL ( Figure 2 The generated read current IB flows through the base region of the selected bipolar transistor to the same selected word line WL1 and is integrated over consecutive time slots t1-t4. The integrated charge from the read current IB is then converted into the output value Bi.

[0097] In this example, the mechanism is executed simultaneously for all selected word lines corresponding to the output values ​​B1, B2, B3, and B4.

[0098] Therefore, in the output vector OUTVECT( Figure 1 Each output value B1, B2, B3, B4 in the above description for B1 is obtained in the same manner, having other memory points MPTij on the same bit lines BL1-BL4 and the same input conversion voltage signals V1-V4, but on other selected word lines and integrator circuit INTG. Therefore, in this practical real-time memory convolution computation technique, the entire output vector OUTVECT is computed once relative to the input vector INVECT.

[0099] Therefore, each output value Bi originates from the input value Aj and the weighting factor Wij provided by the unit's conductance value Gij. Figure 1 Multiplication and addition operations.

[0100] In fact, the voltage VB1 applied to the analog-to-digital converter (ADC) providing Bi can be expressed as follows: VBi = (T / C)*(Gi1*V1 + Gi2*V2 + Gi3*V3 + Gi4*V4), where T is the duration of each time slot t1-t4, and C is the capacitance value of the capacitor element CAP. Therefore, this electrical equation physically provides... Figure 1 The results of the mathematical expression for the convolution multiplication and accumulation operation MACi of Bi are shown.

[0101] The phase-change resistor memory cell PCMij is configured to present a resistance state Gij corresponding to the corresponding weighting factor Wij, for example, according to the above regarding Figure 3The described write technique can set or reset the state of a memory cell, thus corresponding to a binary weighting factor ("on" or "off"). However, this differs from the description in this paper... Figure 4 The exact same technique described applies to multi-level write operations that process multiple (i.e., strictly more than two) conductance values ​​Gij of memory cells and thus multiple weighting factor values.

[0102] Furthermore, since the converted input voltage signals V1-V4 are continuously applied to the selected bit lines BL1-BL4 over the corresponding time slots t1-t4, the read current IB of the cells in the same word line WL1 does not flow through word line WL1 simultaneously. Therefore, the strength of the read current IB is limited, and the voltage drop caused by the resistive element between the selection bipolar transistor BJTij and the output converter OUTCVRT is limited, without reducing the analog value of the signal.

[0103] Along each word line WLi, a voltage drop proportional to the resistance contribution of resistive elements RB1, RB2, RB12, RCWL, and RMWL is generated, as shown by the reference... Figure 5 Detailed explanation. Figure 4 The resistive element depicted in the diagram corresponds to Figure 5 The advantageous compact embodiment is depicted. However, the resistance contribution along the word lines is mainly caused by the word line metal strip RMWL (i.e., the metal strip provided across the array ARR to achieve word line orientation in the array layout).

[0104] Figure 5 A cross-sectional view of the semiconductor stage of an array ARR with a preferred compact embodiment of the bipolar transistor BJTij is shown.

[0105] The selected bipolar transistors BJTij are grouped into multi-emitter bipolar elements MEBJT, and in this example, each group includes four bipolar transistors.

[0106] Each multi-emitter bipolar device (MEBJT) includes a corresponding number (four) of highly doped P-type (P+) emitter regions E1-E4, a shared N-type doped base region NW, and a shared P-type doped collector region PW. The shared base region NW includes two symmetrical highly doped N-type (N+) base terminals (left base BL and right base BR) coupled to the same word line WL1, and the shared collector region PW is grounded. For example, the shared collector region PW is implemented using a semiconductor substrate.

[0107] As an alternative, an NPN bipolar transistor with appropriate complementary activation signals (i.e., word line signals and bit line signals) can be used.

[0108] In the example shown, the multi-emitter bipolar element MEBJT includes four aligned emitter regions E1-E4 and two base regions BL, BR located at opposite ends of the line.

[0109] Different emitter regions E1-E4 are located on the front side of the semiconductor substrate, that is, facing the interconnect metal layer where the phase change memory cell PCMij is located.

[0110] Therefore, for example, each emitter region E1-E4 is coupled to the corresponding phase-change resistor memory cell PCMi1-PCMi4 via contact posts.

[0111] Emitter regions E1-E4 are electrically isolated from each other by a dummy gate structure DUMG formed on the front side of the semiconductor substrate and a shallow trench isolation element SSTI with a depth greater than that of the P+ implanted emitter region. The dummy gate structure DUMG has the same structure as the gate of a MOS transistor, but is not functionally activated due to the presence of the aligned shallow trench isolation element SSTI below.

[0112] As referenced above Figure 2 As mentioned, the selected bipolar transistor BJTij is advantageously configured to have a β gain of less than 1, for example, 0.5, in order to reduce current losses to the collector region PW. The β gain can be configured by changing, for example, the doping concentration of the base region NW and the emitter region P+, as well as the thickness of the base region NW.

[0113] In such a multi-emitter bipolar device MEBJT Figure 4 The resistors RB1, RB2, RB12, RCWL, and RMWL shown correspond to:

[0114] The resistivity of the base region NW at each distance between the external emitter regions E1, E4 and the nearest base terminals BL, BR;

[0115] The resistivity of the base region NW at the distance between each internal emitter region E2, E3 and the nearest external emitter region E1, E4;

[0116] The resistivity of the base region NW at the distance between the two internal emitter regions E2 and E3;

[0117] The contact resistance between the word line WLi and the base region NW can include the resistance of the N+ base terminal, the silicided contact region, and the metal contact post; and

[0118] The resistance of the word line WLi metal strip within the distance between the two bases BL and BR.

[0119] Multiple such multi-emitter bipolar elements (MEBJTs) can be arranged in rows and columns in an array ARR.

[0120] Figure 6 An embodiment of the input converter circuit INCVRT, which allows compensation for process variations and temperature variations in the threshold voltage of a bipolar transistor, is shown.

[0121] The input converter circuit INCVRT includes analog circuitry for the memory point MPT_EMUL, comprising an analog selection bipolar transistor (BJT) and an analog current generator ICELL_EMUL.

[0122] The term "simulation" refers to the reproduction of the actual components and signals provided in the array. Accordingly, the simulated bipolar transistor BJT_EMUL is obtained, for example, by the same manufacturing method and with the same parameters as the selected bipolar transistor BJTij in the array ARR.

[0123] The current generator is configured to generate the current ICELL_EMUL of the actual read current ICELL in the analog array to bias the analog select transistor BJT_EMUL. The analog select transistor BJT_EMUL is diode-connected, i.e., its base is connected to its collector, thereby generating the emitter-gate threshold voltage VBJT under in-situ conditions.

[0124] The emitter-gate threshold voltage VBJT is provided to the positive input of a comparator, which receives a net switching voltage Vnetj from one of the input values ​​Aj at its negative input.

[0125] The term net conversion voltage Vnetj refers to the input signal Aj that is accurately converted into an analog voltage signal Vnetj. For example, the net conversion voltage Vnetj can be generated by a controllable current generator Ij, which is controlled by the input value Aj to bias a feedback resistor between the amplifier's output and the negative input.

[0126] Therefore, the input converter circuit INCVRT is configured to generate each voltage Vj( Figure 4 In the case of j = 1-4), in addition to the net conversion voltage Vnetj for each input value Aj, it also includes the offset voltage VBJT to compensate for the threshold voltage variation of the selected bipolar transistor BJTij.

[0127] Therefore, by incorporating Vj = Vnetj + VBJT into the reference... Figure 2 The expression VBL=VSE+VEB is given, then VSE=Vnetj, and the cell current ICELL is accurately generated by the undistorted analog conversion of the input value Aj.

[0128] Therefore, the process and temperature variations of the threshold voltage of the array's bipolar transistor BJTij are compensated for under actual conditions, while the input value Aj is converted into voltage signals V1-V4.

[0129] Figure 7 An embodiment of the input converter circuit INCVRT is shown that allows compensation for process variations and temperature variations affecting convolution calculations. Specifically, this embodiment allows compensation for variations in the conductance Gij of the resistive phase-change memory cell PCMij in the array and variations in the β gain of the selected bipolar transistor BJTij in the array.

[0130] The integrated circuit CI also includes a time slot calibration circuit T_CLBR, which is configured to adjust the time slot duration T relative to external operating conditions (such as temperature) and to changes in random processes.

[0131] The calibration process can be performed before each convolution calculation or each time the integrated circuit is turned on. The calibration process described below will take no more than a few microseconds.

[0132] The time slot calibration circuit T_CLBR includes a time slot generator T_GEN configured to generate a reference voltage signal V0 during an adjustable time slot T, an analog memory point MPT0, and an output converter analog circuit OUTCVRT_EMUL.

[0133] The simulated memory point MPT0 includes a reference phase-change memory cell PCM0 and a reference bipolar transistor BJT0, both of which simulate those present in the array ARR.

[0134] The reference phase-change memory cell PCM0 is configured to present a reference conductance value G0 in the write-set state. For example, during the testing phase of the production process (often referred to as "EWS," which stands for "Electronic Wafer Sorting"), a reference conductance G0 is defined for each integrated circuit IC.

[0135] The output converter analog circuit OUTCVRT_EMUL includes and Figure 4 The integrator circuit INTG is depicted in a similar configuration to an element in the array ARR, namely an amplifier circuit having a grounded positive input, a negative input coupled to the base terminal of a reference bipolar transistor BJT0, and a capacitive feedback loop coupled from the output to the negative input, the capacitive feedback loop being used for the current flowing from the base terminal to accumulate charge in the capacitor element CAP_EMUL.

[0136] The comparator circuit CMP is configured to compare the output voltage signal VOUT of the integrating amplifier circuit with the reference output voltage signal VREF. The comparison result is converted into an adjustment control signal Adj by the calibration logic circuit LGC, which is suitable for controlling the duration T of the time slot generated by the time slot generator T_GEN.

[0137] The calibration process involves adjusting the time slot duration T relative to the reference phase-change resistor memory cell PCM0 and the reference voltage signal V0 to compensate for variations in the conductance Gij of the phase-change resistor memory cell PCMij and to select the β gain of the bipolar transistor BJTij for possible temperature and process variations.

[0138] For this purpose, the calibration process includes simulating the output voltage VOUT generated by integrating the read current, and includes comparing (CMP) the simulated output value VOUT with a reference output value VREF to adjust (Adj) the time slot duration T, the read current being generated by the reference voltage signal V0 that biases the reference phase-change resistor memory cell PCM0 during the adjustable time slot T.

[0139] Advantageously, the time slot generator T_GEN is configured to generate a reference voltage signal V0, which is the sum of the net reference voltage signal Vnet0 and the bipolar transistor threshold offset VBJT, i.e., V0 = Vnet0 + VBJT, as previously discussed regarding... Figure 6 Described.

[0140] Therefore, according to the general bipolar transistor law IB = IE / (1+β), where ΔQ0 is the reference charge accumulated on the feedback capacitor element CAP_EMUL, it is achieved by applying a reference voltage signal Vnet0.

[0141] ΔQ0 can be expressed as ΔQ0=T0*IB0=T0*IE0 / (1+β0), where G0 is the reference cell in the set state, T0 is the pulse duration defined at the reference room temperature to realize ΔQ0, and VREF corresponds to the voltage VOUT provided by the accumulated reference charge ΔQ0.

[0142] If IE0 = Vnet0 * G0, then: ΔQ0 = T0 * Vnet0 * G0 / (1 + β0).

[0143] Therefore, T0 = (ΔQ0 / Vnet0)*(1+β0) / G0 [Equation 1]

[0144] Then, as β0 and G0 vary with respect to process and temperature, the time-slot calibration circuit T_CLBR adjusts the pulse duration T to compensate for these variations, ensuring that the same amount of reference charge ΔQ0 is accumulated, i.e., V is realized in the loop of the time-slot calibration circuit T_CLBR. OUT =V REF .

[0145] Therefore, for β C and G C (Changed β gain and conductance), calibrated time slot duration T C Equation 1 represents the following:

[0146] T C =(ΔQ0 / Vnet0)*(1+β) C ) / G C [Equation 2]

[0147] Therefore, from input value A j The converted voltage signal Vnet j Provides the accumulated charge ΔQ at room temperature j0 , represented as

[0148] ΔQ j0 =T0*Vnet j *G0 / (1+β0), and, by Equation 1:

[0149] ΔQ j0 =Vnet j *(ΔQ0 / Vnet0) [Equation 3]

[0150] From voltage signal Vnet j The actual conditional cumulative charge ΔQ jC (with in-situ adjustment time slot T) C ) is represented as: ΔQ jC =T C *Vnet j *G C / (1+β C ), where TC comes from Equation 2, ΔQ jC =Vnet j *(ΔQ0 / Vnet0), therefore, according to Equation 3, ΔQ jC =ΔQ j0 .

[0151] This development indicates that, after calibration and obtaining the calibrated time slot TC, for any value Vnet j The accumulated charge remains constant regardless of temperature and random process variations.

[0152] Already combined Figures 1 to 7 The described embodiments advantageously allow the use of very compact bipolar transistors as selectors for phase-change resistor units to perform in-memory convolution calculations. Positive and negative weighting factors can be calculated, and the embodiments can be used for binary weighting factors and multi-level weighting factors.

[0153] The distributed time slots of this embodiment do not provide the cumulative voltage drop effect along the word lines or bit lines of the array and allow for energy savings. This embodiment overcomes the classical constraints of bipolar transistors (such as threshold voltage and β gain variability) and cell conductance variability.

Claims

1. A method for calculating CNVL by convolving input values ​​using weight factors, the method comprising: The input value is converted into a voltage signal, and the voltage signal is continuously applied over the corresponding time slot to the selected bit line in the non-volatile memory point array. Each non-volatile memory point includes a phase-change resistor memory cell and a bipolar selection transistor. The phase-change resistor memory cell is coupled to the bit line and has a resistance state corresponding to a weighting factor. The bipolar selection transistor is coupled in series with the phase-change resistor memory cell and has a base terminal coupled to the word line. The corresponding voltage signal biases the corresponding phase-change resistor memory cell. The bipolar selection transistor is set to have a β gain of less than 1. The read current generated by the voltage signal of the phase-change resistor memory cell with the corresponding bias and flowing through the selected word line is integrated over consecutive time slots; as well as The integrated read current is converted into an output value.

2. The method according to claim 1, further comprising: The decoding operation is performed by selecting a selected bit line for each input value and a selected word line for each output value.

3. The method of claim 1, wherein the bipolar selection transistors are grouped into a multi-emitter bipolar element group, and wherein each bipolar element includes a plurality of emitter regions, a shared base region having two symmetrical base terminals coupled to the same word line, and a shared ground collector region, each phase-change resistor memory cell being coupled to a corresponding emitter region.

4. The method according to claim 1, further comprising: The phase-change resistor memory cell is programmed to a resistance state corresponding to the corresponding weighting factor.

5. The method of claim 4, wherein programming the phase-change resistor memory cell comprises: For each resistor state, ensure that the write current flows in only one direction.

6. The method of claim 1, wherein integrating the read current over the consecutive time slots comprises: An amplifier coupled to a feedback loop is used, the feedback loop including a capacitor element and a switching circuit capable of reversing the polarity of the capacitor element in the feedback loop in response to a symbol control signal.

7. The method of claim 1, wherein converting the input value into the voltage signal comprises: In addition to the net conversion voltage for each input value, an offset voltage is generated to compensate for the threshold voltage of the bipolar selection transistor.

8. The method of claim 7, wherein converting the input value into the voltage signal comprises: The offset voltage is generated in situ by simulating the read current to simulate a bipolar selection transistor under bias conditions.

9. The method of claim 1, wherein the time slot calibration operation comprises: Adjust the time slot duration associated with the reference phase-change resistor memory cell and the reference output value to compensate for possible temperature and process variations in the conductance of the phase-change resistor memory cell and the β gain of the bipolar selection transistor.

10. The method of claim 9, wherein adjusting the duration of the time slot comprises: The simulation integrates the read current to generate an output value, the read current being generated by a reference voltage signal biasing the reference phase-change resistor memory cell during an adjustable time slot, and includes comparing the simulated output value with the reference output value to adjust the time slot duration.

11. An integrated circuit for calculating CNVL by convolving input values ​​using weight factors, the integrated circuit comprising: A non-volatile memory dot array, each non-volatile memory including a phase-change resistor memory cell and a bipolar selection transistor, the phase-change resistor memory cell being coupled to a bit line and configured to provide a resistance state corresponding to a weighting factor, and the bipolar selection transistor being coupled in series with the phase-change resistor memory cell and having a base terminal coupled to a word line, wherein each bipolar selection transistor has a β gain of less than 1. An input converter circuit is configured to provide the input value and convert the input value into a voltage signal, and is configured to continuously apply the voltage signal on a selected bit line over a corresponding time slot; as well as The output converter circuit is configured as follows: The read current generated by the voltage signal of the phase-change resistor memory cell with corresponding bias and flowing through the selected word line is integrated over consecutive time slots, and The integrated read current is converted into an output value.

12. The integrated circuit of claim 11, further comprising a decoder circuit, the decoder circuit being configured to: For each input value, select a chosen bit line, and For each output value, select a chosen word line.

13. The integrated circuit according to claim 11, The bipolar selection transistors are grouped into multi-emitter bipolar elements. Each multi-emitter bipolar element includes multiple emitter regions, a shared base region with two symmetrical base terminals coupled to the same word line, and a shared ground collector region. Each phase-change resistor memory cell is coupled to a corresponding emitter region.

14. The integrated circuit of claim 11, wherein for each selected word line, the output converter circuit comprises: An integrator circuit includes an amplifier coupled to a feedback loop, the feedback loop including a capacitor element and a switching circuit capable of reversing the polarity of the capacitor element in the feedback loop in response to a sign control signal.

15. The integrated circuit of claim 11, wherein the input converter circuit is configured to: Generate an offset voltage to compensate for the threshold voltage of the bipolar selection transistor, and Provides the net conversion voltage for each input value.

16. The integrated circuit of claim 11, wherein the input converter circuit includes analog circuitry for a memory point, the analog circuitry being configured to simulate a bipolar selection transistor in a bias condition by simulating a read current in order to generate an offset voltage in situ.

17. The integrated circuit of claim 11, wherein the time slot calibration circuit is configured to adjust the time slot duration in relation to a reference phase-change resistor memory cell and a reference output value in order to compensate for possible temperature and process variations in the conductance of the resistor phase-change memory cell and the β gain of the bipolar selection transistor.

18. The integrated circuit of claim 17, wherein the time slot calibration circuit comprises: The analog circuitry of the memory point and the analog circuitry of the output converter are configured to simulate the output value generated by integrating the read current, which is generated by a reference voltage signal biasing the reference phase-change resistor memory cell during an adjustable time slot, and the time slot calibration circuit includes a comparator configured to compare the simulated output value with the reference output value in order to control a calibration feedback circuit that adjusts the duration of the time slot.

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