Non-volatile memory and method of data erasure thereof

Abstract

Embodiments of the present application disclose a non-volatile memory and a data erasing method. The memory comprises a plurality of memory cell strings, each of which comprises a selected gate transistor and a memory cell connected in series. The method comprises: applying a step erase voltage with a stepped rising voltage waveform to a memory cell string to be subjected to an erasing operation; during the step erase voltage rising from a middle level to a peak level, raising a voltage of the selected gate transistor from a starting level to a predetermined peak level, and raising a voltage of a predetermined region from a starting level to a predetermined peak level, so as to generate a gate-induced drain leakage current in the memory cell string, the predetermined region being adjacent to the selected gate transistor and comprising at least one memory cell. By applying a bias voltage to the selected gate transistor and the predetermined region adjacent to the selected gate transistor, the gate-induced drain leakage current can be generated in a channel of the memory cell string, and effective data erasing is realized.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and more particularly, to a non-volatile memory and a data erasing method of the non-volatile memory. BACKGROUND

[0002] Recently, non-volatile memories with "vertical" (i.e., in three dimensions (3D)) stacked memory cells are widely used in electronic devices, which usually include multiple levels (e.g., top and bottom levels in a non-volatile memory formed by a dual-stack process) stacked vertically, and in each level, there can be multiple vertically stacked memory cells. In order to effectively read, write and erase in a non-volatile memory with multiple levels, each level can be erased individually.

[0003] In addition, as the number of stacked layers of the non-volatile memory continues to increase, the connection method at the bottom of the channel layer has developed from the traditional selective epitaxy structure to lateral communication and the currently latest bottom communication method. Forming a highly doped semiconductor layer (which usually has the same type of doping impurities as the channel layer) at the bottom to connect the channel layer has become the mainstream method for preparing non-volatile memories, and the non-volatile memory obtained based on the above preparation method is not suitable for bulk erasing, therefore, it is necessary to use gate-induced drain leakage (GIDL) to generate an auxiliary bulk bias to assist the level erasing operation to achieve data erasing of the non-volatile memory.

[0004] Therefore, how to realize efficient non-volatile memory level erasing operation and gate-induced drain leakage erasing operation is a problem that those skilled in the art are eager to solve. SUMMARY

[0005] In order to solve or partially solve the above problems or other problems, various embodiments to be further described below are proposed in the present application.

[0006] One aspect of the embodiments of the present application provides a data erasing method of a non-volatile memory, the memory including a plurality of memory cell strings, each of the memory cell strings being formed on a well-doped region of a substrate and including a series of select gate transistors and memory cells, the method comprising: applying a step erasing voltage to a memory cell string to be subjected to an erasing operation, the step erasing voltage having a voltage waveform rising in steps; and during the step erasing voltage rising from a middle level thereof to a peak level thereof, raising a voltage of the select gate transistor from a starting level thereof to a predetermined peak level thereof and raising a voltage of a predetermined region from a starting level thereof to a predetermined peak level thereof, thereby generating a gate-induced drain leakage current in the memory cell string, wherein the predetermined region is adjacent to the select gate transistor and includes at least one of the memory cells.

[0007] According to one embodiment of the present application, the select gate transistor includes a top select gate transistor connected to the bit line and a bottom select gate transistor connected to the well doped region; and the predetermined region includes at least a first predetermined region and a second predetermined region, wherein the first predetermined region is adjacent to the bottom select gate transistor and includes at least one of the memory cells, and the second predetermined region is adjacent to the top select gate transistor and includes at least one of the memory cells.

[0008] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the predetermined region of the string of memory cells from its starting level to its peak level during the raising of the voltage of the select gate transistor from its starting level to its peak level.

[0009] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the predetermined region of the string of memory cells from its starting level to its peak level at the same time as the raising of the voltage of the select gate transistor from its starting level to its peak level, and the peak level of the select gate transistor is equal to the peak level of the predetermined region.

[0010] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the predetermined region of the string of memory cells from its starting level to its peak level after the raising of the voltage of the select gate transistor from its starting level.

[0011] According to one embodiment of the present application, the memory cells include real memory cells and dummy memory cells, and the first predetermined region is adjacent to the bottom select gate transistor and includes at least one of the first dummy memory cells.

[0012] According to one embodiment of the present application, the dummy memory cells include first dummy memory cells located between the bottom select gate transistor and the well doped region, and the first predetermined region is spaced apart from the substrate by at least one of the first dummy memory cells.

[0013] According to one embodiment of the present application, the method further includes setting the at least one of the first dummy memory cells for spacing to a floating state during the erase operation.

[0014] According to one embodiment of the present application, the method further comprises applying the step erase voltage to at least one of the first dummy memory cells for the interval.

[0015] According to one embodiment of the present application, the memory cells include real memory cells and dummy memory cells, the dummy memory cells including select level dummy memory cells adjacent to the select gate transistors, the method further comprising raising the voltage of the select level dummy memory cells from their starting level to their peak level during the interval in which the step erase voltage is raised from its intermediate level to its peak level.

[0016] According to one embodiment of the present application, the method further comprises raising the voltage of the select level dummy memory cells from their starting level to their peak level during the interval in which the voltage of the select gate transistors is raised from their starting level to their predetermined peak level.

[0017] According to one embodiment of the present application, the method further comprises raising the voltage of the select level dummy memory cells from their starting level to their peak level either simultaneously with the raising of the voltage of the select gate transistors from their starting level to their predetermined peak level, or after the raising of the voltage of the select gate transistors from their starting level.

[0018] According to one embodiment of the present application, raising the voltage of the select gate transistors from their starting level to their predetermined peak level and raising the voltage of predetermined regions from their starting level to their predetermined peak level comprises raising the voltage of the first predetermined region from its starting level to its peak level during the interval in which the voltage of the bottom select gate transistors is raised from their starting level to their peak level, and raising the voltage of the second predetermined region from its starting level to its peak level during the interval in which the voltage of the top select gate transistors is raised from their starting level to their peak level.

[0019] According to one embodiment of the present application, raising the voltage of the select gate transistors from their starting level to their predetermined peak level and raising the voltage of predetermined regions from their starting level to their predetermined peak level comprises raising the voltage of the first predetermined region from its starting level after the voltage of the bottom select gate transistors is raised from their starting level, and raising the voltage of the second predetermined region from its starting level to its predetermined peak level simultaneously with the raising of the voltage of the top select gate transistors from their starting level to their predetermined peak level, and the predetermined peak level of the top select gate transistors is equal to the predetermined peak level of the second predetermined region.

[0020] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the first predetermined region from its starting level to its peak level while raising the voltage of the bottom select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level to the predetermined peak level while raising the voltage of the top select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

[0021] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the first predetermined region from its starting level to its peak level while raising the voltage of the bottom select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level to the predetermined peak level while raising the voltage of the top select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

[0022] According to one embodiment of the present application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes raising the voltage of the first predetermined region from its starting level to its peak level while raising the voltage of the bottom select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level to the predetermined peak level while raising the voltage of the top select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

[0023] Another aspect of the embodiments of the present application provides a non-volatile memory, comprising: a memory array formed on a well doped region of a substrate and comprising a plurality of memory cells, wherein the memory cells in each column are connected to a same bit line to form a memory cell string, a plurality of the memory cell strings are formed as a memory block, the memory block comprises a plurality of levels stacked vertically in a direction perpendicular to the substrate, and the memory cell string comprises a plurality of sub-memory cell strings belonging to different levels; and a control circuit coupled with the memory array and configured to control level selection of the plurality of levels and perform a level erase operation and a gate induced drain leakage (GIDL) erase operation on the selected level according to any one of the data erase methods of the non-volatile memory provided by the aspect of the embodiments of the present application.

[0024] According to one embodiment of the present application, the memory array is a three-dimensional NAND memory array, and the non-volatile memory is a three-dimensional NAND memory.

[0025] Another aspect of the embodiments of the present application provides a memory system, which includes a controller and the non-volatile memory provided by another aspect of the embodiments of the present application, the controller being coupled to the memory and configured to control the memory to store data.

[0026] Another aspect of the embodiments of the present application provides an electronic device, which includes the non-volatile memory provided by another aspect of the embodiments of the present application.

[0027] The non-volatile memory and the data erasing method thereof, the memory system and the electronic device provided by at least one embodiment of the present application can include two time periods, in which the erasing voltage applied to the memory cell string is raised from a starting level to an intermediate level in the first time period, and the erasing voltage is raised from the intermediate level to a peak level in the second time period. By applying an auxiliary voltage (a predetermined peak level) to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor in the second time period, a gate-induced drain leakage current can be generated, so as to realize a high-efficiency non-volatile memory level erasing operation and a gate-induced drain leakage erasing operation.

[0028] Further, according to at least one embodiment of the present application, the auxiliary voltage is applied to the predetermined region adjacent to the select gate transistor during the application of the auxiliary voltage to the select gate transistor of the memory cell string. Specifically, when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor respectively (for example, the auxiliary voltage is applied to the select gate transistor of the memory cell string first, and then the auxiliary voltage is applied to the predetermined region adjacent to the select gate transistor), the breaking performance of the select gate transistor as a selection switch of the memory cell string can be improved, so as to avoid crosstalk and leakage between adjacent memory cell strings; when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the data erasing method of the non-volatile memory can be improved.

[0029] In addition, according to at least one embodiment of the present application, the predetermined region adjacent to the bottom select gate transistor is close to the level to be executed with the erasing operation, so as to improve the gate-induced drain leakage current, and realize a high-efficiency data erasing of the non-volatile memory. BRIEF DESCRIPTION OF DRAWINGS

[0030] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings.

[0031] Figure 1 is a block diagram of a non-volatile memory according to an embodiment of the present application;

[0032] Figure 2 is a partial structural sectional view of a non-volatile memory according to an embodiment of the present application;

[0033] Figure 3 is a partial equivalent circuit schematic diagram of a memory array according to an embodiment of the present application;

[0034] Figure 4 is a flowchart of a data erasing method for a non-volatile memory according to an embodiment of the present application;

[0035] Figure 5 is a partial circuit structural diagram of a non-volatile memory according to an embodiment of the present application;

[0036] Figure 6 is a partial circuit structural diagram of a non-volatile memory according to another embodiment of the present application;

[0037] Figure 7 is a voltage waveform timing chart for a non-volatile memory according to an embodiment of the present application;

[0038] Figure 8 is a voltage waveform timing chart for a non-volatile memory according to another embodiment of the present application;

[0039] Figure 9 is a voltage waveform timing chart for a non-volatile memory according to yet another embodiment of the present application;

[0040] Figure 10 is a voltage waveform timing chart for a non-volatile memory according to yet another embodiment of the present application;

[0041] Figure 11 is a structural schematic diagram of a memory system according to an embodiment of the present application; and

[0042] Figure 12 is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] Example embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0044] It will be further understood that the terms "on," "connected to," "coupled to," or "connected with," when used in this disclosure, can mean that the element or layer is directly on, connected to, coupled to, or connected with, another element or layer, or intervening elements or layers can be present. In contrast, the terms "directly on," "directly connected to," or "directly coupled to" mean that there are no intervening elements or layers present. To this end, the term "connected" can refer to physical, electrical, and / or fluidic connections with or without intervening elements.

[0045] Throughout the specification, like drawing numbers refer to like elements whenever practical. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0046] While the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of one or more embodiments. The term "first," "second," etc. can be used to distinguish different classes or groups of elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. To this end, the term "connected" can refer to physical, electrical, and / or fluidic connections with or without intervening elements.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0049] Figure 1 A block diagram of a non-volatile memory 100 according to one embodiment of this application is shown. Figure 1 As shown, the non-volatile memory 100 includes a memory array 1021 and a control circuit 1011 coupled together. In some embodiments, the memory array 1021 and the control circuit 1011 may be arranged on the same chip. In other embodiments, the memory array 1021 may be arranged on an array chip, and the control circuit 1011 may be arranged on a different chip (e.g., implemented using complementary metal-oxide-semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together by processes such as bonding. In some embodiments, the non-volatile memory 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0050] The non-volatile memory 100 can be configured to store data in the memory array 1021 and perform operations in response to received commands (CMDs). In some embodiments, the non-volatile memory 100 can receive write commands, read commands, erase commands, etc., and can perform operations accordingly.

[0051] In one implementation, the non-volatile memory 100 receives an erase command with an address, and then the non-volatile memory 100 resets one or more memory cells at that address to an unprogrammed state (or erased state), such as "1" for a NAND memory cell.

[0052] Typically, the storage array 1021 may include one or more storage planes 160, and each storage plane 160 may include multiple storage blocks (e.g., Figure 1 The block shown 1 to block N). Each storage block may also include multiple vertically stacked levels (e.g.,Figure 1 The illustrated, block 1 through level M included in the non-volatile memory 100 of FIG. 1. In some examples, the concurrent operations can occur at different storage planes 160. In some embodiments, each of the levels 1 through M is a minimum unit that performs an erase operation.

[0053] In some embodiments, the storage array 1021 is a flash memory array and is implemented using 3D NAND flash technology. In some embodiments, the control circuit 1011 includes a row decoder 110, a page buffer circuit 120, a data input / output (I / O) circuit 130, a voltage generator 140, and a control circuit 150 coupled together. The row decoder 110 can receive an address, referred to as a row address (RA ADDR), generate word line (WL) signals and selection signals (such as top select gate (TSG) signals, bottom select gate (BSG) signals, etc.) based on the row address, and provide the WL signals and the selection signals to the storage array 1021. Further, during an erase operation, the row decoder 110 provided by the present disclosure can provide appropriate WL signals and selection signals.

[0054] The page buffer circuit 120 is coupled to bit lines (BL) of the storage array 1021 and is configured to buffer data during read and write operations. The data I / O circuit 130 is coupled to the page buffer circuit 120 via data lines DL. In one example (e.g., during a write operation), the data I / O circuit 130 is configured to receive data from an external circuit of the non-volatile memory 100 and provide the received data to the storage array 1021 via the page buffer circuit 120.

[0055] The voltage generator 140 is configured to generate voltages at appropriate levels for appropriate operations of the non-volatile memory 100. For example, during a data erase operation, the voltage generator 140 can generate voltages at appropriate levels for bit line voltages suitable for an erase operation, well doping region voltages, various word line voltages, selection voltages, predetermined region voltages, etc. For example, a staircase erase voltage is provided to a well doping region of the storage array 1021 during a data erase operation. A staircase erase assist voltage is provided to the row decoder 110, so that the row decoder 110 can output a top select gate signal at an appropriate voltage level during a data erase operation. A peak voltage of a predetermined region is provided to the row decoder 110, so that the row decoder 110 can output a predetermined region signal at an appropriate voltage level during a data erase operation. A staircase erase voltage is provided to the page buffer circuit 120, so that the page buffer circuit 120 can drive a bit line (BL) at an appropriate voltage level during an erase operation. In addition, the staircase erase voltage can also be applied to the bit line without going through the page buffer circuit 120.

[0056] The control circuit 150 is configured to receive a command (CMD) and an address (ADDR), and based on the command and the address, provide control signals to the circuits such as the row decoder 110, the page buffer circuit 120, the data I / O circuit 130, the voltage generator 140, etc. For example, the control circuit 150 can generate a row address R ADDR and a column address C ADDR based on the address ADDR, and provide the row address R ADDR to the row decoder 110, and provide the column address to the data I / O circuit 130. In another embodiment, the control circuit 150 can control the voltage generator 140 to generate a voltage at an appropriate level based on the received CMD. The control circuit 150 can coordinate the other circuits to provide signals to the memory array 1021 at appropriate times and at appropriate voltage levels.

[0057] The control circuit 150 can include a first portion control circuit 155 configured to generate appropriate control signals to control the other circuits to provide appropriate signals to the memory array 1021 for an erase operation using a hierarchical erase mechanism and a GIDL erase mechanism, in other words, the first portion control circuit 155 is a control circuit for hybrid erase. Signals with appropriate timing and voltage levels for the memory array 1021 can effectuate a data erase operation of the non-volatile memory using the hierarchical erase mechanism and the GIDL erase mechanism. The present application will refer to Figures 4 to 12 The waveforms of the signals are described in detail below.

[0058] Figure 2 A partial structure cross-sectional view of a non-volatile memory 200 according to an embodiment of the present application is shown. As Figure 2 shown, in an embodiment of the present application, the non-volatile memory 200 can include a three-dimensional memory array chip 202 and a peripheral circuit chip 201 electrically coupled together by, for example, a bonding process, etc.

[0059] In some embodiments, the non-volatile memory 200 can include a plurality of array chips 202 and peripheral circuit chips 201. The array chip 202 includes a substrate 203 and a stack structure 290 formed on the substrate 203. The peripheral circuit chip 201 includes a substrate and peripheral circuits formed on the substrate. For simplicity, a main surface of the substrate 203 is referred to as an X Y plane, and a direction perpendicular to the main surface is referred to as a Z direction.

[0060] The substrate 203 and the substrate of the peripheral circuit chip 201 can each be any appropriate substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. In other words, the substrate 203 and the substrate of the peripheral circuit chip 201 can each include a semiconductor material such as a group IV semiconductor, a group III a group V compound semiconductor, or a group II VI oxide semiconductor. The group IV semiconductor can include Si, Ge, or SiGe. As an alternative, the substrate 203 and the substrate of the peripheral circuit chip 201 can each be a bulk wafer or an epitaxial layer, respectively.

[0061] The stack structure 290 includes gate layers 295 and insulating layers 294 which are alternately stacked. The gate layers 295 are made of gate stack materials such as a high dielectric constant (high-k) gate insulator layer and a metal gate (MG) electrode. The insulating layers 294 are made of insulating materials such as silicon nitride and silicon dioxide. The gate layers 295 and the insulating layers 294 are configured to form vertically stacked transistors in the Z direction, the gate layers 295 corresponding to gates of the transistors.

[0062] The nonvolatile memory 200 can include an array of memory cells and peripheral circuits (e.g., a row decoder 110, a page buffer circuit 120, a data I / O circuit 130, a voltage generator 140, a control circuit 150, and the like). The peripheral circuits are formed in the peripheral circuit chip 201, and the array of memory cells is formed in the array chip 202. The array chip 202 can include a core region 01 and a staircase region 02, the array of memory cells being formed in a portion of the core region 01 where the stack structure 290 is located, and including a plurality of vertical strings of memory cells 280. The staircase region 02 can facilitate connections to, for example, gates of memory cells in the strings of memory cells 280, gates of select gate transistors, and the like. The gates of the memory cells in the strings of memory cells 280 correspond to word lines in a memory architecture.

[0063] The strings of memory cells 280 are formed of channel structures 281 which extend through the stack structure 290 and vertically (in the Z direction) into the substrate 203. In other words, the channel structures 281 and the stack structure 290 collectively form the strings of memory cells 280.

[0064] The channel structures 281 can include, in the X The functional layer and the semiconductor layer on the Y plane having a circular shape and extending in the Z direction to the substrate 203 can include a blocking insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), and a tunnel insulating layer (e.g., silicon oxide). The semiconductor layer can be made of any suitable semiconductor material such as polysilicon or monocrystalline silicon, and the semiconductor material can be selected to be undoped or can also be selected to include P-type or N-type doping impurities. In one embodiment, the blocking insulating layer can be formed on the sidewall of the hole for the channel structure 281 that can pass through the stack structure 290 and extend into the substrate 203, and then the charge storage layer, the tunnel insulating layer, the semiconductor layer, and the insulating fill layer can be sequentially stacked from the sidewall. The insulating fill layer can be formed of an insulating material such as silicon oxide and / or silicon nitride, and / or can be formed as an air gap.

[0065] The substrate 203 can include a well doped region such as a highly doped semiconductor layer 205 (or referred to as a well doped region 205) for electrical connection with the semiconductor layer in the channel structure 281. As an option, the semiconductor layer 205 can be electrically connected with the bottom of the semiconductor layer in the channel structure 281, as another option, the semiconductor layer 205 can be electrically connected with the sidewall of the semiconductor layer in the channel structure 281, or electrically connected with the bottom and the sidewall of the semiconductor layer in the channel structure 281.

[0066] The semiconductor layer 205 can be formed as a source conductive connection of the memory cell string 280. The semiconductor layer 205 can include one or more layers. The semiconductor layer 205 can be made of, for example, a silicon material such as intrinsic polysilicon, doped polysilicon such as N-type doped silicon or P-type doped silicon, etc. As an option, the semiconductor layer 205 can also include a metal silicide to improve conductivity. The semiconductor layer 205 is similarly a source conductive connection of other memory cell strings 280 and thus forms an array common source (ACS). In some embodiments, when the memory cell string 280 is configured to be erased in a tier, the semiconductor layer 205 can extend and cover the core region and the staircase region of the memory block to which the tier belongs.

[0067] In some embodiments, the vertically stacked transistors formed by the gate layer 295 and the insulating layer 294 can include a memory cell (or can be referred to as a memory cell transistor) and a select gate transistor (e.g., one or more bottom select gate transistors, or one or more top select gate transistors, etc.). The semiconductor layer of the channel structure 281 described above corresponds to a channel portion of the transistor in the memory cell string 280, and the gate layer 295 corresponds to a gate of the transistor in the memory cell string 280.

[0068] The memory cells can have different threshold voltages based on carrier capture in a portion of the charge storage layer of the channel structure 281 described above, which corresponds to the floating gate of the memory cell. For example, when a large number of holes are captured (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, and the memory cell transistor is in an unprogrammed state corresponding to logic "1" (also known as an erased state). When holes are expelled from the floating gate, the threshold voltage of the memory cell is higher than the predefined value, and therefore the memory cell transistor is in a programmed state corresponding to logic "0".

[0069] A typical transistor includes a gate for controlling a channel, and a drain and a source on each side of the channel. Alternatively, the upper side of the transistor's channel can be called the drain, and the lower side the channel can be called the source. Alternatively, the drain and source can be interchanged in certain drive configurations. Furthermore, the aforementioned top-level select-gate transistor can be connected to the drain above it, and the bottom-level select-gate transistor can be connected to the source below it.

[0070] One or more top-level select-gate transistors are configured to couple / decouple memory cells in memory cell string 280 to bit lines. One or more bottom-level select-gate transistors are configured to couple / decouple memory cells in memory cell string 280 to ACS (common source line).

[0071] The bottom-level select-gate transistor is controlled by the bottom-level select-gate. For example, when the bottom-level select-gate voltage (the voltage applied to the bottom-level select-gate) is greater than the threshold voltage of the bottom-level select-gate transistor, the bottom-level select-gate transistor is turned on, and the memory cell is coupled to the ACS. When the bottom-level select-gate voltage is less than the threshold voltage of the bottom-level select-gate transistor, the bottom-level select-gate transistor is turned off, and the memory cell is decoupled from the ACS. Similarly, the top-level select-gate transistor is controlled by the top-level select-gate.

[0072] In some embodiments, the channel structure 281 in X It has a circular shape in the Y-plane and in the X-plane... Z-plane and Y-plane It has a cylindrical shape in the Z-plane. In the X... In the Y plane, a plurality of channel structures 281 can be provided separately from each other and form an array of memory cells. The array of channel structures 281 can have any appropriate array shape, such as a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. The array of memory cells can be divided into a plurality of memory blocks by gate line gap structures 270 having a pitch from the channel structures 281 in the X direction. Each memory block includes a plurality of levels stacked from bottom to top (Z direction). In other words, a plurality of memory cell strings 280 are formed as a memory block, the memory block includes a plurality of levels stacked vertically in a direction perpendicular to the substrate 203 (Z direction), and thus the memory cell string 280 can include a plurality of sub-memory cell strings belonging to different levels.

[0073] In some embodiments, a redundant level including at least one dummy memory cell is further provided between the plurality of levels. The dummy memory cell and the memory cell are simultaneously prepared, and can be used for process and electrical buffering.

[0074] Figure 3 A partial equivalent circuit schematic diagram of a three-dimensional memory device 300 according to one embodiment of the present application is shown. As Figure 3As shown, by way of example, the three-dimensional memory device 300 can be divided into a plurality of memory blocks, each memory block including two tiers, such as a top tier 452 and a bottom tier 450. The three-dimensional memory device 300 can also include a memory cell string 212 having a plurality of stacked memory cells 340, which can include a plurality of sub-memory cell strings belonging to different tiers, where a sub-memory cell string formed by a plurality of memory cells 340-1 is in the bottom tier 450, and a sub-memory cell string formed by a plurality of memory cells 340-2 is in the top tier 452. The three-dimensional memory device 300 also includes a conductive plug 460 between the top tier 452 and the bottom tier 450. Thus, in the three-dimensional memory device 300 having a plurality of tiers, a memory cell 340-2 in the top tier 452 can be electrically connected with a memory cell 340-1 in the bottom tier 450 to form a memory cell string 212. The memory cell string 212 can also include at least one field effect transistor (e.g., MOSFET) at each end, which are controlled by a bottom select gate 332 and a top select gate 334, respectively. The two respective transistors are referred to as a bottom select gate transistor 332-T and a top select gate transistor 334-T. The stacked memory cells 340 can be controlled by a control gate 333, which includes a control gate 333-1 corresponding to the memory cell 340-1 and 333-2 corresponding to the memory cell 340-2, where the control gate 333 is connected to a word line (not shown) of the three-dimensional memory device 300. A drain terminal of the top select gate transistor 334-T can be connected to a bit line 341, and a source terminal of the bottom select gate transistor 332-T can be connected to a well doped region from which an ACS 464 can be formed and can be shared by the memory cell strings 212 in an entire memory block.

[0075] In a non-volatile memory, the memory cells of each row in each tier are connected to the same word line WL, and the memory cells in each column are connected to the same bit line BL. Each word line can correspond to a page, a memory block is composed of a plurality of pages, and a plane can be composed of a plurality of memory blocks. Further, in a non-volatile memory having a plurality of tiers, each tier can be processed individually for efficient reading, writing, and erasing, for example, each tier in a three-dimensional non-volatile memory can perform an erase operation independently of other tiers. In addition, reading and writing operations can also be performed in a memory page including memory cells sharing the same word line.

[0076] The above describes a three-dimensional non-volatile memory structure including two tiers. The following describes a data erasing method for the three-dimensional non-volatile memory provided by the embodiments of the present application in detail with reference to the accompanying drawings.

[0077] Figure 4 is a flow chart of a data erase method 1000 of a non-volatile memory according to an embodiment of the present application. As shown in Figure 4 the data erase method 1000 of the non-volatile memory includes the following steps:

[0078] Step S1, applying a step erase voltage to a string of memory cells to be erased, the step erase voltage having a stepped rising voltage waveform.

[0079] Step S2, during the step erase voltage rising from its intermediate level to its peak level, raising the voltage of the select gate transistor from its starting level to its predetermined peak level, and raising the voltage of the predetermined region from its starting level to its predetermined peak level, thereby generating a gate-induced drain leakage current in the string of memory cells, wherein the predetermined region is adjacent to the select transistor and includes at least one memory cell.

[0080] The above steps will be described in detail below so that those skilled in the art can more clearly understand the specific implementation of the above method 1000.

[0081] Step S1

[0082] Figure 5 is a partial circuit structure diagram of a non-volatile memory according to an embodiment of the present application. Figure 6 is a partial circuit structure diagram of a non-volatile memory according to another embodiment of the present application.

[0083] In step S1, the non-volatile memory can include a plurality of memory blocks, as shown in Figure 5 The memory block can include a string of memory cells 212 composed of a top tier 452 and a bottom tier 450. Any tier of the above string of memory cells 212 to be erased can be selected as a first tier for tier erase operation, or the entire memory block where the string of memory cells 212 is located can be selected for erase operation. Tier erase operation refers to performing erase operation on at least one tier of the memory block, but not on the entire memory block.

[0084] In an embodiment of the present application, the string of memory cells 212 can include a string of memory cells, a top tier select gate transistor 334-T, and a bottom tier select gate transistor 332-T, wherein TSG represents an electrical signal applied to a top tier select gate for controlling the top tier select gate transistor 334-T, and BSG represents an electrical signal applied to a bottom tier select gate for controlling the bottom tier select gate transistor 332-T.

[0085] Furthermore, redundant layers are provided between the multiple layers, each including at least one pseudo memory cell (e.g., IDPDMY located between the top layer 452 and the bottom layer 450). The pseudo memory cell and the memory cell are fabricated simultaneously and can be used for process and electrical buffering.

[0086] For example, in one embodiment of this application, the memory cell string 212 may include at least one top-level select gate transistor 334-T, which may form a top-level select layer. Alternatively, the top-level select layer may include at least one top-level select gate transistor 334-T and at least one top-level pseudo-memory cell 334'. The top-level pseudo-memory cell 334' and the top-level select gate transistor 334-T may be fabricated simultaneously and used for process and electrical buffering, wherein TSG_DMY represents an electrical signal applied to the gate of the top-level pseudo-memory cell 334'.

[0087] Similarly, the memory cell string 212 may also include a bottom pseudo memory cell 332' adjacent to the bottom select gate transistor 332-T. The bottom pseudo memory cell 332' and the bottom select gate transistor 332-T may be fabricated simultaneously and used for process and electrical buffering, where BSG_DMY represents the electrical signal applied to the gate of the bottom pseudo memory cell 332'.

[0088] The top-level pseudo-memory unit 334' and the bottom-level pseudo-memory unit 332' can be referred to as the selection-level pseudo-memory unit.

[0089] In addition, such as Figure 6 As shown, a redundant layer comprising at least one first dummy memory cell 205' is further disposed between the bottom selected gate transistor 332-T and the well doped region 205 of the substrate. The dummy memory cell and the memory cell in this redundant layer are fabricated simultaneously and can be used for process and electrical buffering. DMY represents an electrical signal applied to a predetermined region of the redundant layer to which the dummy memory cell 205' belongs.

[0090] Figure 7 This is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of this application. Figure 8 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application. Figure 9 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application. Figure 10 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application.

[0091] Currently, the connection mode of the channel layer bottom of the non-volatile memory has developed from the traditional selective epitaxy structure to the lateral communication and the currently latest bottom communication mode. The preparation method of the non-volatile memory that connects the channel layer by forming a highly doped semiconductor layer (which usually has the same type of doped impurities as the channel layer) at the bottom has become the mainstream of the non-volatile memory preparation method, and the non-volatile memory obtained based on the above preparation method is not suitable for body erasing mode, therefore, it is necessary to use gate induced drain leakage (GIDL) to generate auxiliary body bias to assist the erasing operation to realize the data erasing of the non-volatile memory.

[0092] However, with the continuous increase of the stack number of the non-volatile memory, the erasing carriers are usually difficult to reach the storage cells to be operated to realize effective GIDL erasing.

[0093] The erasing method of the non-volatile memory provided by the present application can generate gate induced drain leakage current in the storage cell string to be operated in the data erasing operation by applying an auxiliary voltage (a predetermined peak level) in the predetermined region of the selection transistor and the adjacent selection transistor in the second time period of the data erasing operation, to realize efficient hierarchical erasing operation and gate induced drain leakage erasing operation.

[0094] Specifically, as shown in Figures 5 to 10 , a step erasing voltage with a step-shaped rising voltage waveform can be first applied to a plurality of storage cell strings to be operated in data erasing operation. For example, the above step erasing voltage signal can be applied to the bit line 341 and the well doped region 205 corresponding to the storage cell string 212, respectively.

[0095] For example, as shown in Figure 7 , BL represents the electrical signal applied to the bit line 341. HVNW represents the electrical signal applied to the well doped region 205. The step erasing voltage has a step-shaped voltage waveform, the first step across the time period of T0 to T2, the voltage rises from the starting level to the intermediate level Vepre.

[0096] The second step across the time period of T2 to T3, the voltage rises from the intermediate level Vepre to the peak level Vers. The value of the intermediate level Vepre may, for example, be selected between 1 volt and 4 volts. The value of the peak level Vers may, for example, be selected between 16 volts and 22 volts, and the time period of T2 to T3 is approximately between 0.4 milliseconds and 0.9 milliseconds.

[0097] In addition, WLs represents the electrical signal applied to the gate of each storage cell of the storage cell string 212. Figures 7 to 10The voltage waveform timing diagram is shown when the data erase operation is performed on the whole of the storage block to which the storage cell string 212 belongs. When the data erase operation is performed on the whole of the storage block, the gates of all the storage cells in the storage block to be subjected to the erase operation should be grounded or connected to a low level.

[0098] As an option, the data erase method provided by the present application is also applicable to a hierarchical data erase operation. When the hierarchical data erase operation is performed, the gates of the storage cells to be subjected to the erase operation can be grounded or connected to a low level. Meanwhile, the gates of the storage cells included in other hierarchies which are not subjected to the erase operation are set to a floating state. When the circuit structure of the other hierarchies which are not subjected to the erase operation is in the floating state, it does not assume the function of circuit interconnection. Those skilled in the art will understand that, in the present specification, when an element (or component, assembly, member, etc.) is referred to as being in a floating state, it is intended to indicate that the element (or component, assembly, member, etc.) does not form an electrical path with other elements (or components, assemblies, members, etc.).

[0099] Step S2

[0100] In combination Figure 5 , Figures 7 to 10 When the storage block formed by the plurality of storage cell strings 212 includes only the bottom hierarchy 450 and the top hierarchy 452, in step S2, during the period in which the step erase voltage is raised from its intermediate level to its peak level, the voltage of the select gate transistor can be raised from its starting level to its predetermined peak level, and the voltage of the predetermined region adjacent to the select gate transistor and including at least one storage cell can be raised from its starting level to its predetermined peak level, for example, as follows:

[0101] During the period in which the voltage of the select gate transistor (e.g., the top select gate transistor 334-T and the bottom select gate transistor 332-T) is raised from its starting level to its peak level (e.g., Vtsg and Vbsg), the voltage of the predetermined region (e.g., the second predetermined region 102 and the first predetermined region 101) of the storage cell string is raised from its starting level to its peak level (e.g., Vgidl and Vgidl).

[0102] In other words, during the period in which the voltage of the bottom select gate transistor 332-T is raised from its starting level to its peak level Vbsg, the voltage of the first predetermined region 101 is raised from its starting level to its peak level Vgidl. Alternatively, during the period in which the voltage of the top select gate transistor 334-T is raised from its starting level to its peak level Vtsg, the voltage of the second predetermined region 102 is raised from its starting level to its peak level Vgidl.

[0103] Specifically, asFigure 5 As shown, in one embodiment of this application, the select gate transistor includes a top-level select gate transistor 334-T connected to bit line 341 and a bottom-level select gate transistor 332-T connected to the well-doped region 205 in the substrate. Accordingly, the predetermined region may include at least a first predetermined region 101 and a second predetermined region 102, wherein the first predetermined region 101 is adjacent to the bottom-level select gate transistor 332-T and includes at least one memory cell, and the second predetermined region 102 is adjacent to the top-level select gate transistor 334-T and includes at least one memory cell. Further, the memory cells included in each of the predetermined regions (e.g., the first predetermined region 101 and the second predetermined region 102) may be dummy memory cells. GIDL represents an electrical signal applied to the gate of each memory cell in the predetermined region.

[0104] Combination Figure 5 , Figures 7 to 10 During the period from T2 to T3, when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, electrical signals TSG and BSG can be applied to the top-layer select-gate transistor 334-T and the bottom-layer select-gate transistor 332-T, respectively, to raise them from their initial levels to their peak levels Vtsg and Vbsg. Alternatively, the initial level of the top-layer select-gate transistor 334-T and the bottom-layer select-gate transistor 332-T can be 0 volts, and the values ​​of the peak levels Vtsg and Vbsg can be selected, for example, between 2 volts and 12 volts. Furthermore, during the period from T2 to T3, electrical signals GIDL can also be applied to the first predetermined region 101 and the second predetermined region 102, respectively, to raise them from their initial levels to their peak levels Vgidl. Alternatively, the initial level of the first predetermined region and the second predetermined region can be 0 volts, and the peak level Vgidl can be selected, for example, between 8 and 15 volts. During the second time period, applying an auxiliary voltage (predetermined peak level) to the select gate transistor of the memory cell string and a predetermined region adjacent to the select gate transistor can generate a gate-induced drain leakage current, thereby enabling efficient non-volatile memory level erase operation and gate-induced drain leakage erase operation.

[0105] Alternatively, while raising the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) from its initial level to its peak level (e.g., levels Vtsg and Vbsg), the voltage of a predetermined region of the memory cell string 212 (e.g., first predetermined region 101 and second predetermined region 102) can be raised from its initial level to its peak level Vgidl, with the peak level of the select gate transistor equal to the peak level of the predetermined region. Applying auxiliary voltages to both the select gate transistor of the memory cell string and the predetermined regions adjacent to the select gate transistor simplifies the control circuitry of the non-volatile memory and improves the operability of the non-volatile memory data erasure method.

[0106] Alternatively, after the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) is increased from its initial level to its peak level (e.g., levels Vtsg and Vbsg), the voltage of a predetermined region (e.g., first predetermined region 101 and second predetermined region 102) of the memory cell string 212 can be increased from its initial level to its peak level Vgidl. Applying auxiliary voltages to the select gate transistors of the memory cell string and the predetermined regions adjacent to the select gate transistors can improve the switching performance of the select gate transistors as selectors of the memory cell string and avoid crosstalk and leakage between adjacent memory cell strings.

[0107] Specifically, such as Figure 7 As shown by the dashed circle, in the top layer 452, after the voltage of the top-level select gate transistor 334-T is increased from its initial level, the voltage of the second predetermined region 102 can also be increased from its initial level. The interval between these two operations can be approximately between 0.1 milliseconds and 0.3 milliseconds. Subsequently, the voltage of the top-level select gate transistor 334-T rises to its predetermined peak level Vtsg, and the voltage of the second predetermined region 102 also rises to its predetermined peak level Vgidl. In the bottom layer 450, the voltage of the bottom-level select gate transistor 332-T can be increased from its initial level to its predetermined peak level Vbsg simultaneously with the voltage of the first predetermined region 101 rising from its initial level to its predetermined peak level Vgidl. These two operations are performed simultaneously, and the predetermined peak level Vbsg is equal to the predetermined peak level Vgidl.

[0108] In addition, alternatively, such as Figure 8As shown by the dotted circle, in the top level 452, the voltage of the second predetermined region 102 can be raised from its initial level to its predetermined peak level Vgidl at the same time that the voltage of the top select gate transistor 334-T is raised from its initial level to its predetermined peak level Vtsg, both operations being performed simultaneously and the predetermined peak level Vtsg being equal to the predetermined peak level Vgidl. In the bottom level 450, the voltage of the first predetermined region 101 can be raised from its initial level after the voltage of the bottom select gate transistor 332-T is raised from its initial level, the interval between these two operations being approximately in the range of 0.1 to 0.3 milliseconds. Thereafter, the voltage of the bottom select gate transistor 332-T is raised to its predetermined peak level Vbsg, and the voltage of the first predetermined region 102 is raised to its predetermined peak level Vgidl.

[0109] Further, optionally, as shown by the dotted circle, Figure 9 As shown by the dotted circle, in the top level 452, the voltage of the second predetermined region 102 can be raised from its initial level to its predetermined peak level Vgidl at the same time that the voltage of the top select gate transistor 334-T is raised from its initial level to its predetermined peak level Vtsg, both operations being performed simultaneously and the predetermined peak level Vtsg being equal to the predetermined peak level Vgidl. In the bottom level 450, the voltage of the first predetermined region 101 can be raised from its initial level after the voltage of the bottom select gate transistor 332-T is raised from its initial level, the interval between these two operations being approximately in the range of 0.1 to 0.3 milliseconds. Thereafter, the voltage of the bottom select gate transistor 332-T is raised to its predetermined peak level Vbsg, and the voltage of the first predetermined region 102 is raised to its predetermined peak level Vgidl.

[0110] Further, optionally, as shown by the dotted circle, Figure 10 As shown by the dotted circle, in the top level 452, the voltage of the second predetermined region 102 can be raised from its initial level to its predetermined peak level Vgidl at the same time that the voltage of the top select gate transistor 334-T is raised from its initial level to its predetermined peak level Vtsg, both operations being performed simultaneously and the predetermined peak level Vtsg being equal to the predetermined peak level Vgidl. In the bottom level 450, the voltage of the first predetermined region 101 can be raised from its initial level after the voltage of the bottom select gate transistor 332-T is raised from its initial level, the interval between these two operations being approximately in the range of 0.1 to 0.3 milliseconds. Thereafter, the voltage of the bottom select gate transistor 332-T is raised to its predetermined peak level Vbsg, and the voltage of the first predetermined region 102 is raised to its predetermined peak level Vgidl.

[0111] Further, again referring to Figure 5 ,Figures 7 to 10 In one embodiment of this application, the memory cell string 212 may further include a selection-level pseudo-memory cell, wherein the selection-level pseudo-memory cell includes a bottom pseudo-memory cell 332' adjacent to the bottom selection gate transistor 332-T, and a top pseudo-memory cell 334' adjacent to the top selection gate transistor 334-T. The selection-level pseudo-memory cell is fabricated simultaneously with the selection gate transistor and is used for process and electrical buffering.

[0112] Alternatively, during the T2-T3 period when electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, electrical signals TSG_DMY and BSG_DMY can be applied to the top-level pseudo-memory cell 334' and the bottom-level pseudo-memory cell 332', respectively, causing them to rise from their initial levels to their peak levels Vtsg_dmy and Vbsg_dmy. Alternatively, the initial level of the top-level pseudo-memory cell 334' and the bottom-level pseudo-memory cell 332' can be 0 volts, and the values ​​of the peak levels Vtsg_dmy and Vbsg_dmy can be selected, for example, between 2 volts and 12 volts. Applying voltage to the adjacent selected-level pseudo-memory cells can increase the gate-induced drain leakage (GIDL) current caused by inter-band tunneling, achieving effective gate-induced drain leakage (GIDL) erasure, thereby improving the data erasure efficiency of the non-volatile memory.

[0113] In one embodiment of this application, while the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) is increased from its initial level to its predetermined peak level (e.g., Vtsg and Vbsg), the voltage of the select hierarchy pseudo memory cell (e.g., top pseudo memory cell 334' and bottom pseudo memory cell 332') is increased from its initial level to its peak level (e.g., Vtsg_dmy and Vbsg_dmy).

[0114] For example, as an option, during the period from T2 to T3, such as Figure 7 As shown in the TSG and TSG_DMY curves, the step of applying pressure to the selected level pseudo memory cell can be performed simultaneously with the step of applying pressure to the selected gate transistor. When the two steps are performed simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the non-volatile memory data erasure method can be improved.

[0115] As an alternative, during the period from T2 to T3, such as Figure 7The step of applying voltage to the dummy memory cell of the selected level can be performed after the step of applying voltage to the select gate transistor. When the two steps are performed separately, the select gate transistor can be improved as a selection switch of the memory cell string, and the gate-induced drain leakage current can be improved.

[0116] Further, in combination with Figure 6 , Figure 9 and Figure 10 , in one embodiment of the present application, at least one first dummy memory cell 205' is arranged between the bottom select gate transistor 332-T and the well-doped region 205 of the substrate. The dummy memory cell in the redundant layer is simultaneously prepared with the memory cell, and can be used for process and electrical buffering. DMY represents an electrical signal applied to a predetermined area of the redundant layer to which the dummy memory cell 205' belongs.

[0117] As an option, at least one first dummy memory cell 205' can be arranged between the first predetermined area 101 and the well-doped region 205 of the substrate. By arranging the first dummy memory cell 205' as described above, the adverse effect of the process defect in the substrate on the potential of the first predetermined area can be avoided, and the adverse effect of the process defect in the substrate on the gate-induced drain leakage (GIDL) current can be reduced.

[0118] In addition, during the data erasing operation, the potential of the well-doped region 205 of the substrate can be conducted out by setting the first dummy memory cell 205' to a floating state, so that the control circuit of the non-volatile memory can be simplified, and the operability of the data erasing method of the non-volatile memory can be improved, while improving the gate-induced drain leakage current. In other words, the first dummy memory cell 205' in the floating state can obtain a predetermined peak level of the well-doped region 205 of the substrate through voltage coupling during the data erasing operation, so that a better data erasing effect can be obtained while avoiding the adverse effect of the process defect in the substrate.

[0119] As an option, the first dummy memory cell 205' described above can also be directly applied with an electrical signal DMY. The electrical signal DMY can have the same stepped voltage waveform as the step erase voltage applied to the bit line 341 and the well-doped region 205 of the substrate.

[0120] According to at least one embodiment of this application, an auxiliary voltage device is applied to the select gate transistor of the memory cell string, and an auxiliary voltage is applied to a predetermined region adjacent to the select gate transistor. Specifically, when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor respectively (for example, the auxiliary voltage is applied to the select gate transistor of the memory cell string first, and then the auxiliary voltage is applied to the predetermined region adjacent to the select gate transistor), the switching performance of the select gate transistor as a selector switch of the memory cell string can be improved, and crosstalk and leakage between adjacent memory cell strings can be avoided; when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the non-volatile memory data erasure method can be improved.

[0121] Furthermore, according to at least one embodiment of this application, moving a predetermined region adjacent to the bottom-level select gate transistor closer to the layer to be erased can improve the gate-induced drain leakage current and achieve efficient data erasure of non-volatile memory.

[0122] Figure 11 This is a schematic diagram of the structure of a storage system 10000 according to one embodiment of this application.

[0123] like Figure 11 As shown, at least one embodiment of this application also provides a memory system 10000. The memory system 10000 may include a memory 4000 and a controller 6000. The memory 4000 may be the same as the memory described in any of the embodiments above, and will not be described again in this application. The memory system 10000 may be a two-dimensional memory system or a three-dimensional memory system; the following description uses a three-dimensional memory system as an example.

[0124] The three-dimensional memory system 10000 may include a three-dimensional memory 4000, a host 5000, and a controller 6000. The three-dimensional memory 4000 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 6000 controls the three-dimensional memory 4000 via channel CH, and the three-dimensional memory 4000 can perform operations based on the control of the controller 6000 in response to requests from the host 5000. The three-dimensional memory 4000 receives commands CMD and addresses ADDR from the controller 5000 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 4000 can perform internal operations corresponding to commands on the region selected by the address.

[0125] In some implementations, the three-dimensional memory system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0126] Figure 12 This is a schematic diagram of the structure of the electronic device 20000 provided in the embodiments of this application.

[0127] like Figure 12 As shown, at least one embodiment of this application also provides an electronic device 20000. The electronic device 20000 includes a memory 4000. The memory 4000 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The electronic device 20000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage function. Therefore, the control module 8000 of the electronic device 20000 can be determined according to the specific device type of the electronic device 20000. The control module 8000 can control the three-dimensional memory 4000 through a channel, and the three-dimensional memory 4000 can receive commands CMD and addresses ADDR from the control module 8000 through a channel, and access the region selected from the memory cell array in response to the address. This application does not limit this.

[0128] This application provides a memory, a storage system, and an electronic device. Since it employs the data erasure method for non-volatile memory provided in any of the above embodiments of this application, it has the same beneficial effects as the data erasure method for non-volatile memory described above, and will not be elaborated here.

[0129] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A data erasing method of a nonvolatile memory, characterized by comprising: The memory includes a plurality of strings of memory cells each including a string of select gate transistors and memory cells in series, the plurality of strings of memory cells being formed into a memory block including a plurality of levels stacked vertically, the string of memory cells including a plurality of sub-strings of memory cells belonging to different levels, the method comprising: applying a stepped erase voltage to a string of memory cells to be subjected to an erase operation, the stepped erase voltage having a stepped rising voltage waveform; and during the stepped erase voltage rising from an intermediate level thereof to a peak level thereof, raising a voltage of the select gate transistor from a starting level thereof to a predetermined peak level thereof and raising a voltage of a predetermined region from a starting level thereof to a predetermined peak level thereof, thereby generating a gate-induced drain leakage current in the string of memory cells, wherein the predetermined region is adjacent to the select gate transistor and includes at least one of the memory cells.

2. The method of claim 1 wherein: the select gate transistor includes a top select gate transistor connected to a bit line and a bottom select gate transistor connected to a well doped region in a substrate; and the predetermined region includes at least a first predetermined region adjacent to the bottom select gate transistor and including at least one of the memory cells and a second predetermined region adjacent to the top select gate transistor and including at least one of the memory cells.

3. The method according to claim 1 or 2, characterized in that, raising the voltage of the select gate transistor from the starting level thereof to the predetermined peak level thereof and raising the voltage of the predetermined region from the starting level thereof to the predetermined peak level thereof includes: raising the voltage of the predetermined region of the string of memory cells from the starting level thereof to the peak level thereof during the raising of the voltage of the select gate transistor from the starting level thereof to the peak level thereof.

4. The method of claim 3, wherein, raising the voltage of the select gate transistor from the starting level thereof to the predetermined peak level thereof and raising the voltage of the predetermined region from the starting level thereof to the predetermined peak level thereof includes: raising the voltage of the predetermined region of the string of memory cells from the starting level thereof to the peak level thereof while raising the voltage of the select gate transistor from the starting level thereof to the peak level thereof, the peak level of the select gate transistor being equal to the peak level of the predetermined region.

5. The method of claim 3, wherein, raising the voltage of the select gate transistor from the starting level thereof to the predetermined peak level thereof and raising the voltage of the predetermined region from the starting level thereof to the predetermined peak level thereof includes: raising the voltage of the predetermined region of the string of memory cells from the starting level thereof after the raising of the voltage of the select gate transistor from the starting level thereof.

6. The method of claim 2 wherein: the memory cells include real memory cells and dummy memory cells, the first predetermined region being adjacent to the bottom select gate transistor and including at least one of the dummy memory cells.

7. The method of claim 6, wherein, the dummy memory cells include first dummy memory cells between the bottom select gate transistor and the well doped region, the first predetermined region being spaced apart from the substrate by at least one of the first dummy memory cells.

8. The method of claim 7, wherein, the method further comprising: Setting at least one of the first dummy memory cells for the interval to a floating state during the erase operation.

9. The method of claim 7, wherein, The method further comprises: applying the stepped erase voltage to at least one of the first dummy memory cells for the interval.

10. The method of claim 1, wherein, The memory cells include true memory cells and dummy memory cells, the dummy memory cells include select level dummy memory cells adjacent to the select gate transistors, and the method further comprises: raising the voltage of the select level dummy memory cells from their starting levels to their peak levels during the raising of the stepped erase voltage from its intermediate level to its peak level.

11. The method of claim 10, wherein, The method further comprises: raising the voltage of the select level dummy memory cells from their starting levels to their peak levels during the raising of the voltage of the select gate transistors from their starting levels to their predetermined peak levels.

12. The method of claim 11, wherein, The method further comprises: raising the voltage of the select level dummy memory cells from their starting levels to their peak levels simultaneously with the raising of the voltage of the select gate transistors from their starting levels to their predetermined peak levels; or raising the voltage of the select level dummy memory cells from their starting levels after the raising of the voltage of the select gate transistors from their starting levels.

13. The method of claim 2, wherein, Raising the voltage of the select gate transistors from their starting levels to their predetermined peak levels and raising the voltage of predetermined regions from their starting levels to their predetermined peak levels comprises: raising the voltage of the first predetermined region from its starting level to its peak level during the raising of the voltage of the bottom select gate transistors from their starting levels to their peak levels; and raising the voltage of the second predetermined region from its starting level to its peak level during the raising of the voltage of the top select gate transistors from their starting levels to their peak levels.

14. The method of claim 13, wherein, Raising the voltage of the select gate transistors from their starting levels to their predetermined peak levels and raising the voltage of predetermined regions from their starting levels to their predetermined peak levels comprises: raising the voltage of the first predetermined region from its starting level after the raising of the voltage of the bottom select gate transistors from their starting levels; and raising the voltage of the second predetermined region from its starting level to its predetermined peak level simultaneously with the raising of the voltage of the top select gate transistors from their starting levels to their predetermined peak levels, and the predetermined peak level of the top select gate transistors is equal to the predetermined peak level of the second predetermined region.

15. The method of claim 13, wherein, Raising the voltage of the select gate transistors from their starting levels to their predetermined peak levels and raising the voltage of predetermined regions from their starting levels to their predetermined peak levels comprises: raising the voltage of the first predetermined region from its starting level to its predetermined peak level simultaneously with the raising of the voltage of the bottom select gate transistors from their starting levels to their predetermined peak levels, and the predetermined peak level of the bottom select gate transistors is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level after the raising of the voltage of the top select gate transistors from their starting levels.

16. The method of claim 13, wherein, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes: raising the voltage of the first predetermined region from its starting level to its peak level while raising the voltage of the bottom select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level to the predetermined peak level while raising the voltage of the top select gate transistor from its starting level to its predetermined peak level, and the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

17. The method of claim 13, wherein, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes: raising the voltage of the first predetermined region from its starting level after raising the voltage of the bottom select gate transistor from its starting level; and raising the voltage of the second predetermined region from its starting level to its predetermined peak level after raising the voltage of the top select gate transistor from its starting level.

18. A non-volatile memory, comprising: The non-volatile memory comprises: a memory array formed on a well doped region of a substrate and comprising a plurality of memory cells, wherein the memory cells in each column are connected to a same bit line forming a memory cell string, a plurality of the memory cell strings are formed as a memory block, the memory block comprises a plurality of levels stacked vertically in a direction perpendicular to the substrate, the memory cell string comprises a plurality of sub-memory cell strings belonging to different levels; and a control circuit coupled with the memory array and configured to control level selection of the plurality of levels and perform a level erase operation and a gate induced drain leakage (GIDL) erase operation on the selected level as recited in any one of claims 1-17.

19. The nonvolatile memory of claim 18, wherein, The memory array is a three-dimensional NAND memory array, and the non-volatile memory is a three-dimensional NAND memory.

20. A storage system, comprising: A memory as claimed in claim 18 or 19.

21. An electronic device, comprising: comprises: a memory as claimed in claim 18 or 19.

Images