A memory chip data retention verification method and device

Abstract

A method and device for verifying data storage capability of a memory chip. The method controls the duty cycle of a signal generator to control the power-on and power-off time of the memory chip during erase / write / read operations, and evaluates the reliability of data storage of the memory chip according to whether the inherent data in the memory chip is consistent before and after power-off. The method and device provide verification of the data storage reliability of a FLASH chip when frequently powered on and powered off, and the peripheral circuit and storage scheme of the chip are improved according to the verification result, thereby greatly improving the storage performance of the memory chip.

Description

Technical Field

[0001] This invention relates to the field of chip storage technology, and specifically to a method and apparatus for verifying the data memory capacity of a storage chip. Background Technology

[0002] In applications, there is an extremely low probability that FLASH memory chips will lose internal code or important data. This is a difficult problem in the electronics industry. In extreme cases, the loss of code can directly lead to system paralysis and seriously affect reliability.

[0003] Currently, there is no industry-specific verification method for the data storage reliability of FLASH chips during frequent power-on / power-off cycles. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a method and apparatus for verifying the data memory capacity of a memory chip by precisely controlling the power-down / power-on time, and evaluating the storage reliability of the memory chip.

[0005] The first aspect of this invention provides a method for verifying the data memory capacity of a memory chip, comprising the following steps:

[0006] Write fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N;

[0007] After the power-on data is successfully loaded, the remaining Blocks Block(N-a+1) to BlockN are continuously erased / written / read.

[0008] Adjust the duty cycle of the signal generator to power off the memory chip at the instant the erase / write / read operation begins, i.e., at time t1.

[0009] After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0010] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt);

[0011] After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0012] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt).

[0013] Repeat the above process until the chip is powered off after a delay of T time after the erase / write / read operation, i.e., at time (t1+T), where T is the erase / write / read operation time of the chip;

[0014] If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

[0015] Furthermore, the duty cycle of the adjustment signal generator is controlled manually or automatically by a program setting.

[0016] Furthermore, the timing accuracy of the power-on and / or power-off is controlled to be below 10µs.

[0017] Furthermore, it also includes a step to determine the data memory capacity of the memory chip, and to improve the circuit design of the memory chip based on whether the data in Block1 to Block(Na) has been mistakenly changed and the time of the mistaken change.

[0018] A second aspect of the present invention provides a data memory verification device for a memory chip, comprising a first write operation module, a second erase / write / read operation module, a signal generator, a switching transistor, and a host computer.

[0019] The first write operation module writes fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N;

[0020] The signal generator produces fixed-period pulses to control the switching transistor to turn on / off, corresponding to power-on and power-off; after the power-on data is successfully loaded, the second erase / write / read operation module continuously performs erase / write / read operations on the remaining Blocks Block(N-a+1) to BlockN;

[0021] Adjust the duty cycle of the signal generator to power off the memory chip at the instant the erase / write / read operation begins, i.e., at time t1.

[0022] After power-on, the host computer compares the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0023] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt);

[0024] After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0025] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt).

[0026] Repeat the above process until the chip is powered off after a delay of T time after the erase / write / read operation, i.e., at time (t1+T), where T is the erase / write / read operation time of the chip;

[0027] If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

[0028] Furthermore, the duty cycle of the adjustment signal generator is controlled manually or automatically by a program setting.

[0029] Furthermore, the timing accuracy of the power-on and / or power-off is controlled to be below 10µs.

[0030] Furthermore, the circuit design of the memory chip is improved based on whether the data in Block1 to Block(Na) is mistakenly changed and the time of the mistaken change.

[0031] A third aspect of the present invention provides a data memory verification system for a memory chip, the system comprising:

[0032] Memory and one or more processors;

[0033] The memory is communicatively connected to the one or more processors, and stores instructions that can be executed by the one or more processors. The instructions are executed by the one or more processors to cause the one or more processors to perform the method described above.

[0034] A fourth aspect of the present invention provides a computer-readable storage medium having computer-executable instructions stored thereon, which, when executed by a computing device, are operable to perform the method described above.

[0035] In summary, this invention provides a method and apparatus for verifying the data storage capacity of a memory chip. This method controls the power-on and power-off times of the memory chip during erase / write / read operations by controlling the duty cycle of a signal generator. The reliability of data storage is evaluated by comparing whether the inherent data in the memory chip remains consistent before and after power-off. This method and apparatus provide verification of data storage reliability of FLASH chips during frequent power-on / power-off operations. Based on the verification results, improvements can be made to the chip's peripheral circuitry and storage scheme, thereby significantly improving the storage performance of the memory chip. Attached Figure Description

[0036] Figure 1 This is a flowchart illustrating the data memory capacity verification method for a storage chip according to an embodiment of the present invention.

[0037] Figure 2 This is a flowchart illustrating a specific embodiment of a memory chip data memory verification method according to the present invention;

[0038] Figure 3 This is a structural block diagram of a memory chip data memory verification device according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the structure of a memory chip data memory verification device according to a specific embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0041] The first aspect of this invention provides a method for verifying the data memory capacity of a memory chip, such as... Figure 1 As shown, it includes the following steps:

[0042] Step S100: Write fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N;

[0043] Step S200: After the power-on data is successfully loaded, the remaining Blocks Block(N-a+1) to BlockN are continuously erased / written / read.

[0044] Step S300: Adjust the duty cycle of the signal generator to power off the memory chip at the instant the erase / write / read operation is performed, i.e., at time t1.

[0045] Step S400: After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0046] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt);

[0047] After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0048] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt).

[0049] Repeat the above process until the chip is powered off after a delay of T time after the erase / write / read operation, i.e., at time (t1+T), where T is the erase / write / read operation time of the chip;

[0050] If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

[0051] Specifically, the verification method process is as follows: Figure 2 As shown, the erasing operation is used as an example. Figure 2 In this context, N takes the value 1024, and a takes the value 1019.

[0052] This verification method allows for adjustment of the duty cycle, enabling time-controlled power-down / power-on and precise adjustment of the time ratio, with timing accuracy controlled to below 10µs. By testing the data storage capacity of the memory chip using this method, it's possible to assess whether the design of the peripheral circuitry and storage scheme could lead to erroneous data modification. Ultimately, the verification results and analytical analysis can be combined to design a reliable circuit for the memory chip.

[0053] Furthermore, the duty cycle of the adjustment signal generator is controlled manually or automatically by a program setting.

[0054] Furthermore, it also includes a step to determine the data memory capacity of the memory chip, and to improve the circuit design of the memory chip based on whether the data in Block1 to Block(Na) has been mistakenly changed and the time of the mistaken change.

[0055] A second aspect of the present invention provides a data memory verification device for a memory chip, such as... Figure 3 As shown, it includes a first write operation module, a second erase / write / read operation module, a signal generator, a switching transistor, and a host computer:

[0056] The first write operation module writes fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N;

[0057] The signal generator produces fixed-period pulses to control the switching transistor to turn on / off, corresponding to power-on and power-off; after the power-on data is successfully loaded, the second erase / write / read operation module continuously performs erase / write / read operations on the remaining Blocks Block(N-a+1) to BlockN;

[0058] Adjust the duty cycle of the signal generator to power off the memory chip at the instant the erase / write / read operation begins, i.e., at time t1.

[0059] After power-on, the host computer compares the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0060] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt);

[0061] After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed;

[0062] If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt).

[0063] Repeat the above process until the chip is powered off after a delay of T time after the erase / write / read operation, i.e., at time (t1+T), where T is the erase / write / read operation time of the chip;

[0064] If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

[0065] like Figure 4 The diagram shown is a schematic representation of the specific structure of the verification device of this invention. This invention utilizes the fixed-period pulse mode of a signal generator to control the on / off state of a high-speed PMOS transistor (switching transistor), thereby constructing a power-down / power-on verification device for controlling a memory chip. This creates an asynchronous switching control loop that does not affect the actual operating performance of the circuit. Simultaneously, by adjusting its duty cycle, power-down / power-on is controlled by time, and the precise adjustment of the time ratio can simulate the extreme condition of power failure precisely during the programming, erasing, and reading operations of the memory chip.

[0066] A third aspect of the present invention provides a data memory verification system for a memory chip, the system comprising:

[0067] Memory and one or more processors;

[0068] The memory is communicatively connected to the one or more processors, and stores instructions that can be executed by the one or more processors. The instructions are executed by the one or more processors to cause the one or more processors to perform the method described above.

[0069] A fourth aspect of the present invention provides a computer-readable storage medium having computer-executable instructions stored thereon, which, when executed by a computing device, are operable to perform the method described above.

[0070] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0072] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0073] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0074] In summary, this invention provides a method and apparatus for verifying the data storage capacity of a memory chip. This method controls the power-on and power-off times of the memory chip during erase / write / read operations by controlling the duty cycle of a signal generator. The reliability of data storage is evaluated by comparing whether the inherent data in the memory chip remains consistent before and after power-off. This method and apparatus provide verification of data storage reliability of FLASH chips during frequent power-on / power-off operations. Based on the verification results, improvements can be made to the chip's peripheral circuitry and storage scheme, thereby significantly improving the storage performance of the memory chip.

[0075] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A method for verifying the data storage capacity of a memory chip, characterized in that, Includes the following steps: Write fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N; After the power-on data is successfully loaded, erase / write / read operations are performed on the remaining Blocks Block(N-a+1) to BlockN. Adjust the duty cycle of the signal generator to power off the memory chip at the moment t1 when the erase / write / read operation is just started; After power-on, compare the data in Block1 to Block(Na) to determine whether they have been mistakenly changed; If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt); If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt). Repeat the erase / read / write operation and power-down steps as described above until the chip is powered down after a delay of time T after the erase / write / read operation, i.e., time (t1+T), where T is the erase / write / read operation time of the chip; the timing accuracy of the power-on and / or power-down is controlled to be below 10µs. If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

2. The method for verifying the data storage capacity of a memory chip according to claim 1, characterized in that, The duty cycle of the adjustable signal generator can be controlled manually or automatically by program setting.

3. The method for verifying the data memory capacity of a memory chip according to any one of claims 1-2, characterized in that, It also includes a step to determine the data storage capacity of the memory chip, and to improve the circuit design of the memory chip based on whether the data in Block 1 to Block (Na) has been mistakenly changed and the time of the mistaken change.

4. A data storage capacity verification device for a memory chip, characterized in that, Includes a first write operation module, a second erase / write / read operation module, a signal generator, a switching transistor, and a host computer: The first write operation module writes fixed data into Block 1 to Block (Na) of the memory chip, where N is the total number of Blocks in the memory chip, and 0 < a < N; The signal generator produces fixed-period pulses to control the switching transistor to turn on / off, corresponding to power-on and power-off; after the power-on data is successfully loaded, the second erase / write / read operation module performs erase / write / read operations on the remaining Blocks Block(N-a+1) to BlockN; After power-on, the host computer compares the data in Block1 to Block(Na) to determine whether they have been mistakenly changed; If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip is powered off after a delay of Δt time after the erase / write / read operation, i.e. at time (t1+Δt); If the data in Block1 to Block(Na) is not mistakenly changed, adjust the duty cycle of the signal generator so that the chip loses power after a delay of 2Δt after the erase / write / read operation, i.e., at time (t1+2Δt). Repeat the erase / read / write operation and power-down steps as described above until the chip is powered down after a delay of time T after the erase / write / read operation, i.e., time (t1+T), where T is the erase / write / read operation time of the chip; the timing accuracy of the power-on and / or power-down is controlled to be below 10µs. If the data in Block1 to Block(Na) is mistakenly changed, the result of the memory chip being mistakenly changed is returned.

5. The memory chip data storage capacity verification device according to claim 4, characterized in that, The duty cycle of the adjustable signal generator can be controlled manually or automatically by program setting.

6. The memory chip data storage capacity verification device according to any one of claims 4-5, characterized in that, Improve the circuit design of the memory chip by considering whether the data in Block 1 to Block (Na) has been mistakenly changed and the time when the change occurred.

7. A data storage capacity verification system for a memory chip, characterized in that, The system includes: Memory and one or more processors; The memory is communicatively connected to the one or more processors, and the memory stores instructions that can be executed by the one or more processors. The instructions are executed by the one or more processors to cause the one or more processors to perform the method according to any one of claims 1-3.

8. A computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a computing device, are operable to perform the method of any one of claims 1-3.

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