Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing an etch layer; forming a plurality of first barrier structures on the surface of the etch layer; forming a plurality of second barrier structures on the surface of the etch layer, wherein the materials of the first barrier structures and the second barrier structures are different; forming a first patterned layer having a plurality of first openings, each first opening exposing at least a partial surface of one first barrier structure and one second barrier structure; etching the first barrier structures using the first patterned layer as a mask; forming a second patterned layer having a plurality of second openings, each second opening exposing at least a partial surface of one first barrier structure and one second barrier structure; and etching the second barrier structures using the second patterned layer as a mask. Thus, the process difficulty of the semiconductor structure is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Art

[0002] With the continuous progress of semiconductor integrated circuit manufacturing technology, while the performance is continuously improved, the process of device miniaturization and microminiaturization is also accompanied. More and more advanced processes require as many devices as possible to be realized in as small an area as possible.

[0003] In very large scale integrated circuits, using metal interconnect layers is one of the methods to achieve electrical interconnection between devices. Generally, in high-density metal interconnect layers, a metal-cut layer is used to insulate adjacent metal interconnect layers. Thus, the pitch between the ends of adjacent metal interconnect layers needs to be less than the exposure limit size of the exposure process to increase the density of the metal interconnect layer and improve the integration of the integrated circuit.

[0004] However, the existing manufacturing process of semiconductor structures is still difficult. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to reduce the process difficulty of manufacturing the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an etch layer; forming a plurality of first barrier structures on the surface of the etch layer; forming a plurality of second barrier structures on the surface of the etch layer, the materials of the first barrier structures and the second barrier structures being different; forming a first patterned layer having a plurality of first openings, each first opening exposing at least a part of the surface of 1 first barrier structure and 1 second barrier structure; using the first patterned layer as a mask to etch the first barrier structures; forming a second patterned layer having a plurality of second openings, each second opening exposing at least a part of the surface of 1 first barrier structure and 1 second barrier structure; using the second patterned layer as a mask to etch the second barrier structures.

[0007] Optionally, it further includes: before forming the first patterned layer and the second patterned layer, forming a plurality of third barrier structures on the surface of the etch layer, the third barrier structures including a first barrier layer and a second barrier layer located on the surface of part of the first barrier layer, the material of the first barrier layer being the same as that of the first barrier structures, and the material of the second barrier layer being the same as that of the second barrier structures.

[0008] Optionally, among the plurality of first openings, at least one first opening further exposes a partial surface of at least one third barrier structure.

[0009] Optionally, among the plurality of second openings, at least one second opening further exposes a partial surface of at least one third barrier structure.

[0010] Optionally, a first etching process is adopted to etch the first barrier structure with the first patterned layer as a mask. The first etching process has a first etching rate for the material of the first barrier structure and a second etching rate for the material of the second barrier structure, and the first etching rate is greater than the second etching rate.

[0011] Optionally, the ratio of the first etching rate to the second etching rate is above 5:1.

[0012] Optionally, a second etching process is adopted to etch the second barrier structure with the second patterned layer as a mask. The second etching process has a third etching rate for the material of the first barrier structure and a fourth etching rate for the material of the second barrier structure, and the fourth etching rate is greater than the third etching rate.

[0013] Optionally, the ratio of the fourth etching rate to the third etching rate is above 5:1.

[0014] Optionally, the method for forming the first barrier structure includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of first doped regions in the first barrier material layer; after forming the first doped regions, etching the first barrier material layer until the surface of the layer to be etched is exposed.

[0015] Optionally, the method for forming the first barrier layer includes: before etching the first barrier material layer, forming a plurality of third doped regions in the first barrier material layer, and the ions doped in the third doped regions are the same as the ions doped in the first doped regions.

[0016] Optionally, the method for forming the second barrier structure includes: after forming the first barrier structure and the first barrier layer, forming a second barrier material layer on the surface of the layer to be etched, the surface of the first barrier structure, and the surface of the first barrier layer; forming a plurality of second doped regions in the second barrier material layer on the surface of the layer to be etched; after forming the second doped regions, etching the second barrier material layer until the surface of the layer to be etched, the surface of the first barrier structure, and the surface of the first barrier layer are exposed.

[0017] Optionally, the method for forming the second barrier layer includes: before etching the second barrier material layer, forming a plurality of fourth doped regions in the second barrier material layer on the surface of a part of the first barrier layer, and the ions doped in the fourth doped regions are the same as the ions doped in the second doped regions.

[0018] Optionally, the material of the first barrier structure includes one or a combination of more of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

[0019] Optionally, the material of the second barrier structure includes one or a combination of more of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

[0020] Optionally, it further includes: using the first patterned layer as a mask, after etching the first barrier structure, continuing to use the first patterned layer as a mask to etch the layer to be etched, forming a plurality of first interconnect openings in the layer to be etched, and the first interconnect openings expose the side wall surfaces of the second barrier structure; forming a first interconnect structure in each first interconnect opening.

[0021] Optionally, it further includes: using the second patterned layer as a mask, after etching the second barrier structure, continuing to use the second patterned layer as a mask to etch the layer to be etched, forming a plurality of second interconnect openings in the layer to be etched, and the second interconnect openings expose the side wall surfaces of the first barrier structure; forming a second interconnect structure in each second interconnect opening.

[0022] Optionally, it further includes: using the first patterned layer as a mask, after etching the first barrier structure, continuing to use the first patterned layer as a mask to etch the layer to be etched, forming a plurality of third interconnect openings in the layer to be etched, and the third interconnect openings expose the side wall surfaces of at least one of the second barrier structure and the second barrier layer; forming a third interconnect structure in each third interconnect opening.

[0023] Optionally, it further includes: using the second patterned layer as a mask, after etching the second barrier structure, continuing to use the second patterned layer as a mask to etch the layer to be etched, forming a plurality of fourth interconnect openings in the layer to be etched, and the fourth interconnect openings expose the side wall surfaces of at least one of the first barrier structure and the first barrier layer; forming a fourth interconnect structure in each fourth interconnect opening.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since the materials of the first barrier structure and the second barrier structure are different, after adjusting the etching process parameters, the first barrier structure can be selectively etched using the first patterned layer as a mask. Similarly, the second barrier structure can be selectively etched using the second patterned layer as a mask. Thus, subsequently, when etching the layer to be etched using the first barrier structure and the second patterned layer as masks, the unexposed second barrier structure will not block (the exposed second barrier structure is selectively etched away), and further, a second barrier structure with a longer length can be formed. Similarly, subsequently, when etching the layer to be etched using the second barrier structure and the first patterned layer as masks, the unexposed first barrier structure will not block (the exposed first barrier structure is selectively etched away), and further, a first barrier structure with a longer length can be formed. Since a first barrier structure and a second barrier structure with longer lengths can be formed, the overlay accuracy requirements for the patterns in the length directions of the first barrier structure and the second barrier structure are reduced, the process window for forming the first barrier structure and the second barrier structure is increased, the process difficulty of manufacturing the first barrier structure and the second barrier structure is reduced, and further, the process difficulty of manufacturing the semiconductor structure is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 2 is a schematic structural diagram of each step in the formation process of a semiconductor structure;

[0027] Figures 3 to 22 is a schematic structural diagram of the formation process of the semiconductor structure according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] As described in the background art, the manufacturing process of the existing semiconductor structure is still relatively difficult. The following is an analysis and description in combination with specific embodiments.

[0029] It should be noted that the "surface" in this specification is used to describe the relative positional relationship in space and does not limit whether there is direct contact.

[0030] Figures 1 to 2 is a top view structural diagram of each step in the formation process of a semiconductor structure.

[0031] Please refer to Figure 1 , a layer 100 to be etched is provided, and the layer 100 to be etched includes a first region I and a second region II arranged along a first direction X.

[0032] Please continue to refer to Figure 1 , a first barrier structure 111 spanning the first region I and a second barrier structure 112 spanning the second region II are formed on the layer 100 to be etched.

[0033] Please refer toFigure 2 , an interconnect patterning layer (not shown) is formed on the surface of the layer 100 to be etched, and the interconnect patterning layer exposes the layer 100 to be etched in the first region I and the second region II, the first barrier structure 111 and the second barrier structure 112; using the interconnect patterning layer, the first barrier structure 111 and the second barrier structure 112 as masks, etching the layer 100 to be etched, and forming a plurality of first interconnect openings 121 and a plurality of second interconnect openings 122 in the layer 100 to be etched, and adjacent first interconnect openings 121 are separated by the first barrier structure 111, and adjacent second interconnect openings 122 are separated by the second barrier structure 112.

[0034] After forming a plurality of first interconnect openings 121 and a plurality of second interconnect openings 122, a first interconnect structure (not shown) is formed in each first interconnect opening 121, and a second interconnect structure (not shown) is formed in each second interconnect opening 122.

[0035] However, in the above method, on the one hand, in order to reduce the pitch between adjacent first interconnect structures, in the direction perpendicular to the first direction X, the width dimension of the first barrier structure 111 is small, and similarly, the width dimension of the second barrier structure 112 is small; on the other hand, in order to form the second interconnect opening 122, the first interconnect structure cannot block the layer 100 to be etched in the second region II, and similarly, the second interconnect structure cannot block the layer to be etched in the first region I. Therefore, along the first direction X, the length dimensions of the first barrier structure 111 and the second barrier structure 112 are also small. Since the width dimensions and length dimensions of the first barrier structure 111 and the second barrier structure 112 are both small, therefore, when forming the first barrier structure 111 and the second barrier structure 112, in the first direction X and in the direction perpendicular to the first direction X, the patterns of the first barrier structure 111 and the second barrier structure 112 both require high alignment accuracy, resulting in a small process window when forming the first barrier structure 111 and the second barrier structure 112, and making the process of forming the first barrier structure 111 and the second barrier structure 112 difficult.

[0036] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. By forming a first barrier structure and a second barrier structure with different materials on the surface of the layer to be etched, and respectively using a first patterning layer and a second patterning layer as masks to selectively etch the first barrier structure and the second barrier structure, thereby reducing the requirements for the alignment accuracy of the patterns in the length direction of the first barrier structure and the length direction of the second barrier structure, increasing the process window for forming the first barrier structure and the second barrier structure, and reducing the process difficulty of manufacturing the first barrier structure and the second barrier structure.

[0037] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0038] Figures 3 to 22 It is a schematic structural diagram of the semiconductor structure formation process according to an embodiment of the present invention.

[0039] Please refer to Figure 3 , Figure 3 It is a schematic cross-sectional structure diagram of the semiconductor structure according to an embodiment of the present invention, providing an etch target layer 200.

[0040] In this embodiment, the etch target layer includes a substrate (not shown) and a dielectric layer (not shown) located on the substrate.

[0041] The material of the substrate includes semiconductor materials.

[0042] In this embodiment, the material of the substrate includes silicon.

[0043] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0044] In this embodiment, the substrate has semiconductor devices (not shown), and the semiconductor devices include one or all of PMOS transistors and NMOS transistors. The substrate also includes a substrate interconnect structure (not shown) electrically connected to the semiconductor devices, and an insulating layer (not shown) surrounding the semiconductor devices and the substrate interconnect structure.

[0045] The material of the dielectric layer includes dielectric materials, such as silicon oxide or silicon nitride, etc.

[0046] Next, a plurality of first barrier structures and a plurality of second barrier structures are formed on the surface of the etch target layer 200.

[0047] In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of third barrier structures on the surface of the etch target layer 200, where the third barrier structures include a first barrier layer and a second barrier layer located on the surface of a part of the first barrier layer, the material of the first barrier layer is the same as that of the first barrier structure, and the material of the second barrier layer is the same as that of the second barrier structure.

[0048] In other embodiments, the third barrier structures are not formed.

[0049] For the specific process of forming the several first blocking structures, several second blocking structures, and several third blocking structures, please refer to Figures 4 to 13 。

[0050] Please refer to Figure 4 and Figure 5 , Figure 4 is Figure 5 a schematic cross-sectional structure diagram in the X-X1 direction in Figure 5 . A first barrier material layer 210 is formed on the surface of the layer 200 to be etched; several first doping regions 211 are formed in the first barrier material layer 210.

[0051] The first doping regions 211 provide materials for forming the first blocking structures.

[0052] It should be noted that Figure 5 in Figure 5 , 1 first doping region is schematically shown. The number of the first doping regions can be 1 or multiple. And when the number of the first doping regions is multiple, according to design requirements, the shapes of the first doping regions can be different.

[0053] In this embodiment, the process of forming the first barrier material layer 210 includes a spin coating process or a deposition process. The deposition process is, for example, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD).

[0054] In this embodiment, the method of forming several first doping regions 211 includes: forming a first barrier patterned layer (not shown) on the surface of the first barrier material layer 210. The first barrier patterned layer has several first barrier openings (not shown), and the first barrier openings expose a part of the surface of the first barrier material layer; using the first barrier patterned layer as a mask, performing ion doping on the first barrier material layer 210 to form several first doping regions 211.

[0055] In other embodiments, when the number of the first blocking structures is multiple, multiple first doping processes are performed on the first barrier material layer to form multiple first doping regions. Each first doping process includes: forming a first barrier patterned layer on the surface of the first barrier material layer. The first barrier patterned layer has several first barrier openings, and the first barrier openings expose a part of the surface of the first barrier material layer; using the first barrier patterned layer as a mask, performing a first ion doping step on the first barrier material layer to form a part of the first doping regions among the multiple first doping regions; after forming the first doping regions, removing the first barrier patterned layer.

[0056] Since the multiple first doping regions are formed through multiple first doping processes, a first blocking patterning layer is formed during each first doping process. When the spacing between different first blocking structures is small, the first doping regions corresponding to the first blocking structures can be formed during different first doping processes, that is, the first blocking openings with a relatively close spacing are formed in different first blocking patterning layers. Thus, during the exposure process of the pattern for forming the first blocking openings, some defects such as short circuits or poor pattern size accuracy caused by the relatively close spacing between different first blocking openings can be reduced. The pattern accuracy of the first blocking openings is improved, and thus, the pattern accuracy of the first doping regions and the first blocking structures is improved.

[0057] In this embodiment, the process of the first ion doping step includes an ion implantation process.

[0058] In this embodiment, the first blocking patterning layer is removed after the first doping region 211 is formed.

[0059] In this embodiment, after several first doping regions 211 are formed, several third doping regions 213 are formed in the first blocking material layer 210, and the ions doped in the third doping regions 213 are the same as the ions doped in the first doping regions 211.

[0060] The third doping regions 213 provide materials for forming the first blocking layer.

[0061] Since the ions doped in the third doping regions 213 are the same as the ions doped in the first doping regions 211, the material of the first blocking layer can be the same as the material of the first blocking structure.

[0062] The purpose of making the material of the first blocking layer the same as the material of the first blocking structure is that when the first blocking structure is selectively etched subsequently, the first blocking layer can be selectively etched simultaneously.

[0063] It should be noted that Figure 5 2 third doping regions are schematically shown. The number of the third doping regions can be 1 or multiple. And when the number of the third doping regions is multiple, the shapes of the third doping regions can be different according to design requirements.

[0064] The method for forming several third doping regions 213 includes: forming a third blocking patterning layer (not shown) on the surface of the first blocking material layer 210, with several third blocking openings (not shown) in the third blocking patterning layer, and the third blocking openings exposing part of the surface of the first blocking material layer; using the third blocking patterning layer as a mask, performing a third ion doping step on the first blocking material layer 210 to form several third doping regions 213.

[0065] Since the first blocking patterning layer and the third blocking patterning layer are formed separately, that is, the first blocking opening and the third blocking opening are formed in different blocking patterning layers. Thus, during the exposure process of the patterns for forming the first blocking opening and the third blocking opening, some defects such as short circuit or poor pattern dimension accuracy caused by the close spacing between the first blocking opening and the third blocking opening can be reduced. The pattern accuracy of the first blocking opening and the third blocking opening is improved, and thus, the pattern accuracy of the first doped region 211 and the first blocking structure, as well as the third doped region 213 and the first blocking layer is improved.

[0066] In this embodiment, the process of the third ion doping step includes an ion implantation process, and the ions implanted into the first blocking material layer 210 in the third ion doping step are the same as the ions implanted into the first blocking material layer 210 in the first ion doping step. Thus, it is possible to achieve that the ions doped in the third doped region 213 are the same as the ions doped in the first doped region 211.

[0067] In other embodiments, when the number of the first blocking layers is multiple, a plurality of third doping processes are performed on the first blocking material layer to form a plurality of third doped regions. Each third doping process includes: forming a third blocking patterning layer on the surface of the first blocking material layer, the third blocking patterning layer having a plurality of third blocking openings therein, and the third blocking openings exposing a part of the surface of the first blocking material layer; using the third blocking patterning layer as a mask, performing a third ion doping step on the first blocking material layer to form at least one third doped region among the plurality of third doped regions; and removing the third blocking patterning layer after forming the third doped region.

[0068] Since the plurality of third doped regions are formed through a plurality of third doping processes, and in each third doping process, a third blocking patterning layer is formed. When the spacing between different third blocking structures is small, the third doped regions corresponding to the third blocking structures can be formed in different third doping processes, that is, the third blocking openings with a close spacing are formed in different third blocking patterning layers. Thus, during the exposure process of the patterns for forming the third blocking openings, some defects such as short circuit or poor pattern dimension accuracy caused by the close spacing between different third blocking openings can be reduced. The pattern accuracy of the third blocking openings is improved, and thus, the pattern accuracy of the third doped regions and the first blocking layer is improved.

[0069] In other embodiments, before forming a plurality of first doped regions, a plurality of third doped regions are formed in the first blocking material layer.

[0070] In other embodiments, while forming a plurality of first doped regions, a plurality of third doped regions are formed within the first barrier material layer. The method for simultaneously forming the first doped regions and the third doped regions includes: forming a fifth barrier patterning layer on the surface of the first barrier material layer, the fifth barrier patterning layer having a plurality of first barrier openings and a plurality of third barrier openings, the first barrier openings being used to define the pattern of the first doped regions, and the third barrier openings being used to define the pattern of the third doped regions; using the fifth barrier patterning layer as a mask to perform ion doping on the first barrier material layer to form a plurality of first doped regions and a plurality of third doped regions.

[0071] In this embodiment, after forming the third doped region 213, the third barrier patterning layer is removed.

[0072] Please refer to Figure 6 and Figure 7 , Figure 6 is Figure 7 a schematic cross-sectional structure diagram along the X-X1 direction in, after forming the first doped region 211 and the third doped region 213, etching the first barrier material layer 210 until the surface of the layer to be etched 200 is exposed to form a plurality of first barrier structures 221 and a plurality of first barrier layers 223.

[0073] In this embodiment, the materials of the first barrier structures 221 and the plurality of first barrier layers 223 are the same.

[0074] The materials of the first barrier structures 221 and the first barrier layers 223 include one or a combination of more of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

[0075] The process for etching the first barrier material layer 210 includes at least one of a dry etching process or a wet etching process.

[0076] In another embodiment, no third barrier structure is formed, and the method for forming a plurality of first barrier structures includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of mutually separate first barrier mask structures on the surface of the first barrier material layer; using the first barrier mask structures as a mask to etch the first barrier material layer until the surface of the layer to be etched is exposed.

[0077] In other embodiments, the method for forming a plurality of first barrier structures and a plurality of first barrier layers includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of mutually separate first barrier mask structures and third barrier mask structures on the surface of the first barrier material layer; using the first barrier mask structures and the third barrier mask structures as a mask to etch the first barrier material layer until the surface of the layer to be etched is exposed.

[0078] Please refer to Figures 8 to 10 , Figure 8 which Figure 10 is a schematic cross-sectional structure diagram in the X-X1 direction in Figure 9 which Figure 10 is a schematic cross-sectional structure diagram in the Y-Y1 direction in. After forming the first barrier structure 221 and the first barrier layer 223, a second barrier material layer 230 is formed on the surface of the layer to be etched 200, the surface of the first barrier structure 221, and the surface of the first barrier layer 223; a plurality of second doping regions 232 are formed in the second barrier material layer 230 on the surface of the layer to be etched 200.

[0079] Specifically, forming a plurality of second doping regions 232 in the second barrier material layer 230 on the surface of the layer to be etched 200 means: forming a plurality of second doping regions 232 in the second barrier material layer 230 other than the second barrier material layer 230 on the first barrier structure 221 and the first barrier layer 223.

[0080] In this embodiment, the second doping regions 232 are located between the first barrier structure 221 and the first barrier layer 223.

[0081] The second doping regions 232 provide materials for forming the second barrier structure.

[0082] It should be noted that Figure 10 schematically shows 2 second doping regions in. The number of the second doping regions can be 2, or 1 or more than 2. And when the number of the second doping regions is more than 1, according to design requirements, the shapes of the second doping regions can be different.

[0083] In this embodiment, the process of forming the second barrier material layer 230 includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0084] In this embodiment, the method of forming a plurality of the second doping regions 232 includes: forming a second barrier patterned layer (not shown) on the surface of the second barrier material layer 230, the second barrier patterned layer having a plurality of second barrier openings (not shown), the second barrier openings exposing a part of the surface of the second barrier material layer; using the second barrier patterned layer as a mask, performing ion doping on the second barrier material layer 230 to form a plurality of the second doping regions 232.

[0085] In other embodiments, when the number of the second blocking structures is multiple, a plurality of second doping processes are performed on the second blocking material layer to form a plurality of second doped regions. Each second doping process includes: forming a second blocking patterned layer on the surface of the second blocking material layer, wherein the second blocking patterned layer has a plurality of second blocking openings, and the second blocking openings expose a part of the surface of the second blocking material layer; using the second blocking patterned layer as a mask, performing a second ion doping step on the second blocking material layer to form at least one second doped region among the plurality of second doped regions; and removing the second blocking patterned layer after forming the second doped region.

[0086] Since the plurality of second doped regions are formed through a plurality of second doping processes, and one second blocking patterned layer is formed in each second doping process. When the distance between different second blocking structures is small, the second doped regions corresponding to the second blocking structures can be formed in different second doping processes, that is, the second blocking openings with a relatively close distance are formed in different second blocking patterned layers. Thus, during the exposure process of forming the pattern of the second blocking openings, some defects such as short circuit or poor pattern size accuracy caused by the relatively close distance between different second blocking openings can be reduced. The pattern accuracy of the second blocking openings is improved, and thus, the pattern accuracy of the second doped regions and the second blocking structures is improved.

[0087] In this embodiment, the process of the second ion doping step includes an ion implantation process.

[0088] In this embodiment, the second blocking patterned layer is removed after forming the second doped region 232.

[0089] In this embodiment, after forming a plurality of second doped regions 232, a plurality of fourth doped regions 234 are formed in the second blocking material layer 230 on the surface of a part of the first blocking layer 223, and the ions doped in the fourth doped regions 234 are the same as the ions doped in the second doped regions 232.

[0090] The fourth doped regions 234 provide materials for forming the second blocking layer.

[0091] Since the ions doped in the fourth doped regions 234 are the same as the ions doped in the second doped regions 232, therefore, the material of the second blocking layer can be the same as the material of the second blocking structure.

[0092] The purpose of making the material of the second blocking layer the same as the material of the second blocking structure is that when selectively etching the second blocking structure subsequently, the second blocking layer can be selectively etched simultaneously.

[0093] The method for forming a plurality of fourth doping regions 234 includes: forming a fourth blocking patterned layer (not shown) on the surface of the second blocking material layer 230, the fourth blocking patterned layer having a plurality of fourth blocking openings (not shown), the fourth blocking openings exposing the surface of the second blocking material layer 230 on a part of the surface of the first blocking layer 223; using the fourth blocking patterned layer as a mask, performing a fourth ion doping step on the second blocking material layer 230 to form a plurality of the fourth doping regions 234.

[0094] Since the second blocking patterned layer and the fourth blocking patterned layer are formed separately, that is, the second blocking openings and the fourth blocking openings are formed in different blocking patterned layers. Thus, it is possible to reduce some defects such as short circuit or poor pattern dimension accuracy caused by the close spacing between the second blocking openings and the fourth blocking openings during the exposure process of the patterns for forming the second blocking openings and the fourth blocking openings. The pattern accuracy of the second blocking openings and the fourth blocking openings is improved, and thus the pattern accuracy of the second doping region 232 and the second blocking structure, as well as the fourth doping region 234 and the second blocking layer is improved.

[0095] In this embodiment, the process of the fourth ion doping step includes an ion implantation process, and the ions implanted into the second blocking material layer 230 in the fourth ion doping step are the same as the ions implanted into the second blocking material layer 230 in the second ion doping step. Thus, it is possible to achieve that the ions doped in the fourth doping region 234 are the same as the ions doped in the second doping region 232.

[0096] In other embodiments, when the number of second blocking layers is multiple, a plurality of fourth doping processes are performed on the second blocking material layer to form a plurality of fourth doping regions. Each fourth doping process includes: forming a fourth blocking patterned layer on the surface of the second blocking material layer, the fourth blocking patterned layer having a plurality of fourth blocking openings, the fourth blocking openings exposing the surface of the second blocking material layer on a part of the surface of at least one first blocking layer; using the fourth blocking patterned layer as a mask, performing a fourth ion doping step on the second blocking material layer to form at least one fourth doping region among the plurality of fourth doping regions; after forming the fourth doping region, removing the fourth blocking patterned layer.

[0097] Since the plurality of fourth doped regions are formed through multiple fourth doping processes, a fourth blocking patterning layer is formed during each fourth doping process. When the spacing between different fourth blocking structures is small, the fourth doped regions corresponding to the fourth blocking structures can be formed during different fourth doping processes, that is, the fourth blocking openings with a relatively close spacing are formed in different fourth blocking patterning layers. Thus, during the exposure process of the pattern for forming the fourth blocking openings, some defects such as short circuit or poor pattern dimension accuracy caused by the relatively close spacing between different fourth blocking openings can be reduced. The pattern accuracy of the fourth blocking openings is improved, and thus, the pattern accuracy of the fourth doped regions and the second blocking layer is improved.

[0098] In other embodiments, before forming a plurality of second doped regions, a plurality of fourth doped regions are formed in the second blocking material layer.

[0099] In other embodiments, while forming a plurality of second doped regions, a plurality of fourth doped regions are formed in the second blocking material layer. The method for simultaneously forming the second doped regions and the fourth doped regions includes: forming a sixth blocking patterning layer on the surface of the second blocking material layer, the sixth blocking patterning layer having a plurality of second blocking openings and a plurality of fourth blocking openings, the second blocking openings being used to define the pattern of the second doped regions, and the fourth blocking openings being used to define the pattern of the fourth doped regions; using the sixth blocking patterning layer as a mask to perform ion doping on the second blocking material layer to form a plurality of second doped regions and a plurality of fourth doped regions.

[0100] In this embodiment, after forming the fourth doped region 234, the fourth blocking patterning layer is removed.

[0101] Please refer to Figures 11 to 13 , Figure 11 is Figure 13 the schematic cross-sectional structure diagram along the X-X1 direction in Figure 12 is Figure 13 the schematic cross-sectional structure diagram along the Y-Y1 direction in. After forming the second doped region 232 and the fourth doped region 234, the second blocking material layer 230 is etched until the surface of the layer to be etched 200, the surface of the first blocking structure 221, and the surface of the first blocking layer 223 are exposed, and a plurality of second blocking structures 242 and a plurality of second blocking layers 244 are formed.

[0102] The first blocking layer 223 and the second blocking layer 244 located on the surface of the first blocking layer 223 constitute a third blocking structure.

[0103] In this embodiment, the materials of the second blocking structures 242 and the plurality of second blocking layers 244 are the same.

[0104] The materials of the second blocking structure 242 and the second blocking layer 244 include one or a combination of more than one of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

[0105] The process of etching the second blocking material layer 230 includes at least one of a dry etching process or a wet etching process.

[0106] In another embodiment, no third blocking structure is formed, and the method of forming a plurality of second blocking structures includes: forming a second blocking material layer on the surface of the layer to be etched; forming a plurality of mutually discrete second blocking mask structures on the surface of the second blocking material layer; using the second blocking mask structures as masks to etch the second blocking material layer until the surface of the layer to be etched is exposed.

[0107] In other embodiments, the method of forming a plurality of second blocking structures and a plurality of second blocking layers includes: forming a second blocking material layer on the surface of the layer to be etched, on the surface of the first blocking structure, and on the surface of the first blocking layer; forming a plurality of mutually discrete second blocking mask structures and fourth blocking mask structures on the surface of the second blocking material layer; using the second blocking mask structures and the fourth blocking mask structures as masks to etch the second blocking material layer until the surface of the layer to be etched, the surface of the first blocking structure, and a part of the surface of the first blocking layer are exposed.

[0108] Next, a first patterned layer is formed, the first patterned layer having a plurality of first openings, each first opening exposing at least a partial surface of one first blocking structure 221 and one second blocking structure 242; using the first patterned layer as a mask to etch the first blocking structure 221; forming a second patterned layer, the second patterned layer having a plurality of second openings, each second opening exposing at least a partial surface of one first blocking structure 221 and one second blocking structure 242; using the second patterned layer as a mask to etch the second blocking structure 242.

[0109] Since the first blocking structure 221 and the second blocking structure 242 are different, after adjusting the etching process parameters, the first blocking structure 221 can be selectively etched with the first patterned layer as a mask. Similarly, the second blocking structure 242 can be selectively etched with the second patterned layer as a mask. Thus, subsequently, when etching the layer to be etched 200 with the first blocking structure 221 and the second patterned layer as a mask, it will not be blocked by the unexposed second blocking structure 242 (the exposed second blocking structure 242 is selectively etched and removed). Furthermore, a second blocking structure 242 with a longer length can be formed. Similarly, subsequently, when etching the layer to be etched 200 with the second blocking structure 242 and the first patterned layer as a mask, it will not be blocked by the unexposed first blocking structure 221 (the exposed first blocking structure 221 is selectively etched and removed). Furthermore, a first blocking structure 221 with a longer length can be formed. Since a first blocking structure 221 and a second blocking structure 242 with longer lengths can be formed, the requirements for the overlay accuracy of the patterns in the length directions of the first blocking structure 221 and the second blocking structure 242 are reduced, the process window for forming the first blocking structure 221 and the second blocking structure 242 is increased, and the process difficulty of manufacturing the first blocking structure 221 and the second blocking structure 242 is reduced.

[0110] Since the first blocking layer 223 is made of the same material as the first blocking structure 221, and the second blocking layer 244 is made of the same material as the second blocking structure 242, when the first opening and the second opening also expose the surface of the third blocking structure, similarly, the first blocking layer 223 can be selectively etched while selectively etching the first blocking structure 221, and the exposed second blocking layer 244 can be selectively etched while selectively etching the second blocking structure 242. Thus, a first blocking layer 223 and a second blocking layer 224 with longer lengths can be formed, which will not be elaborated here.

[0111] It should be noted that the order between forming the first patterned layer and etching the first blocking structure 221 with the first patterned layer as a mask, and forming the second patterned layer and etching the second blocking structure 242 with the second patterned layer as a mask does not affect the effect of the technical solution of the present invention. Therefore, the second patterned layer can be formed and the second blocking structure 242 can be etched with the second patterned layer as a mask after forming the first patterned layer and etching the first blocking structure 221 with the first patterned layer as a mask. Alternatively, the first patterned layer can be formed and the first blocking structure 221 can be etched with the first patterned layer as a mask after forming the second patterned layer and etching the second blocking structure 242 with the second patterned layer as a mask.

[0112] For ease of understanding, in this embodiment, taking the example of forming the second patterning layer and using the second patterning layer as a mask to etch the second barrier structure 242, then forming the first patterning layer and using the first patterning layer as a mask to etch the first barrier structure 221 for illustration, the detailed process can be referred to Figures 14 to 21 .

[0113] Please refer to Figure 14 and Figure 15 , Figure 14 is a schematic cross-sectional structure diagram along the Y - Y1 direction in Figure 15 . The second patterning layer 250 is formed, and the second patterning layer 250 has a plurality of second openings 251. Each second opening 251 exposes at least a partial surface of 1 first barrier structure 221 and 1 second barrier structure 242.

[0114] In this embodiment, among the plurality of second openings 251, at least 1 second opening 251 also exposes at least a partial surface of 1 third barrier structure.

[0115] In this embodiment, the method for forming the second patterning layer 250 includes: forming a second patterning material layer on the surface of the layer to be etched 200, the surface of the first barrier structure 221, the surface of the second barrier structure 242, and the surface of the third barrier structure; performing exposure and development on the second patterning material layer to form the second patterning layer 250.

[0116] In this embodiment, the material of the second patterning layer 250 includes photoresist.

[0117] Please continue to refer to Figure 14 and Figure 15 , using the second patterning layer 250 as a mask to etch the second barrier structure 242.

[0118] In this embodiment, a second etching process is adopted to etch the second barrier structure 242 using the second patterning layer 250 as a mask. The second etching process has a third etching rate for the material of the first barrier structure 221, and the second etching process has a fourth etching rate for the material of the second barrier structure 242, and the fourth etching rate is greater than the third etching rate. Thus, selective etching and removal of the second barrier structure 242 are achieved.

[0119] The ratio of the fourth etching rate to the third etching rate is above 5:1.

[0120] If the ratio of the fourth etching rate to the third etching rate is too small, when etching the second barrier structure 242, the exposed first barrier structure 221 is likely to be damaged, which is not conducive to blocking the etching of the layer 200 to be etched under the exposed first barrier structure 221 in the second etching process through the exposed first barrier structure 221. Therefore, by selecting an appropriate ratio of the fourth etching rate to the third etching rate, that is, when the ratio of the fourth etching rate to the third etching rate is above 5:1, it is beneficial to better selectively etch the second barrier structure 242, so as to better block the etching of the layer 200 to be etched under the exposed first barrier structure 221 in the second etching process through the exposed first barrier structure 221.

[0121] In this embodiment, when the second opening 251 exposes the surface of the third barrier structure, since the second barrier layer 244 is located on the surface of a part of the first barrier layer 223, that is, the projection of the second barrier layer 244 on the surface of the layer 200 to be etched is within the projection range of the first barrier layer 223 on the surface of the layer 200 to be etched. Therefore, even if the second opening 251 exposes the surface of the second barrier layer 244 of the third barrier structure or not, through the first barrier layer 223, it is still possible to block the etching of the layer 200 to be etched under the exposed third barrier structure when selectively etching the second barrier structure 242.

[0122] The second etching process includes at least one of a dry etching process and a wet etching process.

[0123] Please refer to Figure 16 and Figure 17 , Figure 16 is a schematic cross-sectional structure diagram along the Figure 17 Y-Y1 direction in

[0124] After etching the second barrier structure 242 with the second patterning layer 250 as a mask, continue to etch the layer 200 to be etched with the second patterning layer 250, the exposed first barrier structure 221 and the first barrier layer 223 as masks, and form a plurality of fourth interconnect openings 252 in the layer 200 to be etched. The fourth interconnect openings 252 expose the side wall surfaces of at least one of the first barrier structure 221 and the first barrier layer 223.

[0125] Please refer to Figure 18 and Figure 19 , Figure 18 is along Figure 19Schematic cross-sectional structure diagram in the X-X1 direction. After removing the second patterning layer 250, the first patterning layer 260 is formed. The first patterning layer 260 has a number of first openings 261, and each first opening 261 exposes at least a partial surface of 1 first barrier structure 221 and 1 second barrier structure 242.

[0126] In this embodiment, among the number of first openings 261, at least 1 first opening 261 also exposes a partial surface of at least 1 third barrier structure.

[0127] In this embodiment, the method of forming the first patterning layer 260 includes: forming a first patterning material layer on the surface of the layer to be etched 200, the surface of the first barrier structure 221, the surface of the second barrier structure 242, and the surface of the third barrier structure; performing exposure and development on the first patterning material layer to form the first patterning layer 260.

[0128] In this embodiment, the material of the first patterning layer 260 includes photoresist.

[0129] Please continue to refer to Figure 18 and Figure 19 , using the first patterning layer 260 as a mask, etch the first barrier structure 221.

[0130] In this embodiment, using a first etching process, with the first patterning layer 260 as a mask, etch the first barrier structure 221. The first etching process has a first etching rate for the material of the first barrier structure 221, and the first etching process has a second etching rate for the material of the second barrier structure 242, and the first etching rate is greater than the second etching rate.

[0131] In this embodiment, the process parameters of the first etching process and the process parameters of the second etching process are different.

[0132] In this embodiment, the ratio of the first etching rate to the second etching rate is 5:1 or more.

[0133] If the ratio of the first etching rate to the second etching rate is too small, when etching the first barrier structure 221, the exposed second barrier structure 242 is likely to be damaged, which is not conducive to blocking the etching of the layer to be etched 200 under the exposed second barrier structure 242 by the first etching process through the exposed second barrier structure 242 during the first etching process. Therefore, by selecting an appropriate ratio of the first etching rate to the second etching rate, that is, when the ratio of the first etching rate to the second etching rate is above 5:1, it is beneficial to perform better selective etching of the first barrier structure 221, so as to better block the etching of the layer to be etched 200 under the exposed second barrier structure 242 by the first etching process through the exposed second barrier structure 242 during the first etching process.

[0134] In this embodiment, when the first opening 261 exposes the surface of the first barrier layer 223 of the third barrier structure, since the material of the first barrier layer 223 is the same as that of the first barrier structure 221, the exposed first barrier layer 223 can be selectively etched and removed while selectively etching the first barrier structure 221. When the first opening 261 exposes the surface of the second barrier layer 244 of the third barrier structure, since the material of the second barrier layer 244 is different from that of the first barrier structure 221, the exposed second barrier layer 244 will not be etched. Thus, through the second barrier layer 244, it is still possible to block the etching of the layer to be etched 200 under the second barrier layer 244 of the exposed third barrier structure during the selective etching of the first barrier structure 221 and the first barrier layer 223.

[0135] The first etching process includes at least one of a dry etching process and a wet etching process.

[0136] Please refer to Figure 20 and Figure 21 , Figure 20 is a schematic cross-sectional structure diagram in the X-X1 direction along Figure 21 . After etching the first barrier structure 221 with the first patterned layer 260 as a mask, continue to etch the layer to be etched 200 with the first patterned layer 260, the exposed second barrier structure 242, and the second barrier layer 244 as masks, and form a plurality of third interconnect openings 262 in the layer to be etched 200, and the third interconnect openings 262 expose the side wall surfaces of at least one of the second barrier structure 242 and the second barrier layer 244.

[0137] In this embodiment, after forming the third interconnect openings 262, remove the first patterned layer 260, the first barrier structure 221, the second barrier structure 242, and the third barrier structure.

[0138] Please refer on the basis of Figure 21 toFigure 22 After removing the first patterning layer 260, the first barrier structure 221, the second barrier structure 242, and the third barrier structure, a third interconnect structure 263 is formed in each third interconnect opening 262, and a fourth interconnect structure 253 is formed in each fourth interconnect opening 252.

[0139] In this embodiment, the method for forming the third interconnect structure 263 and the fourth interconnect structure 253 includes: forming an electrically conductive interconnect material layer on the surface of the layer to be etched 200, in the third interconnect openings 262, and in the fourth interconnect openings 252; and planarizing the electrically conductive interconnect material layer until the surface of the layer to be etched 200 is exposed.

[0140] In another embodiment, the third barrier structure is not formed. Using the first patterning layer as a mask, after etching the first barrier structure, continue to use the first patterning layer as a mask to etch the layer to be etched, and a plurality of first interconnect openings are formed in the layer to be etched, and the side wall surfaces of the second barrier structure are exposed by the first interconnect openings; a first interconnect structure is formed in each first interconnect opening.

[0141] In another embodiment, the third barrier structure is not formed. Using the second patterning layer as a mask, after etching the second barrier structure, continue to use the second patterning layer as a mask to etch the layer to be etched, and a plurality of second interconnect openings are formed in the layer to be etched, and the side wall surfaces of the first barrier structure are exposed by the second interconnect openings; a second interconnect structure is formed in each second interconnect opening.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a layer to be etched; Forming a plurality of first barrier structures on the surface of the layer to be etched; Forming a plurality of second barrier structures on the surface of the layer to be etched, wherein the materials of the first barrier structures and the second barrier structures are different; Forming a first patterned layer having a plurality of first openings, each first opening exposing at least a partial surface of one first barrier structure and a partial surface of one second barrier structure; Using the first patterned layer as a mask, selectively etching away the exposed first barrier structures; Forming a second patterned layer having a plurality of second openings, each second opening exposing at least a partial surface of one first barrier structure and a partial surface of one second barrier structure; Using the second patterned layer as a mask, selectively etching away the exposed second barrier structures; Using the first patterned layer as a mask, after etching the first barrier structures, continuing to use the first patterned layer as a mask to etch the layer to be etched, and forming a plurality of first interconnect openings in the layer to be etched, the first interconnect openings exposing the side wall surfaces of the second barrier structures; Using the second patterned layer as a mask, after etching the second barrier structures, continuing to use the second patterned layer as a mask to etch the layer to be etched, and forming a plurality of second interconnect openings in the layer to be etched, the second interconnect openings exposing the side wall surfaces of the first barrier structures.

2. The method for forming a semiconductor structure according to claim 1, wherein, Further including: Before forming the first patterned layer and the second patterned layer, forming a plurality of third barrier structures on the surface of the layer to be etched, the third barrier structures including a first barrier layer and a second barrier layer located on the surface of a part of the first barrier layer, the material of the first barrier layer being the same as the material of the first barrier structures, and the material of the second barrier layer being the same as the material of the second barrier structures.

3. The method for forming a semiconductor structure according to claim 2, wherein, Among the plurality of first openings, at least one first opening further exposes at least a partial surface of one third barrier structure.

4. The method for forming a semiconductor structure according to claim 2, wherein, Among the plurality of second openings, at least one second opening further exposes at least a partial surface of one third barrier structure.

5. The method for forming a semiconductor structure according to claim 1, wherein, Adopting a first etching process, using the first patterned layer as a mask to etch the first barrier structures, the first etching process having a first etching rate for the material of the first barrier structures and a second etching rate for the material of the second barrier structures, and the first etching rate being greater than the second etching rate.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The ratio of the first etching rate to the second etching rate is above 5:

1.

7. The method for forming a semiconductor structure according to claim 1, wherein, Adopting a second etching process, using the second patterned layer as a mask to etch the second barrier structures, the second etching process having a third etching rate for the material of the first barrier structures and a fourth etching rate for the material of the second barrier structures, and the fourth etching rate being greater than the third etching rate.

8. The method for forming a semiconductor structure according to claim 7, wherein The ratio of the fourth etching rate to the third etching rate is above 5:

1.

9. The method for forming a semiconductor structure according to claim 2, wherein, The method for forming the first barrier structures includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of first doped regions in the first barrier material layer; after forming the first doped regions, etching the first barrier material layer until the surface of the layer to be etched is exposed.

10. The method for forming a semiconductor structure as described in claim 9, wherein, The method for forming the first barrier layer includes: before etching the first barrier material layer, forming a plurality of third doped regions in the first barrier material layer, and the ions doped in the third doped regions are the same as the ions doped in the first doped region.

11. The method for forming a semiconductor structure according to claim 10, wherein, The method for forming the second barrier structure includes: after forming the first barrier structure and the first barrier layer, forming a second barrier material layer on the surface of the layer to be etched, the surface of the first barrier structure, and the surface of the first barrier layer; forming a plurality of second doped regions in the second barrier material layer on the surface of the layer to be etched; after forming the second doped regions, etching the second barrier material layer until the surface of the layer to be etched, the surface of the first barrier structure, and the surface of the first barrier layer are exposed.

12. The method for forming a semiconductor structure according to claim 11, wherein The method for forming the second barrier layer includes: before etching the second barrier material layer, forming a plurality of fourth doped regions in the second barrier material layer on a part of the surface of the first barrier layer, and the ions doped in the fourth doped regions are the same as the ions doped in the second doped region.

13. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first barrier structure includes one or a combination of more of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

14. The method for forming a semiconductor structure according to claim 1, wherein, The material of the second barrier structure includes one or a combination of more of titanium nitride, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

15. The method for forming a semiconductor structure according to claim 1, wherein Further included is: forming a first interconnect structure in each first interconnect opening.

16. The method for forming a semiconductor structure as claimed in claim 1, wherein, forming a second interconnect structure in each second interconnect opening.

17. The method for forming a semiconductor structure according to claim 3, wherein, Further included is: using the first patterning layer as a mask, after etching the first barrier structure, continuing to use the first patterning layer as a mask to etch the layer to be etched, forming a plurality of third interconnect openings in the layer to be etched, and the third interconnect openings expose the side wall surfaces of at least one of the second barrier structure and the second barrier layer; forming a third interconnect structure in each third interconnect opening.

18. The method for forming a semiconductor structure according to claim 4, wherein, Further included is: using the second patterning layer as a mask, after etching the second barrier structure, continuing to use the second patterning layer as a mask to etch the layer to be etched, forming a plurality of fourth interconnect openings in the layer to be etched, and the fourth interconnect openings expose the side wall surfaces of at least one of the first barrier structure and the first barrier layer; forming a fourth interconnect structure in each fourth interconnect opening.

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