Storage nodes after the three-node access device of vertical three-dimensional (3D) memory is formed

Abstract

Systems, methods, and apparatus for storage nodes after formation of a three-node access device for a vertical three-dimensional (3D) memory are provided. An example method includes a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of dielectric material and sacrificial material to form a vertical stack. A plurality of first vertical openings are formed through the vertical stack to form elongated vertical columns with sidewalls in the vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical opening. Portions of the first conductive material are removed to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical columns. A second vertical opening is formed through the vertical stack to expose a first region of the sacrificial material.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to storage nodes after formation of a three-node access device and structures for vertical three-dimensional (3D) memory. Background Art

[0002] Memories are often implemented in electronic systems such as computers, cell phones, handheld devices, etc. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to maintain its data and may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when power is not supplied and may include NAND flash, NAND flash, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross-point memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space is available for manufacturing memory, including DRAM arrays. A corresponding memory cell for a DRAM may include an access device, such as a transistor, having a first source / drain region and a second source / drain region separated by a channel region. The gate may be opposite to the channel region and separated from the channel region by a gate dielectric. Access lines such as word lines are electrically connected to the gate of the DRAM cell. The DRAM cell may include a storage node, such as a capacitor cell, coupled to a digit line via an access device. The access device may be activated by an access line coupled to an access transistor (e.g., to select a cell). The capacitor may store a charge corresponding to the data value (e.g., a logical "1" or "0") of the corresponding cell. Summary of the invention

[0004] One aspect of the present disclosure provides a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, wherein the method comprises: depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings through the vertical stack, the plurality of first vertical openings having a first horizontal direction and a second horizontal direction and extending primarily in the second horizontal direction to form elongated vertical columns having sidewalls in the vertical stack; conformally depositing a first conductive material on a gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical columns; forming a second vertical column through the vertical stack; An opening is formed in the vertical stack, wherein the second vertical opening mainly extends in a first horizontal direction to expose a first area of ​​the sacrificial material; the first area is selectively removed to form a first horizontal opening in the sacrificial material, in which a first source / drain material, a channel material, and a second source / drain material of a horizontally oriented three-node access device are formed; a third vertical opening is formed through the vertical stack, wherein the third vertical opening mainly extends in the first horizontal direction to expose a second area of ​​the sacrificial material; after forming the three-node access device in the first area, the second area is selectively removed to form a second horizontal opening in the sacrificial material, in which a storage node electrically coupled to the first source / drain material is formed.

[0005] Another aspect of the present disclosure provides a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, wherein the method comprises: depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings through the vertical stack, the plurality of first vertical openings having a first horizontal direction and a second horizontal direction and extending primarily in the second horizontal direction to form elongated vertical columns having sidewalls in the vertical stack; conformally depositing a first conductive material on a gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical columns; forming a second vertical opening, the second vertical opening passing through the vertical stack and extending primarily in the first horizontal direction to expose a first region of the sacrificial material; selectively removing the first region to expose a first region of the sacrificial material in the vertical stack; and A first horizontal opening is formed in the sacrificial material extending a first distance (D1) from the second vertical opening; a first source / drain material, a channel material, and a second source / drain material are sequentially deposited in the first horizontal opening using an atomic layer deposition (ALD) process to form a horizontally oriented three-node access device without a body contact; a third vertical opening is formed, the third vertical opening passes through the vertical stack and extends primarily in the first horizontal direction to expose a second region of the sacrificial material; the second region is selectively removed to form a second horizontal opening in the sacrificial material extending a second distance (D2) from the second vertical opening; and after forming the horizontally oriented three-node access device, an atomic layer deposition (ALD) process is used to sequentially deposit: a first electrode electrically in electrical contact with the first source / drain material; a high-k dielectric material on the first electrode; and a second electrode on the high-k dielectric.

[0006] Another aspect of the present disclosure provides a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, wherein the method comprises: depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings through the vertical stack, the plurality of first vertical openings having a first horizontal direction and a second horizontal direction and extending primarily in the second horizontal direction to form elongated vertical columns having sidewalls in the vertical stack; conformally depositing a first conductive material on a gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical columns; forming a second vertical opening through the vertical stack and extending primarily in the first horizontal direction to expose a first sidewall adjacent to a first region of the sacrificial material; selectively removing the first region to expose a first sidewall adjacent to the first region of the sacrificial material; and A first horizontal opening is formed in the sacrificial material; a first source / drain material, a channel material, and a second source / drain material are sequentially formed in the first horizontal opening to form a horizontally oriented three-node access device without a body contact, wherein the first source / drain material is selected to provide an ohmic contact to a first electrode of a storage node; a third vertical opening is formed, the third vertical opening passes through the vertical stack and extends primarily in the first horizontal direction to expose a second sidewall adjacent to a second region of the sacrificial semiconductor material; after forming the horizontally oriented access device, the second region is selectively removed using the source / drain conductive material as an etch stop material to form a second horizontal opening in the sacrificial material extending to the first source / drain material; and the first electrode of the storage node is selectively deposited on the first source / drain material in the second horizontal opening to form a direct electrical contact therewith. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic illustration of a vertical three-dimensional (3D) memory according to many embodiments of the present disclosure.

[0008] Figure 2 is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to many embodiments of the present disclosure.

[0009] Figure 3 is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to many embodiments of the present disclosure.

[0010] Figure 4An example method for forming an array of vertically stacked memory cells to form a three-node access device at one stage of a semiconductor manufacturing process is presented in accordance with many embodiments of the present disclosure.

[0011] Figure 5A-5B An example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process in accordance with many embodiments of the present disclosure is presented.

[0012] Figures 6A to 6E An example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process in accordance with many embodiments of the present disclosure is presented.

[0013] Figures 7A to 7E An example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process in accordance with many embodiments of the present disclosure is presented.

[0014] Figures 8A to 8E An example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process in accordance with many embodiments of the present disclosure is presented.

[0015] Figures 9A to 9E An example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process in accordance with many embodiments of the present disclosure is presented.

[0016] Fig.10 An example of a three-node horizontally-oriented access device coupled to horizontally-oriented storage nodes and to vertically-oriented access lines and horizontally-oriented digit lines is shown in accordance with many embodiments of the present disclosure.

[0017] Fig.11 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with many embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure describe a three-node access device for a vertical three-dimensional (3D) memory. A three-node horizontal access device is formed without a body region contact. As used herein, a three-node is intended to refer to an access device comprising (1) a first source / drain region and (2) a second source / drain region separated by a channel region and (3) one or more gates opposite the channel region. The three-node horizontal access device is integrated with the vertical access line and with the horizontal digit line. According to an embodiment, the three-node horizontal access device can be formed so that the channel region has fewer minority carriers, for example, it can operate without minority carriers, thereby removing the need to control the body potential of the body region of the access device. Advantages of the structures and processes described herein can include a lower off current (Ioff) of the access device compared to a silicon-based (Si-based) access device and / or a reduced gate-induced drain leakage (GIDL) of the access device.

[0019] According to an embodiment, a channel and / or source / drain region replacement manufacturing step is performed before the capacitor cell formation process. Since the body contact to the body region of the access device is not used, the digit line integration can be more easily achieved in the manufacturing process. In addition, due to the shorter channel length and lower source / drain semiconductor manufacturing process overhead, the embodiments described herein can achieve a better lateral scaling path compared to the path achieved with the channel region based on doped polysilicon. Another benefit is that, for example, gas phase doping (GPD) is avoided in the formation of the source / drain region.

[0020] The figures herein follow a numbering convention in which one or more first digits correspond to the figure number of the drawing, and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by using similar numerals. For example, reference numeral 104 may refer to Figure 1 Component "04" in the figure, and similar components can be referenced as Figure 2 204 in FIG. Multiple similar elements in a figure may be referenced by a reference numeral followed by a hyphen and another number or letter. For example, 302-1 may be referenced by Figure 3 302-1 in FIG. 302-2 may refer to element 302-2 which may be similar to element 302-1. Such similar elements may generally be referenced without hyphens and additional numbers or letters. For example, elements 302-1 and 302-2 or other similar elements may be referenced as 302 in general.

[0021] Figure 1 is a block diagram of a device according to many embodiments of the present disclosure. Figure 1 A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is shown. Figure 1 It is shown that the cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. The sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along the second direction (D2) 105. Each sub-cell array in the sub-cell array, such as the sub-cell array 101-2, can include multiple access lines 103-1, 103-2, ..., 103-Q (which can also be referred to as word lines). Moreover, each sub-cell array in the sub-cell array, such as the sub-cell array 101-2, can include multiple digital lines 107-1, 107-2, ..., 107-P (which can also be referred to as bit lines, data lines or readout lines). Figure 1 , digit lines 107-1, 107-2, ..., 107-P are shown extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are shown extending in a third vertical direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal ("XY") plane. The third direction (D3) 111 can be considered to be in a vertical ("Z") plane. Therefore, according to the embodiments described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction, such as the third direction (D3) 111.

[0022] Memory cells such as 110 may include access devices such as access transistors and storage nodes such as capacitors located at the intersection of each access line 103-1, 103-2, ..., 103-Q and each digit line 107-1, 107-2, ..., 107-P. The memory cells may be written or read using access lines 103-1, 103-2, ..., 103-Q and digit lines 107-1, 107-2, ..., 107-P. The digit lines 107-1, 107-2, ..., 107-P can interconnect the memory cells conductively along the horizontal columns of each subcell array 101-1, 101-2, ..., 101-N, and the access lines 103-1, 103-2, ..., 103-Q can interconnect the memory cells conductively along the vertical rows of each subcell array 101-1, 101-2, ..., 101-N. A memory cell, such as 110, can be positioned between an access line, such as 103-2, and a digit line, such as 107-2. Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digit lines 107-1, 107-2, ..., 107-P.

[0023] The digit lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. The digit lines 107-1, 107-2, ..., 107-P in one subcell array, for example, 101-2, may be spaced apart from each other in a vertical direction, for example, in a third direction (D3) 111.

[0024] The access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction relative to the substrate, such as in a third direction (D3) 111. The access lines in one subcell array, such as 101-2, may be spaced apart from each other in a first direction (D1) 109 by an insulating material.

[0025] The gate of a memory cell, such as memory cell 110, can be connected to an access line, such as 103-2, and a first conductive node, such as a first source / drain region, of an access device, such as a transistor, of memory cell 110 can be connected to a digit line, such as 107-2. Each of the memory cells, such as memory cell 110, can be connected to a storage node, such as a capacitor. A second conductive node, such as a second source / drain region, of an access device, such as a transistor, of memory cell 110 can be connected to a storage node, such as a capacitor. Although reference to a first source / drain region and a second source / drain region is used herein to represent two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the “first” source / drain region and / or the “second” source / drain region have some unique meaning. It is intended that only one of the source / drain regions be connected to a digit line, such as 107-2, and the other source / drain region can be connected to a storage node.

[0026] Figure 2 A three-dimensional (3D) semiconductor memory device is shown showing a vertically oriented memory cell stack in an array according to some embodiments of the present disclosure, for example Figure 1 A perspective view of a portion of subcell array 101 - 2 is shown. Figure 3 Shown Figure 2 The unit cell of the 3D semiconductor memory array shown is as follows Figure 1 A perspective view of memory cell 110 is shown.

[0027] like Figure 2 As shown, the substrate 200 may form a bonding Figure 1One subcell array among the plurality of subcell arrays described is, for example, 101 - 2 . For example, the substrate 200 may be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0028] like Figure 2 As shown in the example embodiment of FIG. 1 , the substrate 200 may be fabricated thereon with a vertically oriented memory cell stack extending in a vertical direction, for example, in a third direction (D3) 111 . Figure 1 Memory cell 110 in. According to some embodiments, a vertically oriented memory cell stack may be fabricated such that each memory cell, for example Figure 1 The memory cells 110 in the embodiment are formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3) (also referred to herein as "tiers"). The repeated vertical levels L1, L2, and L3 can be arranged, such as "stacked", in a vertical direction, such as Figure 1 The third direction (D3) 111 is shown. Each of the repeating vertical levels L1, L2, and L3 may include a horizontally oriented access device 230, such as a plurality of discrete components such as regions of transistors and storage nodes such as capacitors, including access line 103-1, 103-2, ..., 103-Q connections and digit line 107-1, 107-2, ..., 107-P connections. The horizontally oriented three-node access device, such as Figure 1 The plurality of discrete components of transistor 110 in can be formed in multiple iterations of vertically repeated layers within each level, as described below in conjunction with Figure 4 and the following etc. are described in more detail and can be found in Figure 1 The illustrated second direction ( D2 ) 105 extends horizontally in a similar second direction ( D2 ) 205 .

[0029] The plurality of discrete components of a horizontally oriented three-node access device 230, such as a transistor, may include a first source / drain region 221 and a second source / drain region 223 extending in a second direction (D2) 205 separated by a channel region 225. The three-node horizontal access device 230 is formed without a body region contact. As used herein, three-node is intended to refer to an access device including (1) a first source / drain region 221 and (2) a second source / drain region 223 separated by a channel region 225, and (3) one or more gates, such as vertical access lines 203-1, 203-2, ..., 203-Q, opposite the channel region 225. In some embodiments, the channel region 225 may include silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include an n-type dopant region, such as a semiconductor material, formed adjacent to a p-type doped channel region, such as a semiconductor material, of an access device to form an n-type conductivity transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include a p-type conductivity channel, such as a doped semiconductor material, formed adjacent to an n-type conductivity channel region, such as a doped semiconductor material, of an access device to form a p-type conductivity transistor. By way of example and not limitation, the n-type dopant may include phosphorus (P) atoms, and the p-type dopant may include boron (B) atoms formed in a relatively doped bulk region of a polysilicon semiconductor material. However, embodiments are not limited to these examples.

[0030] Storage node 227, such as a capacitor, may be connected to a corresponding terminal of the access device. Figure 2 As shown in the example of , a storage node 227, such as a capacitor, can be coupled to a second source / drain region 223 of an access device. The second source / drain region 223 can be labeled similarly and referred to herein as the first source / drain region. Again, the "first" and "second" source / drain labels simply mean that they are separate and different, one connected to a digit line and the other connected to a storage node. A storage node can be or include a memory element capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor including a phase change material, etc. However, the embodiments are not limited to these examples. In some embodiments, the ... Figure 1 The storage node associated with each horizontally oriented access device of the memory cell 110 may similarly be in the same Figure 1 The illustrated second direction ( D2 ) 105 extends in a similar second direction ( D2 ) 205 .

[0031] like Figure 2As shown, a plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P are connected to Figure 1 The plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P may extend in a first direction (D1) 209 similar to the first direction (D1) 109 in FIG. Figure 1 The digit lines 107-1, 107-2, ..., 107-P shown are similar. The multiple horizontally oriented digit lines 207-1, 207-2, ..., 207-P can be arranged along a third direction (D3) 211, such as "stacked". The multiple horizontally oriented digit lines 207-1, 207-2, ..., 207-P can include a conductive material. For example, the conductive material can include one or more of the following: a doped semiconductor such as doped silicon, doped germanium, etc., a conductive metal nitride such as titanium nitride, tantalum nitride, etc., a metal such as tungsten (W), titanium (Ti), tantalum (Ta), etc. and / or a metal semiconductor compound such as tungsten silicide, cobalt silicide, titanium silicide, etc. However, the embodiments are not limited to these examples.

[0032] In each of the vertical levels 213-1 (L1), 213-2 (L2), and 213-M (L3), horizontally oriented memory cells such as Figure 1 The memory cells 110 in the first direction (D1) 209 may be spaced apart from each other. Figure 4 As described in more detail below, the plurality of discrete components of the horizontally-oriented access device 230, such as the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225 extending horizontally in the second direction (D2) 205 and the plurality of horizontally-oriented digit lines 207-1, 207-2, ..., 207-P extending horizontally in the first direction (D1) 209, may be formed in the same plane, such as at the same level, and in the same layer within each level. The plurality of horizontally-oriented digit lines 207-1, 207-2, ..., 207-P extending horizontally in the first direction (D1) 209 may be in electrical contact with the first source / drain region 221 and orthogonal to the horizontally-oriented access device 230, such as a transistor, extending horizontally in the second direction (D2) 205.

[0033] In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer farther from the substrate 200 within a certain level, for example, within the level (L1), compared to the layer in which the discrete components of the laterally oriented access device are formed, for example, the first source / drain region 221 and the second source / drain region 223 separated by the channel 225. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be connected to the top surface of the first source / drain region 221 directly and / or through an additional contact including a metal silicide.

[0034] like Figure 2 As shown in the exemplary embodiment of FIG. 2 , access lines 203-1, 203-2, ..., 203-Q extend in a vertical direction, for example, in a third direction (D3) 211 relative to substrate 200. Further, as Figure 2 As shown, a subcell array such as Figure 1 The access lines 203-1, 203-2, ..., 203-Q in the subcell array 101-2 in the first direction (D1) 209 may be spaced apart from each other in the first direction (D1) 209. The access lines 203-1, 203-2, ..., 203-Q may be provided to extend vertically relative to the substrate 200 between a pair of horizontally oriented three-node access devices 230, such as transistors, in the third direction (D3) 211 but adjacent to each other at a certain level, such as a first level (L1) in the first direction (D1) 209, and the access devices extend laterally in the second direction (D2) 205. Each of the access lines 203-1, 203-2, ..., 203-Q may extend vertically on the sidewalls of the corresponding three-node access devices in the plurality of horizontally oriented three-node access devices 230, such as transistors, in the third direction (D3), the plurality of horizontally oriented three-node access devices being vertically stacked and separated from the channel region by gate dielectrics.

[0035] For example and Figure 3As shown in more detail, a first access line, e.g., 203-1, among the vertically extending access lines may be adjacent to sidewalls of a channel region 225 of a horizontally oriented three-node access device 230, e.g., a first horizontally oriented three-node access device in a transistor, in a first level (L1) 213-1, sidewalls of a channel region 225 of a horizontally oriented three-node access device 230, e.g., a first horizontally oriented three-node access device in a transistor, in a second level (L2) 213-2, and sidewalls of a channel region 225 of a horizontally oriented three-node access device 230, e.g., a first horizontally oriented three-node access device in a transistor, in a third level (L3) 213-M, and the like. Similarly, a second one of the vertically extending access lines, such as 203-2, may be adjacent to a sidewall of a channel region 225 of a horizontally oriented three-node access device 230, such as a second horizontally oriented three-node access device in a transistor, in the first level (L1) 213-1, which is spaced apart from the horizontally oriented three-node access device 230, such as a first horizontally oriented three-node access device in the transistor, in the first level (L1) 213-1 in the first direction (D1) 209. Moreover, a second one of the vertically extending access lines, such as 203-2, may be adjacent to a sidewall of a channel region 225 of a horizontally oriented three-node access device 230, such as a second horizontally oriented three-node access device in a transistor, in the second level (L2) 213-2, and a sidewall of a channel region 225 of a horizontally oriented three-node access device 230, such as a second horizontally oriented three-node access device in a transistor, in the third level (L3) 213-M, and the like. Embodiments are not limited to a particular number of levels.

[0036] The vertically extending access lines 203-1, 203-2, ..., 203-Q may include a conductive material, for example, one of a doped semiconductor material, a conductive metal nitride, a metal and / or a metal-semiconductor compound. The access lines 203-1, 203-2, ..., 203-Q may correspond to the bonding Figure 1 An access line (AL) is depicted, such as a word line (WL).

[0037] like Figure 2 As shown in the example embodiment of FIG. 1 , an insulating layer dielectric (ILD) 250 extending in a first direction (D1) 209 along the end surface of a horizontally oriented three-node access device 230, such as a transistor, may be formed in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-M above the substrate 200. The ILD 250 may connect the vertically stacked memory cell array, such as the memory cell array, to the second direction (D2) 205. Figure 1101-1, 101-2, ..., 101-N are isolated and separated. ILD 250 may include insulating materials, for example, dielectric materials, such as oxide materials, silicon oxide (SiO 2 ) material, silicon nitride (SiN) material, silicon oxynitride material and / or a combination thereof, etc.

[0038] although Figure 2 Although not shown in the figure, the insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may include one or more of the following: silicon oxide material, silicon nitride material and / or silicon oxynitride material, etc. However, the embodiments are not limited to these examples.

[0039] Figure 3 In more detail, a vertically stacked memory cell array according to some embodiments of the present disclosure is shown, for example, Figure 1 The unit cell in the subcell array 101-2 in, for example, Figure 1 The memory cell 110 in FIG. Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 may be impurity-doped regions of a horizontally oriented three-node access device 330, such as a transistor. The first source / drain region 321 and the second source / drain region 323 may also include metal and / or a metal composite material formed using an atomic layer deposition process or the like containing the following: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material and / or indium oxide (In 2 O 3 ) or indium tin oxide (In 2-x Sn x O 3 ) at least one of. However, embodiments are not limited to these examples. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material, such as polysilicon, containing a high level of doping with significant interactions between dopants such as phosphorus (P), boron (B), etc. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions. The first source / drain region 321 and the second source / drain region 323 may be similar to Figure 2 A first source / drain region 221 and a second source / drain region 223 are shown.

[0040] The first source / drain region and the second source / drain region can be separated by a channel 325, such as a channel region, of a horizontally-oriented three-node access device 330, such as a transistor. Channel 325 can be a low-doped (p-) polysilicon material. In some embodiments, channel 325 can be a low-doped (p-) poly-germanium (Ge) material. In some embodiments, channel 325 can be a low-doped (p-) poly-silicon-germanium (poly-SiGe) material. However, in some embodiments, channel 325 can include a semiconductor oxide (also referred to herein as an "oxide semiconductor" or "oxide semiconductor material"). The semiconductor oxide can include any suitable composition; and in some embodiments can include one or more of indium, zinc, tin, and gallium. As used herein, examples of oxide semiconductor materials and / or compositions comprising one or more of indium, zinc, tin, and gallium can include, for example, ZnO x 、InO x SnO 2 、Zn x O y N, Mg x Zn y O z 、In x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、In x Ga y Si z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O b 、Si x In y Zn z O a 、Zn x Sn y O z 、Alx Zn y Sn z O a , Ga x Zn y Sn z O a and Zr x Zn y Sn z O a And other materials.

[0041] In other embodiments, the channel 325 may include a two-dimensional (2D) material. The 2D material may include any suitable composition; and in some embodiments may include one or more of a transition metal dichalcogenide including molybdenum disulfide (MoS 2 ), Molybdenum Diselenide (MoSe 2 ), molybdenum ditelluride (MoTe 2 ), tungsten disulfide (WS 2 ) and tungsten selenide (WSe 2 ). However, the embodiments are not limited to these examples.

[0042] In some embodiments, the channel 325 may include a composite material such as indium gallium zinc oxide (In 2 Ga 2 ZnO 7 ) material (also referred to herein as "IGZO"). In some embodiments, the channel 325 may include multiple layers of In 2 Ga 2 ZnO 7 The channel 325 may include multiple layers of indium (In) in the layer closest to the surface opposite to the gate dielectric. 2 G 2 ZnO 7 A channel 325 is rich in gallium (Ga) in an outer layer farthest from a surface opposite to the gate dielectric relative to the plurality of layers. Moreover, in some embodiments, the channel 325 may include multiple layers of I 2 G 2 ZnO 7 A channel is rich in zinc (Zn) or the like in an outer layer farthest from a surface opposite to the gate dielectric relative to the plurality of layers. However, the embodiments are not limited to these examples.

[0043] and Figure 2 The digit lines 207-1, 207-2, ..., 207-P and Figure 1 A digit line similar to the digit lines 107-1, 107-2, ..., 107-P shown, such as 307-1, may be formed to be in electrical contact with the first source / drain region 321. Figure 3 As shown in the example embodiment, Figure 2 The access lines 203-1, 203-2, ..., 203-Q and Figure 1 The access lines 103-1, 103-2, ..., 103-Q in the same access line, such as 303-1, can extend vertically in a third direction (D3) 311 adjacent to the sidewalls of the horizontally oriented three-node access device 330, such as the channel region 325 of the transistor, which is horizontally conductive between the first source / drain region 321 and the second source / drain region 323 along the second direction (D2) 305. The gate dielectric material 304 can be interposed between the access line 303-1 (a portion of which forms the gate of the horizontally oriented three-node access device 330, such as the gate of the transistor) and the channel region 325. The gate dielectric material 304 can include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc. or a combination thereof. The embodiment is not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and the like.

[0044] Figure 4 Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at one stage of a semiconductor manufacturing process is presented and in accordance with many embodiments of the present disclosure. Figure 4 In the example embodiment shown in the example of , the method includes depositing alternating layers of dielectric material 430-1, 430-2, ..., 430-N (also individually and / or collectively referred to herein as "430") and sacrificial material 432-1, 432-2, ..., 432-N (also individually and / or collectively referred to herein as "432") in repeated iterations to form a vertical stack 401 on the working surface of the semiconductor substrate 400. In one embodiment, the dielectric material 430 can be deposited to a thickness, such as a vertical height in the third direction (D3) in the range of twenty (20) nanometers (nm) to sixty (60) nm. In one embodiment, the sacrificial material 432 can be deposited to a thickness, such as a vertical height in the range of twenty (20) nm to one hundred (100) nm. However, the embodiments are not limited to these examples.

[0045] In one example, the sacrificial materials 432-1, 432-2, ..., 432-N may include sacrificial semiconductor materials such as polysilicon (Si), silicon nitride (SiN), or even oxide-based semiconductor compositions. Although the discussion herein will refer to the sacrificial semiconductor material example, the embodiments are not limited to this example. It is intended that the sacrificial material may be selectively etched relative to the alternating layers of dielectric material 430-1, 430-2, ..., 430-N.

[0046] like Figure 4 As shown, the vertical direction 411 is shown as Figure 1-3 A third direction (D3) similar to the third direction (D3) among the first direction, the second direction, and the third direction shown in , for example, the z direction in the xyz coordinate system. Figure 4 In the example of FIG. 4 , four levels numbered 1, 2, 3, and 4 of repeated iterations of the vertical stack 401 are shown (in FIG. Figure 2 401). However, embodiments are not limited to this example and may include more or fewer iterations. A photolithographic hard mask (HM) layer 435 may be deposited as a top layer on the repeated iterations of the vertical stack 401.

[0047] In some embodiments, dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example and not limitation, dielectric materials 430-1, 430-2, ..., 430-N may include silicon dioxide (SiO 2 In another example, the dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si 3 N 4 ) material (also referred to herein as "SiN"). In another example, the dielectric material 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO x C y ) material (also referred to herein as "SiOC"). In another example, the dielectric material 430-1, 430-2, ..., 430-N may include silicon oxynitride (SiO x N y ) material (also referred to herein as "SiON") and / or a combination thereof. Embodiments are not limited to these examples. In some embodiments, sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may include silicon (Si) materials in a polycrystalline state and / or an amorphous state. In another example, sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may include silicon nitride (SiN) materials. However, embodiments are not limited to these examples.

[0048] The repeated iterations of alternating dielectric material 430-1, 430-2, ..., 430-N layers and sacrificial semiconductor material 432-1, 432-2, ..., 432-N layers may be deposited in a semiconductor manufacturing device according to a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques may be used to deposit alternating layers of dielectric material 430-1, 430-2, ..., 430-N and sacrificial semiconductor material 432-1, 432-2, ..., 432-N in repeated iterations to form a vertical stack 401, such as Figure 4 shown.

[0049] Figure 5A Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process is presented and in accordance with many embodiments of the present disclosure. Figure 5A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 5A In the example embodiment shown in the example of , the method includes forming a vertical opening 500 through the vertical stack to the substrate to form a plurality of access lines having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, as Figure 5A As shown, the plurality of access line vertical openings 500 extend primarily in a second horizontal direction (D2) 505 and may form an elongated vertical column 513 having sidewalls 514 in the vertical stack. The plurality of access line vertical openings 500 may be formed by patterning a photolithographic mask 535 using photolithography techniques, for example, to form a hard mask (HM) on the vertical stack before etching the plurality of access line vertical openings 500.

[0050] Figure 5B is along Figure 5A , which is a cross-sectional view taken along the cutting line AA′ in FIG. 1 , showing another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 5BIt is shown that conductive materials 540-1, 540-2, ..., 540-4 can be formed on the gate dielectric material 538 in the plurality of first vertical openings 500. By way of example and not limitation, the gate dielectric material 538 can be conformally deposited in the plurality of access line vertical openings 500 using a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD), an atomic layer deposition (ALD), or other suitable deposition process to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric material 538 can be deposited to a specific thickness (t1) suitable for a specific design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the gate dielectric material 538 can include silicon dioxide (SiO 2 ) material, alumina (Al 2 O 3 ) materials, high dielectric constant (k) materials such as high-k dielectric materials and / or combinations thereof, as well as Figure 3 As described.

[0051] Further, if Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited on the surface of the gate dielectric material 538 in the plurality of access line vertical openings 500. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited on the surface of the gate dielectric material 538 in the plurality of access line vertical openings 500 using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric material 538. Conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, such as Figure 1 and the access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown below and adapted to specific design rules. For example, the conductive material 540-1, 540-2, ..., 540-4 may be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the conductive material 540-1, 540-2, ..., 540-4 may include a metal such as tungsten (W), a metal composite, titanium nitride (TiN), doped polysilicon, and / or some other combination thereof, as well as Figure 3 As described.

[0052] like Figure 5BAs shown, the conductive materials 540-1, 540-2, ..., 540-4 may be recessed backwards to Figure 5B In the cross-sectional view of FIG. 5 , only the vertical sidewalls along the elongated vertical columns shown as 542-1, 542-2 and 542-3 are retained. The vertical sidewalls can be removed from the first vertical opening, such as by using a suitable selective anisotropic, such as directional, etching process. Figure 5A 500 in the bottom surface of the conductive material 540-1, 540-2, ..., 540-4 to make the conductive material 540-1, 540-2, ..., 540-4 recessed back, thereby exposing the gate dielectric material 538 on the bottom surface to form individual vertical access lines 540-1, 540-2, ..., 540-4, now shown as remaining only on the sidewall 514. Figure 5B As shown, a dielectric material 539 such as oxide or other suitable spin-on dielectric (SOD) can then be deposited in the access line vertical opening 500 using a process such as CVD to fill the access line vertical opening 500. Chemical mechanical planarization (CMP) or other suitable semiconductor manufacturing techniques can be used to planarize the dielectric to the vertical semiconductor stack, such as Figure 4 The top surface of the hard mask 535 of 401 is shown. Subsequent photolithographic material 536, such as a hard mask, can be deposited using CVD and planarized using CMP to cover and seal the conductive material 540-1, 540-2, ..., 540-4 remaining only on the sidewalls 514 of the access line vertical opening 500. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0053] Fig. 6A Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process is presented in and in accordance with many embodiments of the present disclosure. Fig. 6A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Fig. 6A In an example embodiment of the present invention, the method includes patterning the Figure 5B The photolithography masks 636, 536 in FIG. Fig. 6A The method further demonstrates the use of a selective isotropic (eg, non-directional) etching process to remove Figure 5B , 540-4 to separate and individually form a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z, for example Figure 1And the access lines 103-1, 103-2, ..., 103-Q in the following etc. Therefore, in Figure 5B In the cross-sectional view, multiple separate vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown along the side walls of the slender vertical column columns, such as along the side walls of the slender vertical column columns 542-1, 542-2 and 542-3.

[0054] like Fig. 6A As shown in the example of FIG. 1 , a suitable selective isotropic (eg, non-directional) etching process can be used to Figure 5B The exposed conductive material 540-1, 540-2, ..., 540-4 in the back is removed to the access line vertical opening, for example Figure 5A The gate dielectric material 638 in 500 is as shown in FIG. Fig. 6A As shown, a subsequent dielectric material 641 such as an oxide or other suitable spin-on dielectric (SOD) may then be deposited using a process such as CVD or other suitable technique to fill the remaining opening from which the remaining opening is removed. Figure 5B The exposed conductive materials 540-1, 540-2, ..., 540-4 in the vertical semiconductor stack can be planarized using processes such as CMP or other suitable techniques. Figure 4 The top surface of the previous hard mask 635 of 401 is shown. In some embodiments, a subsequent photolithographic material 537, such as a hard mask, may be deposited using CVD and planarized using CMP to cover and seal the Figure 4 , 640-(N+1), ..., 640-(Z-1), and 640-Z above the working surface of the vertical semiconductor stack 401 in the embodiment of the present invention, so that the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z are protected along the sidewalls of the elongated vertical column columns shown as 642-1, 642-2, and 642-3 in the cross-sectional view. However, the embodiments are not limited to these process examples.

[0055] Figure 6B Shown along Fig. 6A A cross-sectional view taken along the cutting line AA′ in FIG. 1 shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6BThe cross-sectional view shown in FIG. 4 is away from a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows repeated iterations of alternating layers of dielectric material 630-1, 630-2, ..., 630-N and sacrificial semiconductor material 632-1, 632-2, ..., 632-N on the semiconductor substrate 400 to form a vertical stack, such as shown in FIG. Figure 4 As shown in 401. Figure 6B As shown, the vertical direction 611 is shown as Figure 1-3 The third direction (D3) 111 of the first direction, the second direction, and the third direction shown in FIG. 1 is similar to the third direction (D3), such as the z direction in the xyz coordinate system. The drawing plane extending from right to left is in the first direction (D1) 609. Figure 6B In the example embodiment of FIG. 6 , dielectric material 641 is shown filling the vertical openings overlying the deposition of residual gate dielectric material 638. A hard mask 637 described above covers the illustrated structure.

[0056] Figure 6C Shown along Fig. 6A A cross-sectional view taken along the cutting line BB′ in FIG. 1 shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6C The cross-sectional view shown in is illustrated as extending in a second direction (D2) 605 along an axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, ..., 630-N and sacrificial semiconductor material 632-1, 632-2, ..., 632-N, along and in which horizontally oriented access devices and horizontally oriented storage nodes such as capacitor cells may be formed within the layers of sacrificial semiconductor material 632-1, 632-2, ..., 632-N. Figure 6C , adjacent opposing vertical access lines 640 - 3 are illustrated by dashed lines indicating locations set inwardly from the plane of the drawing and oriented inwardly.

[0057] Fig.6D Shown along Fig. 6A A cross-sectional view taken along the cutting line CC' in FIG. 1 shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.6DThe cross-sectional view shown in is shown extending in a second direction (D2) 605 along an axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, ..., 630-N and sacrificial semiconductor material 632-1, 632-2, ..., 632-N outside a region where horizontally oriented access devices and horizontally oriented storage nodes such as capacitor cells will be formed within the layers of sacrificial semiconductor material 632-1, 632-2, ..., 632-N. Figure 6C , dielectric material 641 is shown filling spaces between horizontally oriented access devices and horizontally oriented storage nodes of a three-dimensional array of vertically oriented memory cells, which can be spaced apart along a first direction (D1) so as to extend into and out of the plane of the drawing. Repeated iterations of alternating layers of dielectric material 630-1, 630-2, ..., 630-(N+1) and sacrificial semiconductor material 632-1, 632-2, ..., 632-N are shown at the left end of the drawing, where horizontally oriented digit lines such as Figure 1 Digit lines 107 - 1 , 107 - 2 , . . . , 107 -P shown below and so forth may be integrated to form electrical contacts with the second source / drain regions as described in more detail below.

[0058] Fig. 6E Shown along Fig. 6A A cross-sectional view taken along the cutting line D-D' in FIG. 1 shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. The drawings are shown from right to left in the plane of the drawing. Fig. 6E , which extends in a first direction (D1) 609 along an axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, ..., 630-N and sacrificial semiconductor material 632-1, 632-2, ..., 632-N, thereby intersecting across multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and intersecting regions of sacrificial semiconductor material 632-1, 632-2, ..., 632-N, in which channel regions separated from multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) by gate dielectric material 638 can be formed. Fig. 6E, a first dielectric fill material 639 is shown as separating spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which can be formed to extend into and out of the plane of the drawing, as described in more detail below, and can be spaced along a first direction (D1) 609 and vertically stacked into an array extending in a third direction (D3) 611 in a three-dimensional (3D) memory.

[0059] Fig. 7A Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process is presented in and in accordance with many embodiments of the present disclosure. Fig. 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Fig. 7A In an example embodiment of the present invention, the method includes using a photolithography process to pattern the Figure 5A , 5B and the photolithography masks 535, 536 and / or 637, etc. described in 6A-6E. Fig. 7A The method further discloses using one or more etching processes to pass through the vertical stack in the access device area such as Fig. 7A The replacement channel and replacement source / drain transistor regions 742 and Figure 7C The first vertical openings 771-1 and 771-2 are formed in the replacement channel and replacement source / drain transistor regions 742 in the semiconductor substrate. The first vertical openings 771-1 and 771-2 are shown as extending primarily in the first horizontal direction (D1) 709. The one or more etching processes form the first vertical openings 771-1 and 771-2 to be adjacent to the first region of the sacrificial semiconductor material at Figure 7B-7E The vertical stack shown exposes the first sidewall in repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, ..., 732-N. Other listed components may be similar to those in combination with Figure 5A , 5B and those components shown and discussed in 6A-6E.

[0060] According to an embodiment, in Fig. 7A and 7C, 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, ..., 732-N can be removed from repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, ..., 732-N in a vertical stack, for example, a transistor region, to form an access device, for example, a transistor. According to an embodiment, this process is performed before selectively removing the storage node region of the sacrificial semiconductor material in which the capacitor cell is formed. According to one embodiment, the sacrificial semiconductor material 732-1, 732-2, ..., 732-N is an oxide sacrificial semiconductor material (e.g., an oxide semiconductor), such as polycrystalline and / or amorphous silicon dioxide (SiO 2 ).according to Figure 7B-7E In the example embodiment shown, the method includes selectively etching the access device region 742, e.g., the first region, of the sacrificial semiconductor material 732-1, 732-2, ..., 732-N to form a first horizontal opening in the vertical stack at a first horizontal distance 751 (D1) backward from the first vertical openings 771-1 and 771-2. One example of selectively etching the sacrificial semiconductor material 732-1, 732-2, ..., 732-N includes using an atomic layer etching (ALE) process. Other techniques may be used.

[0061] In some embodiments, Figure 7B-7EAs shown, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region in a first horizontal opening as an access device. By way of example and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. An example ALD process for forming the first source / drain region and the second source / drain region is disclosed in co-filed, co-pending U.S. Patent Application No. _____________, Attorney Docket No. 1013.0570001, having at least one co-inventor and entitled “Source / Drain Integration in Three-Node Access Device for Vertical Three Dimensional (3D) Memory”. Another example for channel region formation is disclosed in co-pending U.S. Patent Application No. _____________, Attorney Docket No. 1013.0560001, having at least one co-inventor and entitled “Channel Integration in Three-Node Access Device for Vertical Three Dimensional (3D) Memory.” Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0062] Figure 7B Shown along Fig. 7A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7B The cross-sectional view shown in is away from a plurality of individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, ..., 732-N, such as sacrificial oxide semiconductor material, separated by vertical isolation trenches having walls lined with gate dielectric material 738 and filled with isolation material such as spin-on dielectric (SOD) 741, such as Figure 6B and 6D As explained. Figure 7BAs shown, the vertical direction 711 is shown as Figure 1-3 The third direction (D3) 111 of the first, second and third directions shown in FIG. 709 is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The plane of the drawing extending from right to left is in the first direction (D1) 709.

[0063] Figure 7C Shown along Fig. 7A A cross-sectional view taken along the cutting line BB' in FIG. 1 shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7C , which extends from left to right along the plane of the drawing sheet in a second direction (D2) 705 along the axis of the repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1). However, it is now shown that the sacrificial semiconductor material has been removed in the access device region 742 of the vertically stacked alternating layers to form, for example, horizontal openings 733-1, 733-2, ..., 733-N in the first region 742. It is in these horizontal openings 733-1, 733-2, ..., 733-N that horizontally oriented access devices having first source / drain regions, channel regions, and second source / drain regions can be formed between the vertically alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1). It is in the second region 744 that storage nodes will be formed after the horizontal access devices are formed in the horizontal openings 733-1, 733-2, ..., 733-N.

[0064] exist Figure 7C In an example embodiment of, horizontal openings 730-1, 730-2, ..., 730-N are shown in which access devices having first source / drain regions, channel regions, and second source / drain regions are formed, the openings extending from left to right in the plane of the drawing in a second direction 705 (D2), at a first distance (D1 opening) 751 from vertical openings 771-1 and 771-2 formed in the vertical stack, and along an axis toward horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory. Figure 7C , adjacent relative vertical access lines 740-3 are shown by dashed lines indicating the relative vertical access lines 740-3 disposed inwardly from the plane of the drawing and disposed inwardly. Figure 5A and 5B The remaining walls of the gate dielectric material 738 in the access line trench 500 are separated from the location.

[0065] Fig.7D Shown along Fig. 7A, which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.7D The cross-sectional view shown in is shown extending along an axis of repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-N, 730-(N+1) and horizontal openings 733-1, 733-2, ..., 733-N from left to right in the plane of the drawing sheet in a second direction (D2) 705 outside a region where horizontally oriented access devices and horizontally oriented storage nodes such as capacitor cells are to be formed. Fig.7D , dielectric material 741 is shown filling spaces between horizontally oriented access devices of a three-dimensional array of vertically oriented memory cells, which can be spaced apart along a first direction (D1) so as to extend into and out of the plane of the drawing. Repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) and horizontal openings 733-1, 733-2, ..., 733-N are shown at the left end of the drawing, where a horizontally oriented digit line, such as a digit line, can be placed once the first source / drain region of the horizontal access device is formed. Figure 1 And the digit lines 107-1, 107-2, ..., 107-P shown below and so on are integrated to form electrical contacts.

[0066] Fig. 7E Shown along Fig. 7A A cross-sectional view taken along the cutting line D-D' in FIG. 1 shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. The drawings are shown from right to left in the plane of the drawing. Fig. 7E , which extends in a first direction (D1) 709 along an axis of repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) and horizontal openings 733-1, 733-2, ..., 733-N in which channel regions separated by gate dielectric material 738 from a plurality of individual vertical access lines 740-1, 740-2, ..., 740-4 are to be formed. Fig. 7E In the figure, a first dielectric fill material 739 is shown as separating the spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which can be formed as described in more detail below to extend into and out of the plane of the drawing and can be spaced along a first direction (D1) 709 and vertically stacked into an array extending in a third direction (D3) 711 in a three-dimensional (3D) memory.

[0067] Fig. 8A Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process is presented in and in accordance with many embodiments of the present disclosure. Fig. 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Fig. 8A In the exemplary embodiment of the present invention, the vertical openings 871-1 and 871-2 are kept from Figures 7A-7E However, in Figures 8A-8E in Figure 7C and 7D The horizontal openings 733-1, 733-2, ..., 733-N shown have been formed with Figure 8C Horizontal access devices 898-1, 898-2, ..., 898-N of the first source / drain regions, channel regions, and second source / drain regions of 898-1A, 898-1B, and 898-1C in the vertical stack are formed to extend in the second direction 805 (D2) in the vertically stacked horizontal access device region 842. In addition, as Figure 8C and 8D As shown, horizontal digit lines 899-1, 899-2, 899-N have been formed and integrated to contact the second source / drain region, such as 898-1C. Other listed components may be similar to those shown and discussed in conjunction with FIGS.

[0068] According to an embodiment, in an access device region 842 (eg, a transistor region), Figures 6A-6E The sacrificial semiconductor materials 632-1, 632-2, ..., 632-N in the embodiment have been removed, and the horizontal openings 733-1, 733-2, ..., 733-N have been filled with horizontal access devices 898, such as transistors. According to an embodiment, this process is performed before the storage node region 844 in which the capacitor cell is formed is selectively removed from the sacrificial semiconductor material. According to Figures 8B-8E In the example embodiment shown, the method includes selectively depositing a first source / drain region 838-1A, a channel region 838-1B, and a second source / drain region 838-1C on the substrate using an atomic layer deposition (ALD) process or other suitable deposition technique. Figures 7A-7EIn each of the horizontal openings 733-1, 733-2, ..., 733-N in the first horizontal opening. By way of example and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0069] Figure 8B Shown along Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8B The cross-sectional view shown in FIG. 1 is away from a plurality of individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and shows repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) separated by second regions 844 of sacrificial semiconductor material 832-1, 832-2, ..., 832-N. Figure 8B As shown, the vertical direction 811 is shown as Figure 1-3 The third direction (D3) 111 of the first, second and third directions shown in FIG. 809 is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The plane of the drawing extending from right to left is in the first direction (D1) 809.

[0070] Figure 8C Shown along Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8C The cross-sectional view shown in FIG. 8 is illustrated as extending along an axis of a repeating iteration of alternating layers of dielectric material 830 - 1 , 830 - 2 , . . . , 830 -(N+1) in a second direction ( D2 ) 805 from left to right along the plane of the drawing sheet.

[0071] However, it is now shown that the first source / drain region material, the channel region material, and the second source / drain region material 898-1, 898-2, ..., 898-N have been deposited on Figures 7A-7E, 830-(N+1) vertically alternating layers with dielectric material 830-1, 830-2, ..., 830-(N+1) in the first direction (D1) and extending out from the plane of the drawing sheet. In one example, the integration of horizontal digit lines 899-1, 899-2, ..., 899-N is achieved by filling first vertical opening 871 with a suitable digit line conductive material such as tungsten (W) or a highly doped semiconductor material using a CVD process, and isotropically etching to recess horizontal digit lines 899-1, 899-2, ..., 899-N. Figure 7C-7E The remaining portion of the horizontal openings 733-1, 733-2, ..., 733-N in the PCB is in contact with the second source / drain region, such as 898-1C. In another example, the PCB is filled by using an atomic layer deposition (ALD) process. Figure 7C-7E The remaining portions of the horizontal openings 733-1, 733-2, ..., 733-N in the horizontal openings and make electrical contact with the second source / drain regions, such as 898-1C, to achieve integration of horizontal digit lines 899-1, 899-2, ..., 899-N.

[0072] Thus, without body contacts and with improved formation ordering of capacitor cells, three-node horizontal access devices 838-1, 838-2, ..., 838-N have been formed and integrated into vertical access lines 840-1, 840-2, ..., 840-(Z+1) and into digit lines 899-1, 899-2, ..., 899-N. Advantages of the structures and processes described herein may include lower off current (Ioff) of the access device as compared to silicon-based (Si-based) access devices. Channel regions such as 838-1B may be free of minority carriers of the access device, and thus remove the need to control the body potential of the body region of the access device and / or reduced gate-induced drain leakage (GIDL) of the access device.

[0073] According to an embodiment, a channel and / or source / drain region replacement manufacturing step may be performed prior to the capacitor cell formation process. Since the body contact to the body region of the access device is not used, digit line integration may be more easily achieved in the manufacturing process. In addition, due to the reduced channel length and lower source / drain semiconductor manufacturing process formation overhead, the embodiments described herein may achieve a better lateral scaling path compared to the path achieved with a doped polysilicon based channel region.

[0074] Integration of the first source / drain region, the channel, and the second source / drain region 898-1, 898-2, ..., 898-N of the horizontal access device and integration of the horizontal digit lines 899-1, 899-2, ..., 899-N may be performed according to ALD processes and techniques. One example ALD process for forming the first source / drain region and the second source / drain region is disclosed in co-filed, co-pending U.S. Patent Application No. _____________, Attorney Docket No. 1013.0570001, having at least one co-inventor and entitled “Source / Drain Integration in a Three-Node Access Device for Vertical Three-Dimensional (3D) Memory.” Another example for channel region formation is disclosed in co-filed, co-pending U.S. Patent Application No. _____________, Attorney Docket No. 1013.0560001, having at least one co-inventor and entitled “Channel Integration in a Three-Node Access Device for Vertical Three-Dimensional (3D) Memory.” According to various embodiments, an additional benefit is that eg gas phase doping (GPD) is avoided in the formation of the source / drain regions.Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0075] exist Figure 8C In the example embodiment of FIG. 1 , horizontal access devices 898-1, 898-2, ..., 898-N having a first source / drain region, a channel region, and a second source / drain region are shown, wherein the horizontal access devices are spaced a first distance (D1 opening) ( D2 ) from the first vertical openings 871-1 and 871-2 formed in the vertical stack from left to right in the plane of the drawing in a second direction 805 (D2). Fig. 7A and 7C 751) and extending along the axis of the horizontal access devices and horizontal storage nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. Fig.10 As shown, dielectric material may be deposited to fill vertical openings 871-1 and 871-2. Figure 8C , adjacent relative vertical access line 840-3 is shown by a dashed line indicating a location set inwardly from the plane of the drawing and in an orientation.

[0076] Fig.8DShown along Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.8D The cross-sectional view shown in is shown extending outside a region in a second direction (D2) 805 from left to right in the plane of the drawing along an axis of repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-N, 830-(N+1) and horizontal digit lines 899-1, 899-2, ..., 899-N extending into and out of the plane of the drawing in a first direction (D1) in the region where horizontally-oriented access devices 898-1, 898-2, ..., 898-N and horizontally-oriented storage nodes such as capacitor cells are formed in an access device region 842 and a storage node region 844. Fig.8D , dielectric material 841 is shown filling spaces between horizontally oriented access devices of a three-dimensional array of vertically oriented memory cells, which can be spaced apart along a first direction (D1) so as to extend into and out of the plane of the drawing. Dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal digit lines 899-1, 899-2, ..., 899-N are shown at the left end of the drawing, for example Figure 1 And repeated iterations of alternating layers of digit lines 107-1, 107-2, ..., 107-P shown below, etc., the levels are integrated to form electrical contact with the second source / drain region of the formed horizontal access device, such as 838-1A.

[0077] Fig. 8E Shown along Fig. 8A A cross-sectional view taken along the cutting line D-D' in FIG. 1 shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. The drawings are shown from right to left in the plane of the drawing. Fig. 8E , which extends in a first direction (D1) 809 along an axis of repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) and channel regions of horizontal access devices 898-1, 898-2, ..., 898-N separated from a plurality of individual vertical access lines 840-1, 840-2, ..., 840-4 by gate dielectric material 838. Fig. 8E, a first dielectric fill material 839 is shown as separating spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which can be formed as described in more detail below to extend into and out of the plane of the drawing and can be spaced apart along a first direction (D1) 809 and vertically stacked into an array extending in a third direction (D3) 811 in a three-dimensional (3D) memory.

[0078] Fig. 9A Shows how Figure 1-3 An example method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process is presented in and in accordance with many embodiments of the present disclosure. Fig. 9A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Fig. 9A In an example embodiment of the present invention, the method includes patterning photolithography masks 935, 936, and / or 937 using a photolithography process, such as Figures 6A-6E 635, 636 and / or 637 in . Fig. 9A The method further illustrates using one or more etching processes to form a storage node region 950 (and Fig. 8A and 8C A vertical opening 951 is formed in the vertical stack 844 and extends primarily in the first horizontal direction (D1) 909. The one or more etching processes form the vertical opening 951 to be adjacent to the second region of the sacrificial semiconductor material. Figure 9B-9E The second sidewall is exposed in the vertical stack shown in repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-N and sacrificial semiconductor material 932-1, 932-2, ..., 932-N. Other listed components may be similar to those shown and discussed in connection with FIG. 6 or earlier figures.

[0079] According to an embodiment, a second region 944 of sacrificial semiconductor material 932-1, 932-2, ..., 932-N can be removed from repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-N and sacrificial semiconductor material 932-1, 932-2, ..., 932-N in a vertical stack to form a storage node. According to an embodiment, this process is performed after selectively removing the first source / drain region, the channel region, and the second source / drain region of the sacrificial semiconductor material in which the horizontally oriented access device is formed. According to an embodiment, selectively etching the second region 944 can include performing an atomic layer etching (ALE) process that is selective to the sacrificial semiconductor material 932-1, 932-2, ..., 932-N in the second region 944.

[0080] according to Figure 9B-9E In the example embodiment shown in , the method includes selectively etching the second region 944 of the sacrificial semiconductor material 932-1, 932-2, ..., 932-N to form a second horizontal opening 957 (D2 opening) in the vertical stack at a second horizontal distance backward from the vertical opening 951. In some embodiments, as Figure 9B-9E As shown, the method includes forming a capacitor cell as a storage node in the second horizontal opening. By way of example and not limitation, forming the capacitor includes sequentially depositing a first electrode 961 and a second electrode 956 separated by a cell dielectric 963 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0081] Fig. 9B Shown along Fig. 9A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig. 9B The cross-sectional view shown in is away from a plurality of individual vertical access lines 940-1, 940-2, ..., 940-N, 940-(N+1), ..., 940-(Z-1), and shows repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-(N+1) separated by horizontally oriented capacitor cells on a semiconductor substrate 900 to form a vertical stack, the horizontally oriented capacitor cells having a first electrode 961, such as a bottom cell contact electrode, a cell dielectric 963, and a second electrode 956, such as a top common node electrode. Fig. 9B As shown, the vertical direction 911 is shown as Figure 1-3The third direction (D3) 111 of the first direction, the second direction, and the third direction shown in FIG. 1 is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The plane of the drawing extending from right to left is in the first direction (D1) 909. Fig. 9B In an example embodiment of the present invention, a first electrode 961, e.g., a bottom electrode, is in direct electrical ohmic contact with the source / drain regions of the horizontal access device (formed using the same process as the etch stop), and a second electrode 956 is shown as being separated by a cell dielectric 963 that extends into and out of the plane of the drawing in a second direction (D2) and along an axis toward the horizontal access devices and horizontal storage nodes of a vertically stacked array of memory cells of a three-dimensional (3D) memory.

[0082] The first electrode and the second electrode may be formed of any suitable conductive material, such as doped polysilicon, metals such as titanium (Ti), tungsten (W), etc., and / or conductive metal compositions such as titanium nitride (TiN), tantalum nitride (TaN), etc. Embodiments are not limited to these examples. In various embodiments, the cell dielectric 963 may be a high-k dielectric material and may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobium ore, etc. Embodiments are not limited to these examples.

[0083] Fig. 9C Shown along Fig. 9A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig. 9C The cross-sectional view shown in FIG. 1 is shown extending from left to right along the plane of the drawing sheet in a second direction (D2) 905 along an axis of repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-(N+1), horizontally oriented access devices 998 and integrally formed digit lines 999 in region 942, and subsequently formed storage nodes, such as capacitor cells, formed in region 944. Fig. 9CIn an example embodiment of a horizontally oriented storage node, such as a capacitor cell, is shown as having been formed in this semiconductor manufacturing process, and a first electrode 961, such as a bottom electrode, to be coupled to a source / drain region of a horizontal access device, and a second electrode 956, such as a top electrode, to be coupled to a common electrode plane, such as a ground plane, separated by a cell dielectric 963 are shown. According to an embodiment, after forming a first source / drain region, a channel region, and a second source / drain region in the region of a horizontally oriented access device 998, a first electrode 961, such as a bottom electrode, to be coupled to a source / drain region of a horizontal access device, and a second electrode 956, such as a top electrode, to be coupled to a common electrode plane, such as a ground plane, separated by a cell dielectric 963 are formed.

[0084] exist Fig. 9C In an example embodiment of, a horizontally oriented storage node is shown having a first electrode 961, e.g., a bottom electrode, to be coupled to a source / drain region of a horizontal access device and a second electrode 956, e.g., a top electrode, to be coupled to a common electrode plane such as a ground plane, wherein the first electrode and the second electrode are formed in a second horizontal opening, the second horizontal opening extending in a second direction (D2) from left to right in the plane of the drawing sheet, a second distance 957 (D2 opening) from the vertical opening 951 formed in the vertical stack and along an axis toward the horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory. Fig. 9C , adjacent relative vertical access line 940-3 is shown by a dashed line indicating a location set inwardly from the plane of the drawing and in an orientation.

[0085] Fig.9D Shown along Fig. 9A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.9D The cross-sectional view shown in is shown extending in a second direction (D2) 905 from left to right in the plane of the drawing along an axis of repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-N, 930-(N+1) and sacrificial semiconductor material 932-1, 932-2, ..., 932-N outside of a region in which horizontally oriented access devices and horizontally oriented storage nodes such as capacitor cells are formed. Fig. 9C , dielectric material 941 is shown filling spaces between horizontally oriented access devices of a three-dimensional array of vertically oriented memory cells, which spaces may be horizontally spaced along a first direction (D1) extending into and out of the plane of the drawing. Fig.9DIn the cross-sectional view of FIG. 1 , the second electrode 956 of the capacitor cell structure, e.g., the top common electrode, is shown as existing in the space between horizontally adjacent devices. Repeated iterations of alternating layers of dielectric material layers 930-1, 930-2, ..., 930-(N+1) and integrally formed horizontally oriented digit lines 999 are shown at the left end of the drawing, extending into and out of the plane of the drawing and connecting to source / drain regions of horizontally oriented access devices.

[0086] Fig.9E Shown along Fig. 9A A cross-sectional view taken along the cutting line D-D' in FIG. 1 shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. The drawings are shown from right to left in the plane of the drawing. Fig.9E , which is a cross-sectional view along the dielectric material 930-1, 930-2, ..., 930-(N+1) and the channel region of the horizontally oriented access device 998, such as Fig. 9C The axis of the repeated iterations of alternating layers of 998-1B extends in a first direction (D1) 909, extending into and out of the plane of the drawing sheet and intersecting a plurality of individual vertical access lines 940-1, 940-2, ..., 940-4 separated from the channel region by gate dielectric material 938. Fig.9E , a first dielectric fill material 939 is shown as separating spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which can be formed to extend into and out of the plane of the drawing and can be separated along a first direction (D1) 909 and vertically stacked into an array extending in a third direction (D3) 911 in a three-dimensional (3D) memory.

[0087] Fig.10 A three-node horizontally oriented access device 1042 is shown coupled to horizontally oriented storage nodes 1044 for vertical three-dimensional (3D) memory in accordance with an embodiment of the present disclosure. Fig.10 , a three-node horizontally oriented access device 1042 is shown extending in a second direction (D2) 1005 from left to right in the plane of the drawing. The horizontally oriented access device 1042 is shown as having a first source / drain region 1098-1A in electrical contact with a horizontally oriented storage node 1044, such as a first electrode 1061, such as a bottom electrode of a capacitor cell. The storage node 1044 is further shown as having a dielectric material 1063 separating the first electrode 1061 from a second electrode 1056, such as a top common node electrode of the capacitor cell.

[0088] 1A. A vertically oriented access line 1040-3 is opposite to the channel region 1098-1B and is separated from the channel region by a gate dielectric. The vertically oriented access line 1040-2 is shown by dashed lines indicating that the vertically oriented access line is set into the plane of the drawing and / or is set out from the plane of the drawing. According to specific design rules, the vertically oriented access line 1040 can extend longer and / or shorter than the channel region in the second direction (D2) 1005, for example, to have source / drain over-overlap and / or under-overlap.

[0089] Second source / drain region 1098-1C is shown in electrical contact with channel region 1098-1B and in electrical contact with and integral to horizontally-oriented digit line 1099 extending into and out of the plane of the drawing. Fig.10 As shown, the horizontally-oriented access device 1042 and the horizontally-oriented storage node 1044 can be horizontally separated from adjacent memory cells along the second direction (D2) 1005 by the interlayer dielectric material 1080, and can be vertically separated from stacked adjacent cells in a three-dimensional (3D) memory by dielectric layers 1030-1 and 1030-2.

[0090] Fig.11 1 is a block diagram of an apparatus in the form of a computing system 1100 including a memory device 1103 according to many embodiments of the present disclosure. As used herein, for example, the memory device 1103, the memory array 1110, and / or the host 1102 may also be considered as a "device", respectively. According to an embodiment, as has been described herein, the memory device 1102 may include at least one memory array 1110 having a three-node access device for vertical three-dimensional (3D) memory.

[0091] In this example, the system 1100 includes a host 1102 coupled to a memory device 103 via an interface 1104. In various other types of systems, the computing system 1100 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or an Internet of Things (IoT) enabled device. The host 1102 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that can access the memory 1103. The system 1100 may include separate integrated circuits, or both the host 1102 and the memory device 1103 may be located on the same integrated circuit. For example, the host 1102 may be a system controller of a memory system including a plurality of memory devices 1103, wherein the system controller 1105 provides access to the respective memory devices 1103 through another processing resource such as a central processing unit (CPU).

[0092] exist Figure 1 In the illustrated example, the host 1102 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that may be loaded into the OS (e.g., from the memory device 1103 via the controller 1105). The OS and / or various applications may be loaded from the memory device 1103 by providing access commands from the host 1102 to the memory device 1103 to access data comprising the OS and / or various applications. The host 1102 may also access data utilized by the OS and / or various applications by providing access commands to the memory device 1103 to retrieve the data utilized in the execution of the OS and / or various applications.

[0093] For clarity, system 1100 has been simplified to focus on features that are particularly relevant to the present disclosure. Memory array 1110 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NAND flash array, including at least one three-node access device of a three-dimensional (3D) memory. For example, memory array 1110 may be an unshielded DL 4F2 array such as a 3D-DRAM memory array. Array 1110 may include memory cells arranged into rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digit lines (which may be referred to herein as readout lines or data lines). Although in Figure 1 A single array 1110 is shown in FIG. 1 , but the embodiment is not limited thereto. For example, the memory device 1103 may include many arrays 1110 (eg, many DRAM cell banks).

[0094] The memory device 1103 includes an address circuit system 1106 for latching an address signal provided through the interface 1104. The interface may include, for example, a physical interface (e.g., a data bus, an address bus, and a command bus or a combined data / address / command bus) using a suitable protocol. Such a protocol may be customized or proprietary, or the interface 1104 may use a standardized protocol such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. The address signal is received and decoded by a row decoder 1108 and a column decoder 1112 to access the memory array 1110. Data can be read from the memory array 1110 by sensing the voltage and / or current changes on the sense line using the sense circuit system 1111. The sense circuit system 1111 may include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 1110. The I / O circuit system 1107 may be used to communicate bidirectional data with the host 1102 through the interface 1104. The read / write circuitry 1113 is used to write data to or read data from the memory array 1110. As examples, the circuitry 1113 may include various drivers, latch circuitry, and the like.

[0095] The control circuit system 1105 decodes the signals provided by the host 1102. The signals may be commands provided by the host 1102. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 1110, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuit system 1105 is responsible for executing instructions from the host 1102. The control circuit system 1105 may include a state machine, a sequencer, and / or some other type of control circuit system, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. In some instances, the host 1102 may be a controller external to the memory device 103. For example, the host 1102 may be a memory controller coupled to a processing resource of a computing device.

[0096] The term semiconductor may refer to, for example, a material, a wafer, or a substrate and includes any base semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, and other semiconductor structures. In addition, when reference is made to a semiconductor in the foregoing description, regions / junctions may have been formed in the base semiconductor structure using previous process steps, and the term semiconductor may include the underlying material containing such regions / junctions.

[0097] Figures herein follow numbering conventions, wherein one or more first digits correspond to the figure numbers, and the remaining digits identify elements or components in the drawings. Similar (e.g., identical) elements or components between different figures can be identified by using similar numerals. As should be understood, the elements shown in the various embodiments herein can be added, exchanged and / or eliminated to provide many other embodiments of the present disclosure. In addition, as should be understood, the ratio and / or relative scale of the elements provided in the drawings are intended to display embodiments of the present disclosure and should not be adopted in a limiting sense.

[0098] As used herein, "many" or "a certain amount" of something may refer to one or more of such things. For example, many or a certain amount of memory cells may refer to one or more memory cells. "Multiple" something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term "coupling" may include electrically coupling, directly coupling and / or directly connecting (e.g., by direct physical contact), indirectly coupling and / or connecting to an intermediate element, or wirelessly coupling without an intermediate element. The term "coupling" may further include two or more elements that cooperate or interact with each other (e.g., as in a cause-and-effect relationship). An element coupled between two elements may be located between the two elements and coupled to each of the two elements.

[0099] It should be appreciated that the term vertical explains variations in "exact" vertical due to conventional manufacturing, measurement and / or assembly variations, and that one of ordinary skill in the art should understand what the term "vertical" means. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent to another element," the particular element may cover the other element, may be located above the other element or lateral to the other element, and / or may be in direct physical contact with the other element. For example, lateral to may refer to a horizontal direction (e.g., a y-direction or an x-direction) that may be perpendicular to the z-direction.

[0100] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover the adaptation or variation of the various embodiments of the present disclosure. It should be understood that the above description is carried out in an illustrative manner rather than a restrictive manner. Reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those of skill in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims together with the full scope of equivalents to which such claims are assigned.

Claims

1. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, the method include: depositing alternating layers of dielectric material (430, 630, 730, 830, 930, 1030) and sacrificial material (432, 632, 732, 832, 932) to form a vertical stack (401); forming a plurality of first vertical openings (771, 871) through the vertical stack (401), the plurality of first vertical openings having a first horizontal direction (509, 609, 709, 809, 909) and a second horizontal direction (505, 605, 705, 805, 905, 1005) and extending primarily in the second horizontal direction (505, 605, 705, 805, 905, 1005) to form elongated vertical columns (513, 542, 642) having sidewalls (514) in the vertical stack (401); conformally depositing a first conductive material (540) on a gate dielectric material (538, 638, 738, 838, 938) in the first vertical opening (771, 871); removing portions of the first conductive material (540) to form a plurality of separate vertical access lines (103, 203, 303, 640, 740, 840, 940, 1040) along the sidewalls (514) of the elongated vertical columns (513, 542, 642); forming a second vertical opening through the vertical stack (401), the second vertical opening extending primarily in a first horizontal direction (509, 609, 709, 809, 909) to expose a first region (742, 842) of the sacrificial material (432, 632, 732, 832, 932); selectively removing the first region (742, 842) to form a first horizontal opening (733) in the sacrificial material (432, 632, 732, 832, 932), in which a first source / drain material (221, 321, 898-1A, 1098-1A), a channel material (223, 323, 898-1B, 1098-1B) and a second source / drain material (225, 325, 898-1C, 1098-1C) of a horizontally oriented three-node access device (230, 330, 898, 998) are formed; forming a third vertical opening through the vertical stack (401), the third vertical opening extending primarily in the first horizontal direction (509, 609, 709, 809, 909) to expose a second region (744, 844, 944) of the sacrificial material (432, 632, 732, 832, 932); After forming the three-node access device (230, 330, 898, 998) in the first region (742, 842), the second region (744, 844, 944) is selectively removed to form a second horizontal opening in the sacrificial material (432, 632, 732, 832, 932), in which a second horizontal opening for a storage node (227, 1044) electrically coupled to the first source / drain material (221, 321, 898-1A, 1098-1A) is formed.

2. The method according to claim 1, further comprising: include: selectively removing the first region at a first horizontal distance (D1) (751) from the second vertical opening; as well as Before selectively removing the second region, an atomic layer deposition ALD process is used to sequentially deposit: the first source / drain material of the three-node access device; the channel material; and The second source / drain material. 3 . The method of claim 1 , further comprising depositing multiple layers of source / drain material in the first horizontal opening to form an electrical contact with the storage node at a distal end of the first horizontal opening relative to the second vertical opening.

4. The method of any one of claims 1 to 3, further comprising depositing as part of the first source / drain material a first conductive metal material that does not oxidize when in contact with an oxide semiconductor channel material. The method of claim 4 , wherein depositing the first conductive material comprises depositing a material containing ruthenium (Ru).

6. The method of any one of claims 1 to 3, further comprising depositing a first conductive material comprising a metallic material that forms a conductive oxide when in contact with an oxide semiconductor channel material as a portion of the first source / drain material.

7. The method of claim 6, wherein depositing the first conductive material comprises depositing indium tin oxide (InSnO x )Material.

8. The method according to any one of claims 1 to 3, further comprising: include: After forming the three-node access device, selectively removing the second region at a second horizontal distance (D2) (957) from the third vertical opening to reach the first metal conductive material; as well as Selective etching that is selective to etching the sacrificial oxide semiconductor material and selective to not etching the first metal conductive material is performed to remove the second region.

9. The method of claim 8, further comprising selectively depositing in the second horizontal opening: a first electrode (961) in ohmic contact with the first conductive metal material; A cell dielectric (963) is on the first electrode (961); and A second electrode (956) is formed on the cell dielectric (963) to form a capacitor cell in the second horizontal opening as the storage node.

10. The method of any one of claims 1-3, further comprising integrating a horizontally oriented digit line (107, 207, 307, 899, 999, 1099) to make electrical contact with the second source / drain material.

11. A method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method include: depositing alternating layers of dielectric material (430, 630, 730, 830, 930, 1030) and sacrificial material (432, 632, 732, 832, 932) to form a vertical stack (401); forming a plurality of first vertical openings (771, 871) through the vertical stack (401), the plurality of first vertical openings having a first horizontal direction (509, 609, 709, 809, 909) and a second horizontal direction (505, 605, 705, 805, 905, 1005) and extending primarily in the second horizontal direction (505, 605, 705, 805, 905, 1005) to form elongated vertical columns (513, 542, 642) having sidewalls (514) in the vertical stack (401); conformally depositing a first conductive material (540) on a gate dielectric material (538, 638, 738, 838, 938) in the first vertical opening (771, 871); removing portions of the first conductive material (540) to form a plurality of separate vertical access lines (103, 203, 303, 640, 740, 840, 940, 1040) along the sidewalls (514) of the elongated vertical columns (513, 542, 642); forming a second vertical opening through the vertical stack (401) and extending primarily in the first horizontal direction (509, 609, 709, 809, 909) to expose a first region (742, 842) of the sacrificial material (432, 632, 732, 832, 932); selectively removing the first region (742, 842) to form a first horizontal opening (733) in the sacrificial material (432, 632, 732, 832, 932) extending a first distance (D1) (751) from the second vertical opening; sequentially depositing a first source / drain material (221, 321, 898-1A, 1098-1A), a channel material (223, 323, 898-1B, 1098-1B), and a second source / drain material (225, 325, 898-1C, 1098-1C) in the first horizontal opening (733) using an atomic layer deposition (ALD) process to form a horizontally oriented three-node access device (230, 330, 898, 998) without a body contact; forming a third vertical opening through the vertical stack (401) and extending primarily in the first horizontal direction (509, 609, 709, 809, 909) to expose a second region (744, 844, 944) of the sacrificial material (432, 632, 732, 832, 932); selectively removing the second region (744, 844, 944) to form a second horizontal opening in the sacrificial material (432, 632, 732, 832, 932) extending a second distance (D2) (957) from the second vertical opening; as well as After forming the horizontally oriented three-node access device (230, 330, 898, 998), an atomic layer deposition (ALD) process is used to sequentially deposit: A first electrode (961) electrically connected to the first source / drain material (221, 321, 898-1A, 1098-1A); A high-k dielectric material is on the first electrode (961); and A second electrode (956) is on the high-k dielectric material.

12. The method of claim 11, further comprising depositing a two-dimensional (2D) material comprising one or more of transition metal dichalcogenides as the channel material.

13. The method of claim 11, further comprising depositing a degenerate semiconductor material as the first source / drain material.

14. The method of any one of claims 11 to 13, further comprising depositing a multilayer first source / drain material having a first semiconductor material and a second semiconductor material, wherein the second semiconductor material has an electronic band gap between an electronic band gap of the first semiconductor material and an electronic band gap of the channel material.

15. The method of any one of claims 11 to 13, further comprising using the first source / drain material as an etch stop material while performing the selective etch to remove the second region.

16. A method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method include: depositing alternating layers of dielectric material (430, 630, 730, 830, 930, 1030) and sacrificial material (432, 632, 732, 832, 932) to form a vertical stack (401); forming a plurality of first vertical openings (771, 871) through the vertical stack (401), the plurality of first vertical openings having a first horizontal direction (509, 609, 709, 809, 909) and a second horizontal direction (505, 605, 705, 805, 905, 1005) and extending primarily in the second horizontal direction (505, 605, 705, 805, 905, 1005) to form elongated vertical columns (513, 542, 642) having sidewalls (514) in the vertical stack (401); conformally depositing a first conductive material (540) on a gate dielectric material (538, 638, 738, 838, 938) in the first vertical opening (771, 871); removing portions of the first conductive material (540) to form a plurality of separate vertical access lines (103, 203, 303, 640, 740, 840, 940, 1040) along the sidewalls (514) of the elongated vertical columns (513, 542, 642); forming a second vertical opening through the vertical stack (401) and extending primarily in the first horizontal direction (509, 609, 709, 809, 909) to expose a first region (742, 842) of the sacrificial material (432, 632, 732, 832, 932); selectively removing the first region (742, 842) to form a first horizontal opening (733) in the sacrificial material (432, 632, 732, 832, 932); sequentially forming a first source / drain material (221, 321, 898-1A, 1098-1A), a channel material (223, 323, 898-1B, 1098-1B), and a second source / drain material (225, 325, 898-1C, 1098-1C) in the first horizontal opening (733) to form a horizontally oriented three-node access device (230, 330, 898, 998) without a body contact, wherein the first source / drain material (221, 321, 898-1A, 1098-1A) is selected to provide an ohmic contact to a first electrode (961) of a storage node (227, 1044); forming a third vertical opening through the vertical stack (401) and extending primarily in the first horizontal direction (509, 609, 709, 809, 909) to expose a second region (744, 844, 944) of the sacrificial material (432, 632, 732, 832, 932); After forming the horizontally oriented access device (230, 330, 898, 998), selectively removing the second region (744, 844, 944) using the source / drain conductive material as an etch stop material to form a second horizontal opening in the sacrificial material (432, 632, 732, 832, 932) extending to the first source / drain material (221, 321, 898-1A, 1098-1A); as well as The first electrode (961) of the storage node (227, 1044) is selectively deposited on the first source / drain material (221, 321, 898-1A, 1098-1A) in the second horizontal opening to form direct electrical contact therewith.

17. The method of claim 16, further comprising, after forming the horizontally-oriented access device, selectively depositing: A high-k dielectric material is on the first electrode (961); and A second electrode (956) is formed on the high-k dielectric material to form a horizontally oriented capacitor cell as the storage node.

18. The method of claim 16, further comprising forming a horizontally-oriented storage node with the first electrode such that the horizontally-oriented storage node (227, 1044) is on the same planar level as the first source / drain material in the vertical stack.

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