Fan-out package structure with frame and manufacturing method thereof
By using a frame fan-out packaging structure, the problems of high-density BGA packaging and circuit fan-out in wafer-level packaging are solved, achieving high-density packaging and reducing costs.
Patent Information
- Application Number
- CN202111354580.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-16
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2041-11-16
AI Technical Summary
Existing wafer-level packaging cannot achieve high-density BGA packaging due to chip area limitations. Fan-out wafer-level packaging is difficult to fan out due to wafer warping caused by chip reconstruction and molding, and FCBGA packaging is expensive.
The chip adopts a frame fan-out packaging structure. By setting a frame on the chip and connecting it to the redistribution layer, the chip pins are fanned outward using the frame, and electrical connections are achieved through BGA solder balls. The chip and frame are then encapsulated by a molding compound to form a high-density package.
High-density BGA packaging was achieved, avoiding the difficulties in circuit fan-out caused by wafer warping and reducing manufacturing costs.
Smart Images
Figure CN114068443B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a framed fan-out packaging structure and its manufacturing method. Background Technology
[0002] As electronic devices become increasingly integrated and electronic products move towards lighter and smaller designs, IC chip packaging is also trending towards thinner and smaller sizes, placing increasingly higher demands on packaging technology. Common packaging technologies include wafer-level packaging (WLP), fan-out WLP, and FCBGA packaging. Wafer-level packaging, due to its advantages such as high density, small size, high reliability, and excellent electrothermal performance, perfectly meets the requirements of packaging processes and has gradually become one of the most important packaging forms. However, due to its high I / O density, wafer-level packaging lacks sufficient chip area to achieve high-density BGA packaging. Fan-out WLP is an embedded packaging technology using wafer-level processing. Fan-out WLP technology typically involves cutting individual microchips from a wafer and embedding them onto a new "artificial" wafer. Currently, fan-out packaging using plastic encapsulation processes faces significant challenges in controlling wafer warpage, as chip refactoring and wafer warpage both hinder circuit fan-out. FCBGA packaging, also known as flip-chip ball grid array packaging, is the most common packaging format for graphics accelerator chips. However, FCBGA packaging is expensive, and as the size of the packaged chip gradually increases, the cost of the packaging substrate increases exponentially.
[0003] To address the limitations of existing wafer-level packaging in achieving high-density BGA packaging due to chip area constraints, and the difficulties in fan-out circuitry caused by wafer warpage resulting from chip reconstruction and molding, a new design approach and solution are needed. Summary of the Invention
[0004] Based on existing technology, the objective of this invention is to provide a framed fan-out packaging structure and its manufacturing method, which achieves high-density BGA packaging by fanning out pins through the frame, avoiding the problem of difficult circuit fan-out caused by wafer warping due to chip reconstruction and molding in traditional fan-out wafer-level packaging.
[0005] In a first aspect, addressing the problems existing in the prior art, the present invention provides a framed fan-out packaging structure, comprising:
[0006] chip;
[0007] Pins, located on the front side of the chip;
[0008] A first insulating layer covers the chip;
[0009] a redistribution layer disposed above the first insulating layer and electrically connected to the pins through a via in the first insulating layer;
[0010] a second insulating layer covering the redistribution layer, at least a part of a peripheral area of the redistribution layer not being covered by the second insulating layer;
[0011] a frame connected to at least a part of the peripheral area of the redistribution layer by soldering;
[0012] a plastic encapsulation layer encapsulating the chip and the frame to form a plastic encapsulation body; and
[0013] BGA solder balls electrically connected to the pads on the second insulating layer and the frame.
[0014] In a preferred embodiment of the present application, the pads on the second insulating layer comprise an under bump metallization layer electrically connected to the redistribution layer through a via in the second insulating layer.
[0015] A metal protection layer covers the redistribution layer and the under bump metallization layer.
[0016] In another preferred embodiment of the present application, a part of the pins are fanned out by the frame and electrically connected to the pads on the frame, and another part of the pins are implemented as BGA packaging through the redistribution layer and the under bump metallization layer.
[0017] In yet another preferred embodiment of the present application, the frame is arranged around the front face of the chip to fan out the pins on the front face of the chip outward.
[0018] In another preferred embodiment of the present application, the first insulating layer and the second insulating layer are organic resin or inorganic material.
[0019] In a second aspect of the present application, to solve the problems in the prior art, the present application provides a manufacturing method of a fan-out packaging structure with a frame, comprising:
[0020] forming a first insulating layer on the front face of the chip and removing the first insulating layer at positions corresponding to the pins by photolithography to form vias;
[0021] forming a redistribution layer electrically connected to the pins through the vias;
[0022] forming a second insulating layer covering the redistribution layer, then removing part of the second insulating layer by photolithography to expose at least a part of a peripheral area of the redistribution layer and form vias in the second insulating layer;
[0023] forming pads on the second insulating layer, the pads being electrically connected to the redistribution layer through conductive vias formed in the second insulating layer.
[0024] thinning the chip wafer and cutting the chip wafer into single chips;
[0025] soldering the single chips to a first surface of a frame, the frame being connected to at least a partial peripheral area of the redistribution layer, a second surface of the frame having solder pads;
[0026] forming a plastic encapsulation layer wrapping the single chips and the frame, the solder pads on the second insulating layer and the solder pads on the frame being exposed from the plastic encapsulation layer; and
[0027] balling the solder pads on the second insulating layer and the solder pads on the frame.
[0028] In a preferred embodiment of the present application, the method for forming the first insulating layer and the second insulating layer comprises spraying or vapor deposition.
[0029] In another preferred embodiment of the present application, when forming the redistribution layer, a seed layer is first deposited, the seed layer being made of Ti / Cu composite material or Al, then a circuit is photoetched, and Cu or Al is deposited to form the redistribution layer.
[0030] In yet another preferred embodiment of the present application, the solder pads on the second insulating layer are under bump metallization layers, which are electrically connected to the redistribution layer through through holes in the second insulating layer.
[0031] a metal protection layer covering the redistribution layer and the under bump metallization layers.
[0032] In another preferred embodiment of the present application, the exposed parts of the redistribution layer and the under bump metallization layers are subjected to electroless Ni plating or Au plating or Pd plating to form a metal protection layer.
[0033] The present application has at least the following advantages: the present application proposes a frame-equipped fan-out packaging structure and a method for forming the same, which adopts a frame fan-out pin mode to realize high-density BGA packaging, and avoids the problem of fan-out difficulty of a circuit caused by wafer warping due to chip reconstruction and plastic encapsulation in traditional fan-out wafer-level packaging, and has low manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS
[0034] The present application will be further described below with reference to the embodiments and the accompanying drawings.
[0035] Figure 1 Fig. 1 shows a cross-sectional schematic view of a frame-equipped fan-out packaging structure 100 according to the present application.
[0036] Figures 2A to 2I Fig. 2 shows a process cross-sectional schematic view of forming the frame-equipped fan-out packaging structure 100 according to the present application. DETAILED DESCRIPTION
[0037] It should be noted that the components in the various figures could be shown exaggerated in scale for illustrative purposes and are not necessarily drawn to scale. In the various figures, the same or similar components are denoted by the same reference numerals.
[0038] In the present disclosure, the embodiments are merely intended to illustrate the solutions of the present disclosure and should not be understood as limiting.
[0039] In the present disclosure, the quantifier "one", "a" does not exclude the scenario of multiple elements unless specifically indicated.
[0040] It should also be noted here that in the embodiments of the present disclosure, only a part of the components or assemblies could be shown for the sake of clarity and simplicity, but those skilled in the art could understand that the required components or assemblies could be added according to the specific scenario under the teaching of the present disclosure.
[0041] It should also be noted here that in the scope of the present disclosure, the words "same", "equal", "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the words also cover "substantially the same", "substantially equal", "substantially equal to".
[0042] It should also be noted here that in the description of the present disclosure, the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and are not meant to imply or suggest that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure. In addition, the terms "first", "second" are only for the purpose of description and cannot be understood as implying or suggesting relative importance.
[0043] In addition, the embodiments of the present disclosure describe the process steps in a specific order, however this is only for the convenience of distinguishing the steps and is not limited to the order of the steps, and in different embodiments of the present disclosure, the order of the steps could be adjusted according to the adjustment of the process.
[0044] Figure 1 A cross-sectional schematic view of a fan-out package structure 100 with a frame according to an embodiment of the present disclosure is shown.
[0045] As Figure 1As shown, the frame-equipped fan-out package structure 100 includes a chip 101, pins 102, a first insulating layer 103, a rewiring layer 105, a second insulating layer 106, an under bump metallization layer 107, a metal protection layer 108, a frame 109, a plastic encapsulation layer 110, and BGA solder balls 111.
[0046] The chip 101 can be a logic chip such as a CPU, a DSP, a GPU, an FPGA, etc., a memory chip such as a DRAM, a Flash, etc., or other types of chips such as a SOC, or a sensor such as a MEMS sensor, etc.
[0047] The pins 102 are on the front side of the chip 101. The pins 102 are divided into two types. One type is a pin that needs to be fanned out by the frame 109, and is usually distributed on the edge of the chip 101. The other type is a pin that does not need to be fanned out by the frame 109, and is usually distributed on the inner side of the chip 101. The pin of the chip that does not need to be fanned out by the frame 109 is implemented as a BGA package through the rewiring layer 105 and the under bump metallization layer 107.
[0048] The first insulating layer 103 is arranged on the chip 101.
[0049] The rewiring layer 105 is arranged above the first insulating layer 103 and is electrically connected to the pins 102 through a via (not shown) in the first insulating layer 103.
[0050] The second insulating layer 106 is arranged on the rewiring layer 105, and at least part of the peripheral region of the rewiring layer 105 is not covered by the second insulating layer 106.
[0051] The under bump metallization layer 107 is arranged above the second insulating layer 106 and is electrically connected to the rewiring layer 105 through a via (not shown), thereby achieving electrical connection with the pin of the chip 101 that does not need to be fanned out by the frame 109 on the inner side.
[0052] The metal protection layer 108 is arranged on the rewiring layer 105 and the under bump metallization layer 107 to achieve oxidation resistance protection. The material of the metal protection layer can be a metal such as Ni, Au, Pd, etc.
[0053] The frame 109 is connected to the rewiring layer 105 by welding. The frame 109 is usually made of a metal material. The first face (upper surface) of the frame 109 has pads for placing the BGA solder balls 111. The second face (lower surface) of the frame 109 has welding points for welding with the rewiring layer 105. The frame 109 is arranged around the front side of the chip 101, thereby fanning out the pins on the front side of the chip 101 outward.
[0054] The plastic encapsulation layer 110 encapsulates the chip 101 and the frame 109 to form a plastic encapsulation body. The material of the plastic encapsulation layer 110 can be a conventional plastic encapsulation material such as resin, or a specially modified plastic encapsulation material having a specific stress relative to the chip 101.
[0055] The BGA solder balls 111 are electrically connected to the metal wiring layer 105 and the under bump metallization layer 107, and serve as the electrical and / or signal connection between the package structure and an external system.
[0056] Figures 2A to 2I Fig. 6 shows a process cross-sectional view of manufacturing the fan-out package structure 100 with a frame according to the present application.
[0057] In step 1, a chip wafer 120 to be processed is provided.
[0058] In step 2, as shown in Fig. 2, a first insulating layer 103 is formed on the front side of the chip wafer 120, and then the first insulating layer is removed by photolithography at the positions corresponding to the pins 102 to form the through holes 104. The first insulating layer can be an organic resin or an inorganic material, and the manufacturing method includes spraying, vapor deposition, etc. Figure 2A
[0059] In step 3, as shown in Fig. 3, a redistribution layer 105 is formed to electrically connect the through holes 104 in the first insulating layer 103 and the pins 102. When the redistribution layer 105 is manufactured, a seed layer is first deposited, the seed layer is made of Ti / Cu composite material or Al, then the circuit is photolithographed, and then Cu or Al is deposited to form the redistribution layer. Figure 2B
[0060] In step 4, as shown in Fig. 4, a second insulating layer 106 is formed to cover the redistribution layer 105, and then part of the second insulating layer is removed by photolithography to expose the redistribution layer 105 to be soldered to the frame 109 and to form the through holes 104 at the positions corresponding to the redistribution layer 105 to be electrically connected to the under bump metallization layer. The second insulating layer 106 can be an organic resin or an inorganic material, and the manufacturing method includes spraying, vapor deposition, etc. Figure 2C
[0061] In step 5, as shown in Fig. 5, an under bump metallization layer 107 is formed to electrically connect the through holes in the second insulating layer 106 and the redistribution layer 105. The process of manufacturing the under bump metallization layer 107 is the same as that of manufacturing the redistribution layer 105. Figure 2D
[0062] In step 6, as shown in Fig. 6, chemical plating Ni or Au or Pd is performed on the exposed parts of the redistribution layer 105 and the under bump metallization layer 107 to form a metal protective layer. Figure 2E
[0063] In step 7, as shown in Fig. 7, the frame 109 is soldered to the redistribution layer 105, and then the chip wafer 120 is cut to form the fan-out package structure 100 with a frame.Figure 2F The chip wafer 101 is thinned and diced into single chips. The method of thinning the chip wafer 101 includes grinding and wet etching. The method of dicing the chip wafer 101 includes mechanical dicing, laser dicing and plasma dicing.
[0064] In step 8, the single chip 120 is soldered with the frame 109. The frame 109 is usually made of metal material. The first surface (upper surface) of the frame 109 is provided with pads for placing the BGA solder balls 111. The second surface (lower surface) of the frame 109 is provided with soldering points for soldering with the redistribution layer 105. The frame 109 is arranged around the front surface of the chip, so as to fan out the pins on the front surface of the chip outward. Figure 2G
[0065] In step 9, as shown in FIG. 9, a plastic encapsulation layer 110 is made to encapsulate the single chip 120 and the frame 109, and the single chip 120 and the frame 109 are encapsulated to form an encapsulation body. Figure 2H
[0066] In step 10, as shown in FIG. 10, the encapsulation body is ball-mounted. The BGA solder balls 111 are arranged on the pads 112, wherein the pads 112 include the pads on the frame 109 and the pads in the under bump metallization layer 107. In the under bump metallization layer, the area to be connected with the BGA solder balls 111 is the pad. Figure 2I
[0067] The present application has at least the following beneficial effects: the present application proposes a fan-out package structure with a frame and a manufacturing method thereof. The frame fan-out pin mode can realize high-density BGA packaging, and avoids the problem of line fan-out difficulty caused by wafer warping due to chip reconstruction and encapsulation in traditional fan-out wafer-level packaging. The manufacturing cost is low.
[0068] Although some embodiments of the present application have been described in the present application, those skilled in the art can understand that these embodiments are only shown as examples. Those skilled in the art can think of numerous variants, alternatives and improvements under the teaching of the present application without going beyond the scope of the present application. The appended claims are intended to define the scope of the present application, and thereby cover the methods and structures within the scope of the claims themselves and their equivalent transformations.
Claims
1. A framed fan-out package structure, comprising: chip; Pins, located on the front side of the chip; A first insulating layer covers the chip; A redistribution layer is disposed above the first insulating layer and is electrically connected to the pin through a through-hole in the first insulating layer; A second insulating layer is provided, which covers the redistribution layer, and at least a portion of the peripheral area of the redistribution layer is not covered by the second insulating layer. A frame is connected to at least a portion of the peripheral area of the redistribution layer by welding; the frame is arranged around the front of the chip to fan out the pins on the front of the chip. A molding layer that encapsulates the chip and the frame to form a molding compound; as well as BGA solder balls, which are electrically connected to the pads on the second insulating layer and the frame.
2. The framed fan-out packaging structure as described in claim 1, characterized in that, The pads on the second insulating layer include a bump under-metallization layer, which is electrically connected to the redistribution layer through vias in the second insulating layer; A metal protective layer covers the redistribution layer and the under-bump metallization layer.
3. The framed fan-out packaging structure as described in claim 2, characterized in that, A portion of the pins are fanned out using the frame and electrically connected to pads on the frame, while another portion of the pins are implemented as a BGA package through the redistribution layer and the under-bump metallization layer.
4. The framed fan-out packaging structure as described in claim 1, characterized in that, The first and second insulating layers are made of organic resin or inorganic materials.
5. A method for manufacturing a framed fan-out package structure, comprising: A first insulating layer is fabricated on the front side of the chip, and a through-hole is formed by photolithography at the position corresponding to the pin. A redistribution layer is fabricated, wherein the redistribution layer is electrically connected to the pins through vias; A second insulating layer is fabricated to cover the redistribution layer, and then a portion of the second insulating layer is removed by photolithography to expose at least a portion of the peripheral area of the redistribution layer, and a via is formed in the second insulating layer; A pad is fabricated on the second insulating layer, and the pad is electrically connected to the redistribution layer through a conductive via formed in the second insulating layer. The chip wafer is thinned and cut into individual chips; A single chip is soldered to a first side of a frame, the frame being connected to at least a portion of the peripheral region of the redistribution layer, and a second side of the frame having pads; the frame is arranged around the front side of the chip to fan out the pins on the front side of the chip. Fabricate a molding compound that encapsulates the individual chip and the frame, with pads on the second insulating layer and the frame exposed from the molding compound; and Balls are placed on the pads on the second insulating layer and the pads on the frame.
6. The method for manufacturing the framed fan-out packaging structure as described in claim 5, characterized in that, Methods for fabricating the first and second insulating layers include spraying and vapor deposition.
7. The method for manufacturing the framed fan-out packaging structure as described in claim 5, characterized in that, When fabricating the redistribution layer, a seed layer is first deposited, which is made of Ti / Cu composite material or Al. Then, the circuit is photolithographically patterned, and Cu or Al is deposited to form the redistribution layer.
8. The method for manufacturing the framed fan-out packaging structure as described in claim 5, characterized in that, The pads on the second insulating layer are under-bump metallization layers, which are electrically connected to the redistribution layer through vias in the second insulating layer; A metal protective layer covers the redistribution layer and the under-bump metallization layer.
9. The method for manufacturing a framed fan-out packaging structure as described in claim 8, characterized in that, Chemical plating of Ni, Au, or Pd is performed on the exposed portions of the redistribution layer and the metallization layer under the bumps to form a protective metal layer.
Citation Information
Patent Citations
Die down ball grid array packages and method for making same
CN1773698A