Flexible circuit board for chip on film and chip package including the same

Abstract

A flexible circuit board for a chip on film according to an embodiment includes a substrate including a first surface and a second surface opposite the first surface and including a chip mounting area, a circuit pattern layer disposed on the first surface, and a heat dissipation portion disposed in the chip mounting area, wherein the substrate is formed with at least two or more holes formed in a region overlapping the heat dissipation portion, and the heat dissipation portion includes a heat dissipation pattern layer disposed on the first surface, a connection layer disposed within the hole, and a heat dissipation layer disposed on the second surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0097337, filed on August 4, 2020, pursuant to 35 USC119 and 35 USC365, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments provide a flexible circuit board for chip-on-film with improved heat dissipation characteristics and a chip package including the flexible circuit board. Background Technology

[0004] Recently, various electronic products have been trending towards thinner, smaller, and lighter designs. Therefore, research is underway on how to densely mount semiconductor chips within the narrow areas of electronic devices.

[0005] Among these methods, the chip-on-film (COF) approach, which uses flexible substrates, can be applied to flat panel displays and flexible displays. Furthermore, the COF approach has attracted attention because it can be used in various wearable electronic devices. Additionally, since the COF approach can achieve fine pixel pitch, it can be used to achieve high-resolution displays (QHD) as the number of pixels increases.

[0006] Chip-on-film (COF) is a method of mounting semiconductor chips in the form of a thin film onto a flexible circuit board. For example, the semiconductor chip can be an integrated circuit (IC) chip or a large-scale integrated circuit (LSI) chip.

[0007] Meanwhile, the chips mounted on the flexible circuit board generate heat while driving the chips, and this heat may cause chip failure and reduce the reliability of the chip package.

[0008] Therefore, in chip packaging that includes flexible circuit boards for chips on film, there is a need for flexible circuit boards for chips on film with a new structure that can reduce the heat generated by the chip. Summary of the Invention

[0009] Technical issues

[0010] The embodiments provide a flexible circuit board for chip-on-film with improved heat dissipation characteristics and a chip package including the flexible circuit board.

[0011] Technical solution

[0012] A flexible circuit board for chip-on-film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface, and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation portion disposed in the chip mounting region, wherein the substrate has at least two or more holes formed in a region overlapping with the heat dissipation portion, and the heat dissipation portion includes: a heat dissipation pattern layer disposed on the first surface; a connecting layer disposed within the holes; and a heat dissipation layer disposed on the second surface.

[0013] Beneficial effects

[0014] According to an embodiment, a flexible substrate for chip-on-film can effectively dissipate heat generated in the chip to the outside through holes formed in the substrate and heat dissipation portions disposed on a first surface, a second surface of the substrate, and within the holes.

[0015] In other words, the heat generated from the chip can be collected by the heat dissipation pattern layer, and the heat can be transferred to the heat dissipation layer through the connectors set in multiple holes to dissipate the heat to the outside.

[0016] In addition, heat can be effectively transferred to the heat dissipation layer by forming multiple heat transfer holes, and the heat dissipation layer is formed with an area corresponding to the chip mounting area, thereby easily dissipating the heat generated from the chip to the outside.

[0017] Therefore, since the flexible substrate for chip-on-film according to the embodiment and the chip package including the flexible substrate have improved heat dissipation characteristics, the reliability and driving characteristics of the chip package can be improved. Attached Figure Description

[0018] Figure 1 This is a top view showing a region of the flexible circuit board according to an embodiment.

[0019] Figure 2 and Figure 3 It shows along Figure 1 A view of the cross section taken by line A-A'.

[0020] Figure 4 This is a top view showing a region of a flexible circuit board according to another embodiment.

[0021] Figure 5 It shows along Figure 4 The view of the cross section taken by line B-B'.

[0022] Figure 6 It shows along Figure 4 A view of the cross section taken by line C-C'.

[0023] Figure 7 This is a top view showing a region of a flexible circuit board according to yet another embodiment.

[0024] Figure 8 It shows along Figure 7 The view of the cross section cut by line D-D'.

[0025] Figures 9 to 15 This is a view of various electronic devices including flexible circuit boards according to embodiments. Detailed Implementation

[0026] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the spirit and scope of the invention are not limited to the portion of the described embodiments and can be implemented in various other forms. Furthermore, within the spirit and scope of the invention, one or more elements of the embodiments may be selectively combined and substituted. Moreover, unless otherwise explicitly defined and described, the terms used in the embodiments of the present invention (including technical and scientific terms) are to be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and terms defined, for example, in common dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art.

[0027] Furthermore, the terminology used in the embodiments of the present invention is for describing embodiments and is not intended to limit the invention. In this specification, unless specifically stated in the phrase, the singular form may also include the plural form, and when described as "at least one (or more) of A, B, and C", it may include at least one of all possible combinations of A, B, and C.

[0028] Furthermore, when describing the elements of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish elements from other elements, and do not limit the nature, order, or sequence of the elements.

[0029] Furthermore, when an element is described as being “connected,” “coupled,” or “joined” to another element, it can include not only cases where the element is directly “connected,” “coupled,” or “joined” to another element, but also cases where the element is “connected,” “coupled,” or “joined” to another element through which the element is connected, coupled, or “joined” to another element.

[0030] Furthermore, when described as being formed or set “above” or “below” each element, “above” or “below” can include not only the case where two elements are directly connected to each other, but also the case where one or more other elements are formed or set between the two elements.

[0031] Furthermore, when expressed as "above" or "below", it can include not only the upward direction based on a component, but also the downward direction based on a component.

[0032] In the following description, a flexible substrate for chip-on-film according to an embodiment will be described with reference to the accompanying drawings.

[0033] Figure 1 This is a top view showing a region of the flexible circuit board according to an embodiment. Figure 2 and Figure 3 It shows along Figure 1 A view of the cross section taken by line A-A'.

[0034] refer to Figures 1 to 3 According to the embodiments, the flexible substrate for chip-on-film may include a substrate 100, a circuit pattern layer 200 disposed on the substrate 100, a protective layer 300, and a heat dissipation portion 400.

[0035] The substrate 100 can support the circuit pattern layer 200, the protective layer 300, and the heat dissipation part 400.

[0036] The substrate 100 may include a first surface 1S and a second surface 2S opposite to the first surface 1S. The first surface 1S of the substrate 100 may support the circuit pattern layer 200 and the protective layer 300. In addition, a heat dissipation portion 400 may be provided on the first surface 1S and the second surface 2S of the substrate 100.

[0037] In other words, the circuit pattern layer 200, the protective layer 300, and the heat dissipation part 400 can be respectively disposed on opposite surfaces of the substrate 100.

[0038] The substrate 100 may include a chip mounting region 1A. Specifically, the protective layer 300 is not disposed on the first surface 1S of the substrate 100, and may include the chip mounting region 1A that exposes the substrate 100 and the circuit pattern layer 200.

[0039] The substrate 100 may include a bent region and a region other than the bent region. That is, the substrate 100 may include a bent region that is bent and a non-bent region other than the bent region.

[0040] Substrate 100 may be a flexible substrate. Therefore, substrate 100 may be partially bent. That is, substrate 100 may include flexible plastic. For example, substrate 100 may be a polyimide (PI) substrate. However, the embodiments are not limited to this, and substrate 100 may be a substrate made of a polymer material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc.

[0041] Therefore, the flexible circuit board including the substrate 100 can be used in various electronic devices having curved display devices. For example, the flexible circuit board including the substrate 100 has excellent flexibility characteristics, thus making it suitable for mounting semiconductor chips on wearable electronic devices. In particular, this embodiment can be applied to electronic devices including curved displays.

[0042] The substrate 100 can be an insulating substrate. That is, the substrate 100 can be an insulating substrate that supports various wiring patterns.

[0043] The substrate 100 can have a thickness of 5 μm to 100 μm. For example, the substrate 100 can have a thickness of 10 μm to 90 μm. For example, the substrate 100 can have a thickness of 12 μm to 80 μm. When the thickness of the substrate 100 exceeds 100 μm, the total thickness of the flexible circuit board may increase. When the thickness of the substrate 100 is less than 5 μm, the substrate 100 may be easily affected by heat / stress during chip mounting.

[0044] Multiple holes h can be formed in the substrate 100. Specifically, the holes h can be formed in the region overlapping with the chip mounting region 1A. Heat generated from the chip mounted in the chip mounting region 1A via the holes h formed in the substrate 100 can be dissipated to the outside via the heat dissipation portion 400 provided on the second surface 2S of the substrate.

[0045] The holes and heat dissipation components will be described in detail below.

[0046] The circuit pattern layer 200 can be disposed on the substrate 100. Specifically, the circuit pattern layer 200 can be disposed on the first surface 1S of the substrate 100. The circuit pattern layer 200 can be a plurality of patterned wirings. For example, the plurality of circuit pattern layers 200 can be configured to be spaced apart from each other on the substrate 100.

[0047] The circuit pattern layer 200 can be connected to the chip 500 disposed in the chip mounting area 1A and external devices. Therefore, communication between the chip 500 and external devices and power supply to the chip 500 can be performed.

[0048] The area of ​​substrate 100 may be larger than the area of ​​circuit pattern layer 200. Specifically, the planar area of ​​substrate 100 may be larger than the planar area of ​​circuit pattern layer 200. That is, the circuit pattern layer substrate 200 may be partially disposed on substrate 100. For example, the lower surface of circuit pattern layer 200 may be in contact with a first surface 1S of substrate 100, and substrate 100 may be exposed between multiple circuit pattern layers. Circuit pattern layer 200 may include a conductive material.

[0049] For example, the circuit pattern layer 200 may include a metallic material with excellent conductivity. More specifically, the circuit pattern layer 200 may include copper (Cu). However, the embodiments are not limited thereto, and may include at least one metal selected from copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti), and alloys thereof.

[0050] The circuit pattern layer 200 can be formed as multiple layers. Specifically, the circuit pattern layer 200 may include a first metal layer 210 and a second metal layer 220.

[0051] The first metal layer 210 may be a seed layer of the circuit pattern layer 200. Specifically, the first metal layer 210 may be a seed layer formed on the first surface 1S of the substrate 100 by chemical plating using a metal material such as copper (Cu).

[0052] Furthermore, the second metal layer 220 can be a plating layer. Specifically, the second metal layer 220 can be a plating layer formed by electroplating using the first metal layer 210 as a seed layer.

[0053] The thickness of the first metal layer 210 can be less than the thickness of the second metal layer 220.

[0054] For example, the thickness of the first metal layer 210 can be from 0.7 μm to 2 μm, and the thickness of the second metal layer 220 can be from 10 μm to 25 μm.

[0055] The first metal layer 210 and the second metal layer 220 may comprise the same metallic material. For example, the first metal layer 210 and the second metal layer 220 may comprise copper (Cu).

[0056] The circuit pattern layer 200 can be configured to have a thickness of 5 μm to 25 μm. For example, the circuit pattern layer 200 can be configured to have a thickness of 10 μm to 20 μm. For example, the circuit pattern layer 200 can have a thickness of 13 μm to 17 μm.

[0057] Since the circuit pattern layer 200 undergoes a process of etching the first metal layer 210 by flash etching to separate the circuit pattern layer during manufacturing, the final manufactured circuit pattern layer 200 can be thinner than the first metal layer 210 and the second metal layer 220.

[0058] When the thickness of the circuit pattern layer 200 is less than 5 μm, the resistance of the circuit pattern layer 200 may increase. When the thickness of the circuit pattern layer 200 exceeds 25 μm, it may be difficult to achieve fine patterns.

[0059] Meanwhile, a buffer layer 250 can be further provided between the substrate 100 and the circuit pattern layer 200. The buffer layer 250 can improve the adhesion between the substrate 100 and the circuit pattern layer 200, which are made of different materials.

[0060] The buffer layer 250 can be formed in multiple layers. Specifically, a first buffer layer 251 and a second buffer layer 252 on the first buffer layer 251 can be disposed on the substrate 100. Therefore, the first buffer layer 251 can contact the substrate 100, and the second buffer layer 252 can be configured to contact the circuit pattern layer 200.

[0061] The first buffer layer 251 may include a material that has good adhesion to the substrate 100. For example, the first buffer layer 251 may include nickel (Ni). Furthermore, the second buffer layer 252 may include a material that has good adhesion to the circuit pattern layer 200. For example, the second buffer layer 252 may include chromium (Cr).

[0062] Since the adhesion between the substrate 100 and the circuit pattern layer 200, which are made of different materials, can be improved by the buffer layer 250, delamination of the film of the circuit pattern layer 200 can be prevented.

[0063] The protective layer 300 can be disposed on the circuit pattern layer 200.

[0064] The protective layer 300 may be partially disposed on the circuit pattern layer 200. The protective layer 300 may be disposed while covering the circuit pattern layer 200, and the protective layer 300 may prevent damage or delamination of the film caused by oxidation of the circuit pattern layer 200.

[0065] The protective layer 300 may be partially disposed in areas other than the area where the circuit pattern layer 200 is electrically connected to the chip 500 and external devices such as a display panel or motherboard.

[0066] Protective layer 300 may include solder paste. For example, protective layer 300 may include solder paste comprising a thermosetting resin, a thermoplastic resin, a filler, a curing agent, or a curing accelerator.

[0067] Chip 500 can be disposed in the chip mounting area 1A of substrate 100.

[0068] Chip 500 may include a semiconductor chip. For example, chip 500 may include an integrated circuit (IC) chip or a large-scale integrated circuit (LSI) chip.

[0069] Chip 500 can be disposed on circuit pattern layer 200 on which no protective layer 300 is disposed.

[0070] In detail, the terminals of chip 500 can be electrically connected through direct or indirect contact with circuit pattern layer 200.

[0071] For example, such as Figure 2 and Figure 3 As shown, the first bump 610 can be disposed between the chip 500 and the circuit pattern layer 200, and the chip 500 and the circuit pattern layer 200 can be electrically connected via the first bump 610.

[0072] As mentioned above, the temperature of the chip package may rise due to the heat generated in the chip during the driving process, which may degrade the driving characteristics of the chip package.

[0073] Therefore, the flexible circuit board for chip-on-film according to the embodiment can effectively dissipate the heat generated from the chip through holes and heat dissipation portions formed in the substrate 100 to solve the above-mentioned problems.

[0074] The flexible circuit board for chip-on-film according to an embodiment may include a heat dissipation section 400. The heat dissipation section may include a heat dissipation pattern layer 410, a connection layer 420, and a heat dissipation layer 430.

[0075] In detail, the heat dissipation unit 400 may include a heat dissipation pattern layer 410 disposed on a first surface 1S of the substrate 100, a connection layer 420 disposed inside a hole h formed in the substrate 100, and a heat dissipation layer 430 disposed on a second surface 2S of the substrate 100.

[0076] The heat dissipation pattern layer 410, the connecting layer 420, and the heat dissipation layer 430 may comprise the same material. The heat dissipation pattern layer 410, the connecting layer 420, and the heat dissipation layer 430 may be integrally formed.

[0077] The heat dissipation pattern layer 410, the connection layer 420, and the heat dissipation layer 430 may include the same materials as the circuit pattern layer 300. For example, the heat dissipation pattern layer 410, the connection layer 420, and the heat dissipation layer 430 may include a metallic material such as copper (Cu).

[0078] The heat dissipation pattern layer 410 can be disposed at a position overlapping with the chip mounting area 1A of the substrate 100. That is, the heat dissipation pattern layer 410 can be disposed at a position overlapping with the hole h formed in the substrate 100.

[0079] The area of ​​the heat dissipation pattern layer 410 can be smaller than the area of ​​the chip mounting region 1A. Furthermore, the area of ​​the heat dissipation pattern layer 410 can be smaller than the area of ​​the heat dissipation layer 430.

[0080] For example, the area of ​​the thermal pattern layer 410 may be 10% or more of the area of ​​the chip mounting region 1A. More specifically, the area of ​​the thermal pattern layer 410 may be 20% or more of the area of ​​the chip mounting region 1A. More specifically, the area of ​​the thermal pattern layer 410 may be 30% or more of the area of ​​the chip mounting region 1A. More specifically, the area of ​​the thermal pattern layer 410 may be 50% or more of the area of ​​the chip mounting region 1A.

[0081] When the area of ​​the heat dissipation pattern layer 410 is less than 10% of the area of ​​the chip mounting area 1A, it is difficult to effectively collect the heat generated by the chip 500, and the heat dissipation characteristics of the heat dissipation part may deteriorate.

[0082] The heat dissipation pattern layer 410 can be connected to the chip 500.

[0083] refer to Figure 2 The second bump 620 can be disposed between the heat dissipation pattern layer 410 and the chip 500, and the heat dissipation pattern layer 410 and the chip 500 can be connected via the second bump 620.

[0084] Since the heat dissipation pattern layer 410 and the chip 500 are directly connected via a second bump 620 with high thermal conductivity, the heat generated from the chip 500 can be effectively transferred to the heat dissipation pattern layer 410.

[0085] The thermal pattern layer 410 may not be electrically connected to the chip 500, but may only be physically connected to it. That is, the thermal pattern layer 410 may not be connected to the terminals of the chip 500. The thermal pattern layer 410 is used to effectively collect the heat generated by the chip 500 without requiring an electrical connection to the terminals of the chip 500.

[0086] Alternatively, the heat dissipation pattern layer 410 can be electrically connected to the chip 500. That is, the heat dissipation pattern layer 410 can be electrically connected to the power source in the terminal portion of the chip 500 that generates the most heat. In this case, the heat dissipation pattern layer 410 can be connected to the power source in the circuit pattern layer 200. Thus, the heat generated from the power source of the chip 500 that generates the most heat in the terminals of the chip 500 can be transferred to the heat dissipation portion through the power source of the flexible substrate for the chip on film for effective heat dissipation.

[0087] Alternatively, refer to Figure 3 The heat dissipation pattern layer 410 and the chip 500 can have a separation distance d and can be set to be spaced apart from each other.

[0088] Therefore, due to the second bump 620 formed in the heat dissipation section, the chip 500 can be stably mounted on the flexible substrate for chip-on-film.

[0089] A hole h can be formed in the substrate 100. Specifically, at least one hole h can be formed in the chip mounting region 1A of the substrate 100. That is, one or more holes h can be formed in the chip mounting region 1A of the substrate 100.

[0090] The hole h can be disposed in a region that overlaps with the region where the heat dissipation pattern layer 410 is disposed. Furthermore, the hole h can be disposed in a region that overlaps with the region where the heat dissipation layer 430 is disposed. That is, the hole h can be disposed in a region that overlaps with both the heat dissipation pattern layer 410 and the heat dissipation layer 430.

[0091] When there is only one hole overlapping the heat dissipation pattern layer 410, the heat from the chip can be effectively transferred to the heat dissipation pattern layer 410. However, the efficiency of heat transfer from the heat dissipation pattern layer 410 to the heat dissipation layer 430 is reduced, which may reduce the overall heat dissipation efficiency. Therefore, in the flexible circuit board for chip-on-film according to the embodiment, there may be multiple holes h overlapping the heat dissipation pattern layer 410.

[0092] In the heat dissipation pattern layer 410, the length L in the first direction, which is the longitudinal direction of the chip 500, can be greater than the width in the second direction, which is the width direction of the chip 500. Therefore, heat dissipation efficiency can be improved by widening the overlapping area between the chip 500 and the heat dissipation pattern layer 410.

[0093] In the plurality of holes h, the first separation distance d1 between them in the first direction can be smaller than the second separation distance d2 between them in the second direction. The second separation distance d2 can be more than 1.01 times and less than 5 times, more than 1.02 times and less than 4 times, more than 1.05 times and less than 3 times, or more than 1.1 times and less than 2 times the first separation distance d1. Since the second separation distance d2 is greater than the first separation distance d1, the heat generated in the area that does not overlap with the chip 500 can be more effectively dissipated to the heat dissipation layer 430 through the plurality of holes h.

[0094] The third separation distance d3, which serves as the minimum separation distance between the heat dissipation pattern layer 410 and the circuit pattern layer 200 in the second direction, can be greater than the second separation distance d2 between the holes h in the second direction. The third separation distance d3 can be more than 1.01 times and less than 5 times, more than 1.02 times and less than 4 times, more than 1.05 times and less than 3 times, or more than 1.1 times and less than 2 times the second separation distance d2. Because the third separation distance d3 is greater than the second separation distance d2, contact between the heat dissipation pattern layer 410 and the circuit pattern layer 200 during the process can be prevented, thereby improving the reliability of the flexible circuit board.

[0095] The circuit pattern layer 200 has multiple circuit patterns, and the fourth separation distance d4, which is the minimum separation distance between adjacent circuit patterns, can be less than the first separation distance d1. The first separation distance d1 can be more than 2 and less than 50 times, more than 3 and less than 30 times, more than 5 and less than 20 times, or more than 6 and less than 10 times the fourth separation distance. Since the first separation distance d1 is greater than the minimum separation distance between circuit patterns, it can prevent the holes h from connecting to each other, thus effectively forming the connection layer 420 formed inside the holes h. When the first separation distance d1 is less than twice the minimum separation distance between circuit patterns, when adjacent holes connect to form a connection layer, the connection layer may not be completely formed inside the holes, and a connection break may occur between the heat dissipation pattern layer 410 and the heat dissipation layer 430, so that the heat generated by the chip cannot be effectively transferred to the heat dissipation layer. When the first separation distance exceeds 50 times the minimum separation distance between circuit patterns, the heat of the chip can be well transferred to the heat dissipation pattern layer 410, but the efficiency of transferring the heat of the heat dissipation pattern layer 410 to the heat dissipation layer 430 is reduced, so the overall heat dissipation efficiency may be reduced.

[0096] The width w of the heat dissipation pattern layer 410 in the second direction can be greater than the third separation distance d3, which is the circuit separation distance between the circuit pattern and the heat dissipation pattern layer. The width w of the heat dissipation pattern layer 410 can be more than 1.01 times and less than 10 times, more than 1.05 times and less than 8 times, more than 1.1 times and less than 5 times, or more than 1.5 times and less than 3 times the third separation distance d3. This prevents connection between the heat dissipation pattern layer and the circuit, and allows the heat dissipation pattern layer to absorb as much heat generated from the chip as possible.

[0097] The ratio of the length of the heat dissipation pattern layer in the first direction to its width in the second direction (length / width) can be 0.5 to less than 5 times, 0.8 to less than 4 times, 1 to less than 3 times, or 1.2 to less than 2.5 times the ratio of the length of the chip in the first direction to its width in the second direction (length / width). Furthermore, the area of ​​the heat dissipation pattern layer 410 can be more than 5%, 10%, 15%, 20%, 25%, or 30% of the area of ​​the chip. Alternatively, the area of ​​the heat dissipation pattern layer 410 can be more than 5% and less than 90%, more than 10% and less than 80%, more than 15% and less than 75%, more than 20% and less than 70%, more than 25% and less than 65%, or more than 30% and less than 60% of the area of ​​the chip.

[0098] That is, since the thermal pattern layer is formed most similarly to the lower surface of the chip (the surface on the flexible circuit board side), heat collected at the edge of the chip can be absorbed and dissipated at the edge of the thermal pattern layer. Furthermore, since the chip and the thermal pattern layer are formed in similar shapes, the thermal pattern layer can effectively absorb heat generated from the chip in multiple directions.

[0099] A connecting layer 420 may be disposed within the aperture h. The heat dissipation pattern layer 410 and the heat dissipation layer 430 may be connected via the connecting layer 420. For example, after a buffer layer such as palladium (Pd) is disposed on the inner surface of the aperture h, a connecting layer 420 comprising a metal such as copper (Cu) may be disposed.

[0100] The connection layer 420 can transfer heat generated from the chip to the heat dissipation layer 430. To effectively transfer heat to the heat dissipation layer 430, the connection layer 420 can have two or more holes h. More specifically, the number of holes h can be ten or more. Even more specifically, the number of holes h can be fifty or more.

[0101] Therefore, since the area of ​​the heat dissipation pattern layer 410 can be widened, a large amount of heat generated from the chip 500 can be collected and transferred to the heat dissipation layer 430 via the connection layer formed in the multiple holes h, thereby effectively transferring the heat of the chip 500 to the outside.

[0102] The heat dissipation layer 430 can be disposed on the second surface 2S of the substrate 100. The heat dissipation layer 430 can be disposed in the area corresponding to the chip mounting area 1A of the substrate 100.

[0103] The area of ​​the heat dissipation layer 430 can be larger than the area of ​​the heat dissipation pattern layer 410. The area of ​​the heat dissipation layer 430 can be an area corresponding to the area of ​​the chip mounting region 1A. Therefore, the heat collected by the heat dissipation pattern layer 410 and transferred via the interconnect layer 420 can be effectively dissipated to the outside via the heat dissipation layer 430.

[0104] The heat dissipation layer 430 can be configured to have a thickness of 5 μm to 25 μm. For example, the heat dissipation layer 430 can have a thickness of 10 μm to 20 μm. For example, the heat dissipation layer 430 can have a thickness of 13 μm to 17 μm.

[0105] When the thickness of the heat dissipation layer 430 is less than 5 μm, the heat generated from the chip may not be effectively dissipated to the outside, which may degrade the heat dissipation characteristics of the chip package. In addition, when the thickness of the heat dissipation layer 430 exceeds 25 μm, the overall thickness of the chip package may increase the thickness of the heat dissipation layer 430.

[0106] Additionally, although not shown in the figure, a protective layer can be provided below the heat dissipation layer 430. This prevents oxidation and damage to the heat dissipation layer 430, thereby improving the heat dissipation characteristics and reliability of the chip package.

[0107] According to an embodiment, a flexible substrate for chip-on-film can effectively dissipate heat generated in the chip to the outside through holes formed in the substrate and heat dissipation components disposed on a first surface, a second surface of the substrate, and within the holes.

[0108] In other words, the heat generated from the chip can be collected by the heat dissipation pattern layer, and the heat can be transferred to the heat dissipation layer through the connectors set in multiple holes to dissipate the heat to the outside.

[0109] In addition, heat can be effectively transferred to the heat dissipation layer by forming multiple heat transfer holes, and the heat dissipation layer is formed with an area corresponding to the chip mounting area, thereby easily dissipating the heat generated from the chip to the outside.

[0110] Therefore, since the flexible substrate for chip-on-film according to the embodiment and the chip package including the flexible substrate have improved heat dissipation characteristics, the reliability and driving characteristics of the chip package can be improved.

[0111] In the following text, reference will be made to Figures 4 to 6 A flexible substrate for chip-on-film and a chip package including the flexible substrate are described according to another embodiment.

[0112] In the description of a flexible substrate for chip-on-film and a chip package including the flexible substrate according to another embodiment, the same descriptions as those for the flexible substrate for chip-on-film and the chip package including the flexible substrate according to the embodiment will be omitted, and the same reference numerals will be given to these components.

[0113] refer to Figures 4 to 6 According to another embodiment, a flexible substrate for chip-on-film and a chip package including the flexible substrate may include multiple thermal pattern layers. Specifically, a first thermal pattern layer 401 and a second thermal pattern layer 402 may be included on the substrate 100.

[0114] exist Figures 4 to 6 The illustration shows two heat dissipation pattern layers, but the embodiment is not limited to this and may include three or more heat dissipation pattern layers.

[0115] The first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be configured to be spaced apart from each other.

[0116] The areas of the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be smaller than the area of ​​the chip mounting region 1A. Furthermore, the areas of the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be smaller than the area of ​​the heat dissipation layer 430.

[0117] At least one of the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be electrically connected to the chip 500.

[0118] refer to Figure 5 The second bump 620 is disposed between at least one of the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 and the chip 500, and the heat dissipation pattern layer 410 and the chip 500 can be electrically connected via the second bump 620.

[0119] Figure 5 The illustration shows that both the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 are connected to the chip 500 via the second bump 620, but the embodiment is not limited to this. At least one of the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 may not be electrically connected to the chip 500 and may be spaced apart from each other or physically connected to the chip 500. That is, the terminal portion of the chip and the second bump may not be connected.

[0120] The first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be connected to the heat dissipation layer 430 disposed on the second surface 2S of the first substrate 100 via the connecting portion 420.

[0121] In other words, the first heat dissipation pattern layer 401 and the second heat dissipation pattern layer 402 can be connected to the same heat dissipation layer 430 disposed on the second surface 2S of the first substrate 100 via the connecting portion 420.

[0122] According to another embodiment, a flexible substrate for chip-on-film and a chip package including the flexible substrate may include multiple thermal pattern layers.

[0123] Therefore, even if one of the heat dissipation pattern layers is damaged, the heat dissipation unit 400 can maintain its heat dissipation characteristics, thereby increasing the lifespan of the heat dissipation characteristics.

[0124] In the following text, reference will be made to Figure 7 and Figure 8 A flexible substrate for chip-on-film and a chip package including the flexible substrate are described according to yet another embodiment.

[0125] In the description of a flexible substrate for chip-on-film and a chip package including the flexible substrate according to yet another embodiment, descriptions that are the same as or similar to those in the description of the flexible substrate for chip-on-film and the chip package including the flexible substrate according to the above embodiments will be omitted, and the same reference numerals will be assigned to the same parts.

[0126] refer to Figure 7 and Figure 8 According to another embodiment, the flexible substrate for chip-on-film and the chip package including the flexible substrate may further include an extended pattern layer 210. Specifically, the extended pattern layer 210 connecting the circuit pattern layer 200 and the heat dissipation pattern layer 410 may be disposed on the first surface 1S of the substrate 100.

[0127] The extended pattern layer 210 may be a pattern layer extending from the circuit pattern layer 200. The extended pattern layer 210 may be configured to contact the circuit pattern layer 200 and the heat dissipation pattern layer 410.

[0128] Figure 7 The example shows two extended pattern layers 210, but the embodiment is not limited to this; the number of extended pattern layers 210 may be one or more.

[0129] In a flexible substrate for chip-on-film and a chip package including the flexible substrate according to another embodiment, a second bump connecting the heat dissipation pattern layer and the chip is not required due to the extended pattern layer. That is, since the heat dissipation pattern layer and the chip are connected via a circuit pattern layer and a connection pattern layer, heat generated from the chip can be effectively transferred to the heat dissipation pattern layer without the need for a second bump.

[0130] In the above embodiments, the chip and the flexible substrate for the chip-on-film are illustrated using bump electrical connections, but the embodiments are not limited to this; the chip can be bonded to the circuit pattern layer 200 by wires. In this case, in the circuit pattern layer 200 on which the protective layer 300 is not disposed, a tin plating layer can be provided to facilitate wire bonding. For example, the plating layer may include a first tin plating layer with a low tin content and a second tin plating layer disposed on the first tin plating layer and including pure tin with a high tin content. Therefore, wire bonding with the circuit pattern layer 200 can be facilitated.

[0131] In this case, the chip and the circuit pattern of the flexible substrate used for chip-on-film are connected by wires, but the chip and the heat dissipation pattern layer can be physically connected or electrically connected via bumps.

[0132] In the following text, reference will be made to Figures 9 to 15 Examples of various electronic devices including flexible circuit boards for chips on a film are described according to embodiments.

[0133] refer to Figure 9 The flexible circuit board for chip-on-film according to the embodiment can be used in edge displays.

[0134] Additionally, refer to Figure 10The flexible circuit board for chip-on-film according to the embodiment can be included in a foldable flexible electronic device. Therefore, the touch device including it can be a flexible touch device. Thus, a user can fold or bend it by hand, and this flexible touch window can be applied to wearable touch devices, etc.

[0135] Additionally, refer to Figures 11 to 13 The flexible circuit board for chip-on-film according to the embodiments can be applied to various electronic devices that utilize foldable display devices. (Reference) Figures 11 to 13 Foldable display devices can have foldable covers. They can be included in various portable electronic products. Specifically, they can be included in mobile terminals (mobile phones), laptops (portable computers), etc. Therefore, while increasing the display area of ​​portable electronic products, the size of the device can be reduced during storage and transportation, thereby improving portability. This improves the convenience for users of portable electronic products. However, the embodiments are not limited to this; of course, foldable display devices can be used in various electronic products.

[0136] Additionally, refer to Figure 14 The flexible circuit board for chip-on-film according to the embodiments can be included in various wearable touch devices including curved displays. Therefore, electronic devices including the flexible circuit board for all-in-one chip-on-film according to the embodiments can reduce thickness, size, or weight.

[0137] Additionally, refer to Figure 15 The flexible circuit board for chip-on-film according to the embodiments can be used in various electronic devices with display sections, such as TVs, monitors and laptops.

[0138] However, the embodiments are not limited thereto. Of course, the flexible circuit board for chip-on-film according to the embodiments can be used in various electronic devices having a flat panel display or a display with a curved shape.

[0139] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, the features, structures, and effects shown in each embodiment can be combined or modified by those skilled in the art for other embodiments. Therefore, it should be understood that anything related to such combinations and modifications is included within the scope of this invention.

[0140] Furthermore, while the foregoing primarily describes embodiments, these embodiments are merely examples and not intended to limit the invention. Those skilled in the art will understand that various changes and applications not mentioned above can be made without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified. Additionally, it should be understood that differences associated with such changes and applications are included within the scope of the invention as defined by the appended claims.

Claims

1. A flexible circuit board for chip-on-film, the flexible circuit board comprising: A substrate, the substrate including a first surface and a second surface opposite to the first surface, and including a chip mounting region; A circuit pattern layer disposed on the first surface; as well as A heat dissipation unit is disposed in the chip mounting area. The substrate has at least two holes formed in the region overlapping with the heat dissipation portion, and The heat dissipation unit includes: A heat dissipation pattern layer is disposed on the first surface; A connecting layer, the connecting layer being disposed within the hole; and A heat dissipation layer is disposed on the second surface. The first direction, which is the vertical direction, and the second direction, which is the width direction, are defined for the chip disposed in the chip mounting area. The first distance in the first direction between adjacent holes is defined. The second distance in the second direction between adjacent holes is defined. The third distance between the heat dissipation pattern layer and the circuit pattern layer in the second direction is defined. The fourth distance between adjacent circuit pattern layers is defined. Wherein, the first distance is less than the second distance. Wherein, the third distance is greater than the second distance. The fourth distance is less than the first distance.

2. The flexible circuit board according to claim 1, wherein, The heat dissipation pattern layer, the connecting layer, and the heat dissipation layer are integrally formed.

3. The flexible circuit board according to claim 1, wherein, The area of ​​the heat dissipation pattern layer is smaller than the area of ​​the heat dissipation layer.

4. The flexible circuit board according to claim 1, wherein, The area of ​​the heat dissipation pattern layer is more than 5% of the chip area.

5. The flexible circuit board according to claim 1, wherein, The heat dissipation pattern layer includes a first heat dissipation pattern layer and a second heat dissipation pattern layer spaced apart from each other, and The first heat dissipation pattern layer and the second heat dissipation pattern layer are connected to the same heat dissipation layer.

6. The flexible circuit board according to claim 5, wherein, The first heat dissipation pattern layer is connected to at least two of the connecting layers.

7. The flexible circuit board according to claim 1, further comprising: A connection pattern layer is provided, which connects the circuit pattern layer and the heat dissipation pattern layer.

8. The flexible circuit board according to claim 1, wherein, The circuit pattern layer includes a first metal layer and a second metal layer located on the first metal layer, and The thickness of the first metal layer is less than the thickness of the second metal layer.

9. The flexible circuit board according to claim 1, wherein, The thickness of the substrate is from 5 μm to 100 μm.

10. The flexible circuit board according to claim 1, wherein, The thickness of the circuit pattern layer is 5 μm to 25 μm.

11. The flexible circuit board according to claim 1, wherein, The area of ​​the heat dissipation pattern layer is more than 10% of the area of ​​the chip mounting area.

12. The flexible circuit board according to claim 1, wherein, The length of the heat dissipation pattern layer in the first direction is greater than the width of the heat dissipation pattern layer in the second direction.

13. The flexible circuit board according to claim 12, wherein, The ratio of the length of the heat dissipation pattern layer in the first direction to the width of the heat dissipation pattern layer in the second direction is 0.5 to 5 times the ratio of the length of the chip in the first direction to the width of the chip in the second direction.

14. A chip package, comprising: A substrate, the substrate including a first surface and a second surface opposite to the first surface, and including a chip mounting region; A circuit pattern layer disposed on the first surface; A chip, which is electrically connected to the circuit pattern layer; as well as A heat dissipation unit is disposed in the chip mounting area. The substrate has at least two holes formed in the region overlapping with the heat dissipation portion, and The heat dissipation unit includes: A heat dissipation pattern layer is disposed on the first surface; A connecting layer, the connecting layer being disposed within the hole; and A heat dissipation layer is disposed on the second surface. The heat dissipation pattern layer, the connecting layer, and the heat dissipation layer are integrally formed. The chip is defined by a first direction as its vertical direction and a second direction as its width direction. The first distance in the first direction between adjacent holes is defined. The second distance in the second direction between adjacent holes is defined. The third distance between the heat dissipation pattern layer and the circuit pattern layer in the second direction is defined. The fourth distance between adjacent circuit pattern layers is defined. Wherein, the first distance is less than the second distance. Wherein, the third distance is greater than the second distance. The fourth distance is less than the first distance.

15. The chip package according to claim 14, wherein, The heat dissipation pattern layer is spaced apart from the chip.

16. The chip package according to claim 14, wherein, The heat dissipation pattern layer is connected to the chip via bumps.

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