A redistribution layer structure and construction method thereof

Abstract

The present invention relates to the field of chip packaging technology, and provides a redistribution layer structure and a construction method thereof. The structure comprises a first polyimide layer and a first redistribution layer, wherein the first polyimide layer has a first via; one or more second polyimide layers and second redistribution layers, wherein the second polyimide layer has a second via; and a third polyimide layer, wherein the third polyimide layer has a third via; wherein the first and second vias comprise a plurality of small-aperture vias of a first aperture, and the third via comprises a large-aperture via of a second aperture, wherein the first aperture is smaller than the second aperture.

Description

Technical Field

[0001] The present invention generally relates to the field of chip packaging technology. Specifically, the present invention relates to a redistribution layer structure and a construction method thereof. Background Art

[0002] Re-distribution layer (RDL) technology has significantly contributed to the development of many advanced packaging technologies. It is widely used in fan-in and fan-out wafer-level packaging (WLP) and through-silicon via (TSV) technology. RDL technology is also frequently used in high-end 2.5D multi-chip integrated system packaging, such as 3D integrated circuit (IC) packaging.

[0003] However, as the types, performance, and scale of electronic hardware continue to evolve, end-user electronic products are moving towards multifunctionality, intelligence, and miniaturization. We have entered the era of high-density system-level packaging. With the significant increase in packaging density, the number of RDL layers is also increasing. However, traditional redistribution layer structures do not perform well when there are many RDL layers. In particular, when the redistribution layer structure has overlapping vias or when the vias in the redistribution layer structure are large, the via pads at both ends of the transmission line structure in the redistribution layer structure will be extremely uneven, which in turn affects the production of the underlying RDL layer and subsequent assembly processes. Summary of the Invention

[0004] To at least partially solve the above problems in the prior art, the present invention proposes a redistribution layer structure comprising:

[0005] a first dielectric layer and a first redistribution layer, wherein the first dielectric layer has a first via hole;

[0006] One or more second dielectric layers and second redistribution layers, wherein the second dielectric layer has a second via hole; and

[0007] a third dielectric layer, wherein the third dielectric layer has a third via hole;

[0008] The first and second via holes include a plurality of small-aperture via holes, and the third via hole includes a large-aperture via hole. The aperture of the small-aperture via hole is smaller than that of the large-aperture via hole.

[0009] In one embodiment of the present invention, the redistribution layer structure further comprises:

[0010] a substrate on which a passivation layer and a pad are arranged;

[0011] a passivation layer disposed between the silicon wafer and the first dielectric layer; and

[0012] A pad is arranged at the first via hole.

[0013] In one embodiment of the present invention, the redistribution layer structure further includes a stud bump, and the stud bump is arranged at the third via hole.

[0014] In one embodiment of the present invention, it is provided that the aperture of the small-aperture via hole is in the range of 5-20 μm, and the aperture of the large-aperture via hole is in the range of greater than or equal to 30 μm.

[0015] In one embodiment of the present invention, the openings of the first vias and the second vias on the first hole plate of the first redistribution layer are arranged alternately.

[0016] The present invention also provides a method for constructing the redistribution layer structure, the method comprising the following steps:

[0017] The first dielectric layer is constructed on the substrate, the passivation layer and the pad, and the first via hole is photoetched on the first dielectric layer.

[0018] constructing the first redistribution layer;

[0019] constructing the second dielectric layer, and photoetching the second via hole on the second dielectric layer;

[0020] constructing the second redistribution layer; and

[0021] The third dielectric layer is constructed, and the third via hole is photoetched on the third dielectric layer.

[0022] In one embodiment of the present invention, photoresist is coated on the first via hole and the first dielectric layer, a pattern of the first redistribution layer is photoetched, and the first redistribution layer is constructed by electroplating; and

[0023] Photoresist is coated on the second via hole and the second dielectric layer, a pattern of the second redistribution layer is photoetched, and the second redistribution layer is constructed by electroplating.

[0024] According to one embodiment of the present invention, the first to third dielectric layers are formed by spin coating a dielectric.

[0025] In one embodiment of the present invention, the method for constructing a redistribution layer structure further comprises electroplating the pillar bump at the third via hole.

[0026] In one embodiment of the present invention, the method for constructing a redistribution layer structure further includes wafer thinning and dicing.

[0027] The present invention has at least the following beneficial effects: the present invention replaces the common large-aperture vias in the prior art by adopting a combination of multiple small-aperture vias, so that the hole plate of the redistribution layer at the via is flatter after electroplating; the present invention effectively enhances the bonding force between the upper and lower redistribution layers at the via by adopting a combination of multiple small-aperture vias, greatly reducing the risk of deformation and even cracks; and the present invention can add redundant dielectric layer windows by adopting a combination of multiple small-aperture vias, which greatly improves the ability of the redistribution layer to fully transmit signals even in the event of process defects; in addition, compared with the traditional redistribution layer process, the technical solution adopted by the present invention does not increase additional costs and has high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To further illustrate the advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope of the present invention. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0029] Figure 1 A schematic diagram of a redistribution layer structure in the prior art is shown.

[0030] Figure 2 A schematic diagram of a redistribution layer structure in one embodiment of the present invention is shown.

[0031] Figure 3 A flowchart of constructing a redistribution layer structure in one embodiment of the present invention is shown.

[0032] Figure 4 —8 shows a schematic structural diagram of the process of constructing a redistribution layer structure in one embodiment of the present invention.

[0033] Figure 9 A schematic diagram of a redistribution layer structure with stacked vias in one embodiment of the present invention is shown.

[0034] Figure 10 A schematic diagram of the arrangement of through-hole openings on a perforated plate in another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] It should be noted that the components in the drawings may be shown exaggeratedly for the sake of illustration and are not necessarily correct to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.

[0036] In the present invention, unless otherwise specified, the phrases "disposed on," "disposed above," and "disposed above" do not exclude the presence of intermediate components. Furthermore, "disposed on or above" merely indicates the relative positional relationship between two components and, in certain circumstances, such as after reversing the product orientation, can be converted to "disposed below or below," and vice versa.

[0037] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0038] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0039] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added according to the needs of the specific scenario. In addition, unless otherwise stated, the features of different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or description of this application.

[0040] It should also be noted that, within the scope of the present invention, terms such as "same," "equal," and "equal to" do not imply absolute equality of values, but rather allow for a certain reasonable error. In other words, such terms also encompass "substantially the same," "substantially equal," and "substantially equal." Similarly, in the present invention, terms such as "perpendicular to" and "parallel to" indicating direction also encompass the meaning of "substantially perpendicular to" and "substantially parallel to."

[0041] In addition, the numbering of the steps of the methods of the present invention does not limit the order in which the steps are to be performed. Unless otherwise specified, the steps of the methods may be performed in different orders.

[0042] The present invention will be further described below with reference to the accompanying drawings in conjunction with specific embodiments.

[0043] Figure 1 FIG. 1 shows a schematic diagram of a redistribution layer structure with large-sized openings. Figure 1As shown, RDL structures with large via openings can severely deform, significantly impacting subsequent RDL and C4 (Controlled Collapsed Chip Connection) bump fabrication, as well as product assembly. Furthermore, large-opening RDL structures also suffer from poor bonding between the upper and lower RDL layers at the vias. Furthermore, due to the single opening of the vias and the resulting RDL deformation, signal transmission quality at the vias cannot be guaranteed.

[0044] like Figure 2 As shown, in one embodiment of the present invention, a redistribution layer structure is provided by taking a copper pillar product under a 3P3M structure as an example. The structure may include a silicon wafer (Silicon) 201, a bond pad (Bond Pad) 202, a passivation layer (Passivation) 203, first to third polyimide (Polyimide PI) layers 204-206, first and second redistribution layers (RDL) 207-208, first to third vias (Via) 209-211 and a pillar bump (Pillar Bump) 212.

[0045] In actual production, the silicon wafer 201, the pad 202 and the passivation layer 203 can be provided by incoming wafers, wherein the pad 202 and the passivation layer 203 are arranged above the silicon wafer 201, the pad 202 can be connected to the first via 209, and the passivation layer 203 can be bonded to the first polyimide layer 204.

[0046] The first to third polyimide layers 204-206 respectively have first to third vias 209-211. The first via 209 connects the pad 202 and the first redistribution layer 207, the second via 210 connects the first redistribution layer 207 and the second redistribution layer 208, and the third via connects the second redistribution layer 208 and the stud bump 212. The first and second vias 209, 210 can be composed of multiple small vias, while the third via 220 can be a single large via. For example, the first and second vias 209, 210 can each include multiple small vias of the same aperture. Alternatively, the first and second vias 209, 210 can each include multiple small vias of different apertures. These small vias can be laid out and / or arranged according to specific rules based on actual needs. For ease of description, the aperture of these small vias is referred to as the first aperture, and the aperture of the large via is referred to as the second aperture. The first pore size is smaller than the second pore size. The first pore size may be in the range of 5-20 μm, and the second pore size may generally be in the range of 30 μm or greater. However, those skilled in the art will appreciate that the number of polyimide layers and redistribution layers is not limited to the above examples, and those skilled in the art may select appropriate values ​​based on the actual needs of the product.

[0047] Combination of the above Figure 2 The specific embodiment describes a redistribution layer structure according to the present invention. However, those skilled in the art should understand that the redistribution layer structure according to the present invention is not limited to the specific materials disclosed in the above specific embodiments. In other embodiments of the present invention, the silicon wafer 201 can be a substrate of any other material, for example, including a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.; alternatively, the substrate can also be made of an electrically non-conductive material such as glass, plastic, or sapphire wafer. The first to third polyimide layers 204-206 can be dielectric layers of any other material. The dielectric layer can be an inorganic material such as silicon oxide, silicon oxynitride, borosilicate glass, phosphorus silicate glass (PSG), borophosphorus silicate glass (BPSG), fluorinated glass silicate glass (FSG), low-K dielectric, etc.; it can also be an organic material such as polyimide, photosensitive epoxy resin, solder mask ink, green paint, dry film, photosensitive build-up layer material, BCB (bisbenzocyclobutene resin) or PBO (phenylbenzobisoxazole resin).

[0048] like Figure 3 In one embodiment of the present invention, a method for preparing the redistribution layer structure is provided, which may include the following steps:

[0049] Step 100: Figure 4As shown, a layer of PI is spin-coated on the incoming wafer to construct the first polyimide layer 204, and the first via 209 is constructed on the first polyimide layer 204 by a photolithography process, wherein the first via 209 is composed of a plurality of small vias of the first aperture.

[0050] Step 200: Figure 5 As shown, photoresist is coated on the first via 209 and the first polyimide layer 204, and the pattern of the first redistribution layer 207 is photoetched. The first redistribution layer 207 is then constructed by electroplating. In the method of the present invention, since a combination of multiple small vias of the first aperture is used at the first via, replacing the large aperture vias commonly used in the prior art, the redistribution layer electroplated using this technical solution will have a flatter hole disk shape at the via. At the same time, since the technical solution adopted in the embodiment of the present invention constitutes a redundant design of the via conductive structure, the probability of successful signal transmission at the via can be greatly improved.

[0051] Step 300: Figure 6 As shown, in Figure 5 A layer of PI is spin-coated on the structure shown to construct the second polyimide layer 205 , and the second via hole 210 is constructed on the second polyimide layer 205 by a photolithography process, wherein the second via hole 210 is composed of a plurality of small via holes of the first aperture.

[0052] Step 400: Figure 7 As shown, photoresist is coated on the second via hole 210 and the second polyimide layer 205, and the pattern of the second redistribution layer 208 is photoetched, and then the second redistribution layer 208 is constructed by electroplating.

[0053] Step 500: Figure 8 As shown, in Figure 7 A PI layer is spin-coated on the structure shown to construct the third polyimide layer 206 , and the third via hole 211 is constructed on the third polyimide layer 206 by photolithography, wherein the third via hole 211 is a large via hole of the second aperture for connecting the pillar bump 212 .

[0054] Step 600: Electroplating the pillar bump 212 at the third via hole 211 to form Figure 2 The structure shown is formed, and the wafer is thinned and cut to complete the product packaging process.

[0055] In particular, for structures that require overlapping holes, the advantages of the technical solution of the present invention will be more obvious. Figure 9As shown, when both the first via hole 209 and the second via hole 210 need to be opened on the same hole plate of the first redistribution layer 207, the following can be done: Figure 10 As shown, the opening positions of the first via hole 209 and the second via hole 210 on the hole plate of the first redistribution layer 207 are staggered, so as to make the hole plate of the first redistribution layer 207 more flat. Figure 10 As shown, the opening 111 of the first through hole 209 of the inner ring and the opening 112 of the second through hole 210 of the outer ring can be staggered. In addition, the above openings can also be staggered in other arrangements, not limited to Figure 10 The arrangement of the inner and outer rings is shown in FIG.

[0056] Combination of the above Figures 3 to 10 The specific embodiment describes a method for preparing a redistribution layer structure according to the present invention. However, those skilled in the art should understand that the method for preparing a redistribution layer structure according to the present invention is not limited to the specific process disclosed in the above specific embodiment. In other embodiments of the present invention, the first to third polyimide layers 204-206 can be made of dielectric layers of any other materials. The dielectric layer can be an inorganic material such as silicon oxide, silicon oxynitride, borosilicate glass, phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated glass silicate glass (FSG), low-K dielectric, etc.; it can also be an organic material such as polyimide, photosensitive epoxy resin, solder mask ink, green paint, dry film, photosensitive build-up layer material, BCB (bis(benzocyclobutene) resin) or PBO (phenylbenzobisoxazole resin). The dielectric layer can be made by rolling, spin coating, spraying, printing, non-rotational coating, hot pressing, vacuum lamination, immersion, pressure bonding, etc.

[0057] The present invention replaces the common large-aperture vias in the prior art by adopting a combination of multiple small-aperture vias, so that the hole plate of the redistribution layer at the via is flatter after electroplating; the present invention can effectively enhance the bonding force between the upper and lower redistribution layers at the via by adopting a combination of multiple small-aperture vias, greatly reducing the risk of deformation and even cracks; and the present invention can add redundant dielectric layer openings by adopting a combination of multiple small-aperture vias, which can greatly improve the ability of the redistribution layer to fully transmit signals even in the event of process defects; in addition, compared with the traditional redistribution layer process, the technical solution adopted by the present invention does not increase additional costs and has high practical value.

[0058] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations may be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims

1. A redistribution layer structure, characterized in that: include: a first dielectric layer and a first redistribution layer, wherein the first dielectric layer has a first via hole; One or more second dielectric layers and second redistribution layers, wherein the second dielectric layer has a second via hole; a third dielectric layer, wherein the third dielectric layer has a third via hole; and a column bump, the column bump being arranged at the third via hole; The first and second via holes include a plurality of small-aperture via holes, and the third via hole includes a large-aperture via hole. The aperture of the small-aperture via hole is smaller than that of the large-aperture via hole.

2. The redistribution layer structure according to claim 1, wherein: Also includes: a substrate on which a passivation layer and a pad are arranged; a passivation layer disposed between the substrate and the first dielectric layer; as well as A pad is arranged at the first via hole.

3. The redistribution layer structure according to claim 1, wherein: The aperture of the small aperture via is 5-20 μ m, the aperture of the large aperture via is greater than or equal to 30 μ within the range of m.

4. The redistribution layer structure according to claim 1, wherein: The openings of the first via holes and the second via holes on the first hole plate of the first redistribution layer are arranged alternately.

5. A method for constructing the redistribution layer structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: constructing the first dielectric layer on the substrate, the passivation layer and the pad, and photoetching the first via hole on the first dielectric layer; constructing the first redistribution layer; constructing the second dielectric layer, and photoetching the second via hole on the second dielectric layer; constructing the second redistribution layer; as well as The third dielectric layer is constructed, and the third via hole is photoetched on the third dielectric layer.

6. The method for constructing a redistribution layer structure according to claim 5, wherein: Coating photoresist on the first via hole and the first dielectric layer, photoetching a pattern of the first redistribution layer, and constructing the first redistribution layer by electroplating; as well as A photoresist is coated on the second via hole and the second dielectric layer, a pattern of the second redistribution layer is photoetched, and the second redistribution layer is structured by electroplating.

7. The method for constructing a redistribution layer structure according to claim 5, wherein: The first to third dielectric layers are formed by spin coating a dielectric.

8. The method for constructing a redistribution layer structure according to claim 5, wherein: Also included is electroplating the stud bump at the third via.

9. The method for constructing a redistribution layer structure according to claim 5, wherein: It also includes wafer thinning and dicing.

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