Semiconductor package

Abstract

A semiconductor package includes: a first redistribution substrate; a first semiconductor chip mounted on the first redistribution substrate; a first molding layer located on the first redistribution substrate and covering a top surface and side surfaces of the first semiconductor chip; a second redistribution substrate located on the first molding layer; and an adhesive film located between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers the top surface of the first molding layer. The side surfaces of the adhesive film are coplanar with the side surfaces of the second redistribution substrate.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0096713, filed on August 3, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor package, and more specifically, to a semiconductor package including a redistributed substrate. Background Technology

[0004] Semiconductor packages are designed to implement integrated circuit chips for use in electronic products. Typically, semiconductor packages are configured to mount semiconductor chips onto printed circuit boards (PCBs), and bonding wires or bumps are used to electrically connect the semiconductor chips to the PCB. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide a semiconductor package with improved reliability.

[0006] According to one aspect of this disclosure, a semiconductor package includes: a first redistribution substrate; a first semiconductor chip mounted on the first redistribution substrate; a first molding layer located on the first redistribution substrate, the first molding layer covering a top surface and a side surface of the first semiconductor chip, the top surface being remote from the first redistribution substrate; a second redistribution substrate located on the first molding layer; and an adhesive film located between the second redistribution substrate and the first molding layer, wherein the adhesive film is spaced apart from the first semiconductor chip and covers the top surface of the first molding layer, and wherein the side surface of the adhesive film is coplanar with the side surface of the second redistribution substrate.

[0007] According to one aspect of this disclosure, a semiconductor package includes: a first redistribution substrate; a first semiconductor chip mounted on the first redistribution substrate; a first molding layer located on the first redistribution substrate, the first molding layer covering a top surface and a side surface of the first semiconductor chip, the top surface being remote from the first redistribution substrate; a second redistribution substrate located on the first molding layer; a second semiconductor chip mounted on the second redistribution substrate; and an adhesive film located between the second redistribution substrate and the first molding layer, wherein the second redistribution substrate includes: an upper dielectric layer; connection pads exposed by the upper dielectric layer; and connection terminals located on a bottom surface of the connection pads, wherein the adhesive film extends in a first direction parallel to the top surface of the first semiconductor chip, the adhesive film contacts the top surface of the first molding layer and the bottom surface of the upper dielectric layer of the second redistribution substrate, and wherein the width of the adhesive film in the first direction is equal to the width of the first redistribution substrate in the first direction.

[0008] According to one aspect of this disclosure, a semiconductor package includes: a first redistribution substrate; a first semiconductor chip mounted on the first redistribution substrate; a first molding layer located on the first redistribution substrate, the first molding layer covering a top surface and a side surface of the first semiconductor chip, the top surface of the first semiconductor chip being remote from the first redistribution substrate; a second redistribution substrate located on the first molding layer; a second semiconductor chip mounted on the second redistribution substrate; a second molding layer located on the second redistribution substrate, the second molding layer covering a top surface and a side surface of the second semiconductor chip; an adhesive film located between the second redistribution substrate and the first molding layer; a conductive structure penetrating the first molding layer and connecting the first redistribution substrate to the second redistribution substrate; and an external terminal located on a bottom surface of the first redistribution substrate, wherein the first redistribution substrate includes: a lower bump pattern contacting the external terminal; a first connection pad contacting the conductive structure; a plurality of first redistribution patterns connecting the first connection pad to the lower bump pattern; and

[0009] A lower dielectric layer surrounds a plurality of first redistribution patterns, wherein the side surface of the adhesive film is coplanar with the side surface of the first molding layer. Attached Figure Description

[0010] Figure 1A A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0011] Figure 1B and Figure 1C It shows Figure 1A A magnified view of part A.

[0012] Figure 2A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0013] Figure 3 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0014] Figure 4 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0015] Figures 5 to 10 , Figure 12 and Figure 13 A cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment is shown.

[0016] Figure 11 It shows Figure 10 A magnified view of part B. Detailed Implementation

[0017] In this description, the same reference numerals may indicate the same parts. A semiconductor package and a method of manufacturing the same according to this disclosure will now be described below.

[0018] It will be understood that when an element or layer is referred to as being "above," "over," "below," "under," or "connected to," or "coupled to," the element or layer is directly above, above, below, under, or directly connected to, or directly coupled to, the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," above, below, under, or directly connected to, or directly coupled to, the other element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same element.

[0019] For ease of description, spatial relative terms such as “above,” “over,” “on,” “above,” “below,” “under,” “below,” “below,” etc., may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0020] For the sake of brevity, conventional components of semiconductor devices may or may not be described in detail in this article.

[0021] Figure 1A A cross-sectional view illustrating a semiconductor package according to some example embodiments is shown. Figure 1B and Figure 1C The display shows Figure 1A A magnified view of part A.

[0022] Reference Figure 1A According to some example embodiments, a semiconductor package 1 may include a first redistribution substrate 100, a first semiconductor chip 200, a first molding layer 300, a second redistribution substrate 400, and an adhesive film 800. The first redistribution substrate 100 may include a lower bump pattern 110, a first redistribution pattern 150, a first bonding pad 120, and lower dielectric layers 101, 102, 103, and 104. Lower dielectric layers 101, 102, 103, and 104 may include a first lower dielectric layer 101, a second lower dielectric layer 102, a third lower dielectric layer 103, and a fourth lower dielectric layer 104.

[0023] like Figure 1A As shown, a lower bump pattern 110 may be disposed in a first lower dielectric layer 101. The first lower dielectric layer 101 may expose the bottom surface of the lower bump pattern 110. An external terminal 700 may be disposed on the bottom surface of the lower bump pattern 110. The lower bump pattern 110 may define the location where the external terminal 700 is disposed. The lower bump pattern 110 may serve as a pad for the external terminal 700. The lower bump pattern 110 may include a metallic material such as copper. The lower bump pattern 110 may not include, for example, titanium. Multiple lower bump patterns 110 may be disposed, and the multiple lower bump patterns 110 may be spaced apart from each other in a first direction D1. In this description, the first direction D1 may be parallel to the top surface of the first semiconductor chip 200, and the second direction D2 may be perpendicular to the top surface of the first semiconductor chip 200. For ease of description, the following description uses a single lower bump pattern 110 as an example.

[0024] A first lower dielectric layer 101, a second lower dielectric layer 102, a third lower dielectric layer 103, and a fourth lower dielectric layer 104 may be disposed on the lower bump pattern 110 (e.g., disposed above the lower bump pattern 110 in direction D2). The first lower dielectric layer 101 may cover the top and side surfaces of the lower bump pattern 110. The first lower dielectric layer 101 may be the lowermost dielectric layer among the first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104. The first lower dielectric layer 101 may not cover the bottom surface of the lower bump pattern 110. The bottom surface 100b of the first lower dielectric layer 101 may correspond to the bottom surface of the first redistributed substrate 100. The bottom surface 100b of the first lower dielectric layer 101 may be located at a level substantially the same as the level of the bottom surface of the lower bump pattern 110. For example, the bottom surface 100b of the first lower dielectric layer 101 may be coplanar with the bottom surface of the lower bump pattern 110. In this description, the term "horizontal" may refer to vertical horizontal, and the difference in horizontality can be measured in a direction perpendicular to the bottom surface 100b of the first lower dielectric layer 101. The first lower dielectric layer 101 may comprise an organic material such as a photosensitive polymer. In this description, the photosensitive polymer may comprise one or more of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The first lower dielectric layer 101 may be a positive photosensitive polymer, but this disclosure is not limited thereto.

[0025] The second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104 may be sequentially disposed on the first lower dielectric layer 101. The second lower dielectric layer 102 may cover the top surface of the first lower dielectric layer 101. The third lower dielectric layer 103 may cover the top surface of the second lower dielectric layer 102. The fourth lower dielectric layer 104 may cover the top surface of the third lower dielectric layer 103. The first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104 may comprise the same material as each other. The second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104 may comprise, for example, a photosensitive polymer. There may be no obvious boundary between the first lower dielectric layer 101 and the second lower dielectric layer 102, between the second lower dielectric layer 102 and the third lower dielectric layer 103, or between the third lower dielectric layer 103 and the fourth lower dielectric layer 104, but this disclosure is not limited thereto. The first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104 may have side surfaces that are vertically aligned with each other. The first redistribution substrate 100 may have a side surface 100c, which includes the side surfaces of the first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104.

[0026] A first redistribution pattern 150 may be disposed on the top surface of each of a plurality of lower bump patterns 110. The first redistribution pattern 150 may be disposed within a first lower dielectric layer 101, a second lower dielectric layer 102, a third lower dielectric layer 103, and a fourth lower dielectric layer 104. The first redistribution pattern 150 may be surrounded by the first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104. Each of the first redistribution patterns 150 may include a seed pattern 151 and a conductive pattern 153 disposed on the seed pattern 151. The seed pattern 151 may include a conductive material such as copper, titanium, or alloys thereof. The conductive pattern 153 may include a metallic material such as copper.

[0027] Each of the first redistribution patterns 150 may include a via portion 150V and a line portion 150P. The line portion 150P may be disposed on the via portion 150V (e.g., above the via portion 150V in direction D2) and connected to the via portion 150V. The line portion 150P may have a greater width or length than the via portion 150V. The line portion 150P may have a main axis extending in a first direction D1. The line portion 150P may extend parallel to the first direction D1, and the via portion 150V may protrude from the line portion 150P toward the bottom surface 100b of the first redistribution substrate 100. The first redistribution pattern 150 may be aligned to allow its via portion 150V to face the bottom surface 100b of the first redistribution substrate 100. The via portion 150V of each of the first redistribution patterns 150 may contact the top surface of one of the lower bump patterns 110 or contact the line portion 150P of the lower first redistribution pattern 150. The line portion 150P of each of the first redistribution patterns 150 can contact the first connection pad 120 or the via portion 150V of the upper first redistribution pattern 150.

[0028] For example, the via portion 150V of the first redistribution pattern 150 closest to the lower bump pattern 110 can correspondingly contact the top surface of the lower bump pattern 110. The conductive pattern 153 of the first redistribution pattern 150 may not directly contact the lower bump pattern 110. The seed pattern 151 can correspondingly be inserted between the conductive pattern 153 of the first redistribution pattern 150 and the top surface of the lower bump pattern 110. The seed pattern 151 can directly contact the top surface of the lower bump pattern 110. Alternatively, some of the via portions 150V in the first redistribution pattern 150 can correspondingly contact the top surface of the lower first redistribution pattern 150.

[0029] First connection pads 120 may be disposed on adjacent first redistribution patterns 150. Each of the first connection pads 120 may include a seed pattern and a conductive pattern disposed on the seed pattern. A first connection pad 120 may include a via portion connected to the underlying first redistribution pattern 150, and may also include a pad portion on the via portion. The pad portion may be exposed by a fourth lower dielectric layer 104. The first connection pads 120 may define the location of a lower connection terminal 250 or conductive structure 310, details of which will be described below. First connection pads 120 may be coupled to the first redistribution pattern 150 below the first connection pad 120. For example, the first connection pad 120 may contact the conductive pattern 153 of the first redistribution pattern 150 below the first connection pad 120. The first connection pads 120 may include a conductive material. For example, the first connection pads 120 may include a metal such as copper, titanium, aluminum, tungsten, or any alloy thereof. There is no limitation on the number of stacked first lower dielectric layers 101, second lower dielectric layers 102, third lower dielectric layers 103 and fourth lower dielectric layers 104 or the number of stacked first redistribution patterns 150, and these numbers can be varied.

[0030] A first semiconductor chip 200 may be mounted on the top surface 100a of a first redistributed substrate 100. The first semiconductor chip 200 may include a first chip pad 205. The first chip pad 205 may be exposed on the bottom surface of the first semiconductor chip 200. The first semiconductor chip 200 may include an integrated circuit. The integrated circuit may be disposed adjacent to the bottom surface of the first semiconductor chip 200. The integrated circuit may include memory circuitry, logic circuitry, or a combination thereof. The first chip pad 205 may be electrically connected to the integrated circuit. In this description, a component "connected to" another component may include a component physically connected to the other component, electrically connected and directly connected to the other component, or electrically connected and indirectly connected to the other component.

[0031] A lower connection terminal 250 may be disposed between a first chip pad 205 of the first semiconductor chip 200 and a first connection pad 120 of the first redistribution substrate 100, thereby electrically connecting the first chip pad 205 to the first connection pad 120. The lower connection terminal 250 may include one or more of solder, pillars, and bumps. The lower connection terminal 250 may include a conductive material such as solder material. Solder material may include, for example, tin, bismuth, lead, silver, or any alloy thereof. The first semiconductor chip 200 may be electrically connected to the first redistribution substrate 100 via the lower connection terminal 250. For example, the lower connection terminal 250 may be electrically connected to at least one of the first redistribution patterns 150 of the first redistribution substrate 100.

[0032] A conductive structure 310 may be disposed on the top surface 100a of the first redistribution substrate 100. The conductive structure 310 may be disposed on the first connection pad 120 and may be coupled to both the first connection pad 120 and the connection terminal 405 of the second redistribution substrate 400 as described in detail below. For example, the conductive structure 310 may have a top surface 310a in contact with the connection terminal 405 and the adhesive film 800, and may also have a bottom surface in contact with the first connection pad 120. The conductive structure 310 may be spaced apart from the first semiconductor chip 200 in a first direction D1. When viewed in a plane, the conductive structure 310 may be disposed on an edge region of the first redistribution substrate 100. For example, the conductive structure 310 may extend in a second direction D2, thereby connecting the first redistribution substrate 100 to the second redistribution substrate 400. The conductive structure 310 may be electrically connected to the first semiconductor chip 200 through the first redistribution substrate 100. The conductive structure 310 may comprise a metal such as copper.

[0033] A first bottom filler layer 230 may be disposed between the first semiconductor chip 200 and the top surface 100a of the first redistribution substrate 100. The first bottom filler layer 230 may seal the lower connection terminal 250. The first bottom filler layer 230 may include a dielectric polymer such as an epoxy polymer.

[0034] A first molding layer 300 may be disposed on the first redistribution substrate 100 to cover the first semiconductor chip 200. For example, the first molding layer 300 may cover the top surface and side surfaces of the first semiconductor chip 200, as well as the side surfaces of the first bottom fill layer 230. In this case, the top surface of the semiconductor chip 200 may be defined as a surface remote from the first redistribution substrate 100, such as... Figure 1A As shown in the diagram. The first molding layer 300 can fill the gap between the first semiconductor chip 200 and the conductive structure 310, as well as the gaps between the plurality of conductive structures 310. The first molding layer 300 can cover the uppermost dielectric layer among the first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104. The uppermost dielectric layer can be the fourth lower dielectric layer 104. The first molding layer 300 can include a dielectric polymer such as an epoxy molding compound. Alternatively, the first bottom fill layer 230 can be omitted, and the first molding layer 300 can also extend into the gap between the first semiconductor chip 200 and the first redistributed substrate 100, thereby sealing the lower connection terminal 250.

[0035] The first molding layer 300 may have a top surface 300a located at a level higher than the top surface of the first semiconductor chip 200. The top surface 300a of the first molding layer 300 may be located at a level substantially the same as the top surface 310a of the conductive structure 310. For example, the top surface 300a of the first molding layer 300 may be coplanar with the top surface 310a of the conductive structure 310. The first molding layer 300 may have a side surface 300c vertically aligned with a corresponding side surface 100c in the first redistribution substrate 100. In other words, the side surface 300c of the first molding layer 300 may be coplanar with a corresponding side surface 100c in the first redistribution substrate 100.

[0036] External terminals 700 may be disposed on the bottom surface 100b of the first redistribution substrate 100. For example, external terminals 700 may be disposed on the bottom surface of the lower bump pattern 110 and may be electrically connected to the lower bump pattern 110. External terminals 700 may directly contact the lower bump pattern 110. Therefore, external terminals 700 may be electrically connected to the first semiconductor chip 200 via the first redistribution pattern 150 of the first redistribution substrate 100 and the lower connection terminal 250 of the first semiconductor chip 200. External terminals 700 may include solder, bumps, pillars, or combinations thereof. External terminals 700 may include solder material. Figure 1A As shown, the pitch between the multiple external terminals 700 can be greater than the pitch between the multiple lower connection terminals 250.

[0037] An adhesive film 800 may be disposed on the top surface 300a of the first molding layer 300 and the top surface 310a of the conductive structure 310. The adhesive film 800 may extend parallel to the first direction D1, thereby covering the top surface 300a of the first molding layer 300 and the top surface 310a of the conductive structure 310. The adhesive film 800 will be discussed in further detail below.

[0038] The second redistribution substrate 400 may be disposed on the adhesive film 800. The second redistribution substrate 400 may include a second lower connection pad 410, a second upper connection pad 420, a second redistribution pattern 450, a first upper dielectric layer 401, a second upper dielectric layer 402, a third upper dielectric layer 403, and a connection terminal 405.

[0039] The second lower connection pad 410 can be disposed within the first upper dielectric layer 401. The first upper dielectric layer 401 can cover the side surfaces of the second lower connection pad 410, but may not cover the bottom surface of the second lower connection pad 410. This configuration can expose the bottom surface of the second lower connection pad 410. A connection terminal 405 can be disposed on the bottom surface of the second lower connection pad 410. The second lower connection pad 410 can be vertically aligned with the connection terminal 405 and the conductive structure 310. The second lower connection pad 410 can define the location where the connection terminal 405 is disposed. The second lower connection pad 410 can include a metallic material such as copper. The second lower connection pad 410 may not include, for example, titanium. Multiple second lower connection pads 410 can be disposed, and the multiple second lower connection pads 410 can be spaced apart from each other in the first direction D1.

[0040] A first upper dielectric layer 401, a second upper dielectric layer 402, and a third upper dielectric layer 403 may be disposed on the second lower connection pad 410 (e.g., disposed above the second lower connection pad 410 in direction D2). The first upper dielectric layer 401 may cover a portion of the side surface and the top surface of the second lower connection pad 410. The first upper dielectric layer 401 may be the lowermost dielectric layer among the first upper dielectric layer 401, the second upper dielectric layer 402, and the third upper dielectric layer 403. The first upper dielectric layer 401 may not cover the bottom surface of the second lower connection pad 410. The first upper dielectric layer 401 may have a bottom surface 400b corresponding to the bottom surface of the second redistribution substrate 400. The bottom surface 400b of the first upper dielectric layer 401 may be coplanar with the bottom surface of the second lower connection pad 410. The first upper dielectric layer 401 may include an organic material such as a photopolymer. The first upper dielectric layer 401 may be a positive photosensitive polymer, but this disclosure is not limited thereto.

[0041] The second upper dielectric layer 402 and the third upper dielectric layer 403 may be sequentially disposed on the first upper dielectric layer 401. The second upper dielectric layer 402 may cover the top surface of the first upper dielectric layer 401. The third upper dielectric layer 403 may cover the top surface of the second upper dielectric layer 402. The second upper dielectric layer 402 and the third upper dielectric layer 403 may comprise the same material as the first upper dielectric layer 401. The second upper dielectric layer 402 and the third upper dielectric layer 403 may comprise, for example, a photosensitive polymer. There may be no obvious boundary between the first upper dielectric layer 401 and the second upper dielectric layer 402, or between the second upper dielectric layer 402 and the third upper dielectric layer 403, but this disclosure is not limited thereto. The first upper dielectric layer 401, the second upper dielectric layer 402, and the third upper dielectric layer 403 may have sidewalls that are vertically aligned with each other (e.g., coplanar). The second redistribution substrate 400 may have a side surface 400c, which includes sidewalls of a first upper dielectric layer 401, a second upper dielectric layer 402, and a third upper dielectric layer 403.

[0042] The second redistribution pattern 450 may be disposed on the top surface of each of the plurality of second lower connection pads 410. The second redistribution pattern 450 may be disposed within a first upper dielectric layer 401, a second upper dielectric layer 402, and a third upper dielectric layer 403. The second redistribution pattern 450 may be surrounded by the first upper dielectric layer 401, the second upper dielectric layer 402, and the third upper dielectric layer 403. Each of the second redistribution patterns 450 may include a seed pattern 451 and a conductive pattern 453 disposed on the seed pattern 451. The seed pattern 451 may include a conductive material such as copper, titanium, or alloys thereof. The conductive pattern 453 may include a metallic material such as copper.

[0043] Each of the second redistribution patterns 450 may include a through-hole portion 450V and a line portion 450P. Each through-hole portion 450V and line portion 450P of the second redistribution pattern 450 may be substantially the same as the through-hole portion 150V and line portion 150P of each of the first redistribution patterns 150.

[0044] A line portion 450P may be disposed on and connected to a via portion 450V. The line portion 450P may have a spindle extending in a first direction D1. The line portion 450P may extend parallel to the first direction D1, and the via portion 450V may protrude from the line portion 450P toward the bottom surface 400b of the second redistribution substrate 400. Each of the second redistribution patterns 450 may be aligned to allow its via portion 450V to face the bottom surface 400b of the second redistribution substrate 400. The via portion 450V of each of the second redistribution patterns 450 may contact the top surface of the second lower connection pad 410 or the line portion 450P of the lower second redistribution pattern 450. The line portion 450P of each of the second redistribution patterns 450 may contact the second upper connection pad 420 or the via portion 450V of the upper second redistribution pattern 450.

[0045] For example, the via portion 450V of the second redistribution pattern 450 closest to the second lower connection pad 410 can correspondingly contact the top surface of the second lower connection pad 410. The conductive pattern 453 of the second redistribution pattern 450 may not directly contact the second lower connection pad 410. The seed pattern 451 can correspondingly be inserted between the conductive pattern 453 of the second redistribution pattern 450 and the top surface of the second lower connection pad 410. The seed pattern 451 can directly contact the top surface of the second lower connection pad 410. Alternatively, some of the via portions 450V in the second redistribution pattern 450 can correspondingly contact the top surface of the lower redistribution pattern 450.

[0046] The second upper connection pad 420 may be disposed on the third upper dielectric layer 403 and within the second molding layer 600, which will be discussed below. The third upper dielectric layer 403 may be located on the uppermost dielectric layer of the first upper dielectric layer 401, the second upper dielectric layer 402, and the third upper dielectric layer 403. The second molding layer 600 may cover the side surfaces of the second upper connection pad 420 but may not cover the top surface of the second upper connection pad 420. The second upper connection pad 420 may define the location of the upper connection terminal 550. The second upper connection pad 420 may be coupled to an adjacent second redistribution pattern 450. For example, the second upper connection pad 420 may contact the conductive pattern 453 of the adjacent second redistribution pattern 450. The second upper connection pad 420 may include a conductive material. For example, the second upper connection pad 420 may include a metal such as copper, titanium, aluminum, tungsten, or any alloy thereof. The number of the first dielectric layer 401, the second dielectric layer 402, and the third dielectric layer 403, as well as the number of the second redistribution pattern 450, can be varied and are not limited to those shown.

[0047] In an embodiment, the via portion 450V of the second redistribution pattern 450 can be aligned to face the top surface 400a of the second redistribution substrate 400. For example, the via portion 450V can be disposed on and connected to the line portion 450P. The line portion 450P can extend parallel to the first direction D1, and the via portion 450V can protrude from the line portion 450P toward the top surface 400a of the second redistribution substrate 400. The line portion 450P of each of the second redistribution patterns 450 can contact the second lower connection pad 410 or the via portion 450V of the lower second redistribution pattern 450. The via portion 450V of each of the second redistribution patterns 450 can contact the second upper connection pad 420 or the line portion 450P of the upper second redistribution pattern 450. For example, the second upper connection pad 420 may include a pad portion and a via portion disposed on the pad portion. The pad portion of the second upper connection pad 420 can be connected to a via portion 450V of one of the adjacent second redistribution patterns 450. In this case, the upper connection terminal 550 can be omitted on the second upper connection pad 420. Therefore, the second upper connection pad 420 can contact the second chip pad 505 of the second semiconductor chip 500, which will be discussed below.

[0048] According to some example embodiments, the thickness H1 of the first redistributed substrate 100 in the second direction D2 may be equal to or greater than the thickness H2 of the second redistributed substrate 400 in the second direction D2. Values ​​of approximately 5 μm to approximately 50 μm may be given as the thickness H1 of the first redistributed substrate 100 in the second direction D2 and the thickness H2 of the second redistributed substrate 400 in the second direction D2.

[0049] The second semiconductor chip 500 may be mounted on the top surface 400a of the second redistributed substrate 400. The second semiconductor chip 500 may include a second chip pad 505. The second chip pad 505 may be exposed on the bottom surface of the second semiconductor chip 500. The second semiconductor chip 500 may include an integrated circuit. The integrated circuit may be disposed adjacent to the bottom surface of the second semiconductor chip 500. The integrated circuit may include memory circuitry, logic circuitry, or a combination thereof. The second chip pad 505 may be electrically connected to the integrated circuit. In this description, a component "connected to" another component may include a component physically connected to the other component, electrically connected and directly connected to the other component, or electrically connected and indirectly connected to the other component.

[0050] An upper connection terminal 550 may be disposed between a second chip pad 505 of the second semiconductor chip 500 and a second upper connection pad 420 of the second redistribution substrate 400, thereby electrically connecting the second chip pad 505 to the second upper connection pad 420. The upper connection terminal 550 may be substantially the same as the lower connection terminal 250. The second semiconductor chip 500 may be electrically connected to the second redistribution substrate 400 via the upper connection terminal 550. For example, the upper connection terminal 550 may be electrically connected to at least one of the second redistribution patterns 450 of the second redistribution substrate 400.

[0051] A second molding layer 600 may be disposed on the second redistribution substrate 400 to cover the second semiconductor chip 500. For example, the second molding layer 600 may cover the top surface and side surfaces of the second semiconductor chip 500. The second molding layer 600 may also extend into the gap between the second semiconductor chip 500 and the second redistribution substrate 400 to seal the upper connection terminal 550. The second molding layer 600 may cover the uppermost dielectric layer among the first upper dielectric layer 401, the second upper dielectric layer 402, and the third upper dielectric layer 403. The uppermost dielectric layer may be the third upper dielectric layer 403. The second molding layer 600 may have a side surface 600c that is vertically aligned with the corresponding side surface 400c of the second redistribution substrate 400. The side surface 600c of the second molding layer 600 may be coplanar with the corresponding side surface 400c of the second redistribution substrate 400. The second molding layer 600 may include the same material as the first molding layer 300. The second molding layer 600 may include a dielectric polymer such as an epoxy-based molding compound. Alternatively, the bottom filler layer may also be interposed in the gap between the second redistribution substrate 400 and the second semiconductor chip 500.

[0052] Reference Figure 1B A connecting terminal 405 can be inserted between the conductive structure 310 and the second lower connecting pad 410. The connecting terminal 405 can be vertically aligned with the conductive structure 310. The connecting terminal 405 can contact the top surface 310a of the conductive structure 310 and the bottom surface 410b of the second lower connecting pad 410, and can electrically connect the conductive structure 310 to the second redistribution pattern 450. The connecting terminal 405 can penetrate the adhesive film 800. The connecting terminal 405 can have a side surface surrounded by the adhesive film 800. The side surface of the connecting terminal 405 can directly contact the adhesive film 800.

[0053] The connecting terminal 405 may include a first portion 405U and a second portion 405B. The first portion 405U may be disposed on and connected to the second portion 405B. The second portion 405B may surround the lower portion of the first portion 405U. The first portion 405U may include solder, bumps, pillars, or any combination thereof. The first portion 405U may include a conductive material such as a metal. The second portion 405B may include a metallic material such as tin or indium. For example, the first portion 405U may include the same material as the second portion 405B. For another example, the first portion 405U may include a material different from the second portion 405B. For example, the first portion 405U and the second portion 405B may have a clear boundary therebetween, but this disclosure is not limited thereto.

[0054] According to some example embodiments, such as Figure 1B As shown, the maximum width W1 of the connecting terminal 405 in the first direction D1 can be smaller than the width W2 of the conductive structure 310 in the first direction D1. For example, a value of approximately 0.4 to approximately 0.8 can be given as the ratio of the maximum width W1 of the connecting terminal 405 in the first direction D1 to the width W2 of the conductive structure 310 in the first direction D1. Therefore, the top surface 310a of the conductive structure 310 can contact both the connecting terminal 405 and the adhesive film 800.

[0055] According to some example embodiments, such as Figure 1C As shown, the maximum width W1' of the connecting terminal 405 in the first direction D1 can be substantially the same as the width W2 of the conductive structure 310 in the first direction D1. Therefore, the second portion 405B of the connecting terminal 405 can cover the entire top surface 310a of the conductive structure 310. The top surface 310a of the conductive structure 310 can contact the connecting terminal 405, but can avoid contacting the adhesive film 800.

[0056] Return to reference Figure 1AThe adhesive film 800 can be inserted between the first molding layer 300 and the second redistribution substrate 400. The adhesive film 800 can extend parallel to the first direction D1 and can fill the gap between the top surface 300a of the first molding layer 300 and the bottom surface 400b of the second redistribution substrate 400. The adhesive film 800 can cover the entire top surface 300a of the first molding layer 300. The adhesive film 800 can surround the side surface of the connection terminal 405 and can seal the connection terminal 405. The adhesive film 800 can contact the top surface 300a of the first molding layer 300, the top surface 310a of the conductive structure 310, the bottom surface 400b of the second redistribution substrate 400, the bottom surface 410b of the second upper connection pad 410, and the side surface of the connection terminal 405. The adhesive film 800 can include a dielectric material. For example, the adhesive film 800 can include one or more of adhesive polymers, thermosetting polymers, and dielectric polymers. The adhesive film 800 can be used to attach and fix the second redistribution substrate 400 to the first molding layer 300.

[0057] The adhesive film 800 may have a side surface 800c that is vertically aligned with the side surface 100c of the first redistribution substrate 100, the side surface 400c of the second redistribution substrate 400, the side surface 300c of the first molding layer 300, and the side surface 600c of the second molding layer 600. For example, the side surface 800c of the adhesive film 800 may be coplanar with both the side surface 400c of the second redistribution substrate 400 and the side surface 300c of the first molding layer 300. The width W0 of the adhesive film 800 in the first direction D1 may be the same as the width of the first redistribution substrate 100 in the first direction D1. Although not shown, according to some example embodiments, the adhesive film may also be disposed on the second molding layer 600. A redistribution substrate or a semiconductor package may also be disposed on the adhesive film. Thus, a semiconductor package comprising a plurality of stacked packages can be provided. Figure 2 A cross-sectional view illustrating a semiconductor package according to some example embodiments is shown. Those discussed above will not be described again, but the differences will be discussed in detail below.

[0058] Reference Figure 2 According to some example embodiments, the semiconductor package 2 may include a first redistribution substrate 100, a first semiconductor chip 200, a first molding layer 300, a second redistribution substrate 400, a second semiconductor chip 500, and an adhesive film 800, and may also include a bonding substrate 320. The first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the second semiconductor chip 500, and the adhesive film 800 can be coupled with... Figure 1A and Figure 1B The ones discussed in the text are basically the same.

[0059] A bonding substrate 320 may be disposed on the first redistributed substrate 100. The bonding substrate 320 may have a substrate via 390 penetrating therethrough. For example, the substrate via 390 may be formed to penetrate the top and bottom surfaces of a printed circuit board that may constitute the bonding substrate 320. When viewed in plan view, the substrate via 390 may be formed on the central portion of the first redistributed substrate 100. A first semiconductor chip 200 may be disposed in the substrate via 390 of the bonding substrate 320. The first semiconductor chip 200 may be spaced apart from the inner wall of the bonding substrate 320.

[0060] The bonding substrate 320 may include a base layer 327 and conductive structures 321, 323, and 325. The base layer 327 may include a single layer or multiple stacked layers. The base layer 327 may include a dielectric material. For example, the base layer 327 may include a carbon-based material, ceramic, or polymer. A substrate via 390 may penetrate the base layer 327. The conductive structures 321, 323, and 325 may be disposed in the base layer 327. The conductive structures 321, 323, and 325 may include a first pad 321, a conductive via 325, and a second pad 323. The first pad 321 may be exposed on the top surface of the bonding substrate 320, and the second pad 323 may be exposed on the bottom surface of the bonding substrate 320. The conductive via 325 may be disposed between the first pad 321 and the second pad 323. The conductive via 325 may penetrate the base layer 327 and may be coupled to the first pad 321 and the second pad 323. The second pad 323 can be electrically connected to the first pad 321 via a conductive via 325. The first pad 321, the second pad 323, and the conductive via 325 can be vertically aligned with each other, but this disclosure is not limited thereto. The conductive structures 321, 323, and 325 can include metals. The conductive structures 321, 323, and 325 can include, for example, copper, aluminum, tungsten, titanium, tantalum, iron, or any alloy thereof.

[0061] A connecting bump 260 may be disposed between the first redistribution substrate 100 and the connecting substrate 320. The connecting bump 260 may be interposed between the second pad 323 and its corresponding first connecting pad 120, and coupled to the first pad 321 and the corresponding first connecting pad 120 of the second pad 323. Conductive structures 321, 323, and 325 may be electrically connected to the first redistribution substrate 100 via the connecting bump 260. The connecting bump 260 may include one or more of solder balls, bumps, and pillars. The connecting bump 260 may include a metallic material. A second underfill layer 240 may be disposed in the gap between the first redistribution substrate 100 and the connecting substrate 320, thereby sealing the connecting bump 260. The second underfill layer 240 may include a dielectric polymer.

[0062] The first molding layer 300 may fill the substrate aperture 390 of the connecting substrate 320. For example, the first molding layer 300 may fill the gap between the first semiconductor chip 200 and the connecting substrate 320. The first molding layer 300 may cover the top and side surfaces of the first semiconductor chip 200, the side surface of the first bottom filler layer 230, the side surface of the second bottom filler layer 240, and the inner wall of the connecting substrate 320. The top surface 300a of the first molding layer 300 may be located at the same level as the top surface 320a of the connecting substrate 320. For example, the top surface 300a of the first molding layer 300 may be coplanar with the top surface 320a of the connecting substrate 320. The first molding layer 300 may include a dielectric polymer such as an epoxy polymer. For example, the first molding layer 300 may include an adhesive dielectric film such as an Ajinomoto composite film (ABF).

[0063] An adhesive film 800 may be disposed on the top surface 300a of the first molding layer 300 and the top surface 320a of the connecting substrate 320. The adhesive film 800 may extend parallel to the first direction D1 and may cover the top surface 300a of the first molding layer 300 and the top surface 320a of the connecting substrate 320. The side surface 800c of the adhesive film 800 may be vertically aligned with the side surface 320c of the connecting substrate 320. For example, the side surface 800c of the adhesive film 800 may be coplanar with the side surface 320c of the connecting substrate 320.

[0064] A connection terminal 405 may be disposed on a first pad 321 of the connection substrate 320. The connection terminal 405 may be vertically aligned with the first pad 321. The connection terminal 405 may be coupled to the first pad 321, and thus electrically connect the second redistribution substrate 400 to the connection substrate 320. The connection terminal 405 may be surrounded by an adhesive film 800.

[0065] Figure 3 A cross-sectional view illustrating a semiconductor package according to some example embodiments is shown. Those discussed above will not be described again, but the differences will be discussed in detail below.

[0066] Reference Figure 3 According to some example embodiments, the semiconductor package 3 may include a first redistribution substrate 100, a first semiconductor chip 200, a first molding layer 300, a second redistribution substrate 400, and an adhesive film 800. The first molding layer 300, the second redistribution substrate 400, and the adhesive film 800 can be coupled with… Figure 1A and Figure 1B The ones discussed in the text are essentially the same. Conversely, it is possible to neither provide a first bottom filler layer 230 nor a lower connection terminal 250.

[0067] The first redistribution substrate 100 may include a lower bump pattern 110, a first redistribution pattern 150, a first bonding pad 120, and lower dielectric layers 101, 102, 103, and 104. The lower dielectric layers 101, 102, 103, and 104 may include a first lower dielectric layer 101, a second lower dielectric layer 102, a third lower dielectric layer 103, and a fourth lower dielectric layer 104. The lower bump pattern 110 and the lower dielectric layers 101, 102, 103, and 104 may be coupled with… Figure 1A and Figure 1B The ones discussed in the text are basically the same.

[0068] A first redistribution pattern 150 may be disposed on the top surface of each of a plurality of lower bump patterns 110. The first redistribution pattern 150 may be disposed within a first lower dielectric layer 101, a second lower dielectric layer 102, a third lower dielectric layer 103, and a fourth lower dielectric layer 104. The first redistribution pattern 150 may be surrounded by the first lower dielectric layer 101, the second lower dielectric layer 102, the third lower dielectric layer 103, and the fourth lower dielectric layer 104. Each of the first redistribution patterns 150 may include a conductive pattern 153 and a seed pattern 151 disposed on the conductive pattern 153. The seed pattern 151 may include a conductive material such as copper, titanium, or alloys thereof. The conductive pattern 153 may include a metallic material such as copper.

[0069] Each of the first redistribution patterns 150 may include a via portion 150V and a line portion 150P. The via portion 150V may be disposed on and connected to the line portion 150P. The line portion 150P may have a greater width or length than the via portion 150V. The line portion 150P may have a main axis extending in a first direction D1. The line portion 150P may extend parallel to the first direction D1, and the via portion 150V may protrude from the line portion 150P toward the top surface 100a of the first redistribution substrate 100. The first redistribution pattern 150 may be aligned to allow its via portion 150V to face the top surface 100a of the first redistribution substrate 100. The line portion 150P of each of the first redistribution patterns 150 may contact the top surface of one of the lower bump patterns 110 or contact the via portion 150V of the lower first redistribution pattern 150. The via portion 150V of each of the first redistribution patterns 150 can contact the first connection pad 120 or the line portion 150P of the first redistribution pattern 150 above it.

[0070] For example, the line portion 150P closest to the lower bump pattern 110 in the first redistribution pattern 150 can contact the corresponding top surface of the lower bump pattern 110. The conductive pattern 153 closest to the lower bump pattern 110 in the first redistribution pattern 150 can directly contact the corresponding top surface of the lower bump pattern 110. The seed pattern 151 can be correspondingly inserted between the conductive pattern 153 of the first redistribution pattern 150 and the conductive pattern 153 of the upper first redistribution pattern 150. Alternatively, some of the through-hole portions 150V in the first redistribution pattern 150 can contact the corresponding bottom surface of the upper first redistribution pattern 150.

[0071] A first connection pad 120 may be disposed on the fourth lower dielectric layer 104. The first connection pad 120 may be interposed between the conductive structure 310 and the first redistribution pattern 150, thereby electrically connecting the conductive structure 310 to the first redistribution pattern 150. The first connection pad 120 may contact a via portion 150V of at least one of the first redistribution patterns 150. The first connection pad 120 may comprise a metal such as copper, titanium, aluminum-tungsten, or any alloy thereof.

[0072] A first semiconductor chip 200 may be mounted on a top surface 100a of a first redistribution substrate 100. The first semiconductor chip 200 may include a first chip pad 205. The first chip pad 205 may be exposed on a bottom surface of the first semiconductor chip 200. The first semiconductor chip 200 may include an integrated circuit. The integrated circuit may be disposed adjacent to the bottom surface of the first semiconductor chip 200. The integrated circuit may include memory circuitry, logic circuitry, or a combination thereof. The first chip pad 205 may be electrically connected to the integrated circuit. In this description, a component “connected to” another component may include a component physically connected to the other component, electrically connected and directly connected to the other component, or electrically connected and indirectly connected to the other component. The first chip pad 205 may be connected to at least one of the first redistribution patterns 150 included in the first redistribution substrate 100. For example, the first chip pad 205 may have a bottom surface that contacts a via portion 150V of at least one of the first redistribution patterns 150. Therefore, the first semiconductor chip 200 may be electrically connected to the first redistribution substrate 100.

[0073] Figure 4 A cross-sectional view illustrating a semiconductor package according to some example embodiments is shown. Those discussed above will not be described again, but the differences will be discussed in detail below.

[0074] Reference Figure 4According to some example embodiments, the semiconductor package 4 may include a first redistribution substrate 100, a first semiconductor chip 200, a first molding layer 300, a second redistribution substrate 400, a second semiconductor chip 500, and an adhesive film 800, and may also include a bonding substrate 320. The first redistribution substrate 100 and the first semiconductor chip 200 may be coupled with... Figure 3 The first redistribution substrate 100 and the first semiconductor chip 200 discussed herein are substantially the same. The first molding layer 300 can be coupled with... Figure 2 The first molding layer 300 discussed earlier is essentially the same. The second redistribution substrate 400 and the second semiconductor chip 500 can be... Figure 1A and Figure 1B The second redistributed substrate 400 and the second semiconductor chip 500 discussed herein are essentially the same. The adhesive film 800 can be coupled with… Figure 2 The adhesive film 800 discussed in the previous section is essentially the same. The connecting substrate 320 can be connected to... Figure 2 The connection substrate 320 discussed in the article is similar.

[0075] A bonding substrate 320 may be disposed on the first redistributed substrate 100. The bonding substrate 320 may have a substrate via 390 penetrating therethrough. For example, the substrate via 390 may be formed to penetrate the top and bottom surfaces of a printed circuit board constituting the bonding substrate 320. When viewed in a planar view, the substrate via 390 may be formed on the central portion of the first redistributed substrate 100. A first semiconductor chip 200 may be disposed in the substrate via 390 of the bonding substrate 320. The first semiconductor chip 200 may be spaced apart from the inner wall of the bonding substrate 320.

[0076] The connection substrate 320 may include a base layer 327 and conductive structures 321, 323, and 325. The conductive structures 321, 323, and 325 may include a first pad 321, a conductive via 325, and a second pad 323. Neither connection bumps nor an underfill layer may be provided between the connection substrate 320 and the first redistribution substrate 100. The connection substrate 320 may have a bottom surface located at the same horizontal height as the top surface 100a of the first redistribution substrate 100. For example, the second pad 323 may be connected to at least one of the first redistribution patterns 150. In such a configuration, the second pad 323 may contact a via portion 150V of at least one of the first redistribution patterns 150.

[0077] [Manufacturing Method]

[0078] Figures 5 to 10 , Figure 12 and Figure 13 A cross-sectional view is shown illustrating a method of manufacturing a semiconductor package according to some example embodiments. Figure 11The display shows Figure 10 A magnified view of part B.

[0079] Reference Figure 5 A first initial redistribution substrate 100p can be formed on a carrier substrate 900. A release layer 910 can be interposed between the carrier substrate 900 and the lower bump pattern 110 and between the carrier substrate 900 and the first initial lower dielectric layer 101p. The release layer 910 can attach the first initial redistribution substrate 100p to the carrier substrate 900. The formation of the first initial redistribution substrate 100p may include: forming a seed layer; forming a resist pattern with openings on the seed layer; using the seed layer as an electrode to form a conductive layer in the openings; removing the resist pattern; patterning the seed layer; depositing a dielectric layer; and performing a patterning process.

[0080] For example, a seed layer may be formed on the release layer 910. The seed layer may cover the top surface of the release layer 910. A deposition process may be performed to form the seed layer. The seed layer may include a conductive material. For example, the seed layer may include copper, titanium, or alloys thereof.

[0081] An open resist pattern can be formed on the seed layer. The opening can define the shape of the lower bump pattern 110. The opening of the resist pattern can expose the top surface of the seed layer. The resist pattern can include a photoresist material.

[0082] The seed layer in the opening can be used as an electrode to form the lower bump pattern 110. The lower bump pattern 110 can be formed by performing an electroplating process using the seed layer as an electrode. The electroplating process can be terminated before the lower bump pattern 110 extends to the top surface of the resist pattern. A stripping process can be performed to remove the resist pattern. Therefore, the seed layer can be exposed from the outside under the resist pattern.

[0083] The exposed seed layer can be patterned through an etching process. The top surface of the release layer 910 can be exposed between multiple lower bump patterns 110. A first initial lower dielectric layer 101p can be formed on the lower bump patterns 110. The first initial lower dielectric layer 101p can conformally cover the exposed release layer 910 and the top and side surfaces of the lower bump patterns 110. The first initial lower dielectric layer 101p can be formed by a coating process such as spin coating or slot coating. The first initial lower dielectric layer 101p can be patterned to form vias, where via portions of a first redistribution pattern 150 will be formed. The first initial lower dielectric layer 101p can be rigidly cured through a curing process. The above process can be repeated to form a first initial redistribution substrate 100p comprising a stacked first initial lower dielectric layer 101p, a second initial lower dielectric layer 102p, a third initial lower dielectric layer 103p, and a fourth initial lower dielectric layer 104p. A first connection pad 120 can be formed on the first initial redistribution substrate 100p. The first connection pad 120 can be exposed on the fourth initial lower dielectric layer 104p.

[0084] Reference Figure 6 Conductive structures 310 can be formed on the top surface of some of the exposed first connection pads 120. The conductive structures 310 can be formed using the same method as used to form the lower bump pattern 110 of the first initial redistribution substrate 100p. For example, a resist pattern with openings can be formed on the first initial redistribution substrate 100p. An electroplating process can be performed to fill the openings, and the resist pattern can be removed to form the conductive structures 310. The conductive structures 310 can be formed such that each has a relatively small width in the first direction D1 and a relatively large length in the second direction D2, such as... Figure 6 As shown in the image.

[0085] Reference Figure 7A first semiconductor chip 200 can be mounted on a first initial redistribution substrate 100p. For example, the first semiconductor chip 200 can be disposed on the first initial redistribution substrate 100p. In this step, the first semiconductor chip 200 may include a first chip pad 205, which may face the first initial redistribution substrate 100p. The first chip pad 205 may be aligned correspondingly with a first connection pad 120. A lower connection terminal 250 may be formed on a corresponding first connection pad 120. The lower connection terminal 250 may contact the corresponding first chip pad 205. The first semiconductor chip 200 may be electrically connected to a first redistribution pattern 150 through the lower connection terminal 250. A first underfill layer 230 may be formed to fill the gap between the first semiconductor chip 200 and the first initial redistribution substrate 100p. The first underfill layer 230 may surround and seal the lower connection terminal 250.

[0086] Reference Figure 8 A first initial molding layer 300p can be formed on a first initial redistribution substrate 100p to cover the first semiconductor chip 200. The first initial molding layer 300p can fill the gaps between conductive structures 310 and the gaps between the first semiconductor chip 200 and the conductive structures 310. A planarization process, such as chemical mechanical polishing (CMP), can be performed on the top surface 300a of the first initial molding layer 300p. The planarization process can continue until the top surface 310a of the conductive structures 310 is exposed. Therefore, the top surface 300a of the first initial molding layer 300p can be coplanar with the top surface 310a of the conductive structures 310.

[0087] Reference Figure 9 and Figure 10An adhesive film 800 can be formed on the top surface 300a of the first initial molding layer 300p and the top surface 310a of the conductive structure 310. The adhesive film 800 can contact and adhere to the top surfaces 300a of the first initial molding layer 300p and the top surface 310a of the conductive structure 310. For example, the adhesive film 800 may comprise a photocurable resin or a thermocurable resin and can be attached in a non-cured state. A second initial redistribution substrate 400p can be formed on the adhesive film 800. In this step, the second initial redistribution substrate 400p may comprise a second redistribution pattern 450 and a first portion 405U of the connection terminal, which will be discussed below. The second initial redistribution substrate 400p can be formed by a method substantially the same as that used to form the first initial redistribution substrate 100p. The second initial redistribution substrate 400p can be fabricated in a space separate from the space used to fabricate the first initial redistribution substrate 100p. The first initial redistribution substrate 100p and the second initial redistribution substrate 400p can be formed simultaneously in different spaces. The second initial redistribution substrate 400p can be positioned to allow the first portion 405U to face the top surface of the adhesive film 800. The first portion 405U can be vertically aligned with the corresponding conductive structure 310.

[0088] Typically, increased process time increases manufacturing costs, and warpage defects are likely to occur when complex subsequent processes are performed on the first initial redistribution substrate 100p formed in an early stage of manufacturing. According to some example embodiments of this disclosure, the first initial redistribution substrate 100p and the second initial redistribution substrate 400p can be formed in different spaces and can be fixed to each other by an adhesive film 800. Therefore, compared to forming the first initial redistribution substrate 100p and then the second initial redistribution substrate 400p, the example embodiments can reduce process steps, reduce manufacturing costs, and improve product reliability. Furthermore, in the case of forming the first initial redistribution substrate 100p and then the second initial redistribution substrate 400p, if a defect occurs in a portion of the second initial redistribution substrate 400p during manufacturing, it may be necessary to discard the first semiconductor chip 200 mounted at the location corresponding to said portion. According to some example embodiments of this disclosure, the second initial redistribution substrate 400p can be manufactured separately, and defect inspection can be performed before the second initial redistribution substrate 400p is fixed to the first initial redistribution substrate 100p. In this case, the first initial redistribution substrate 100p can be used to set dummy chips in the region corresponding to the defect location of the second initial redistribution substrate 400p, thus preventing the consumption of good chips. Therefore, manufacturing costs can be effectively reduced.

[0089] Reference Figure 10 and Figure 11 Pressure can be applied to the top surface of the second initial redistribution substrate 400p, so that the adhesive film 800 can adhere to the second initial redistribution substrate 400p. When the adhesive film 800 is in a flexible state, this pressure can allow the adhesive film 800 to accommodate the first portion 405U.

[0090] Under specific pressure conditions, heat can be applied to the adhesive film 800. The adhesive film 800 may contain conductive particles 801. Heat and pressure can force the conductive particles 801 to flow and aggregate within the adhesive film 800. For example, the conductive particles 801 may aggregate between the conductive structure 310 and the first portion 405U. The conductive particles 801 may adhere to the surface of the first portion 405U and the top surface 310a of the conductive structure 310, thereby forming a... Figure 1B and Figure 1C The second portion 405B is shown. Therefore, a connection terminal 405 comprising the first portion 405U and the second portion 405B can be formed. Some of the conductive particles 801 may not aggregate but may remain in the adhesive film 800. The adhesive film 800 may have some conductive particles 801 on its portion vertically stacked with the cross-section or on the first semiconductor chip 200 not adjacent to the first portion 405U of the connection terminal 405. The remaining conductive particles 801 may not be electrically connected to the first portion 405U of the connection terminal 405.

[0091] Reference Figure 12 A second semiconductor chip 500 can be mounted on the second initial redistribution substrate 400p. For example, the second semiconductor chip 500 can be disposed on the second initial redistribution substrate 400p. In this step, the second semiconductor chip 500 may include a second chip pad 505, which may face the second initial redistribution substrate 400p. The second chip pad 505 may be aligned with a corresponding second upper connection pad 420. An upper connection terminal 550 may be formed on the corresponding second upper connection pad 420. The upper connection terminal 550 may contact the corresponding second chip pad 505. The second semiconductor chip 500 may be electrically connected to the second redistribution pattern 450 through the upper connection terminal 550. A second initial molding layer 600p may be formed on the second initial redistribution substrate 400p to cover the second semiconductor chip 500. The second initial molding layer 600p may cover the top surface and side surfaces of the second semiconductor chip 500 and the top surface of the second initial redistribution substrate 400p.

[0092] Reference Figure 13The release layer 910 and the carrier substrate 900 can be removed from the first initial lower dielectric layer 101p, which exposes the bottom surface of the first initial lower dielectric layer 101p and the bottom surface of the lower bump pattern 110. External terminals 700 can be correspondingly formed on the exposed bottom surface of the lower bump pattern 110. The formation of the external terminals 700 may include performing a solder ball attachment process.

[0093] Refer to Figure 1 and Figure 13 The first initial redistribution substrate 100p, the first initial molding layer 300p, the second initial redistribution substrate 400p, and the second initial molding layer 600p can be cut along the tangent SL, so that multiple semiconductor packages 1 can be separated from each other. Therefore, semiconductor packages according to some example embodiments of this disclosure can be manufactured.

[0094] According to this disclosure, an adhesive film can be disposed between a first redistributed substrate and a second redistributed substrate. The first redistributed substrate and the second redistributed substrate can be fixed to each other by the adhesive film. Therefore, it is possible to reduce process time and improve the reliability of semiconductor packages.

[0095] This detailed description should not be construed as limiting oneself to the embodiments set forth herein, and is intended to cover various combinations, modifications, and variations of the embodiments without departing from the spirit and scope of this disclosure. The appended claims should be construed as including other embodiments.

Claims

1. A semiconductor package, comprising: First redistributed substrate; A first semiconductor chip is mounted on the first redistributed substrate; A first molding layer is located on the first redistribution substrate, the first molding layer covering the top surface and side surface of the first semiconductor chip, the top surface being remote from the first redistribution substrate; A second redistributed substrate is located on the first molding layer and includes connection pads and connection terminals located on the bottom surface of the connection pads. A conductive structure that connects the first redistributed substrate to the second redistributed substrate; as well as An adhesive film is located between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers the top surface of the first molding layer. Wherein, the side surface of the adhesive film is coplanar with the side surface of the second redistributed substrate. The connection terminal includes a first portion and a second portion surrounding the lower part of the first portion, and The second part is formed by forcing conductive particles in the adhesive film to flow and aggregate between the conductive structure and the first part through heat and pressure. The second part covers the top surface of the conductive structure; The maximum width of the first portion in the first direction is less than the width of the conductive structure in the first direction; and The maximum width of the second portion in the first direction is equal to the width of the conductive structure in the first direction, which is parallel to the top surface of the first semiconductor chip.

2. The semiconductor package according to claim 1, wherein, The side surface of the adhesive film is coplanar with the side surface of the first redistributed substrate.

3. The semiconductor package according to claim 1, in, The first redistributed substrate includes a lower dielectric layer. Wherein, the second redistributed substrate includes an upper dielectric layer, and The lower dielectric layer and the upper dielectric layer comprise a photosensitive polymer.

4. The semiconductor package according to claim 1, in, The second redistributed substrate further includes an upper dielectric layer; The connection pads are exposed by the upper dielectric layer; and The connection terminal is located between the conductive structure and the connection pad, and is surrounded by the adhesive film.

5. The semiconductor package according to claim 4, wherein, The connection terminal is vertically aligned with the conductive structure.

6. The semiconductor package according to claim 1, wherein, The thickness of the first redistributed substrate is greater than the thickness of the second redistributed substrate.

7. The semiconductor package according to claim 1, wherein, The thickness of the second redistributed substrate is in the range of 5 μm to 50 μm.

8. The semiconductor package according to claim 1, wherein, The first redistributed substrate includes: Multiple first redistribution patterns are connected to the first semiconductor chip; and The lower dielectric layer surrounds the first redistribution pattern. Each of the plurality of first redistribution patterns includes a corresponding seed pattern and a corresponding conductive pattern located on the corresponding seed pattern.

9. A semiconductor package, comprising: First redistributed substrate; A first semiconductor chip is mounted on the first redistributed substrate; A first molding layer is located on the first redistribution substrate, the first molding layer covering the top surface and side surface of the first semiconductor chip, the top surface being remote from the first redistribution substrate; A second redistributed substrate is located on the first molding layer; A conductive structure that connects the first redistributed substrate to the second redistributed substrate; A second semiconductor chip is mounted on the second redistributed substrate; as well as An adhesive film is located between the second redistribution substrate and the first molding layer. The second redistributed substrate includes: Top dielectric layer; Connection pads, which are exposed by the upper dielectric layer; and A connection terminal, located on the bottom surface of the connection pad. The adhesive film extends in a first direction parallel to the top surface of the first semiconductor chip, and contacts the top surface of the first molding layer and the bottom surface of the upper dielectric layer of the second redistributed substrate. Wherein, the width of the adhesive film in the first direction is equal to the width of the first redistributed substrate in the first direction. The connection terminal includes a first portion and a second portion surrounding the lower part of the first portion, and The second part is formed by forcing conductive particles in the adhesive film to flow and aggregate between the conductive structure and the first part through heat and pressure. The second part covers the top surface of the conductive structure; The maximum width of the first portion in the first direction is less than the width of the conductive structure in the first direction; and The maximum width of the second portion in the first direction is equal to the width of the conductive structure in the first direction.

10. The semiconductor package according to claim 9, wherein, The connecting terminals are surrounded by the adhesive film.

11. The semiconductor package according to claim 9, wherein, The side surface of the first molded layer is coplanar with the side surface of the adhesive film.

12. The semiconductor package of claim 11, wherein the conductive structure penetrates the first molding layer and extends vertically.

13. The semiconductor package of claim 9, further comprising a connection substrate located on the first redistributed substrate, the connection substrate surrounding a side surface of the first semiconductor chip. in, The connecting substrate includes a base layer. Wherein, the first molding layer is located between the connecting substrate and the first semiconductor chip, and The adhesive film covers the top surface of the substrate layer.

14. The semiconductor package of claim 13, wherein, The second redistribution substrate also includes a plurality of second redistribution patterns surrounded by the upper dielectric layer. The connection terminals connect the conductive structure to a plurality of second redistribution patterns on the second redistribution substrate, and The connecting terminal is in contact with the adhesive film.

15. A semiconductor package, comprising: First redistributed substrate; A first semiconductor chip is mounted on the first redistributed substrate; A first molding layer is located on the first redistribution substrate, the first molding layer covers the top surface and side surface of the first semiconductor chip, the top surface of the first semiconductor chip being away from the first redistribution substrate; A second redistributed substrate is located on the first molding layer; A second semiconductor chip is mounted on the second redistributed substrate; A second molding layer is located on the second redistribution substrate, and the second molding layer covers the top surface and side surface of the second semiconductor chip; An adhesive film is located between the second redistributed substrate and the first molding layer; A conductive structure that penetrates the first molding layer and connects the first redistributed substrate to the second redistributed substrate; as well as External terminals, which are located on the bottom surface of the first redistribution liner. Wherein, the first redistributed substrate includes: The lower bump pattern contacts the external terminal; Connecting pads that are in contact with the conductive structure; Multiple first redistribution patterns connect the connection pads to the lower bump pattern; and The lower dielectric layer surrounds the plurality of first redistribution patterns. Wherein, the side surface of the adhesive film is coplanar with the side surface of the first molding layer, and the second redistributed substrate includes connection terminals that are in contact with the conductive structure. The connection terminal includes a first portion and a second portion surrounding the lower part of the first portion, and The second part is formed by forcing conductive particles in the adhesive film to flow and aggregate between the conductive structure and the first part through heat and pressure. The second part covers the top surface of the conductive structure; The maximum width of the first portion in the first direction is less than the width of the conductive structure in the first direction; The maximum width of the second portion in the first direction is equal to the width of the conductive structure in the first direction; and The first direction is parallel to the top surface of the first semiconductor chip.

16. The semiconductor package of claim 15, wherein, The second redistributed substrate includes: The upper connection pad is connected to the second semiconductor chip; The lower connecting pad is vertically aligned with the conductive structure; Multiple second redistribution patterns connect the upper connection pad to the lower connection pad; and An upper dielectric layer is provided, which surrounds the plurality of second redistribution patterns; The connection terminal is located on the bottom surface of the lower connection pad.

17. The semiconductor package of claim 15, further comprising: The lower connection terminal is located between the connection pad and the first semiconductor chip; as well as A first bottom filler layer surrounds the lower connection terminal and fills the gap between the bottom surface of the first semiconductor chip and the top surface of the first redistributed substrate. The first semiconductor chip is electrically connected to the second redistributed substrate via the lower connection terminal, the first redistributed pattern, and the conductive structure.

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