Semiconductor structure, forming method and mask

Abstract

A semiconductor structure, a forming method and a mask plate, the forming method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprises a first device area, a dummy device area, a second device area and a third device area arranged in sequence along a first row, the third device area, the second device area, the dummy device area and the first device area arranged in sequence along a second row, and the first device area, the dummy device area, the second device area and the third device area in the first row are respectively arranged in central symmetry with the first device area, the dummy device area, the second device area and the third device area in the second row. According to the embodiment of the present application, the first shielding layer exposes the first device area and the dummy device area, the area exposed by the first shielding layer is larger, the process window of the first shielding layer is larger, the process difficulty of forming the first shielding layer is reduced, and the overlay accuracy of the first shielding layer is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and more particularly to a semiconductor structure, a forming method and a mask. BACKGROUND

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuit, wherein the memory device accounts for a considerable proportion in the integrated circuit products. With the development of semiconductor technology, the memory device is applied more widely, and it is required to form the memory device and other devices in a chip at the same time to form an embedded semiconductor storage device. For example, the memory device is embedded in a central processing unit, and it is required to make the memory device compatible with the embedded central processing unit platform, and to keep the original specifications and corresponding electrical properties of the memory device.

[0003] Generally, it is required to make the memory device compatible with the embedded standard logic device. For the embedded semiconductor device, it is usually divided into a logic region and a memory region, the logic region usually includes logic devices, and the memory region includes memory devices. With the development of memory technology, various types of semiconductor memories appear, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. Since the static random access memory has the advantages of low power consumption and fast working speed, the static random access memory and its forming method have attracted more and more attention.

[0004] However, the performance of the static random access memory in the semiconductor device formed by the prior art needs to be further improved, so that the overall performance of the semiconductor device is poor. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure, a forming method and a mask, and to improve the electrical properties of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure forming method, comprising: providing a substrate, the substrate comprising a substrate, a channel structure separated on the substrate, a pseudo gate structure crossing the channel structure, the pseudo gate structure covering part of the top wall and part of the side wall of the channel structure, the substrate comprising a first device area, a pseudo device area, a second device area and a third device area arranged in sequence along a first row, a third device area, a second device area, a pseudo device area and a first device area arranged in sequence along a second row, and the first device area, the pseudo device area, the second device area and the third device area in the first row being arranged in central symmetry with the first device area, the pseudo device area, the second device area and the third device area in the second row respectively; removing the pseudo gate structure to form a gate opening; after forming the gate opening, a first shielding layer is formed, the first shielding layer exposing the first device area and the pseudo device area, or the first shielding layer exposing the third device area and the second device area.

[0007] Correspondingly, the embodiment of the present application also provides a semiconductor structure, comprising: a substrate, the substrate comprising a substrate, a channel structure separated on the substrate, a gate opening crossing the channel structure and a source-drain doped layer in the channel structure on both sides of the gate opening, the gate opening exposing part of the top wall and part of the side wall of the channel structure, the substrate comprising a first device area, a pseudo device area, a second device area and a third device area arranged in sequence along a first row, a third device area, a second device area, a pseudo device area and a first device area arranged in sequence along a second row, and the first device area, the pseudo device area, the second device area and the third device area in the first row being arranged in central symmetry with the first device area, the pseudo device area, the second device area and the third device area in the second row respectively; a first shielding layer on the substrate, the first shielding layer exposing the first device area and the pseudo device area, or the first shielding layer exposing the third device area and the second device area.

[0008] Correspondingly, the embodiment of the present application also provides a mask for forming a memory cell, comprising: a substrate, a channel structure separated on the substrate, a pseudo gate opening exposing the channel structure and a source-drain doped layer in the channel structure on both sides of the pseudo gate opening, the pseudo gate opening exposing part of the top wall and part of the side wall of the channel structure, the substrate comprising a first device area, a pseudo device area, a second device area and a third device area arranged in sequence along a first row, a third device area, a second device area, a pseudo device area and a first device area arranged in sequence along a second row, and the first device area, the pseudo device area, the second device area and the third device area in the first row being arranged in central symmetry with the first device area, the pseudo device area, the second device area and the third device area in the second row respectively; the mask comprising: a mask pattern for forming a first shielding layer, the first shielding layer exposing the first device area and the pseudo device area, or exposing the third device area and the second device area.

[0009] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

[0010] In the method for forming a semiconductor structure provided by the embodiment of the application, after the gate opening is formed, a work function layer is generally formed in the gate opening, and after the work function layer is formed, a first shielding layer is formed, the first shielding layer exposes the first device area and the dummy device area, the area exposed by the first shielding layer is large, so that the process window for forming the first shielding layer is large, the process difficulty for forming the first shielding layer is reduced, the overlaying accuracy of the first shielding layer is improved, in the subsequent step of removing the work function layer in the first device area by taking the first shielding layer as a mask, the work function layer in the first device area is not prone to residual, which prepares for the subsequent formation of a corresponding work function layer in the first device area, so that the work function layer subsequently formed in the first device area can better adjust the threshold voltage of the first device area, which is beneficial to improving the electrical performance of the semiconductor structure; the first shielding layer exposes the third device area and the second device area, the area exposed by the first shielding layer is large, so that the process window for forming the first shielding layer is large, the process difficulty for forming the first shielding layer is reduced, the overlaying accuracy of the first shielding layer is improved, in the subsequent step of removing the work function layer in the second device area and the third device area by taking the first shielding layer as a mask, the work function layer in the second device area and the third device area is not prone to residual, which prepares for the subsequent formation of a corresponding work function layer in the second device area and the third device area, so that the work function layer subsequently formed in the second device area can better adjust the threshold voltage of the second device area, and the work function layer subsequently formed in the third device area can better adjust the threshold voltage of the third device area, which is beneficial to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1 to 5 is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 6 to 15 is a structure diagram corresponding to each step in a first embodiment of a method for forming a semiconductor structure of the application;

[0013] Figures 16 to 18 is a structure diagram corresponding to each step in a second embodiment of a method for forming a semiconductor structure of the application;

[0014] Figures 19 to 21 is a structure diagram corresponding to each step in a third embodiment of a method for forming a semiconductor structure of the application;

[0015] Figures 22 to 24 is a structure diagram corresponding to each step in a fourth embodiment of a method for forming a semiconductor structure of the application;

[0016] Figure 25 and Figure 26 is a structural schematic diagram of a first embodiment of the semiconductor structure of the present application;

[0017] Figure 27 is a structural schematic diagram of a second embodiment of the semiconductor structure of the present application;

[0018] Figure 28 is a structural schematic diagram of a third embodiment of the semiconductor structure of the present application;

[0019] Figure 29 is a structural schematic diagram of a fourth embodiment of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0020] The currently formed semiconductor structure still has the problem of poor performance. The reasons for poor device performance will be analyzed in combination with a forming method of a semiconductor structure.

[0021] Reference Figures 1 to 5 is a structural schematic diagram corresponding to each step in a forming method of a semiconductor structure.

[0022] As Figure 1 and Figure 2 shown, Figure 2 I and III in are cross-sectional views at aa, Figure 2 II in is a cross-sectional view at bb, a substrate is provided, the substrate includes a substrate 1, a fin 2 separated on the substrate 1, a pseudo-gate structure 3 across the fin 2, and a source-drain doped layer 4 in the fin 2 on both sides of the pseudo-gate structure 3, the pseudo-gate structure 3 covers part of the top wall and part of the side wall of the fin 2, the substrate includes a first device region I, a pseudo-device region IV, a second device region II and a third device region III arranged in sequence along a first row, a third device region III, a second device region II, a pseudo-device region IV and a first device region I arranged in sequence along a second row, and the first device region I, the pseudo-device region IV, the second device region II and the third device region III in the first row are respectively arranged as central symmetry with the first device region I, the pseudo-device region IV, the second device region II and the third device region III in the second row.

[0023] As Figure 3 shown, the pseudo-gate structure 3 is removed to form a gate opening 7; a first shielding layer 5 covering the first device region I and the third device region II and exposing the pseudo-device region IV and the second device region II is formed; a first work function layer (not shown in the figure) is formed on the bottom surface and the sidewall of the gate opening 7 of the pseudo-device region IV and the second device region II exposed by the first shielding layer 5.

[0024] As Figure 4As shown, after the first work function layer is formed, the first shielding layer 5 is removed; after removing the first shielding layer 5, the second shielding layer 6 is formed to expose the third device region III, and the second work function layer (not shown in the figure) is formed in the third device region III exposed by the second shielding layer 6.

[0025] like Figure 5 As shown, after the second work function layer is formed, the second shielding layer 6 is removed; after removing the second shielding layer 6, the third shielding layer 8 is formed, covering the second device region II, the third device region III, and the pseudo device region IV, and exposing the first device region I; the third work function layer (not shown in the figure) is formed in the first device region I exposed by the third shielding layer 8.

[0026] Semiconductor devices are evolving towards higher integration and smaller size. The regions of the first device region I, the second device region II, and the third device region III are becoming smaller. Correspondingly, the exposed areas of the third shielding layer 8, the first shielding layer 5, and the second shielding layer 6 are also smaller. During the formation of the third shielding layer 8, the first shielding layer 5, and the second shielding layer 6, even with slight overlay errors, the third shielding layer 8 may not easily expose the gate opening in the first device region I, the first shielding layer 5 may not easily expose the gate opening in the second device region II, and the second shielding layer 6 may not easily expose the gate opening in the third device region III. When the semiconductor structure is working, the first work function layer formed in the second device region II cannot effectively regulate the threshold voltage of the second device region II, the second work function layer of the third device region II cannot effectively regulate the threshold voltage of the third device region III, and the third work function layer of the first device region I cannot effectively regulate the threshold voltage of the first device region I.

[0027] To solve the technical problem, the semiconductor structure provided by the embodiment of the present application is characterized in that: after the gate opening is formed, a work function layer is generally formed in the gate opening; after the work function layer is formed, a first shielding layer is formed, the first shielding layer exposes the first device area and the dummy device area, the area exposed by the first shielding layer is large, so that the process window for forming the first shielding layer is large, the process difficulty for forming the first shielding layer is reduced, the overlaying precision of the first shielding layer is improved, in the subsequent step of removing the work function layer in the first device area by taking the first shielding layer as a mask, the work function layer in the first device area is not easy to have residues, which can prepare for the subsequent formation of the corresponding work function layer in the first device area, so that the work function layer subsequently formed in the first device area can better adjust the threshold voltage of the first device area, which is beneficial to improve the electrical performance of the semiconductor structure; the first shielding layer exposes the third device area and the second device area, the area exposed by the first shielding layer is large, so that the process window for forming the first shielding layer is large, the process difficulty for forming the first shielding layer is reduced, the overlaying precision of the first shielding layer is improved, in the subsequent step of removing the work function layer in the second device area and the third device area by taking the first shielding layer as a mask, the work function layer in the second device area and the third device area is not easy to have residues, which can prepare for the subsequent formation of the corresponding work function layer in the second device area and the third device area, so that the work function layer subsequently formed in the second device area can better adjust the threshold voltage of the second device area, the work function layer subsequently formed in the third device area can better adjust the threshold voltage of the third device area, which is beneficial to improve the electrical performance of the semiconductor structure.

[0028] Figures 6 to 15 is the structure schematic diagram corresponding to each step in the embodiment of the method for forming the semiconductor structure of the present application.

[0029] Reference Figure 6 and Figure 7 , Figure 7 I and III in Figure 6 is a sectional view at AA in Figure 7 II in Figure 6The cross-sectional view at the middle BB provides a base, the base includes a substrate 100, a channel structure 101 separated on the substrate 100, a dummy gate structure 102 crossing the channel structure 101, the dummy gate structure 102 covering part of the top wall and part of the sidewall of the channel structure 101, the base includes a first device region I, a dummy device region IV, a second device region II and a third device region III arranged in sequence along a first row, a third device region III, a second device region II, a dummy device region IV and a first device region I arranged in sequence along a second row, and the first device region I, the dummy device region IV, the second device region II and the third device region III in the first row are respectively center-symmetrically arranged with the first device region I, the dummy device region IV, the second device region II and the third device region III in the second row.

[0030] The base provides a process basis for subsequent formation of a semiconductor structure.

[0031] In the embodiment, the semiconductor structure is used to constitute an SRAM device, specifically, the SRAM device is a six-transistor static random access memory (six-transistor SRAM, 6T-SRAM), and correspondingly, the SRAM device includes two pairs of pull-up transistors (PU), pull-down transistors (PD) and pass-gate transistors (PG), and the two pull-up transistors, pull-down transistors and pass-gate transistors are in a center-symmetric structure. The first device region I is used to form a pass-gate transistor, the second device region II is used to form a pull-up transistor, and the third device region III is used to form a pull-down transistor.

[0032] In the embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0033] In the embodiment, the forming method of the semiconductor structure is used to form a fin field-effect transistor (FinFET) as an example, and correspondingly, the channel structure 101 is a fin. In other embodiments, the forming method of the semiconductor structure is used to form a gate-all-around transistor (GAA), and correspondingly, the channel structure is one or more channel stacks, and the channel stack includes a sacrificial layer and a channel layer on the sacrificial layer.

[0034] In the embodiment, the material of the channel structure 101 is silicon. In other embodiments, the material of the channel structure can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0035] It should be noted that in the step of providing the substrate, the channel structure 101 is formed in the first device region I, the second device region II and the third device region III, and the extension direction of each channel structure 101 is the same.

[0036] It should be noted that the substrate further comprises an isolation layer (not shown in the figure) located on the substrate 100 exposed by the channel structure 101, and the isolation layer covers part of the sidewall of the channel structure 101.

[0037] The isolation layer is used to achieve electrical isolation between each channel structure 101.

[0038] In the embodiment, the material of the isolation layer is a dielectric material.

[0039] Specifically, the material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride. In the embodiment, the material of the isolation layer is silicon oxide.

[0040] The dummy gate structure 102 occupies a spatial position for the subsequent formation of the gate structure.

[0041] In the embodiment, the channel structure 101 is a fin, and in the step of forming the dummy gate structure 102, the dummy gate structure 102 spans the fin and covers part of the top wall and part of the sidewall of the fin. In other embodiments, the channel structure is one or more channel stacks, and in the step of forming the dummy gate structure, the dummy gate structure spans the channel stack and covers part of the top wall and part of the sidewall of the channel stack.

[0042] In the embodiment, the material of the dummy gate structure 102 is polysilicon.

[0043] The step of forming the dummy gate structure 102 includes: forming a gate oxide material layer (not shown in the figure) on the substrate 100 and the channel structure 101; forming a gate material layer (not shown in the figure) on the gate oxide material layer; etching the gate material layer to form a gate layer and etching the gate oxide material layer to form a gate oxide layer, the gate layer and the gate oxide layer serving as an initial dummy gate structure (not shown in the figure); removing the initial gate structure at the junction of the first device region I and the dummy device region IV, and the remaining initial gate structure serving as the dummy gate structure 102.

[0044] It should be noted that in the step of forming the dummy gate structure 102, two separate dummy gate structures 102 are formed, and the two dummy gate structures 102 are located in the first row and the second row, respectively.

[0045] In the step of removing the initial gate structure at the junction of the first device region I and the dummy device region IV, the initial gate structure at the junction of the first device region I and the dummy device region IV in the first row and the initial gate structure at the junction of the first device region I and the dummy device region IV in the second row are removed.

[0046] In the step of providing the substrate, the sidewall of the dummy gate structure 102 is also formed with a sidewall spacer 104, and the source-drain doped layer 103 is formed in the channel structure 101 on both sides of the dummy gate structure 102 and the sidewall spacer 104.

[0047] In the process of forming the source-drain doped layer in the channel structure 101, the sidewall spacer 104 serves to protect the sidewall of the dummy gate structure 102, and the sidewall spacer 104 can also serve to define the area where the source-drain doped layer 103 is formed.

[0048] In this embodiment, the material of the sidewall spacer 104 includes SiN. In other embodiments, the material of the sidewall spacer can also include SiON, SiBCN or SiCN.

[0049] In operation of the semiconductor structure, the source-drain doped layer 103 provides stress to the channel to increase the migration rate of the carriers.

[0050] In this embodiment, the first device region I and the third device region III are NMOS (Negative channel Metal Oxide Semiconductor), and the second device region II is PMOS (Positive Channel Metal Oxide Semiconductor).

[0051] The method for forming the semiconductor structure includes: in the step of providing the substrate, an etch-resistant layer 112 is also formed on the sidewall of the sidewall spacer 104 and the top of the source-drain doped layer 103; after the etch-resistant layer 112 is formed, an interlayer dielectric layer 105 is formed on the substrate 100 exposed by the dummy gate structure 102, and the interlayer dielectric layer 105 covers the sidewall of the dummy gate structure 102 and exposes the top wall of the dummy gate structure 102.

[0052] Subsequently, the interlayer dielectric layer 105 and the etch-resistant layer 112 are etched to form an opening exposing the source-drain doped layer 103, and in the process of etching the interlayer dielectric layer 105, the etch-resistant layer 112 serves to define a temporary etching stop position.

[0053] The material of the etch-resistant layer 112 can be one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron carbon silicon nitride. In this embodiment, the material of the etch-resistant layer 112 is silicon nitride.

[0054] The interlayer dielectric layer 105 serves to electrically isolate adjacent devices.

[0055] In this embodiment, the material of the interlayer dielectric layer 105 is an insulating material. Specifically, the material of the interlayer dielectric layer 105 includes silicon oxide.

[0056] The method for forming the interlayer dielectric layer 105 includes: forming an interlayer dielectric material layer (not shown in the figure) covering the substrate and the dummy gate structure 102; removing the interlayer dielectric material layer higher than the dummy gate structure 102, and the remaining interlayer dielectric material layer as the interlayer dielectric layer 105.

[0057] Referring to Figure 8 , the dummy gate structure 102 is removed to form the gate opening 106.

[0058] The gate opening 106 is prepared for forming the work function layer of the first device region I, the second device region II and the third device region III.

[0059] In the embodiment, the wet etching process is used to remove the dummy gate structure 102. The wet etching process has a high etching rate, is simple to operate and has low process cost.

[0060] Specifically, the material of the dummy gate structure 102 includes silicon oxide and polysilicon. The wet solution used in the corresponding wet etching process includes hydrogen fluoride solution and tetramethylammonium hydroxide (TMAH).

[0061] In other embodiments, the method for forming the semiconductor structure is used to form a fully-surrounded gate transistor, and the sacrificial layer is also removed in the step of forming the gate opening. The removal of the sacrificial layer is prepared for forming the work function layer of the fully-surrounded channel layer.

[0062] Referring to Figure 9 , the method for forming the semiconductor structure further includes: forming the first work function layer 107 in the gate opening 106 before forming the first shielding layer.

[0063] In the operation of the semiconductor structure, the first work function layer 107 is used to adjust the threshold voltage of the pass-gate transistor in the first device region I.

[0064] In the embodiment, in the 6T-SRAM device, the pass-gate transistor is an NMOS, and correspondingly, the material of the first work function layer 107 includes one or more of titanium aluminide, tantalum carbide, aluminum and titanium carbide.

[0065] In the embodiment, the method for forming the semiconductor structure is used to form a fin field effect transistor, the channel structure 101 is a fin, and in the step of forming the first work function layer 107 in the gate opening 106, the first work function layer 107 is formed on the top surface and the sidewall of the channel structure 101 in the gate opening 106. Thus, in the operation of the semiconductor structure, the first work function layer 107 can adjust the opening and closing of the pass-gate transistor. In other embodiments, the method for forming the semiconductor structure is used to form a fully-surrounded gate structure, and correspondingly, the first work function layer is formed on the surface of the channel layer.

[0066] In order to simplify the forming process of the first work function layer 107, the first work function layer 107 is formed on the whole substrate 100, so as to expand the process window of the first work function layer 107 and improve the forming quality of the first work function layer 107 correspondingly. The first work function layer 107 is formed by using a conformal coating process, and correspondingly, the first work function layer 107 is also formed on the top of the interlayer dielectric layer 105, the side wall of the side wall layer 104 exposed by the gate opening 106, and the isolation layer.

[0067] In the embodiment, the first work function layer 107 is formed by using an atomic layer deposition (ALD) process. The atomic layer deposition process is based on a self-limiting reaction process of an atomic layer deposition process, and the deposited film can reach the thickness of a single atom. Since the atomic layer deposition process can accurately deposit one atomic layer in each cycle, the atomic layer deposition process is beneficial to accurately control the thickness of the first work function layer 107. In addition, the film prepared by the ALD process has the characteristics of good bonding strength, consistent film thickness, good composition uniformity, and good conformality, which is beneficial to improve the thickness uniformity and film quality of the first work function layer 107. In other embodiments, the first work function layer can also be formed by using a metal organic chemical vapor deposition (MOCVD) process.

[0068] The forming method of the semiconductor structure further includes: after the gate opening 106 is formed, forming the first work function layer 107, and before the first work function layer 107 is formed, forming a gate dielectric layer 109 on the bottom surface and the side wall of the gate opening in the first device region I, the second device region II, the third device region III, and the dummy device region IV.

[0069] The gate dielectric layer 109 is used to electrically isolate the subsequently formed gate structure and the channel structure 101, and electrically isolate the subsequently formed gate structure and the source / drain doped layer 103.

[0070] It should be noted that the material of the gate dielectric layer 109 is a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0071] In the embodiment, the material of the gate dielectric layer 109 is HfO2. In other embodiments, the material of the gate dielectric layer can also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0072] Reference is made to Figure 10 and Figure 11 , Figure 11 I and III in the above areFigure 10 a cross-sectional view at AA, Figure 11 II is Figure 10 a cross-sectional view at BB, after forming the gate opening 106, a first shielding layer 108 is formed (as shown in Figure 10 The first shielding layer 108 exposes the third device region III and the second device region II.

[0073] The first shielding layer 108 exposes the third device region III and the second device region II, and the area exposed by the first shielding layer 108 is large, so that the process window for forming the first shielding layer 108 is large, the process difficulty for forming the first shielding layer 108 is reduced, the overlay accuracy of the first shielding layer 108 is improved, and in the subsequent step of removing the first work function layer 107 in the second device region II and the third device region III with the first shielding layer 108 as a mask, the first work function layer 107 in the second device region II and the third device region III is not easy to exist residual, which can prepare for the subsequent formation of the corresponding work function layer in the second device region II and the third device region III, so that the work function layer formed in the second device region II can better adjust the threshold voltage of the second device region II, and the work function layer formed in the third device region III can better adjust the threshold voltage of the third device region III, which is beneficial to improve the electrical performance of the semiconductor structure.

[0074] The first shielding layer 108 serves as an etching mask for subsequent etching of the first work function layer 107, and the first shielding layer 108 reduces the probability of damage to the first work function layer 107 in the first device region I.

[0075] In this embodiment, the first shielding layer 108 is a material that can act as a mask and is easy to remove, so as to reduce damage to the first work function layer in the first device region I when the first shielding layer 108 is removed subsequently.

[0076] In this embodiment, the material of the first shielding layer 108 is an organic material, for example: BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, spin on carbon (SOC), DUO (Deep UV Light Absorbing Oxide) material or APF (Advanced Patterning Film) material.

[0077] The forming step of the first shielding layer 108 includes: forming a first shielding material layer (not shown in the figure) covering the first device region I, the second device region II, the third device region III and the dummy device region IV; patterning the first shielding material layer, and the remaining first shielding material layer serves as the first shielding layer 108.

[0078] In this embodiment, the spin coating process is used to form the first shielding material layer. The first shielding material layer formed by the spin coating process has high flatness.

[0079] In this embodiment, the dry etching process is used to pattern the first shielding material layer to form the first shielding layer 108. The dry etching process has anisotropic etching characteristics and good etching profile control, which is conducive to making the morphology of the first shielding layer 108 meet the process requirements and improving the removal efficiency of the first shielding material layer. In addition, the dry etching process is easy to control the etching stop position and is not easy to cause damage to other film layers.

[0080] With reference to Figure 11 , the forming method of the semiconductor structure further includes: removing the first work function layer 107 in the gate opening 106 of the second device region II and the third device region III with the first shielding layer 108 as a mask.

[0081] The removal of the first work function layer 107 in the gate opening 106 of the second device region II and the third device region III prepares for the subsequent formation of the corresponding work function layer in the gate opening 106 of the second device region II and the third device region III, respectively.

[0082] In this embodiment, the wet etching process is used to remove the first work function layer 107 in the second device region II and the third device region III with the first shielding layer 108 as a mask. The wet etching process is an isotropic etching process, which has a high etching rate and is simple to operate and low in process cost.

[0083] It should be noted that in the step of removing the first work function layer 107 in the gate opening 106 of the second device region II and the third device region III, the first work function layer 107 on the top of the etching-resistant layer 112, the sidewall of the sidewall layer 104 and the surface of the isolation layer in the second device region II and the third device region III are also removed.

[0084] The forming method of the semiconductor structure further includes: removing the first shielding layer 108 after removing the first work function layer 107 in the gate opening 106 of the second device region II and the third device region III.

[0085] The first shielding layer 108 is removed to prepare for forming the second work function layer in the second device region II and the third device region III, the forming area of the second work function layer is large, the process window of forming the second work function layer is large, the forming quality of the corresponding second work function layer is high, and the first shielding layer 108 is not easy to contaminate the machine.

[0086] Reference Figure 12 After the first work function layer 107 in the gate opening 106 of the second device region II and the third device region III is removed, the second work function layer 110 is formed in the gate opening 106 of the second device region II and the third device region III.

[0087] In the embodiment, the target area of the second work function layer 110 is the third device region III, and the third device region III is used to form a pull-down transistor.

[0088] In the working process of the semiconductor structure, the second work function layer 110 is used to adjust the threshold voltage of the pull-down transistor in the third device region III.

[0089] In the 6T-SRAM device, the pull-down transistor is an NMOS, and accordingly, the material of the second work function layer 110 includes one or more of titanium aluminide, tantalum carbide, aluminum, and titanium carbide.

[0090] It should be noted that in the step of forming the second work function layer 110 in the gate opening 106 of the third device region III, the second work function layer 110 is also formed in the first device region I, the second device region II, and the dummy device region IV.

[0091] Specifically, in the step of forming the second work function layer 110, the second work function layer 110 is formed on the top surface and the sidewall of the channel structure 101 in the gate opening 106, so that in the working process of the semiconductor structure, the second work function layer 110 can adjust the opening and closing of the pull-down transistor. In other embodiments, the forming method of the semiconductor structure is used to form a fully-enclosed gate structure, and the second work function layer is formed on the surface of the channel layer.

[0092] In order to simplify the forming process of the second work function layer 110, the second work function layer 110 is formed on the entire substrate 100, in order to expand the process window of the second work function layer 110, and accordingly improve the forming quality of the second work function layer 110, the second work function layer 110 is formed by using a conformal coating process; accordingly, the second work function layer 110 is also formed on the top of the interlayer dielectric layer 105, the sidewall of the sidewall layer 104 exposed by the gate opening 106, and the isolation layer.

[0093] In this embodiment, the second work function layer 110 is formed by using an atomic layer deposition process. In other embodiments, the second work function layer can also be formed by using a metal organic chemical vapor deposition process.

[0094] After the first shielding layer 108 is removed, the second work function layer 110 is formed in the first device region I, the second device region II, the third device region III, and the dummy device region IV, which is conducive to increasing the process window of the second work function layer 110, so that the formation quality of the second work function layer 110 is higher.

[0095] It should be noted that in the first device region I, the second work function layer 110 is formed on the first work function layer 107, and when the semiconductor structure is working, the second work function layer 110 in the first device region I has little effect on the threshold voltage adjustment of the transmission gate transistor by the first work function layer 107.

[0096] Reference Figure 13 and Figure 14 , Figure 14 I and III in Figure 13 is a cross-sectional view at AA in Figure 14 II in Figure 13 is a cross-sectional view at BB in The method for forming the semiconductor structure further includes: forming a second shielding layer 111 covering the first device region I and the third device region III, and exposing the second device region II and the dummy device region IV.

[0097] The second shielding layer 111 exposes the second device region II and the dummy device region IV, and the area exposed by the second shielding layer 111 is large, so that the process window of forming the second shielding layer 111 is large, the process difficulty of forming the second shielding layer 111 is reduced, the overlaying precision of the second shielding layer 111 is improved, and in the subsequent step of removing the second work function layer 110 in the second device region II and the dummy device region IV by using the second shielding layer 111 as a mask, the second work function layer 110 in the second device region II and the third device region III is not easy to exist.

[0098] The second shielding layer 111 serves as an etching mask for subsequent etching of the second work function layer 110, and the second shielding layer 111 reduces the probability of damage to the first work function layer 107 of the first device region I and the second work function layer 110 of the second device region II.

[0099] In this embodiment, the second shielding layer 111 is a material that can play a masking role and is easy to remove, so that when the second shielding layer 111 is removed subsequently, damage to the first work function layer 107 of the first device region I and the second work function layer 110 of the third device region is reduced.

[0100] In the embodiment, the material of the second shielding layer 111 is an organic material, for example, BARC material, ODL material, photoresist, DARC material, spin-on carbon, DUO material or APF material.

[0101] The forming step of the second shielding layer 111 includes: forming a second shielding material layer (not shown in the figure) covering the first device region I, the second device region II, the third device region III and the dummy device region IV; patterning the second shielding material layer, and the remaining second shielding material layer serves as the second shielding layer 111.

[0102] In the embodiment, the spin coating process is used to form the second shielding material layer. The second shielding material layer formed by the spin coating process has high flatness.

[0103] In the embodiment, the dry etching process is used to pattern the second shielding material layer to form the second shielding layer 111. The dry etching process has anisotropic etching characteristics and good etching profile control, which is conducive to making the morphology of the second shielding layer 111 meet the process requirements and improving the removal efficiency of the second shielding material layer. In addition, the dry etching process is easy to control the etching stop position and is not easy to cause damage to other film layers.

[0104] Reference Figure 14 The second work function layer 110 in the gate opening 106 of the second device region II is removed by taking the second shielding layer 111 as a mask.

[0105] The second work function layer 110 in the gate opening 106 of the second device region II is removed, which prepares for the subsequent formation of the third work function layer in the gate opening 106 of the second device region II.

[0106] In the embodiment, the second work function layer 110 of the second device region II is etched by taking the second shielding layer 111 as a mask and using the wet etching process. The wet etching process is an isotropic etching process, which has high etching rate and is simple to operate and low in process cost.

[0107] It should be noted that in the process of removing the second work function layer 110 in the gate opening 106 of the second device region II, the second work function layer 110 in the gate opening 106 of the dummy device region IV is also removed.

[0108] The forming method of the semiconductor structure further includes: after removing the second work function layer 110 of the second device region II, removing the second shielding layer 111.

[0109] The second shielding layer 111 is removed to prepare for forming a third work function layer in the second device region II. The third work function layer has a large forming area, a large process window, and a high forming quality. The second shielding layer 111 is less likely to contaminate the machine.

[0110] With reference to Figure 15 After the second shielding layer 111 is removed, the third work function layer 113 is formed in the gate opening 106 of the second device region II using the second shielding layer 111 as a mask.

[0111] In this embodiment, the target area of the third work function layer 113 formed after the second shielding layer 111 is removed is the second device region II, which is used to form a pull-up transistor.

[0112] In operation of the semiconductor structure, the third work function layer 113 is used to adjust the threshold voltage of the pull-up transistor in the second device region II.

[0113] In this embodiment, in the 6T-SRAM device, the pull-up transistor is a PMOS, and accordingly, the material of the third work function layer 113 includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0114] In this embodiment, the forming method of the semiconductor structure is used to form a fin field effect transistor, and the channel structure 101 is a fin. In the step of forming the third work function layer 113 in the gate opening 106, the third work function layer 113 is formed on the top surface and the sidewall of the channel structure 101 in the gate opening 106. Thus, in operation of the semiconductor structure, the third work function layer 113 can adjust the opening and closing of the pull-up transistor. In other embodiments, the forming method of the semiconductor structure is used to form a fully surrounded gate structure, and accordingly, the third work function layer is formed on the surface of the channel layer.

[0115] To simplify the forming process of the third work function layer 113, the third work function layer 113 is formed on the entire substrate 100. To expand the process window of the third work function layer 113 and accordingly improve the forming quality of the third work function layer 113, the third work function layer 113 is formed by a conformal coating process. Accordingly, the third work function layer 113 is also formed on the top of the interlayer dielectric layer 105, the sidewall of the sidewall layer 104 exposed by the gate opening 106, and the isolation layer.

[0116] In this embodiment, the atomic layer deposition process is used to form the third work function layer 113. In other embodiments, the metal organic chemical vapor deposition process can also be used to form the third work function layer.

[0117] After the second shielding layer 110 is removed, the third work function layer 113 is formed in the first device region I, the second device region II, the third device region III and the dummy device region IV, which is beneficial to increase the process window of the third work function layer 113, so that the forming quality of the third work function layer 113 is higher.

[0118] It should be noted that in the first device region I and the third device region III, the third work function layer 113 is formed on the second work function layer 110, and accordingly, in the working of the semiconductor structure, the third work function layer 113 has less influence on the threshold voltage of the transmission gate transistor in the first device region I, and the third work function layer 113 has less influence on the threshold voltage of the pull-down transistor in the third device region III.

[0119] Reference Figures 16 to 18 is the structure diagram corresponding to each step in the second embodiment of the forming method of the semiconductor structure.

[0120] The same as the first embodiment is that after the gate opening 206 is formed, the first shielding layer exposes the third device region III and the second device region II, and the same as the first embodiment will not be repeated here. The difference between the first embodiment and the first embodiment is that:

[0121] Reference Figure 16 The forming method of the semiconductor structure further comprises: forming a first work function layer (not shown in the figure) in the gate opening 206.

[0122] In the embodiment, the target area of the first work function layer is the gate opening of the second device region II.

[0123] In the working of the semiconductor structure, the first work function layer can adjust the opening and closing of the pull-up transistor. Reference Figure 17 After the first work function layer is formed, the second shielding layer 211 covering the dummy device region IV and the second device region II is formed, and the first device region I and the third device region III are exposed; the first work function layer in the gate opening 206 of the first device region I and the third device region III is removed with the second shielding layer 211 as a mask.

[0124] In the process of removing the first work function layer in the first device region I and the third device region III with the second shielding layer 211 as a mask, the second shielding layer 211 protects the first work function layer in the second device region II from being damaged.

[0125] The first work function layer of the first device region I and the third device region III is removed, so as to prepare for forming a second work function layer in the first device region I and the third device region III; and because the second shielding layer 211 exposes the first device region I and the third device region III at the same time, the area exposed by the second shielding layer 211 is large, so that the process window for forming the second shielding layer is large, the process difficulty for forming the second shielding layer is reduced, and the overlaying accuracy of the second shielding layer is improved.

[0126] The method for forming the semiconductor structure further includes: after removing the first work function layer in the gate opening of the first device region I and the third device region III, removing the second shielding layer 211.

[0127] After removing the second shielding layer 211, a second work function layer (not shown in the figure) is formed in the gate opening 206 of the first device region I and the third device region III.

[0128] The target region of the second work function layer is the gate opening 206 of the first device region I.

[0129] In the embodiment, the method for forming the semiconductor structure is used to form a fin field effect transistor, the channel structure 201 is a fin, and in the step of forming the second work function layer in the gate opening 206, the second work function layer is formed on the top surface and the sidewall of the channel structure 201 in the gate opening 206. Thus, when the semiconductor structure works, the second work function layer can adjust the opening and closing of the transmission gate transistor. In other embodiments, the method for forming the semiconductor structure is used to form a fully surrounded gate structure, and the corresponding second work function layer is formed on the surface of the channel layer.

[0130] In order to simplify the forming process of the second work function layer, the second work function layer is formed on the whole substrate, the process window of the second work function layer is expanded, and the forming quality of the second work function layer is improved correspondingly.

[0131] Reference Figure 18 After the second work function layer is formed, the first shielding layer 208 is formed, and the first shielding layer 208 exposes the third device region III and the second device region II.

[0132] The first shielding layer 208 prepares for removing the second work function layer of the third device region III and the second device region II.

[0133] Specifically, the first shielding layer 208 covers the first device region I and the dummy device region IV, and exposes the third device region III and the second device region II. The area covered by the corresponding first shielding layer 208 and the area exposed by the corresponding first shielding layer 208 are both large, so that the process window of the first shielding layer 208 is large, the process difficulty of forming the first shielding layer 208 is reduced, and the overlay accuracy of the first shielding layer 208 is improved. In the subsequent process of removing the second work function layer in the third device region III and the second device region II, the second work function layer in the first device region I is not easy to be etched by mistake, and the second work function layer in the third device region III is not easy to have residual, so that the third work function layer formed in the third device region III in the subsequent process can better adjust the threshold voltage of the third device region.

[0134] With reference to Figure 18 The second work function layer in the gate opening of the third device region III and the second device region II is removed by taking the first shielding layer 208 as a mask. After the second work function layer in the gate opening of the third device region III and the second device region II is removed, the first shielding layer 208 is removed. After the first shielding layer 208 is removed, the third work function layer is formed in the gate opening 206 of the third device region III.

[0135] It should be noted that the wet etching process is usually used to remove the second work function layer in the gate opening 206 exposed by the first shielding layer 208. In the step of removing the second work function layer in the gate opening 206 of the second device region II, the etching rate of the second work function layer is greater than the etching rate of the first work function layer, so that when the semiconductor structure works, the first work function layer in the second device region II can well adjust the threshold voltage of the pull-up transistor.

[0136] It should be noted that in the step of forming the third work function layer in the gate opening 206 of the third device region III, the third work function layer is also formed on other regions on the substrate. The process window of forming the third work function layer is improved, and the forming quality of the third work function layer is improved.

[0137] With reference to Figures 19 to 21 is a structure diagram corresponding to each step in the third embodiment of the method for forming the semiconductor structure.

[0138] The same as the first embodiment, which will not be repeated here. The difference between the first embodiment and the first embodiment is that the first shielding layer exposes the first device region and the dummy device region.

[0139] With reference to Figure 19 The method for forming the semiconductor structure further comprises: forming a first work function layer (not shown in the figure) in the gate opening.

[0140] In this embodiment, the target area of the first work function layer is the gate opening of the second device region II.

[0141] In this embodiment, the semiconductor structure forming method is used to form a fin field effect transistor, the channel structure 201 is a fin, and in the step of forming the first work function layer in the gate opening 206, the first work function layer is formed on the top surface and the sidewall of the channel structure 201 in the gate opening 206. Thus, when the semiconductor structure is in operation, the first work function layer can adjust the on and off of the pull-up transistor. In other embodiments, the semiconductor structure forming method is used to form a fully surrounded gate structure, and the corresponding first work function layer is formed on the surface of the channel layer.

[0142] In order to simplify the forming process of the first work function layer, the first work function layer is formed on the entire substrate, and in order to expand the process window of the first work function layer, the forming quality of the first work function layer is correspondingly improved.

[0143] Reference Figure 20 After the first work function layer is formed, the second shielding layer 311 covering the dummy device region IV and the second device region II is formed, and the first device region I and the third device region III are exposed. The first work function layer in the gate opening 306 of the first device region I and the third device region III is removed with the second shielding layer 311 as a mask.

[0144] In the process of removing the first work function layer in the gate opening of the first device region I and the third device region III with the second shielding layer 311 as a mask, the second shielding layer 311 protects the first work function layer in the second device region II from being damaged.

[0145] The first work function layer in the gate opening of the first device region I and the third device region III is removed, which prepares for the subsequent formation of the second work function layer in the first device region I and the third device region III. Moreover, because the second shielding layer 311 exposes the first device region I and the third device region III at the same time, the area exposed by the second shielding layer 311 is large, so that the process window of the second shielding layer is large, the process difficulty of forming the second shielding layer is reduced, and the overlaying precision of the second shielding layer is improved.

[0146] The semiconductor structure forming method further includes: after the first work function layer in the gate opening of the first device region I and the third device region III is removed, the second shielding layer 311 is removed.

[0147] After the second shielding layer 311 is removed, the second work function layer (not shown in the figure) is formed in the gate opening 306 of the first device region I, the second device region II, and the third device region III.

[0148] The target region of the second work function layer is the gate opening 306 of the third device region III.

[0149] In this embodiment, the method for forming a semiconductor structure is used to form a fin field effect transistor, the channel structure 301 is a fin, and in the step of forming the second work function layer in the gate opening 306, the second work function layer is formed on the top surface and the sidewall of the channel structure 301 in the gate opening 306. Thus, when the semiconductor structure is in operation, the second work function layer can adjust the on and off of the transmission gate transistor. In other embodiments, the method for forming a semiconductor structure is used to form a fully surrounded gate structure, and the corresponding second work function layer is formed on the surface of the channel layer.

[0150] In order to simplify the forming process of the second work function layer, form the second work function layer on the entire substrate, expand the process window of the second work function layer, and correspondingly improve the forming quality of the second work function layer.

[0151] Reference Figure 21 After the second work function layer is formed, the first shielding layer 308 is formed, and the first shielding layer 308 exposes the first device region I and the dummy device region IV.

[0152] The first shielding layer 308 prepares for subsequent removal of the second work function layer in the first device region I.

[0153] Specifically, the first shielding layer 308 covers the third device region III and the second device region II, exposes the first device region I and the dummy device region IV, and correspondingly, the area exposed by the first shielding layer 308 is large, so that the process window of the first shielding layer 308 is large, the process difficulty of forming the first shielding layer 308 is reduced, the overlaying accuracy of the first shielding layer 308 is improved, and in the subsequent process of removing the second work function layer in the first device region I, it is not easy to mis-etch the second work function layer in the third device region III, and the second work function layer in the first device region I is not easy to exist residual, so that the third work function layer formed in the first device region I in the subsequent process can better adjust the threshold voltage of the first device region.

[0154] Continue to refer to Figure 21 The second work function layer in the gate opening 306 of the first device region I is removed with the first shielding layer 308 as a mask; after the second work function layer in the gate opening 306 of the first device region I is removed, the first shielding layer 308 is removed; after the first shielding layer 308 is removed, the third work function layer is formed in the gate opening 306 of the first device region I.

[0155] It should be noted that in the step of removing the second work function layer in the gate opening 306 of the first device region I, the second work function layer in the gate opening 306 of the dummy device region IV will also be removed.

[0156] It should be noted that in the step of forming the third work function layer in the gate opening 306 of the first device region I, the third work function layer is also formed on other regions on the substrate, the process window of forming the third work function layer is increased, and the forming quality of the third work function layer is improved accordingly.

[0157] Reference Figures 22 to 24 is the structure diagram corresponding to each step in the fourth embodiment of the method for forming the semiconductor structure.

[0158] The embodiment is the same as the first embodiment, and details are not repeated here. The embodiment is different from the first embodiment in that the first shielding layer exposes the first device region and the dummy device region.

[0159] Reference Figure 22 The method for forming the semiconductor structure further includes forming a first work function layer (not shown in the figure) in the gate opening.

[0160] In the embodiment, the target region of the first work function layer is the gate opening of the third device region III.

[0161] In the embodiment, the method for forming the semiconductor structure is used to form a fin field effect transistor, the channel structure 401 is a fin, and in the step of forming the first work function layer in the gate opening 406, the first work function layer is formed on the top surface and the sidewall of the channel structure 401 in the gate opening 406. Thus, when the semiconductor structure works, the first work function layer can adjust the opening and closing of the pull-down transistor. In other embodiments, the method for forming the semiconductor structure is used to form a fully surrounded gate structure, and the first work function layer is formed on the surface of the channel layer accordingly.

[0162] In order to simplify the forming process of the first work function layer, the first work function layer is formed on the entire substrate, so as to expand the process window of the first work function layer and improve the forming quality of the first work function layer.

[0163] Reference Figure 23 After the first work function layer is formed, the first shielding layer 408 is formed, and the first shielding layer 408 exposes the first device region I and the dummy device region IV.

[0164] The first shielding layer 408 exposes the third device region III and the dummy device region IV. The first shielding layer 408 has a large exposed area, so that the process window of the first shielding layer 408 is large, the process difficulty of forming the first shielding layer 408 is reduced, the overlay accuracy of the first shielding layer 408 is improved, and in the subsequent step of removing the first work function layer in the first device region I with the first shielding layer 408 as a mask, the first work function layer in the first device region I is less likely to have residues, which prepares for the subsequent formation of the second work function layer in the first device region I, so that the second work function layer formed in the first device region I can better adjust the threshold voltage of the first device region I, which is beneficial to improve the electrical performance of the semiconductor structure.

[0165] The first shielding layer 408 serves as an etching mask for the subsequent etching to remove the first work function layer in the first device region I, so that the first shielding layer 408 reduces the probability of damage to the first work function layer in the first device region I.

[0166] The method for forming the semiconductor structure further includes: removing the first work function layer in the gate opening 406 of the first device region I and the dummy device region IV with the first shielding layer 408 as a mask.

[0167] The first work function layer in the gate opening 406 of the first device region I is removed, which prepares for the subsequent formation of the second work function layer in the gate opening of the first device region I.

[0168] The method for forming the semiconductor structure further includes: removing the first shielding layer 408 after removing the first work function layer in the gate opening 406 of the first device region I.

[0169] After the first shielding layer 408 is removed, the second work function layer (not shown in the figure) is formed in the gate opening 406 of the first device region I, the second device region II, and the third device region III.

[0170] The target region of the second work function layer is the gate opening 406 of the first device region I.

[0171] In this embodiment, the method for forming the semiconductor structure is used to form a fin field effect transistor, and the channel structure 401 is a fin. In the step of forming the second work function layer in the gate opening 406, the second work function layer is formed on the top surface and the sidewall of the channel structure 401 in the gate opening 406. Thus, when the semiconductor structure works, the second work function layer can adjust the opening and closing of the transmission gate transistor. In other embodiments, the method for forming the semiconductor structure is used to form a fully surrounded gate structure, and the corresponding second work function layer is formed on the surface of the channel layer.

[0172] In order to simplify the formation process of the second work function layer, the second work function layer is formed on the entire substrate, the process window of the second work function layer is expanded, and the formation quality of the second work function layer is correspondingly improved.

[0173] Reference Figure 24 After the second work function layer is formed, the second shielding layer 411 covering the first device region I and the third device region III and exposing the dummy device region IV and the second device region II is formed.

[0174] The second shielding layer 411 is prepared for subsequent removal of the second work function layer in the second device region II.

[0175] Specifically, the second shielding layer 411 covers the first device region I and the third device region III and exposes the dummy device region IV and the second device region II, and the area exposed by the second shielding layer 411 is large, so that the process window of the second shielding layer 411 is large, the process difficulty of forming the second shielding layer 411 is reduced, the overlay accuracy of the second shielding layer 411 is improved, and in the subsequent process of removing the second work function layer in the second device region II, the first work function layer in the first device region I and the first work function layer in the third device region III are not easy to be etched by mistake.

[0176] Continuing to refer to Figure 24 The second work function layer in the gate opening 406 of the second device region II is removed with the second shielding layer 411 as a mask; after the second work function layer in the gate opening of the second device region II is removed, the second shielding layer 411 is removed; after the second shielding layer 411 is removed, the third work function layer is formed in the gate opening 406 of the second device region II.

[0177] It should be noted that in the step of removing the second work function layer in the gate opening 406 of the second device region II, the second work function layer in the gate opening 406 of the dummy device region IV is also removed.

[0178] It should be noted that in the step of forming the third work function layer in the gate opening 406 of the second device region II, the third work function layer is also formed on other regions on the substrate, and the process window of forming the third work function layer is improved, and the formation quality of the third work function layer is improved.

[0179] Correspondingly, the embodiment of the present application also provides a semiconductor structure. Reference Figure 25 and Figure 26 , Figure 26 I and III in Figure 25 the cross-sectional view at AA, Figure 26 II in Figure 25 the cross-sectional view at BB, which shows a structure schematic diagram of the first embodiment of the semiconductor structure of the present application.

[0180] The semiconductor structure comprises: a substrate, the substrate comprises a substrate 500, a channel body separated from the substrate 500, a gate opening 506 crossing the channel body, and source-drain doped layers in the channel body on both sides of the gate opening 506, the gate opening 506 exposes part of the top wall and part of the side wall of the channel body, the substrate comprises a first device region I, a dummy device region, a second device region II and a third device region III arranged in sequence along a first row, a third device region III, a second device region II, a dummy device region and a first device region I arranged in sequence along a second row, and the first device region I, the dummy device region, the second device region II and the third device region III in the first row are respectively arranged as central symmetry with the first device region I, the dummy device region, the second device region II and the third device region III in the second row; a first shielding layer 508 is located on the substrate, and the first shielding layer 508 exposes the third device region III and the second device region II.

[0181] The first shielding layer exposes the third device region III and the second device region II, and the area exposed by the first shielding layer 508 is relatively large, so that the process window for forming the first shielding layer 508 is relatively large, the process difficulty for forming the first shielding layer 508 is reduced, the overlaying precision of the first shielding layer 508 is improved, and in the subsequent step of removing the first work function layer in the second device region II and the third device region III with the first shielding layer 508 as a mask, the first work function layer in the second device region II and the third device region III is not easy to exist residual, which can prepare for the subsequent formation of the second work function layer in the third device region III and the third work function layer in the second device region II, so that the third work function layer formed in the second device region II can better adjust the threshold voltage of the second device region II, and the second work function layer formed in the third device region III can better adjust the threshold voltage of the third device region III, which is beneficial to improve the electrical performance of the semiconductor structure.

[0182] In the embodiment, the semiconductor structure is used to constitute an SRAM device, specifically, the SRAM device is a six-transistor static random access memory (six-transistor SRAM, 6T-SRAM), and correspondingly, the SRAM device comprises two pairs of pull-up transistors (PU), pull-down transistors (PD) and pass-gate transistors (PG), and the two pull-up transistors, pull-down transistors and pass-gate transistors all have a central symmetric structure. The first device region I is used to form a pass-gate transistor, the second device region II is used to form a pull-up transistor, and the third device region III is used to form a pull-down transistor.

[0183] The substrate 500 provides a process basis for the subsequent formation of the semiconductor structure.

[0184] In this embodiment, the material of the substrate 500 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0185] In this embodiment, the semiconductor structure is a fin field-effect transistor (FinFET), and accordingly, the channel body 501 is a fin. In other embodiments, the semiconductor structure is a gate-all-around transistor (GAA), and accordingly, the channel body is one or more channel layers spaced apart in the normal direction of the surface of the substrate.

[0186] In this embodiment, the material of the channel body 501 is silicon. In other embodiments, the material of the channel body can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide.

[0187] In this embodiment, the channel body 501 is located in the first device region I, the second device region II and the third device region III, and the extension directions of the channel bodies 501 are the same.

[0188] It should be noted that the semiconductor structure further includes an isolation layer (not shown in the figure) located on the exposed substrate 500 of the channel body 501, and the isolation layer covers part of the sidewall of the channel body 501.

[0189] The isolation layer is used to achieve electrical isolation between the channel bodies 501.

[0190] In this embodiment, the material of the isolation layer is a dielectric material.

[0191] Specifically, the material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0192] The gate opening 506 is prepared for subsequent formation of the work function layer of the first device region I, the second device region II and the third device region III.

[0193] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the gate opening 506 exposes part of the top wall and part of the sidewall of the fin. In other embodiments, the semiconductor structure is a gate-all-around structure, and the gate opening exposes the channel layer.

[0194] When the semiconductor structure is in operation, the source-drain doping layer 503 provides stress to the channel to improve the migration rate of the carriers.

[0195] In the embodiment, the first device region I and the third device region III are NMOS (Negative channel Metal Oxide Semiconductor), and the second device region II is PMOS (Positive Channel Metal Oxide Semiconductor).

[0196] When the semiconductor structure is in operation, the source-drain doped layer of the PMOS applies compression stress to the channel under the gate structure, and the compression channel can improve the mobility of the holes. Specifically, the material of the source-drain doped layer of the PMOS is silicon germanium or silicon doped with P-type ions. Specifically, the P-type ions include one or more of B, Ga and In.

[0197] When the semiconductor structure is in operation, the source-drain doped layer of the NMOS applies tensile stress to the channel under the gate structure, and the tensile channel can improve the mobility of the electrons. Specifically, the material of the source-drain doped layer of the NMOS is silicon carbide, silicon phosphide or silicon doped with N-type ions. Specifically, the N-type ions include one or more of P, As and Sb.

[0198] The semiconductor structure further comprises a sidewall layer 504 located on the sidewall of the gate opening 506.

[0199] The sidewall layer 504 functions to define the area of the gate opening 506, and the sidewall layer 504 can also function to define the area where the source-drain doped layer 503 is formed.

[0200] In the embodiment, the material of the sidewall layer 504 includes SiN. In other embodiments, the material of the sidewall layer can also include SiON, SiBCN or SiCN.

[0201] The semiconductor structure further comprises an etch-resistant layer 512 located on the sidewall of the sidewall layer 504 and on the top of the source-drain doped layer 503, and an interlayer dielectric layer 505 located on the substrate 500 on the side of the gate opening.

[0202] Subsequently, the interlayer dielectric layer 505 and the etch-resistant layer 512 are etched to form an opening exposing the source-drain doped layer 503. In the process of etching the interlayer dielectric layer 505, the etch-resistant layer 512 is used to define a temporary etching stop position.

[0203] The material of the etch-resistant layer 512 can be one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron carbon silicon nitride. In the embodiment, the material of the etch-resistant layer 512 is silicon nitride.

[0204] The interlayer dielectric layer 505 is used for electrical isolation between adjacent devices.

[0205] In this embodiment, the material of the interlayer dielectric layer 505 is insulating material. Specifically, the material of the interlayer dielectric layer 505 includes silicon oxide.

[0206] The first shielding layer 508 is a material capable of functioning as a mask and easy to remove, so as to reduce damage to the first work function layer in the first device region I when the first shielding layer 508 is removed subsequently.

[0207] In this embodiment, the material of the first shielding layer 508 is organic material, for example, BARC material, ODL material, photoresist, DARC material, spin-on carbon, DUO material or APF material.

[0208] The semiconductor structure further includes: the first work function layer 507, located between the gate opening 506 and the first shielding layer 508 in the first device region I.

[0209] In this embodiment, the first work function layer 507 is located on the top surface and the sidewall of the fin 501 exposed by the gate opening 506. In other embodiments, the first work function layer is formed on the surface of the channel layer.

[0210] In operation of the semiconductor structure, the first work function layer 507 is used to adjust the threshold voltage of the pass transistor in the first device region I.

[0211] In this embodiment, in the 6T-SRAM device, the pass transistor is NMOS, and accordingly, the material of the first work function layer 507 includes one or more of titanium aluminide, tantalum carbide, aluminum and titanium carbide.

[0212] The semiconductor structure further includes: the gate dielectric layer 509, and between the first work function layer 507 and the substrate.

[0213] The gate dielectric layer 509 is used to electrically isolate the first work function layer 507 and the channel body 501, and to electrically isolate the first work function layer 507 and the source / drain doped layer 503.

[0214] It should be noted that the material of the gate dielectric layer 509 is high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0215] In this embodiment, the material of the gate dielectric layer 509 is HfO2. In other embodiments, the material of the gate dielectric layer can also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3.

[0216] It should be noted that the gate dielectric layer 509 is also located on the bottom surface and the sidewall of the gate opening 506 in the second device region II and the third device region III.

[0217] Reference Figure 27 Fig. 4 shows a structural schematic diagram of a second embodiment of the semiconductor structure.

[0218] The same parts of the embodiment and the first embodiment will not be described here again, and the different parts of the embodiment and the first embodiment are as follows:

[0219] The semiconductor structure further comprises: a first work function layer located in the gate opening 606 of the second device region II; and a second work function layer located between the gate opening 606 of the first device region and the first shielding layer 608.

[0220] In the working process of the semiconductor structure, the first work function layer is used to adjust the threshold voltage of the pull-up transistor in the second device region II.

[0221] In the working process of the semiconductor structure, the second work function layer of the first device region I is used to adjust the threshold voltage of the pull-down transistor in the third device region III.

[0222] Reference Figure 28 Fig. 5 shows a structural schematic diagram of a third embodiment of the semiconductor structure.

[0223] The same parts of the embodiment and the first embodiment will not be described here again, and the different parts of the embodiment and the first embodiment are as follows:

[0224] The first shielding layer 708 exposes the first device region I and the dummy device region IV.

[0225] The first shielding layer 708 exposes the third device region III and the dummy device region, and the area exposed by the first shielding layer 708 is large, so that the process window of the first shielding layer 708 is large, the process difficulty of forming the first shielding layer 708 is reduced, the overlaying precision of the first shielding layer 708 is improved, in the subsequent step of removing the second work function layer in the first device region with the first shielding layer 708 as a mask, the second work function layer in the first device region is not easy to exist residual, which can prepare for the subsequent formation of the third work function layer in the first device region, so that the third work function layer formed in the first device region can better adjust the threshold voltage of the first device region, which is conducive to improving the electrical performance of the semiconductor structure.

[0226] The semiconductor structure further comprises: a first work function layer and a second work function layer located on the first work function layer, located between the gate opening 706 of the second device region and the first shielding layer 708; and the second work function layer is located between the gate opening 706 of the third device region III and the first shielding layer 708.

[0227] In the working process of the semiconductor structure, the first work function layer is used to adjust the threshold voltage of the pull-up transistor in the second device region II.

[0228] In operation of the semiconductor structure, the second work function layer of the third device region III is used to adjust the threshold voltage of the pull-down transistor in the third device region III.

[0229] Reference Figure 29 Fig. 4 shows a structural schematic diagram of a fourth embodiment of the semiconductor structure.

[0230] The same parts of the embodiment and the first embodiment will not be described here again. The difference between the embodiment and the first embodiment is that:

[0231] The first shielding layer 808 exposes the first device region I and the dummy device region IV.

[0232] The first shielding layer 808 exposes the third device region III and the dummy device region. The area exposed by the first shielding layer 808 is large, so that the process window of the first shielding layer 808 is large, the process difficulty of forming the first shielding layer 808 is reduced, the overlay accuracy of the first shielding layer 808 is improved, and in the subsequent step of removing the first work function layer in the first device region I with the first shielding layer 808 as a mask, the first work function layer in the first device region I is not easy to exist residual, which can prepare for the subsequent formation of the second work function layer in the first device region I, so that the second work function layer formed in the first device region I can better adjust the threshold voltage of the first device region I, which is conducive to improving the electrical performance of the semiconductor structure.

[0233] The semiconductor structure further comprises a first work function layer (not shown in the figure) located between the gate opening of the second device region II and the third device region and the first shielding layer 808.

[0234] The target area of the first work function layer is the third device region III.

[0235] In operation of the semiconductor structure, the first work function layer is used to adjust the threshold voltage of the pull-down transistor in the third device region III.

[0236] Correspondingly, the embodiment of the present application also provides a mask plate.

[0237] The mask is used for forming a memory cell, the memory cell comprises a substrate, a channel structure separated on the substrate, a dummy gate opening exposing the channel structure, and a source / drain doping layer in the channel structure on both sides of the dummy gate opening, the dummy gate opening exposes part of the top wall and part of the side wall of the channel structure, the substrate comprises a first device area, a dummy device area, a second device area and a third device area arranged in sequence along a first row, a third device area, a second device area, a dummy device area and a first device area arranged in sequence along a second row, and the first device area, the dummy device area, the second device area and the third device area in the first row are respectively arranged in a central symmetry with the first device area, the dummy device area, the second device area and the third device area in the second row. The mask comprises: a mask pattern for forming a first shielding layer, the first shielding layer exposes the first device area and the dummy device area, or exposes the third device area and the second device area.

[0238] After the gate opening is formed, a work function layer is usually formed in the gate opening, after the work function layer is formed, a first shielding layer is formed, the first shielding layer exposes the first device area and the dummy device area, the area exposed by the first shielding layer is large, so that the process window of forming the first shielding layer is large, the process difficulty of forming the first shielding layer is reduced, the overlay accuracy of the first shielding layer is improved, in the subsequent step of removing the work function layer in the first device area with the first shielding layer as a mask, the work function layer in the first device area is not easy to exist residual, which can prepare for the subsequent formation of corresponding work function layer in the first device area, so that the work function layer formed in the first device area can better adjust the threshold voltage of the first device area, which is beneficial to improve the electrical performance of the semiconductor structure; the first shielding layer exposes the third device area and the second device area, the area exposed by the first shielding layer is large, so that the process window of forming the first shielding layer is large, the process difficulty of forming the first shielding layer is reduced, the overlay accuracy of the first shielding layer is improved, in the subsequent step of removing the work function layer in the second device area and the third device area with the first shielding layer as a mask, the work function layer in the second device area and the third device area is not easy to exist residual, which can prepare for the subsequent formation of corresponding work function layer in the second device area and the third device area, so that the work function layer formed in the second device area can better adjust the threshold voltage of the second device area, the work function layer formed in the third device area can better adjust the threshold voltage of the third device area, which is beneficial to improve the electrical performance of the semiconductor structure.

[0239] In the embodiment, the storage unit is an SRAM device, specifically, the SRAM device is a six-transistor static random access memory (6T-SRAM), and correspondingly, the SRAM device includes two pairs of pull-up transistors (PU), pull-down transistors (PD) and pass-gate transistors (PG), and the two pairs of pull-up transistors, pull-down transistors and pass-gate transistors are in a central symmetric structure. The first device region I is used for forming the pass-gate transistors, the second device region II is used for forming the pull-up transistors, and the third device region III is used for forming the pull-down transistors.

[0240] The semiconductor structure in the embodiment can be formed by using the forming method in the foregoing embodiments or other forming methods. For the specific description of the semiconductor structure in the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0241] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a channel structure discrete on the substrate, and a pseudo-gate structure spanning the channel structure, the pseudo-gate structure covering part of the top wall and part of the sidewall of the channel structure, the substrate including a first device region, a pseudo-device region, a second device region and a third device region arranged sequentially along a first row, and a third device region, a second device region, a pseudo-device region and a first device region arranged sequentially along a second row, wherein the first device region, pseudo-device region, second device region and third device region in the first row are respectively centrally symmetrically arranged with the first device region, pseudo-device region, second device region and third device region in the second row; Remove the pseudo-gate structure to form a gate opening; After the gate opening is formed, a first shielding layer is formed, which exposes the first device region and the dummy device region, or the first shielding layer exposes the third device region and the second device region. The step of forming the first masking layer includes: forming a masking material layer covering the first device area, the second device area, the third device area, and the dummy device area; patterning the masking material layer, with the remaining masking material layer serving as the first masking layer; wherein, the step of forming the first masking layer includes: forming a masking material layer covering the first device area, the second device area, the third device area, and the dummy device area; patterning the masking material layer, with the remaining masking material layer serving as the first masking layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: before forming the first shielding layer, forming a first work function layer in the gate opening; After the first work function layer is formed, the first shielding layer is formed, and in the step of forming the first shielding layer, the first shielding layer exposes the third device region and the second device region. The method for forming the semiconductor structure further includes: using the first shielding layer as a mask, removing the first work function layer in the gate openings of the second device region and the third device region; After removing the first work function layer from the gate openings of the second and third device regions, remove the first shielding layer; After removing the first shielding layer, a second work function layer is formed in the gate openings of the first device region, the second device region, and the third device region; The method for forming the semiconductor structure further includes: forming a second shielding layer that covers the first device region and the third device region, and exposes the second device region and the dummy device region; The second work function layer in the gate opening of the second device region is removed using the second shielding layer as a mask. After removing the second work function layer from the gate opening of the second device region, remove the second shielding layer; After removing the second shielding layer, a third work function layer is formed in the gate opening of the second device region.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: before forming the first shielding layer, forming a first work function layer in the gate opening; After the first work function layer is formed, a second shielding layer is formed that covers the pseudo device area and the second device area, and exposes the first device area and the third device area. Using the second shielding layer as a mask, the first work function layer in the gate openings of the first device region and the third device region is removed; After removing the first work function layer in the gate openings of the first device region and the third device region, remove the second shielding layer; After removing the second shielding layer, a second work function layer is formed in the gate openings of the first device region, the second device region, and the third device region; After the second work function layer is formed, the first shielding layer is formed, and the first shielding layer exposes the third device region and the second device region; The method for forming the semiconductor structure further includes: using the first shielding layer as a mask to remove the second work function layer in the gate opening of the third device region and the second device region; After removing the second work function layer from the gate openings of the third device region and the second device region, the first shielding layer is removed; after removing the first shielding layer, a third work function layer is formed in the gate opening of the third device region.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: before forming the first shielding layer, forming a first work function layer in the gate opening; After the first work function layer is formed, a second shielding layer is formed that covers the pseudo device area and the second device area, and exposes the first device area and the third device area. Using the second shielding layer as a mask, the first work function layer in the gate openings of the first device region and the third device region is removed; After removing the first work function layer in the gate openings of the first device region and the third device region, remove the second shielding layer; After removing the second shielding layer, a second work function layer is formed in the gate openings of the first device region, the second device region, and the third device region; After the second work function layer is formed, the first shielding layer is formed, and the first shielding layer exposes the first device area and the pseudo device area; The method for forming the semiconductor structure further includes: using the first shielding layer as a mask to remove the second work function layer in the gate opening of the first device region and the dummy device region; After removing the second work function layer from the gate openings of the first device region and the dummy device region, remove the first shielding layer; After removing the first shielding layer, a third work function layer is formed in the gate opening of the first device region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: before forming the first shielding layer, forming a first work function layer in the gate opening; After the first work function layer is formed, the first shielding layer is formed, and the first shielding layer exposes the first device area and the pseudo device area; The method for forming the semiconductor structure includes: using the first shielding layer as a mask, removing the first work function layer in the gate opening of the first device region and the dummy device region; After removing the first work function layer in the gate opening of the first device region, remove the first shielding layer; After removing the first shielding layer, a second work function layer is formed in the gate openings of the first device region, the second device region, and the third device region; The method for forming the semiconductor structure further includes: after forming the second work function layer, forming a second shielding layer that covers the first device region and the third device region, and exposes the second device region and the dummy device region; The second work function layer in the gate opening of the second device region is removed using the second shielding layer as a mask. After removing the second work function layer from the gate opening of the second device region, remove the second shielding layer; After removing the second shielding layer, a third work function layer is formed in the gate opening of the second device region.

6. The method for forming a semiconductor structure according to any one of claims 2 to 5, characterized in that, The first work function layer, the second work function layer, and the third work function layer are formed by one or both of atomic layer deposition (ALD) and metal-organic chemical vapor deposition (MOCVD).

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first shielding layer includes one or more of the following: BARC material, ODL material, photoresist, DARC material, spin-coated carbon, DUO material, and APF material.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The shielding material layer is formed using a spin coating process.

9. The method for forming a semiconductor structure according to any one of claims 2 to 5, characterized in that, The first work function layer was removed using a wet etching process.

10. The method for forming a semiconductor structure according to any one of claims 2 to 5, characterized in that, The second work function layer was removed using a wet etching process.

11. The method for forming a semiconductor structure according to any one of claims 2 to 5, characterized in that, The channel structure includes, in the step of providing a substrate, a fin-like portion of the channel structure. The pseudo-gate structure spans the fin and covers part of the top wall and part of the side wall of the fin; In the step of forming the first work function layer, the first work function layer is formed on the top surface and sidewall of the channel structure in the gate opening; In the step of forming the second work function layer, the second work function layer is formed on the top surface and sidewall of the channel structure in the gate opening; In the step of forming the third work function layer, the third work function layer is formed on the top surface and sidewalls of the channel structure in the gate opening.

12. The method for forming a semiconductor structure according to any one of claims 2 to 5, characterized in that, In the substrate provision step, the channel structure is one or more channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; The pseudo-gate structure spans the channel stack and covers part of the top wall and part of the sidewall of the channel stack; In the step of removing the pseudo-gate structure, the sacrificial layer is also removed; In the step of forming the first work function layer, the first work function layer is formed on the surface of the channel layer; In the step of forming the second work function layer, the second work function layer is formed on the surface of the channel layer; In the step of forming the third work function layer, the third work function layer is formed on the surface of the channel layer.

13. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a channel body discretely disposed on the substrate, a gate opening spanning the channel body, and source / drain doped layers located on both sides of the gate opening in the channel body. The gate opening exposes a portion of the top wall and a portion of the side wall of the channel body. The substrate includes a first device region, a dummy device region, a second device region, and a third device region arranged sequentially along a first row, and a third device region, a second device region, a dummy device region, and a first device region arranged sequentially along a second row. The first device region, dummy device region, second device region, and third device region in the first row are respectively centrally symmetrically arranged with the first device region, dummy device region, second device region, and third device region in the second row. A first shielding layer is located on the substrate, the first shielding layer exposing the first device area and the dummy device area, or the first shielding layer exposing the third device area and the second device area.

14. The semiconductor structure as described in claim 13, characterized in that, The semiconductor structure further includes a first work function layer located between the gate opening of the first device region and the first shielding layer.

15. The semiconductor structure as described in claim 13, characterized in that, The semiconductor structure also includes: The first work function layer is located in the gate opening of the second device region; The second work function layer is located between the gate opening in the first device region and the first shielding layer.

16. The semiconductor structure as described in claim 13, characterized in that, The semiconductor structure also includes: A first work function layer and a second work function layer located on the first work function layer are located between the gate opening of the second device region and the first shielding layer. The second work function layer is located between the gate opening of the third device region and the first shielding layer.

17. The semiconductor structure as claimed in claim 13, characterized in that, The semiconductor structure includes: The first work function layer is located between the gate openings of the second and third device regions and the first shielding layer.

18. The semiconductor structure according to any one of claims 14 to 17, characterized in that, The channel body is a fin, and the gate opening exposes part of the top wall and part of the side wall of the fin; The first work function layer is formed on the top surface and sidewalls of the exposed fin in the gate opening.

19. The semiconductor structure according to any one of claims 14 to 17, characterized in that, The channel body is one or more channel layers spaced apart in the normal direction of the substrate surface; the gate opening exposes the channel layer; The first work function layer is formed on the surface of the channel layer.

20. A photomask for forming a memory cell, the memory cell comprising: The substrate comprises a channel structure discretely disposed on the substrate, a dummy gate opening exposing the channel structure, and source / drain doped layers in the channel structure located on both sides of the dummy gate opening. The dummy gate opening exposes part of the top wall and part of the side wall of the channel structure. The substrate includes a first device region, a dummy device region, a second device region, and a third device region arranged sequentially along a first row, and a third device region, a second device region, a dummy device region, and a first device region arranged sequentially along a second row. The first device region, dummy device region, second device region, and third device region in the first row are respectively centrally symmetrically arranged with the first device region, dummy device region, second device region, and third device region in the second row. The photomask is characterized in that it comprises: A mask pattern is used to form a first masking layer, which exposes the first device area and the dummy device area, or exposes the third device area and the second device area.

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