Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method for fabricating the same are disclosed. The semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate. The isolation layer is disposed on the substrate, and the trench penetrates the isolation layer and exposes a portion of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate is disposed on the semiconductor active structure. The method for fabricating the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed to penetrate the isolation layer and expose a portion of the substrate. The semiconductor active structure is formed in the trench. The floating gate is formed on the semiconductor active structure.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to a semiconductor memory device having a semiconductor active structure disposed in a trench and a method for fabricating the same. BACKGROUND

[0002] A semiconductor memory is a semiconductor element used for storing data in a computer or an electronic product, which can be roughly classified into a volatile memory and a non-volatile memory. The non-volatile memory is widely used because of its characteristic of not losing stored data due to interruption of power supply. As one of the non-volatile memories, a SONOS memory structure mainly has a nitride layer interposed between two oxide layers, the nitride layer serving as a charge trap layer, and the two oxide layers disposed above and below the charge trap layer serving as a charge tunnel layer and a charge block layer, respectively. The oxide-nitride-oxide (hereinafter referred to as ONO) structure, which is a main element for information storage, is disposed on a semiconductor substrate, and a floating silicon gate is disposed thereon, so that it is called a SONOS memory.

[0003] However, as computer microprocessors become more and more powerful, there is an increasing demand for a large-capacity and low-cost memory. In order to meet this trend and the continuous challenge of high integration of semiconductor technology, the memory structure is more and more miniaturized, so that the manufacturing process of the memory structure is more and more complicated, thereby causing many problems in the manufacturing process and making it difficult to effectively improve the manufacturing yield. SUMMARY

[0004] The present invention provides a semiconductor memory device and a method for fabricating the same, which forms a semiconductor active structure in a trench penetrating an isolation layer, thereby avoiding the influence of the edge shape of a shallow trench isolation formed in a semiconductor material on the subsequent formation of a floating gate, and achieving the effect of improving the yield of the manufacturing process.

[0005] One embodiment of the present invention provides a semiconductor memory device, which includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate. The isolation layer is disposed on the substrate. The trench penetrates the isolation layer and exposes a portion of the substrate. The semiconductor active structure is disposed in the trench. The floating gate is disposed on the semiconductor active structure.

[0006] One embodiment of the present invention provides a method for fabricating a semiconductor memory device, comprising the following steps: forming an isolation layer on a substrate; forming a trench through the isolation layer and exposing a portion of the substrate; forming a semiconductor active structure in the trench; and forming a floating gate on the semiconductor active structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a top view schematically showing a semiconductor memory device according to a first embodiment of the present invention;

[0008] Figure 2 For the Figure 1 A cross-sectional view shown along the line A-A';

[0009] Figure 3 is a schematic diagram of a semiconductor memory device according to a second embodiment of the present invention;

[0010] Figures 4 to 17 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention, wherein

[0011] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0012] Figure 6 For the Figure 5 The cross-sectional view is shown along the BB' line;

[0013] Figure 7 For the Figure 5 The cross-sectional view shown along the C-C' line;

[0014] Figure 8 for Figure 7 Schematic diagram of the situation afterwards;

[0015] Figure 9 for Figure 8 Schematic diagram of the situation afterwards;

[0016] Figure 10 For the Figure 9 A cross-sectional view shown along the D-D' line;

[0017] Figure 11 for Figure 9 Schematic diagram of the situation afterwards;

[0018] Figure 12 For the Figure 11 A cross-sectional view shown along line E-E';

[0019] Figure 13 for Figure 12 Schematic diagram of the situation afterwards;

[0020] Figure 14 forFigure 13 Subsequent status schematic diagram;

[0021] Figure 15 For along Figure 14 Cross-sectional view as indicated by the section line F-F';

[0022] Figure 16 For Figure 14 Subsequent status schematic diagram;

[0023] Figure 17 For Figure 16 Subsequent status schematic diagram;

[0024] Figure 18 Schematic diagram of a semiconductor memory device according to a third embodiment of the present application;

[0025] Figure 19 Schematic diagram of a semiconductor memory device according to a fourth embodiment of the present application.

[0026] Explanation of main element symbols

[0027] 10 substrate

[0028] 10A active (driving) region

[0029] 20 isolation structure

[0030] 21 etch stop layer

[0031] 22 isolation layer

[0032] 22A first layer

[0033] 22B second layer

[0034] 22P isolation block

[0035] 24 first patterned mask layer

[0036] 26 second patterned mask layer

[0037] 30 semiconductor active structure

[0038] 32 dielectric layer

[0039] 34 first material layer

[0040] 36 second material layer

[0041] 40 storage layer

[0042] 42 first oxide layer

[0043] 44 nitride layer

[0044] 46 second oxide layer

[0045] 91 First Etching Process

[0046] 92 Second etching process

[0047] 93 Patterning production process

[0048] 101 Semiconductor Memory Device

[0049] 102 Semiconductor storage devices

[0050] 103 Semiconductor storage device

[0051] 104 Semiconductor storage device

[0052] CG control gate

[0053] D1 First direction

[0054] D2 Second direction

[0055] D3 third direction

[0056] FG Floating Gate

[0057] P1 Part 1

[0058] P2 Part 2

[0059] S1 top surface

[0060] S2 upper surface

[0061] S3 top surface

[0062] S4 top surface

[0063] S5 top surface

[0064] TR Groove

[0065] W Width

[0066] W1 width

[0067] W2 width

[0068] W3 width

[0069] W4 width

[0070] W5 width

[0071] W6 width

[0072] W7 Width

[0073] W8 Width DETAILED DESCRIPTION

[0074] The following detailed description of the application discloses sufficient information to enable one of ordinary skill in the art to practice the application. The embodiments described below are to be considered in a descriptive sense only and not limiting. Various modifications in form and detail can be made therein by those skilled in the art without departing from the spirit and scope of the application.

[0075] Before further description of the embodiments, the following terms are first defined for use throughout this document.

[0076] The terms "on," "over," and "above" should be interpreted in the broadest context to mean not only "directly on" something, but also to include the meaning of being on something with other intervening features or layers therebetween, and "over" or "above" something not only means "over" or "above" something, but also can include the meaning of being "over" or "above" something without other intervening features or layers therebetween (i.e., directly on something).

[0077] The use of ordinal terms such as "first," "second," etc., in the description and claims should not be construed to mean that a preceding or following order is intended, unless specifically stated otherwise. Rather, the ordinal terms are used as identifiers to distinguish between different elements, steps, etc., having the same name.

[0078] The term "etching" is used herein generally to describe a fabrication process to pattern a material such that at least a portion of the material remains after the etching process is complete. For example, it should be understood that a method to etch silicon generally includes patterning a photoresist layer over the silicon, and then removing the silicon from areas not protected by the photoresist layer. Thus, the silicon in areas protected by the photoresist layer can remain after the etching process is complete. However, in other embodiments, etching can include methods that do not use photoresist, but at least a portion of the etched material can remain after the etching process is complete.

[0079] The above description can be used to distinguish between "etching" and "removing." When a material is "etched," at least a portion of the material can remain after the etching is complete. In contrast, when a material is "removed," substantially all of the material can be removed during the process. However, in some embodiments, "removing" can be considered a broad term that includes etching.

[0080] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0081] See also Figure 1 and Figure 2 . Figure 1 FIG. 1 is a top view of a semiconductor memory device 101 according to a first embodiment of the present invention. Figure 2 For the Figure 1 The cross-sectional view shown along the A-A' line. Figure 1 and Figure 2 As shown, a semiconductor memory device 101 includes a substrate 10, a plurality of isolation structures 20, a plurality of floating gates FG, a plurality of control gates CG, a dielectric layer 32, and a memory layer 40. The substrate 10 may include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or other suitable semiconductor substrate types. The isolation structures 20 may be shallow trench isolation (STI) structures formed in the substrate 10 to define a plurality of active regions 10A in the substrate 10. In other words, the active regions 10A may be part of the substrate 10 and have the same material composition as the substrate 10. The shallow trench isolation structures may be formed by forming trenches in the substrate 10 that do not penetrate the substrate 10 and then filling the trenches with a single layer or multiple layers of an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials), but the present invention is not limited thereto. Each isolation structure 20 may extend substantially along a first direction D1 in a top view of the semiconductor memory device 101, and each control gate CG may extend substantially along a second direction D2 in a top view of the semiconductor memory device 101 to extend substantially along a second direction D2 with respect to the plurality of isolation structures 20 and the plurality of active regions 10A in the thickness direction of the substrate 10 (e.g., Figure 1 and Figure 2 The second direction D2 partially overlaps the first direction D1 (as shown in FIG). In some embodiments, the second direction D2 may be substantially perpendicular to the first direction D1, but is not limited thereto. Each floating gate FG may be disposed between the control gate CG and the active region 10A and located where the control gate CG and the active region 10A overlap in the third direction D3. A dielectric layer 32 may be disposed between each floating gate FG and the corresponding active region 10A, and a memory layer 40 may be disposed between the control gate CG and the corresponding floating gate FG.

[0082] In some embodiments, the dielectric layer 32 can comprise silicon oxide, silicon oxynitride, or other suitable dielectric material, the floating gate FG and the control gate CG can respectively comprise conductive material such as non-metallic conductive material (e.g., doped polysilicon), metallic conductive material, or other suitable conductive material, and the storage layer 40 can comprise a charge storage structure composed of multiple layers of material, but the application is not limited in this regard. For example, in some embodiments, the storage layer 40 can comprise a first oxide layer 42, a nitride layer 44, and a second oxide layer 46 stacked on top of each other, the first oxide layer 42 and the second oxide layer 46 can respectively comprise silicon oxide or other suitable oxide material, and the nitride layer 44 can comprise silicon nitride or other suitable nitride material, so the storage layer 40 can be regarded as an oxide-nitride-oxide (ONO) structure, but the application is not limited in this regard.

[0083] In some embodiments, the method of fabricating the floating gate FG can comprise, but is not limited to, the following steps. First, the upper portion of the isolation structure 20 can be adjusted to be higher than the active region 10A in the third direction D3 by a fabrication process. Then, the dielectric layer 32 and the conductive material to form the floating gate FG can be formed on the active region 10A and between adjacent isolation structures 20. Next, the storage layer 40 and the conductive material to form the control gate CG can be formed, and the conductive material and the storage layer 40 can be patterned by a patterning fabrication process to form the control gate CG. In some embodiments, the conductive material to form the floating gate FG can be patterned together with the control gate CG in the above-mentioned patterning fabrication process to form the floating gate FG between the control gate CG and the active region 10A, but the application is not limited in this regard.

[0084] However, in some embodiments, the end of the isolation structure 20 in the extension direction (e.g., the first direction D1) can have a curved edge affected by the fabrication process, so if the alignment is off (e.g., the control gate CG is shifted to the right) in the above-mentioned patterning fabrication process, the shape of the floating gate FG formed can be affected by the curved edge of the isolation structure 20, causing the distance between adjacent floating gates FG to be too small or short-circuiting to occur. The above-mentioned condition can affect the production yield of the semiconductor memory device 101, and when the memory cell of the semiconductor memory device needs to be continuously scaled down in design, the process window of each component can be relatively reduced, which is not conducive to production. Figure 1 The control gate CG shown is shifted to the right Figure 1 of the floating gate FG, the shape of the floating gate FG formed can be affected by the curved edge of the isolation structure 20, causing the distance between adjacent floating gates FG to be too small or short-circuiting to occur. The above-mentioned condition can affect the production yield of the semiconductor memory device 101, and when the memory cell of the semiconductor memory device needs to be continuously scaled down in design, the process window of each component can be relatively reduced, which is not conducive to production.

[0085] Different embodiments of the present application will be described below, and for simplicity of illustration, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same elements in different embodiments of the present application are denoted by the same reference numerals, so as to facilitate mutual comparison between the embodiments.

[0086] Please refer to Figure 3 . Figure 3 The schematic diagram of the semiconductor storage device 102 of the second embodiment of the present application is shown. As shown, the semiconductor storage device 102 includes a substrate 10, an isolation layer 22, a trench TR, a semiconductor active structure 30, and a floating gate FG. The isolation layer 22 is disposed on the substrate 10. The trench TR penetrates the isolation layer 22 and exposes a portion of the substrate 10. The semiconductor active structure 30 is disposed in the trench TR. The floating gate FG is disposed on the semiconductor active structure 30. Figure 3

[0087] In the present embodiment, the substrate 10 can include a semiconductor substrate, an insulating substrate, or a substrate formed of other suitable material, and the semiconductor active structure 30 is disposed in the trench TR penetrating the isolation layer 22 in the third direction D3, so the material composition of the semiconductor active structure 30 can be different from that of the substrate 10. In some embodiments, the semiconductor active structure 30 can include a single layer or multiple layers of semiconductor material, such as amorphous silicon semiconductor material, single crystal silicon semiconductor material, polycrystalline silicon semiconductor material, or other suitable type of semiconductor material, and the isolation layer 22 can include a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or other suitable insulating material.

[0088] In addition, in some embodiments, the semiconductor storage device 102 can further include an etching stop layer 21 disposed between the isolation layer 22 and the substrate 10, and the trench TR can further penetrate the etching stop layer 21. The etching stop layer 21 can include nitride (such as silicon nitride) or other suitable dielectric material different from the material of the isolation layer 22 and having a desired etching selectivity ratio with the material of the isolation layer 22. In some embodiments, the trench TR can be formed by etching the isolation layer 22 and the etching stop layer 21, and due to the characteristics of the etching fabrication process, the upper width (such as the width W2 shown in FIG. 2) of the trench TR can be greater than the lower width (such as the width W1 shown in FIG. 2) of the trench TR. Figure 3 Figure 3 ​​In some embodiments, the upper surface S2 of the semiconductor active structure 30 can be lower than the upper surface S1 of the isolation layer 22 in the thickness direction (e.g., the third direction D3) of the substrate 10, so the distance between the upper surface S2 of the semiconductor active structure 30 and the substrate 10 in the third direction D3 can be less than the distance between the upper surface S1 of the isolation layer 22 and the substrate 10 in the third direction D3, but not limited thereto. In addition, the floating gate FG can be disposed on the semiconductor active structure 30 and at least partially located in the trench TR. In some embodiments, the semiconductor active structure 30 disposed in the trench TR can directly contact the isolation layer 22 and the etching stop layer 21, so the shape of the semiconductor active structure 30 can be affected by the shape of the trench TR, but not limited thereto. For example, the upper width (e.g., the width W) of the semiconductor active structure 30 can also be greater than the lower width (e.g., the width W1) of the semiconductor active structure 30, the upper width of the semiconductor active structure 30 can be slightly less than the upper width of the trench TR, and the lower width of the semiconductor active structure 30 can be substantially equal to the lower width of the trench TR, but not limited thereto.

[0089] In some embodiments, the upper surface (e.g., the upper surface S2 shown in Figure 3 FIG. 1) of the semiconductor active structure 30 can be lower than the upper surface (e.g., the upper surface S1 shown in Figure 3 FIG. 1) of the isolation layer 22 in the thickness direction (e.g., the third direction D3) of the substrate 10, so the distance between the upper surface S2 of the semiconductor active structure 30 and the substrate 10 in the third direction D3 can be less than the distance between the upper surface S1 of the isolation layer 22 and the substrate 10 in the third direction D3, but not limited thereto. In addition, the floating gate FG can be disposed on the semiconductor active structure 30 and at least partially located in the trench TR. In some embodiments, the semiconductor active structure 30 disposed in the trench TR can directly contact the isolation layer 22 and the etching stop layer 21, so the shape of the semiconductor active structure 30 can be affected by the shape of the trench TR, but not limited thereto. For example, the upper width (e.g., the width W) of the semiconductor active structure 30 can also be greater than the lower width (e.g., the width W1) of the semiconductor active structure 30, the upper width of the semiconductor active structure 30 can be slightly less than the upper width of the trench TR, and the lower width of the semiconductor active structure 30 can be substantially equal to the lower width of the trench TR, but not limited thereto. Figure 3 Figure 3 In some embodiments, the upper width (e.g., the width W) of the semiconductor active structure 30 can also be greater than the lower width (e.g., the width W1) of the semiconductor active structure 30, the upper width of the semiconductor active structure 30 can be slightly less than the upper width of the trench TR, and the lower width of the semiconductor active structure 30 can be substantially equal to the lower width of the trench TR, but not limited thereto.

[0090] In addition, in some embodiments, the isolation layer 22 can be divided into a plurality of mutually separated isolation blocks 22P by the trench TR, each isolation block 22P can be surrounded by the trench TR in the horizontal direction (e.g., the first direction D1 and the second direction D2), and the upper width (e.g., the width W4 shown in Figure 3 FIG. 1) of each isolation block 22P can be less than the lower width (e.g., the width W5 shown in Figure 3 ​In other words, each isolation block 22P may have a structure that is narrow at the top and wide at the bottom, while the semiconductor active structure 30 and the trench TR may each have a structure that is wide at the top and narrow at the bottom, but the present invention is not limited thereto.

[0091] In some embodiments, the semiconductor memory device 102 may further include a dielectric layer 32, a memory layer 40, and a control gate CG. The dielectric layer 32 may be disposed between the floating gate FG and the semiconductor active structure 30 and at least partially disposed in the trench TR. The memory layer 40 may be disposed on the floating gate FG and the dielectric layer 32, and the control gate CG may be disposed on the memory layer 40. In some embodiments, the dielectric layer 32 may be partially disposed on the isolation layer 22, and the upper surface of the floating gate FG (e.g., Figure 3 The upper surface S3 shown in FIG. 3 may be connected to the upper surface of the dielectric layer 32 (eg Figure 3 ) are substantially coplanar, but the present invention is not limited thereto. It is worth noting that, in some embodiments, the aforementioned top surfaces S1, S2, S3, and S4 may be the topmost surfaces of the isolation layer 22, the semiconductor active structure 30, the floating gate FG, and the dielectric layer 32 in the third direction D3, respectively, but the present invention is not limited thereto. It is worth noting that, in some embodiments, the material composition of the dielectric layer 32 may be the same as that of the isolation layer 22. In this case, the dielectric layer 32 connected to the isolation block 22P may be integrated with the isolation block 22P without a distinct interface, thereby causing the top of the isolation block 22P to become wider (i.e., the portion where the isolation block 22P and the dielectric layer 32 are integrated), resulting in each isolation block 22P having a relatively wider top and bottom portion and a relatively narrower middle portion, but the present invention is not limited thereto.

[0092] By disposing a semiconductor active structure 30 in the trench TR penetrating the isolation layer 22 and disposing a floating gate FG on the semiconductor active structure 30, short circuits between adjacent floating gates FG due to the edge of the isolation layer 22 can be avoided, thereby improving the manufacturing process tolerance and increasing the production yield.

[0093] See also Figures 3 to 17 . Figures 4 to 17 The diagram shows a method for manufacturing the semiconductor memory device 102 according to the present embodiment, wherein Figure 5 Draws Figure 4 Schematic diagram of the situation afterwards, Figure 6 For the Figure 5 The cross-sectional view shown along the BB' section line is as follows: Figure 7 For the Figure 5 The cross-sectional view shown along the C-C' line, Figure 8 Draws Figure 7 Schematic diagram of the situation afterwards,Figure 9 Draws Figure 8 Schematic diagram of the situation afterwards, Figure 10 For the Figure 9 The cross-sectional view shown along the D-D' section line is as follows: Figure 11 Draws Figure 9 Schematic diagram of the situation afterwards, Figure 12 For the Figure 11 The cross-sectional view shown along the E-E' line is Figure 13 Draws Figure 12 Schematic diagram of the situation afterwards, Figure 14 Draws Figure 13 Schematic diagram of the situation afterwards, Figure 15 For the Figure 14 The cross-sectional view shown along the F-F' line, Figure 16 Draws Figure 14 Schematic diagram of the situation afterwards, Figure 17 Draws Figure 16 The following diagram shows the situation: Figure 3 Can be considered as Figure 17 The cross-sectional view shown by the G-G' section line. Figure 3 As shown, the method for fabricating the semiconductor memory device 102 of this embodiment may include the following steps. First, an isolation layer 22 is formed on a substrate 10, and a trench TR is formed through the isolation layer 22 to expose a portion of the substrate 10. Then, a semiconductor active structure 30 is formed in the trench TR, and a floating gate FG is formed on the semiconductor active structure 30.

[0094] To further illustrate, the method for manufacturing the semiconductor memory device 102 of this embodiment may include but is not limited to the following steps. Figures 4 to 7 As shown, an isolation layer 22 can be formed on the substrate 10, and a first patterned mask layer 24 can be formed on the isolation layer 22. Then, a first etching process 91 is performed on the isolation layer 22 using the first patterned mask layer 24 as an etching mask to form a first portion P1 of the trench TR, and the first patterned mask layer 24 can be removed after the first etching process 91. In some embodiments, an etching stop layer 21 can be formed on the substrate 10 before forming the isolation layer 22, so the isolation layer 22 can be formed on the etching stop layer 21. In addition, the above-mentioned first etching process 91 can stop on the etching stop layer 21, so after the first etching process 91, the first portion P1 of the trench TR can penetrate the isolation layer 22 in the third direction D3 without penetrating the etching stop layer 21, thereby achieving the effect of protecting the substrate 10, but not limited to this. As Figures 5 to 7As shown, the trench TR can include a plurality of first portions P1, each first portion P1 extending along the first direction D1, and the plurality of first portions P1 can be arranged in a repeating pattern along the second direction D2, but the disclosure is not limited thereto. In some embodiments, the first etching process 91 can include a dry etching process or other suitable etching process, and as a result of the characteristics of the etching process, the upper width (e.g., width W2 as shown in Figure 6 ) of each first portion P1 can be greater than the lower width (e.g., width W1 as shown in Figure 6 ) of each first portion P1, but the disclosure is not limited thereto.

[0095] Then, as shown in Figures 8 to 10 , a second patterned mask layer 26 can be formed on the isolation layer 22, and a second etching process 92 can be performed on the isolation layer 22 and the etch stop layer 21 using the second patterned mask layer 26 as an etching mask, so as to form the second portions P2 of the trench TR, and the second patterned mask layer 26 can be removed after the second etching process 92. In other words, the trench TR can include a plurality of first portions P1 and a plurality of second portions P2, the first portions P1 can be formed by the first etching process described above, and the second portions P2 can be formed by the second etching process 92, and the second etching process 92 can be performed after the first etching process. In addition, in some embodiments, the second etching process 92 can include a dry etching process or other suitable etching process, and as a result of the characteristics of the etching process, the upper width (e.g., width W6 as shown in Figure 10 ) of each second portion P2 can be greater than the lower width (e.g., width W5 as shown in Figure 10 ) of each second portion P2, but the disclosure is not limited thereto. In addition, in some embodiments, the second etching process 92 can include a first etching step and a second etching step performed after the first etching step, the first etching step can be used to etch the isolation layer 22 to form the second portions P2 of the trench TR, and the first etching step can stop on the etch stop layer 21, and the second etching step can etch the etch stop layer 21 exposed by the first portions P1 and the second portions P2 of the trench TR, so that the first portions P1 and the second portions P2 of the trench TR respectively penetrate downward through the etch stop layer 21 to expose portions of the substrate 10. In other words, the process conditions of the second etching step can be different from the process conditions of the first etching step, thereby reducing the negative effects of the second etching process 92 on the substrate 10.

[0096] As shown in Figure 9 , the second portions P2 of the trench TR can be formed by the second etching process 92, and the first portions P1 of the trench TR can be formed by the first etching process 91. In addition, as shown in Figure 10As shown, each second portion P2 can extend along the second direction D2, and the plurality of second portions P2 can intersect with the plurality of first portions PI and connect with each other. In addition, the isolation layer 22 can be divided into a plurality of isolation blocks 22P by the first portions PI and the second portions P2 of the trench TR, each of the isolation blocks 22P can be surrounded by the plurality of first portions PI and the plurality of second portions P2 of the trench TR in the horizontal direction (e.g., the first direction D1 and the second direction D2), and an upper width (e.g., the width W8 shown in Figure 10 ) of each of the isolation blocks 22P can be less than a lower width (e.g., the width W7 shown in Figure 10 ) of each of the isolation blocks 22P, but the disclosure is not limited thereto.

[0097] Then, as shown in Figure 11 and Figure 12 , a semiconductor active structure 30 can be formed in the trench. In some embodiments, the semiconductor active structure 30 can be formed on the substrate 10 and in the trench TR by a deposition fabrication process, an epitaxial growth fabrication process, or other suitable methods, so the semiconductor active structure 30 can directly contact the substrate, but the disclosure is not limited thereto. In addition, in some embodiments, the fabrication process conditions for forming the semiconductor active structure 30 or / and the semiconductor active structure 30 can be etched back so that the upper surface S2 of the semiconductor active structure 30 is still lower than the upper surface SI of the isolation layer 22 in the third direction D3, but the disclosure is not limited thereto.

[0098] Next, as shown in Figure 13 , a dielectric layer 32 can be conformally formed on the isolation layer 22 and the semiconductor active structure 30, and a first material layer 34 can be formed on the dielectric layer 32. The first material layer 34 can be used to form the floating gate as described above, and the first material layer 34 can include a conductive material such as a non-metallic conductive material (e.g., doped polysilicon), a metallic conductive material, or other suitable conductive material. In some embodiments, the first material layer 34 can fill the space left in the trench TR and partially formed outside the trench TR, but the disclosure is not limited thereto. Then, as shown in Figures 13 to 15 , part of the first material layer 34 can be removed to expose part of the dielectric layer 32 by a planarization fabrication process. The planarization fabrication process can include a chemical mechanical polishing (CMP) fabrication process, an etch-back fabrication process, or other suitable planarization methods. In some embodiments, the dielectric layer 32 can be used as a stop layer in the planarization fabrication process, so after the planarization fabrication process, the upper surface S4 of the dielectric layer 32 can be substantially coplanar with the upper surface S5 of the first material layer 34, but the disclosure is not limited thereto.

[0099] Then, as shown in Figure 16As shown, a memory layer 40 may be formed entirely on the first material layer 34 and the dielectric layer 32, and a second material layer 36 may be formed on the memory layer 40. The second material layer 36 may be used to form the control gate described above, and the second material layer 36 may include a conductive material such as a non-metallic conductive material (such as doped polysilicon), a metallic conductive material, or other suitable conductive materials. Figure 16 、 Figure 17 as well as Figure 3 As shown, a patterning process 93 may be performed on the second material layer 36 and the memory layer 40 to form a plurality of control gates CG and the memory layer 40 located below the control gates CG. The patterning process 93 may include a photolithography process or other suitable patterning method. Furthermore, in some embodiments, the first material layer 34 may also be patterned by the patterning process 93 to form a plurality of floating gates FG in the overlapping region between the control gates CG and the semiconductor active structure 30 in the third direction D3, but this is not limited thereto.

[0100] In the manufacturing method of the present embodiment, since the isolation layer 22 can be divided by the first portion P1 and the second portion P2 extending in different directions in the trench TR to form a plurality of isolation blocks 22P, the ends of the isolation blocks 22P in their extension direction (e.g., the first direction D1) are less likely to have curved edges. This can improve the manufacturing process tolerance of the patterning process 93 used to form the control gate CG and the floating gate FG, thereby achieving the effect of improving the production yield.

[0101] See also Figure 18 . Figure 18 FIG. 1 is a schematic diagram of a semiconductor memory device 103 according to a third embodiment of the present invention. Figure 18 As shown, the difference from the second embodiment is that the upper surface S3 of the floating gate FG in the semiconductor memory device 103 can be substantially coplanar with the upper surface S1 of the isolation layer 22, so the memory layer 40 can directly contact the floating gate FG, the dielectric layer 32 and the isolation layer 22, but the present invention is not limited thereto. In the method for manufacturing the semiconductor memory device 103, when the first material layer for forming the floating gate FG is planarized (for example, similar to the above-mentioned process), the first material layer for forming the floating gate FG is planarized. Figure 15 In the case of a situation where the upper surface S1 of the isolation layer 22 is not present, the dielectric layer 32 located on the upper surface S1 of the isolation layer 22 may also be removed, so that the upper surface S3 of the floating gate FG is substantially coplanar with the upper surface S1 of the isolation layer 22, but the present invention is not limited thereto. By removing the dielectric layer 32 located on the isolation layer 22, the thickness of the dielectric layer between the control gate CG and the semiconductor active structure 30 can be reduced, which positively improves the operating performance of the semiconductor memory device 103.

[0102] See also Figure 19. Figure 19 FIG. 1 is a schematic diagram of a semiconductor memory device 104 according to a fourth embodiment of the present invention. Figure 19 As shown, in the semiconductor memory device 104, the isolation layer 22 may include a first layer 22A and a second layer 22B. The second layer 22B may be disposed on the first layer 22A, and the material composition of the first layer 22A may be different from the material composition of the second layer 22B. For example, the dielectric constant of the second layer 22B may be lower than the dielectric constant of the first layer 22A, thereby enhancing the isolation effect of the upper portion, but the present invention is not limited to this. In addition, since the semiconductor active structure 30 is formed in the trench TR that penetrates the second layer 22B of the isolation layer 22, the first layer 22A of the isolation layer 22, and the etching stop layer 21, the semiconductor active structure 30 may directly contact the sidewalls of the second layer 22B of the isolation layer 22, the first layer 22A of the isolation layer 22, and the etching stop layer 21, but the present invention is not limited to this. It is worth noting that the isolation layer 22 having a multi-layer structure in this embodiment can also be applied to other embodiments of the present invention according to design requirements.

[0103] In summary, in the semiconductor storage device and its manufacturing method of the present invention, a semiconductor active structure can be formed in a trench penetrating the isolation layer, so that the isolation block formed by the trench is less likely to have a curved edge at the end in its extension direction, thereby improving the manufacturing process tolerance range of the patterning process used to form the control gate and the floating gate, thereby achieving the effect of improving the production yield.

[0104] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor memory device, characterized in that: include: substrate; an isolation layer disposed on the substrate; a groove penetrating the isolation layer and exposing a portion of the substrate; A semiconductor active structure is disposed in the trench; as well as The floating gate is disposed in the trench and located on the semiconductor active structure. 2 . The semiconductor memory device as claimed in claim 1 , wherein a material composition of the semiconductor active structure is different from a material composition of the substrate. 3 . The semiconductor memory device according to claim 1 , wherein an upper width of the trench is greater than a lower width of the trench. 4 . The semiconductor memory device as claimed in claim 1 , wherein an upper width of the semiconductor active structure is greater than a lower width of the semiconductor active structure. 5 . The semiconductor memory device according to claim 1 , wherein the isolation layer comprises at least one isolation block surrounded by the trench, and an upper width of the at least one isolation block is smaller than a lower width of the at least one isolation block. 6 . The semiconductor memory device as claimed in claim 1 , wherein an upper surface of the semiconductor active structure is lower than an upper surface of the isolation layer in a thickness direction of the substrate. 7 . The semiconductor memory device as claimed in claim 1 , wherein an upper surface of the floating gate is coplanar with an upper surface of the isolation layer.

8. The semiconductor memory device according to claim 1, further comprising: An etching stop layer is disposed between the isolation layer and the substrate, wherein the trench also penetrates the etching stop layer.

9. The semiconductor memory device according to claim 1 , wherein the isolation layer comprises: First floor; as well as The second layer is disposed on the first layer, wherein the semiconductor active structure directly contacts the first layer and the second layer. 10 . The semiconductor memory device according to claim 9 , wherein a material composition of the first layer is different from a material composition of the second layer.

11. A method for manufacturing a semiconductor memory device, comprising: forming an isolation layer on a substrate; forming a trench penetrating the isolation layer and exposing a portion of the substrate; forming a semiconductor active structure in the trench; as well as A floating gate is formed on the semiconductor active structure and is disposed in the trench.

12. The method for manufacturing a semiconductor memory device according to claim 11, wherein the trench comprises: a plurality of first portions, wherein each of the first portions extends along a first direction; as well as A plurality of second portions are provided, wherein each of the second portions extends along a second direction, and the plurality of second portions intersect with the plurality of first portions.

13. The method for manufacturing a semiconductor memory device according to claim 12, wherein the plurality of first portions are formed by a first etching process, and the plurality of second portions are formed by a second etching process, and the second etching process is performed after the first etching process.

14. The method for manufacturing a semiconductor memory device according to claim 12, wherein the isolation layer comprises at least one isolation block surrounded by the plurality of first portions and the plurality of second portions of the trench, and an upper width of the at least one isolation block is smaller than a lower width of the at least one isolation block. 15 . The method for manufacturing a semiconductor memory device according to claim 12 , wherein an upper width of each of the first portions is greater than a lower width of each of the first portions. 16 . The method for manufacturing a semiconductor memory device according to claim 12 , wherein an upper width of each of the second portions is greater than a lower width of each of the second portions. 17 . The method for manufacturing a semiconductor memory device according to claim 11 , wherein an upper width of the semiconductor active structure is greater than a lower width of the semiconductor active structure. 18 . The method for manufacturing a semiconductor memory device according to claim 11 , wherein an upper surface of the semiconductor active structure is lower than an upper surface of the isolation layer in a thickness direction of the substrate.

19. The method for manufacturing a semiconductor memory device according to claim 11, wherein an upper surface of the floating gate is coplanar with an upper surface of the isolation layer.

20. The method for manufacturing a semiconductor memory device according to claim 11, further comprising: Before forming the isolation layer, an etch stop layer is formed on the substrate, wherein the trench also penetrates the etch stop layer.

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