Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. The present technology provides a semiconductor device. The semiconductor device includes: a laminate including insulating patterns and conductive patterns alternately layered with each other; a channel layer including a first channel portion protruding from the laminate and a second channel portion in the laminate, and passing through the laminate; and a conductive line surrounding the first channel portion, and the first channel portion including a metal silicide.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional semiconductor memory device includes memory cells arranged in a three-dimensional form, thereby reducing an area occupied by the memory cells per unit area of a substrate.

[0003] To increase the integration of a three-dimensional semiconductor memory device, the number of layers of memory cells can be increased. As the number of layers of memory cells increases, the operation reliability of the three-dimensional semiconductor memory device can decrease. SUMMARY

[0004] A semiconductor device according to an embodiment of the disclosure can include a stack including insulating patterns and conductive patterns alternately stacked with each other, a channel layer including a first channel portion protruding from the stack and a second channel portion in the stack and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion can include a metal silicide.

[0005] A semiconductor device according to an embodiment of the disclosure can include a stack including insulating patterns and conductive patterns alternately stacked with each other, a channel layer including a first channel portion protruding from the stack and a second channel portion in the stack and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion, the second channel portion, and the conductive line can include different materials.

[0006] A method of manufacturing a semiconductor device according to an embodiment of the disclosure can include forming a support structure, forming a stack on the support structure, forming a channel layer passing through the stack, removing the support structure to expose a first protruding portion of the channel layer, forming a diffusion metal layer in contact with the first protruding portion, performing a heat treatment to change the first protruding portion into a first channel portion, and removing the diffusion metal layer.

[0007] A method of manufacturing a semiconductor device according to an embodiment of the disclosure can include forming a support structure, forming a stack on the support structure, forming a channel layer passing through the stack, removing the support structure to expose an upper surface and a sidewall of a first protruding portion of the channel layer, forming a diffusion metal layer covering the upper surface and the sidewall of the first protruding portion, and performing a heat treatment to change the first protruding portion into a first channel portion. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1Ais a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 1B is Figure 1A is an enlarged view of a region A of

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15 are cross-sectional views showing a manufacturing method of a semiconductor device according to Figure 1A and Figure 1B .

[0011] Figure 10B is an enlarged view of a region B of Figure 10A

[0012] Figure 11B is an enlarged view of a region C of Figure 11A

[0013] Figure 12B is an enlarged view of a region D of Figure 12A

[0014] Figure 13B is an enlarged view of a region E of Figure 13A

[0015] Figure 14B is an enlarged view of a region F of Figure 14A

[0016] Figure 16 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0017] Figure 17 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The specific structure or function described in the present specification or the present application disclosed according to the embodiments of the concept is only for the purpose of describing the embodiments of the concept according to the present disclosure. The embodiments of the concept according to the present disclosure can be performed in various forms, and should not be interpreted as being limited to the embodiments described in the present specification or the application.

[0019] ​​​​​It will be understood that, although the terms first, second, and third etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. The terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0020] It will be understood that when an element or layer is referred to as being "around", "over", "on", "connected to", "coupled to" or "in contact with" another element or layer, it can be directly on, connected to, coupled to, over, around or in contact with the other element or layer, or one or more intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly" "around", "over", "on", "connected to", "coupled to" or "in contact with" another element or layer, there are no intervening elements or layers present. Throughout the specification, like reference signs refer to like elements.

[0021] Embodiments of the present disclosure provide a semiconductor device capable of improving operation reliability and a manufacturing method of the semiconductor device.

[0022] In the semiconductor device according to the embodiment of the present technology, a portion of the channel layer that is in contact with the conductive line can be formed of a metal silicide, and thus the conductive line can be formed of a metal material.

[0023] Figure 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B is Figure 1A is a magnified view of a region A of

[0024] Referring to Figure 1A and Figure 1B , the semiconductor device can include a cell region CER and a connection region COR. The cell region CER and the connection region COR can be regions divided in a planar direction.

[0025] A semiconductor device can include a substrate 100. The substrate 100 can have a shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can intersect each other. For example, the first direction D1 and the second direction D2 can be orthogonal to each other. The substrate 100 can extend from a cell region CER to a connection region COR. For example, the substrate 100 can extend in the first direction D1. The substrate 100 can include a semiconductor material. For example, the substrate 100 can include silicon.

[0026] A first insulating layer 110 can be disposed on the substrate 100. The first insulating layer 110 can cover the substrate 100. The first insulating layer 110 can include an insulating material. For example, the first insulating layer 110 can include an oxide.

[0027] A peripheral transistor TR can be disposed between the substrate 100 and the first insulating layer 110. The peripheral transistor TR can be a transistor constituting a peripheral circuit of the semiconductor device.

[0028] The peripheral transistor TR can include an impurity region IR, a gate insulating layer GI, and a gate GM. The impurity region IR can be disposed in the substrate 100. The impurity region IR can be formed by doping an impurity into the substrate 100. A channel of the peripheral transistor TR can be formed between the impurity regions IR. The gate GM can be spaced apart from the substrate 100 with the gate insulating layer GI interposed therebetween. The gate GM can include a conductive material, and the gate insulating layer GI can include an insulating material.

[0029] An element isolation layer ST can be disposed in the substrate 100. The element isolation layer ST can electrically isolate the peripheral transistors TR constituting the peripheral circuit from each other. The element isolation layer ST can include an insulating material.

[0030] A first contact CT1 and a first conductor CB1 can be disposed in the first insulating layer 110. The gate GM and the impurity region IR of the peripheral transistor TR can be in contact with the first contact CT1. The first contact CT1 and the first conductor CB1 can be electrically connected to the peripheral transistor TR. Each of the first contact CT1 and the first conductor CB1 can include a conductive layer and a barrier layer surrounding the conductive layer. For example, the conductive layer can include copper, tungsten, or aluminum. For example, the barrier layer can include titanium, titanium nitride, tantalum, or tantalum nitride. A width of the first contact CT1 can decrease as the first contact CT1 approaches the peripheral transistor TR. The first contact CT1 can extend in a third direction D3. The third direction D3 can intersect the first direction D1 and the second direction D2. For example, the third direction D3 can be orthogonal to the first direction D1 and the second direction D2.

[0031] A second insulating layer 120 can be disposed on the first insulating layer 110. The second insulating layer 120 can cover the first insulating layer 110. The second insulating layer 120 can include an insulating material. For example, the second insulating layer 120 can include an oxide.

[0032] A second conductor CB2, a third conductor CB3, and a second contact CT2 can be disposed in the second insulating layer 120. The second conductor CB2 can be disposed in the cell region CER. The second conductor CB2 can contact the first conductor CB1 disposed in the cell region CER. The second conductor CB2 can be a conductive line extending in the first direction D1. The second conductor CB2 can be used as a bit line of the semiconductor device.

[0033] The third conductor CB3 can be disposed in the connection region COR. The third conductor CB3 can contact the first conductor CB1 disposed in the connection region COR.

[0034] The second contact CT2 can contact the third conductor CB3. The second contact CT2 can be disposed in the connection region COR. The second contact CT2 can extend in the third direction D3. A width of the second contact CT2 can increase as the second contact CT2 approaches the peripheral transistor TR.

[0035] Each of the second conductor CB2 and the third conductor CB3 and the second contact CT2 can include a conductive layer and a barrier layer.

[0036] A third insulating layer 130 can be disposed on the second insulating layer 120. The third insulating layer 130 can cover the second insulating layer 120. The third insulating layer 130 can include an insulating material. For example, the third insulating layer 130 can include an oxide.

[0037] A fourth insulating layer 140 can be disposed on the third insulating layer 130. The fourth insulating layer 140 can cover the third insulating layer 130. The fourth insulating layer 140 can include an insulating material. For example, the fourth insulating layer 140 can include an oxide.

[0038] A third contact CT3 can be disposed in the second to fourth insulating layers 120, 130, and 140. The third contact CT3 can pass through the third insulating layer 130 and the fourth insulating layer 140. The third contact CT3 can contact the second conductor CB2. The third contact CT3 can be disposed in the cell region CER. Each third contact CT3 can include a conductive layer and a barrier layer. The third contact CT3 can extend in the third direction D3. A width of the third contact CT3 can increase as the third contact CT3 approaches the peripheral transistor TR.

[0039] A stack STA can be disposed on the fourth insulating layer 140. The stack STA can include a first stack portion STA1 in the cell region CER and a second stack portion STA2 in the connection region COR.

[0040] The first stack portion STA1 can include first insulating patterns IP1 and conductive patterns CP alternately stacked with each other in the third direction D3. The first insulating patterns IP1 can include an insulating material. For example, the first insulating patterns IP1 can include an oxide. The conductive patterns CP can include a gate conductive layer. The gate conductive layer can include a conductive material. For example, the gate conductive layer can include at least one of a doped silicon layer, a metal silicide layer, tungsten, nickel, and cobalt. The gate conductive layer can be used as a word line connected to a memory cell or a select line connected to a select transistor. The conductive patterns CP of the first stack portion STA1 can further include a gate barrier layer surrounding the gate conductive layer. For example, the gate barrier layer can include titanium, titanium nitride, tantalum, or tantalum nitride.

[0041] The second stack portion STA2 can include first insulating patterns IP1 and second insulating patterns IP2 alternately stacked with each other in the third direction D3. The first insulating patterns IP1 can include an insulating material. For example, the first insulating patterns IP1 can include an oxide. The second insulating patterns IP2 can include a material different from that of the first insulating patterns IP1. For example, the second insulating patterns IP2 can include a nitride.

[0042] The first insulating patterns IP1 of the second stack portion STA2 can be disposed at the same level as the first insulating patterns IP1 of the first stack portion STA1. The first insulating patterns IP1 of the second stack portion STA2 and the first insulating patterns IP1 of the first stack portion STA1 can be formed successively without a boundary. The second insulating patterns IP2 of the second stack portion STA2 can be disposed at the same level as the conductive patterns CP of the first stack portion STA1.

[0043] A fill layer FI can be disposed through the first stack portion STA1 of the stack STA. The fill layer FI can extend in the third direction D3. The fill layer FI can pass through the first insulating patterns IP1 and the conductive patterns CP of the first stack portion STA1 of the stack STA. The first insulating patterns IP1 and the conductive patterns CP of the first stack portion STA1 of the stack STA can surround the fill layer FI. The fill layer FI can include an insulating material. For example, the fill layer FI can include an oxide.

[0044] A channel layer CL can be provided through the first stacked portion STA1 of the laminate STA. The channel layer CL can extend in the third direction D3. The channel layer CL can pass through the first insulating pattern IP1 and the conductive pattern CP of the first stacked portion STA1 of the laminate STA. The first insulating pattern IP1 and the conductive pattern CP of the first stacked portion STA1 of the laminate STA can surround the channel layer CL. The channel layer CL can surround the fill layer FI.

[0045] The channel layer CL can be connected to the second conductor CB2 through the third contact CT3. The semiconductor device can include Figure 1A the third contact CT3 and the second conductor CB2 shown, and can include Figure 1A a third contact and a second conductor not shown in FIG. 1. The channel layer CL not connected to Figure 1A the third contact CT3 and the second conductor CB2 shown can be connected to Figure 1A a third contact and a second conductor not shown in FIG. 1. The channel layer CL can be electrically connected to the peripheral transistor TR through the third contact CT3, the second conductor CB2, the first conductor CB1, and the first contact CT1.

[0046] The channel layer CL can include a first channel portion CL1 protruding from the first stacked portion STA1 of the laminate STA, and a second channel portion CL2 and a third channel portion CL3 in the first stacked portion STA1 of the laminate STA. The first channel portion CL1 can be a portion protruding above the first stacked portion STA1 of the laminate STA. The first channel portion CL1 can be a portion surrounding a sidewall of the fill layer FI. The third channel portion CL3 can be a portion in contact with the third contact CT3 below the first stacked portion STA1 of the laminate STA. The third channel portion CL3 can be a portion covering a lower surface of the fill layer FI. The second channel portion CL2 can be a portion connecting the first channel portion CL1 and the third channel portion CL3 between the first channel portion CL1 and the third channel portion CL3. The second channel portion CL2 can extend in the third direction D3 and pass through a plurality of conductive patterns CP and first insulating patterns IP1. The second channel portion CL2 can be a portion surrounding a sidewall of the fill layer FI.

[0047] The first channel portion CL1 can include a material different from materials of the second channel portion CL2 and the third channel portion CL3. The second channel portion CL2 and the third channel portion CL3 can include polysilicon. The first channel portion CL1 can include a metal silicide. For example, the first channel portion CL1 can include a metal silicide that can be formed at a temperature of 450℃ or less. For example, the first channel portion CL1 can include a metal silicide that can be formed by combining a metal and silicon at a temperature of 450℃ or less. For example, the first channel portion CL1 can include nickel silicide. For example, a composition of the nickel silicide included in the first channel portion CL1 can be NiSi. The first channel portion CL1 and the second channel portion CL2 can form an ohmic contact.

[0048] A memory layer ML can be provided through the first stacked portion STA1 of the stack STA. The memory layer ML can extend in the third direction D3. The memory layer ML can pass through the first insulating pattern IP1 and the conductive pattern CP of the first stacked portion STA1 of the stack STA. The first insulating pattern IP1 and the conductive pattern CP of the first stacked portion STA1 of the stack STA can surround the memory layer ML. The memory layer ML can surround the second channel portion CL2 and the third channel portion CL3 of the channel layer CL.

[0049] The memory layer ML can include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer can include a material capable of charge tunneling. For example, the tunnel insulating layer can include an oxide. In one embodiment, the data storage layer can include a material capable of trapping charge. For example, the data storage layer can include a nitride. In another embodiment, the data storage layer can include various materials according to a data storage method. For example, the data storage layer can include silicon, a phase change material, or a nanodot. The blocking layer can include a material capable of blocking charge movement. For example, the blocking layer can include an oxide.

[0050] A fourth contact portion CT4 can be disposed through the third insulating layer 130, the fourth insulating layer 140, and the second stacked portion STA2 of the stack STA. The fourth contact portion CT4 can extend in the third direction D3. The fourth contact portion CT4 can pass through the first insulating pattern IP1 and the second insulating pattern IP2 of the second stacked portion STA2 of the stack STA. The first insulating pattern IP1 and the second insulating pattern IP2 of the second stacked portion STA2 of the stack STA can surround the fourth contact portion CT4. A portion of the fourth contact portion CT4 can protrude above the second stacked portion STA2 of the stack STA. The fourth contact portion CT4 can include a conductive layer and a barrier layer. The fourth contact portion CT4 can be in contact with the second contact portion CT2.

[0051] A slit insulating layer SLI can be disposed through the fourth insulating layer 140 and the first stacked portion STA1 of the stack STA. The slit insulating layer SLI can extend in the second direction D2 and the third direction D3. The slit insulating layer SLI can pass through the first insulating pattern IP1 and the conductive pattern CP of the first stacked portion STA1 of the stack STA. The conductive patterns CP on both sides of the slit insulating layer SLI can be spaced apart from each other in the first direction D1 by the slit insulating layer SLI. The first insulating patterns IP1 on both sides of the slit insulating layer SLI can be spaced apart from each other in the first direction D1 by the slit insulating layer SLI.

[0052] The slit insulating layer SLI can include the same material as the third insulating layer 130. For example, the slit insulating layer SLI can include an oxide. The slit insulating layer SLI can be formed continuously without a boundary with the third insulating layer 130.

[0053] A fourth conductor CB4 can be disposed over the first layer stack portion STAl of the stack structure STA. The fourth conductor CB4 can extend from the cell region CER to the connection region COR. The fourth conductor CB4 can be a conductive line extending in the first direction Dl. The fourth conductor CB4 can function as a source line of the semiconductor device. The fourth conductor CB4 can be in contact with the first channel portion CLl of the channel layer CL. The fourth conductor CB4 can surround the first channel portion CLl of the channel layer CL. The fourth conductor CB4 can include a material different from that of the first channel portion CLl and the second channel portion CL2. In one embodiment, the fourth conductor CB4 can be in direct contact with the first channel portion CLl. In one embodiment, the fourth conductor CB4 can be in direct contact with the second portion CLlb of the first channel portion CLl. In one embodiment, a barrier layer BR of the fourth conductor CB4 can be in direct contact with the first channel portion CLl. In one embodiment, a barrier layer BR of the fourth conductor CB4 can be in direct contact with the second portion CLlb of the first channel portion CLl. In one embodiment, the first portion CLla can be in direct contact with the second channel portion CL2. In one embodiment, the second portion CLlb is spaced apart from the second channel portion CL2.

[0054] The fourth conductor CB4 can include a conductive layer CO and a barrier layer BR. The conductive layer CO and the barrier layer BR can include different materials. The conductive layer CO can include a metal different from that included in the barrier layer BR. For example, the conductive layer CO can include copper, tungsten, or aluminum. For example, the barrier layer BR can include titanium, titanium nitride, tantalum, or tantalum nitride.

[0055] The barrier layer BR of the fourth conductor CB4 can cover the first channel portion CLl of the channel layer CL. The barrier layer BR of the fourth conductor CB4 can be in contact with the first channel portion CLl of the channel layer CL. The conductive layer CO of the fourth conductor CB4 can be spaced apart from the stack structure STA and the first channel portion CLl of the channel layer CL with the barrier layer BR of the fourth conductor CB4 interposed therebetween.

[0056] A fifth conductor CB5 can be disposed on the second layer stack portion STA2 of the stack structure STA. The fifth conductor CB5 can be disposed in the connection region COR. The fifth conductor CB5 can be in contact with the fourth contact CT4. The fifth conductor CB5 can include a conductive layer CO and a barrier layer BR. The barrier layer BR of the fifth conductor CB5 can be in contact with the fourth contact CT4. The conductive layer CO of the fifth conductor CB5 can be spaced apart from the stack structure STA and the fourth contact CT4 with the barrier layer BR of the fifth conductor CB5 interposed therebetween.

[0057] A fifth insulating layer 150 covering the fourth conductor CB4 and the fifth conductor CB5 can be provided. A portion of the fifth insulating layer 150 can be provided between the fourth conductor CB4 and the fifth conductor CB5. The fourth conductor CB4 and the fifth conductor CB5 can be spaced apart from each other in the first direction D1 by the fifth insulating layer 150. The fourth conductor CB4 and the fifth conductor CB5 can be electrically separated from each other by the fifth insulating layer 150. The fifth insulating layer 150 can include an insulating material. For example, the fifth insulating layer 150 can include an oxide.

[0058] A fifth contact CT5 and a sixth contact CT6 can be provided in the fifth insulating layer 150. The fifth contact CT5 can be in contact with the fourth conductor CB4. The fifth contact CT5 can be provided in the cell region CER. The fifth contact CT5 can extend in the third direction D3. A width of the fifth contact CT5 can decrease as the fifth contact CT5 approaches the stack STA and the peripheral transistor TR.

[0059] The sixth contact CT6 can be in contact with the fifth conductor CB5. The sixth contact CT6 can be provided in the connection region COR. The sixth contact CT6 can extend in the third direction D3. A width of the sixth contact CT6 can decrease as the sixth contact CT6 approaches the stack STA and the peripheral transistor TR. Each of the fifth contact CT5 and the sixth contact CT6 can include a conductive layer and a barrier layer.

[0060] A sixth conductor CB6 and a seventh conductor CB7 can be provided in the fifth insulating layer 150. The sixth conductor CB6 can be in contact with the fifth contact CT5. The sixth conductor CB6 can be provided in the cell region CER. The sixth conductor CB6 can extend in the first direction D1. For example, the sixth conductor CB6 can include aluminum.

[0061] The seventh conductor CB7 can be in contact with the sixth contact CT6. The seventh conductor CB7 can be provided in the connection region COR. The seventh conductor CB7 can extend in the first direction D1. For example, the seventh conductor CB7 can include aluminum.

[0062] The channel layer CL can be electrically connected to the sixth conductor CB6 through the fourth conductor CB4 and the fifth contact CT5. The peripheral transistor TR in the connection region COR can be electrically connected to the seventh conductor CB7 through the first contact CT1, the first conductor CB1, the third conductor CB3, the second contact CT2, the fourth contact CT4, the fifth conductor CB5, and the sixth contact CT6.

[0063] Reference Figure 1BThe first channel portion CL1 of the channel layer CL can include a first portion CL1a in the first stacked portion STA1 of the stack STA and a second portion CL1b in the fourth conductor CB4. The first portion CL1a of the first channel portion CL1 can be surrounded by the first stacked portion STA1 of the stack STA. The second portion CL1b of the first channel portion CL1 can be surrounded by the fourth conductor CB4. A level of a boundary between the first portion CL1a and the second portion CL1b of the first channel portion CL1 can be the same as a level of a boundary between the first stacked portion STA1 of the stack STA and the fourth conductor CB4. The second portion CL1b of the first channel portion CL1 can protrude above the first stacked portion STA1 of the stack STA. A level of a boundary between the second channel portion CL2 and the first portion CL1a of the first channel portion CL1 can be lower than the level of the boundary between the first stacked portion STA1 of the stack STA and the fourth conductor CB4. The second portion CL1b of the first channel portion CL1 can include a first outer wall SW1 and a first top surface TO1.

[0064] The barrier layer BR of the fourth conductor CB4 can include a junction portion BR_C in contact with the first channel portion CL1 of the channel layer CL. The junction portion BR_C can surround the first channel portion CL1. The junction portion BR_C can be formed along a surface of the first channel portion CL1. The junction portion BR_C can be in contact with the first outer wall SW1 and the first top surface TO1 of the second portion CL1b of the first channel portion CL1. The junction portion BR_C can be conformally formed on the first outer wall SW1 and the first top surface TO1 of the second portion CL1b of the first channel portion CL1. The junction portion BR_C can include a second outer wall SW2 and a second top surface TO2. The barrier layer BR of the fourth conductor CB4 can include a material different from materials of the first channel portion CL1 and the second channel portion CL2 of the channel layer CL.

[0065] The conductive layer CO of the fourth conductor CB4 can surround the junction portion BR_C. The conductive layer CO of the fourth conductor CB4 can be in contact with the second top surface TO2 and the second outer wall SW2 of the junction portion BR_C. The conductive layer CO of the fourth conductor CB4 can include a material different from materials of the barrier layer BR, the first channel portion CL1, and the second channel portion CL2 of the fourth conductor CB4.

[0066] The fill layer FI can include a first fill portion FI1 in the first channel portion CL1 and a second fill portion FI2 in the second channel portion CL2. The first fill portion FI1 can be surrounded by the first channel portion CL1. The second fill portion FI2 can be surrounded by the second channel portion CL2. A width of the first fill portion FI1 can be smaller than a width of the second fill portion FI2. A width of the first fill portion FI1 in the first direction D1 can be smaller than a width of the second fill portion FI2 in the first direction D1.

[0067] A lower surface of the conductive layer CO of the fourth conductor CB4 can be recessed to define a first recessed portion RC1. A space defined by the first recessed portion RC1 can have a cylindrical shape with a width that is not uniform. The first recessed portion RC1 can be filled with the junction portion BR_C, the first channel portion CL1, and the first fill portion FI1. The junction portion BR_C, the first channel portion CL1, and the first fill portion FI1 can be provided in the first recessed portion RC1.

[0068] In the semiconductor device according to one embodiment of the present disclosure, because the first channel portion CL1 of the channel layer CL is formed of a metal silicide and the second channel portion CL2 is formed of polysilicon, an ohmic contact can be formed between the first channel portion CL1 and the second channel portion CL2. Thus, it is not necessary to form an ohmic contact between the first channel portion CL1 and the barrier layer BR of the fourth conductor CB4, and thus the barrier layer BR of the fourth conductor CB4 can be formed directly on the first channel portion CL1 without high-temperature heat treatment.

[0069] In the semiconductor device according to one embodiment of the present disclosure, because the first channel portion CL1 serving as a junction overlap region of the channel layer CL is formed of a metal silicide, the junction overlap region of the channel layer CL can be formed without high-temperature heat treatment, and a change in characteristics of the selection transistor due to deterioration of the selection transistor caused by high-temperature heat treatment can be prevented.

[0070] In the semiconductor device according to one embodiment of the present disclosure, the first channel portion CL1, which is a junction-overlap region of the channel layer CL, is formed of a metal silicide. Thus, the grain boundaries in the first channel portion CL1 can be relatively small compared to grain boundaries in a channel layer formed of polysilicon. Further, the first channel portion CL1 can be formed to have a uniform thickness. Thus, the level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be uniformly formed. The level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be formed so that the boundary between the first channel portion CL1 and the second channel portion CL2 is adjacent to the selection line, and the boundary between the first channel portion CL1 and the second channel portion CL2 does not horizontally overlap with the selection line. Thus, since the distance between the selection line and the first channel portion CL1 can be uniform, a relatively uniform cell current can be generated, and the characteristics of the selection transistor can be uniform.

[0071] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A and Figure 12B are cross-sectional views each illustrating a method for manufacturing a semiconductor device according to Figure 13A and Figure 13B . Figure 14A is an enlarged view of a region B of Figure 14B . Figure 15 is an enlarged view of a region C of Figure 1A . Figure 1A is an enlarged view of a region D of Figure 1A . Figure 1A is an enlarged view of a region E of Figure 1A . Figure 16 is an enlarged view of a region F of Figure 16 .

[0072] For brief description, the same reference numerals are used for components already described with reference to Figure 17 and Figure 17 , and overlapping description is omitted.

[0073] The manufacturing method described below is merely one embodiment of a method for manufacturing a semiconductor device according to Figure 16 and ​ , and is not limited thereto. ​ and ​The method of manufacturing a semiconductor device is not limited to the following manufacturing method.

[0074] Referring to ​ A support structure 200 can be formed. The support structure 200 can have a shape of a plate extending along a plane defined by the first direction D1 and the second direction D2. The support structure 200 can include a material having etching selectivity with respect to an oxide and a nitride. For example, the support structure 200 can include silicon.

[0075] A stack STA can be formed on the support structure 200. The stack STA can include first and second alternately stacked insulating layers IL1 and IL2 in a third direction D3. The first stacked insulating layer IL1 can include an insulating material. For example, the first stacked insulating layer IL1 can include an oxide. The second stacked insulating layer IL2 can include a material different from that of the first stacked insulating layer IL1. For example, the second stacked insulating layer IL2 can include a nitride.

[0076] Referring to ​ A memory layer ML, a channel layer CL, and a fill layer FI can be formed in the cell region CER through the stack STA. The steps of forming the memory layer ML, the channel layer CL, and the fill layer FI can include forming a first hole H01 through the stack STA in the cell region CER, and forming the memory layer ML, the channel layer CL, and the fill layer FI in the first hole H01.

[0077] When the first hole H01 through the stack STA is formed, the first and second stacked insulating layers IL1 and IL2 can be patterned. The patterned first and second stacked insulating layers IL1 and IL2 can be defined as first and second insulating patterns IP1 and IP2.

[0078] A lowermost portion of the first hole H01 can be disposed in the support structure 200. The lowermost portion of the first hole H01 can be surrounded by the support structure 200. A portion of each of the memory layer ML, the channel layer CL, and the fill layer FI can be disposed in the support structure 200. The above-described portion of each of the memory layer ML, the channel layer CL, and the fill layer FI can be surrounded by the support structure 200.

[0079] Subsequently, a fourth insulating layer 140 can be formed on the stack STA. The fourth insulating layer 140 can cover the memory layer ML and the channel layer CL.

[0080] Referring to ​ The second insulating pattern IP2 in the cell region CER can be replaced with a conductive pattern CP, and a slit insulating layer SLI and a third insulating layer 130 can be formed.

[0081] For example, a slit SL can be formed in the cell region CER through the stack STA, and the second insulating pattern IP2 exposed through the slit SL can be removed. The conductive pattern CP can be formed in the empty space where the second insulating pattern IP2 is removed.

[0082] The second insulating pattern IP2 in the connection region COR can not be replaced by the conductive pattern CP and can be left as it is. A portion of the stack STA including the conductive pattern CP and the first insulating pattern IP1 can be defined as a first stack portion STA1. A portion of the stack STA including the first insulating pattern IP1 and the second insulating pattern IP2 can be defined as a second stack portion STA2.

[0083] After the conductive pattern CP is formed, the slit insulating layer SLI and the third insulating layer 130 can be formed. The slit insulating layer SLI and the third insulating layer 130 can be simultaneously formed by depositing one deposition material. After the slit insulating layer SLI and the third insulating layer 130 are formed, the upper surface of the third insulating layer 130 can be polished.

[0084] Referring to ​ A fourth contact CT4 can be formed through the second stack portion STA2, the fourth insulating layer 140, and the third insulating layer 130 of the stack STA. The step of forming the fourth contact CT4 can include a step of forming a second hole HO2 through the second stack portion STA2, the fourth insulating layer 140, and the third insulating layer 130 of the stack STA, and a step of forming the fourth contact CT4 in the second hole HO2. A lowermost portion of the second hole HO2 can be disposed in the support structure 200. The lowermost portion of the second hole HO2 can be surrounded by the support structure 200. A portion of the fourth contact CT4 can be disposed in the support structure 200. The above-described portion of the fourth contact CT4 can be surrounded by the support structure 200.

[0085] Referring to ​ A second insulating layer 120 can be formed on the third insulating layer 130. A second contact CT2 connected to the fourth contact CT4 and a third contact CT3 connected to the channel layer CL can be formed. A third conductor CB3 connected to the second contact CT2 and a second conductor CB2 connected to the third contact CT3 can be formed.

[0086] Referring to ​ A peripheral transistor TR, a first insulating layer 110, a first contact CT1, and a first conductor CB1 can be formed on the substrate 100.

[0087] Referring to ​A wafer bonding process can be performed. The wafer bonding process can include the following steps: inverting the support structure 200, bonding the second conductor CB2 and the first conductor CB1 in the cell region CER, bonding the third conductor CB3 and the first conductor CB1 in the connection region COR, and bonding the first insulating layer 110 and the second insulating layer 120. Since the second conductor CB2 and the first conductor CB1 are bonded in the cell region CER, the channel layer CL can be electrically connected to the peripheral transistor TR.

[0088] Referring to ​ The support structure 200 can be removed. Since the support structure 200 is inverted in the wafer bonding process, the support structure 200 can be exposed, and the support structure 200 can be removed by an etching process. The support structure 200 can be selectively removed by using an etching material capable of selectively etching the support structure 200.

[0089] When the support structure 200 is removed, a first protrusion PT1 of the memory layer ML can be exposed. The first protrusion PT1 of the memory layer ML can be a portion protruding above the first stacked portion STA1 of the stack STA. When the support structure 200 is removed, an upper surface and an outer wall of the first protrusion PT1 of the memory layer ML can be exposed. When the support structure 200 is removed, a second protrusion PT2 of the fourth contact CT4 can be exposed. The second protrusion PT2 of the fourth contact CT4 can be a portion protruding above the second stacked portion STA2 of the stack STA. When the support structure 200 is removed, an upper surface and an outer wall of the second protrusion PT2 of the fourth contact CT4 can be exposed.

[0090] Referring to ​ and ​A first protruding portion PT1 of the memory layer ML protruding above the first stacked portion STA1 of the stack STA can be removed. The step of removing the first protruding portion PT1 of the memory layer ML can include sequentially removing a portion of the barrier layer, a portion of the data storage layer, and a portion of the tunnel insulating layer. The first protruding portion PT1 of the memory layer ML is removed, and thus a third protruding portion PT3 of the channel layer CL can be exposed. The third protruding portion PT3 of the channel layer CL can be a portion protruding above the first stacked portion STA1 of the stack STA. The first protruding portion PT1 of the memory layer ML is removed, and thus an upper surface and an outer wall of the third protruding portion PT3 of the channel layer CL can be exposed. The exposed outer wall of the third protruding portion PT3 can be defined as a third outer wall SW3, and the exposed upper surface of the third protruding portion PT3 can be defined as a third upper surface TO3. The third protruding portion PT3 of the channel layer CL can be a portion located at a level higher than the first stacked portion STA1 of the stack STA. The third protruding portion PT3 of the channel layer CL can be disposed at a level higher than the memory layer ML from which the first protruding portion PT1 is removed.

[0091] Referring to ​ and ​ A diffusion metal layer DML can be formed on the stack STA. The diffusion metal layer DML can include a metal material. For example, the diffusion metal layer DML can include nickel platinum. For example, a composition of the nickel platinum included in the diffusion metal layer DML can be NiPt. The diffusion metal layer DML can include an element that can diffuse into the channel layer CL. For example, the diffusion metal layer DML can include nickel that can diffuse into the channel layer CL. The diffusion metal layer DML can be conformally formed on the stack STA. The diffusion metal layer DML can cover the first stacked portion STA1 and the second stacked portion STA2 of the stack STA. The diffusion metal layer DML can cover the third protruding portion PT3 and the second protruding portion PT2. The diffusion metal layer DML can be formed by a deposition process. The diffusion metal layer DML can be in contact with the third protruding portion PT3 and the second protruding portion PT2.

[0092] The diffusion metal layer DML can include a capping portion CAP surrounding the third protrusion PT3 of the channel layer CL. The capping portion CAP can be a portion of the diffusion metal layer DML that is in contact with the third outer wall SW3 and the third upper surface TO3 of the third protrusion PT3 of the channel layer CL. The capping portion CAP can be formed along the third outer wall SW3 and the third upper surface TO3 of the third protrusion PT3 of the channel layer CL, and thus the capping portion CAP can have a shape corresponding to the third protrusion PT3 of the channel layer CL. An outer wall of the capping portion CAP can be defined as a fourth outer wall SW4, and an upper surface of the capping portion CAP can be defined as a fourth upper surface TO4.

[0093] Referring to ​ and ​ A first channel portion CL1 of the channel layer CL can be formed. A composition of a portion of the channel layer CL can be changed, and thus the first channel portion CL1 can be formed. A composition of the third protrusion PT3 of the channel layer CL and a portion adjacent to the third protrusion PT3 can be changed, and thus the first channel portion CL1 can be formed. A portion of the channel layer CL other than the first channel portion CL1 can be defined as a second channel portion CL2.

[0094] The first channel portion CL1 can be formed by a heat treatment. For example, the first channel portion CL1 can be formed by a rapid thermal annealing (RTA) process. The heat treatment can be performed at a temperature of 290°C to 450°C.

[0095] An element included in the diffusion metal layer DML can be diffused into the third protrusion PT3 of the channel layer CL by a heat treatment, and the first channel portion CL1 can be formed. For example, nickel included in the diffusion metal layer DML can be diffused into the channel layer CL by a heat treatment. For example, the nickel diffused into the channel layer CL can be combined with silicon in the channel layer CL, and the first channel portion CL1 formed in this way can include nickel silicide. For example, a composition of the nickel silicide included in the first channel portion CL1 can be NiSi. The first channel portion CL1 and the second channel portion CL2 can form an ohmic contact. A level of a boundary between the second channel portion CL2 and the first channel portion CL1 can be set adjacent to an uppermost conductive pattern CP serving as a selection line. The level of the boundary between the second channel portion CL2 and the first channel portion CL1 can be set at a level lower than an upper surface of the stack STA.

[0096] At the same time as the composition is changed, the volume of a portion of the channel layer CL can be increased. Accordingly, the first channel portion CL1 can be formed to have a volume larger than the volume of the third protrusion PT3. For example, the width of the first channel portion CL1 in the first direction D1 can be larger than the width of the third protrusion PT3 in the first direction D1. Also, the length of the first channel portion CL1 in the third direction D3 can be larger than the length of the third protrusion PT3 in the third direction D3. For example, the thickness of the first channel portion CL1 in the first direction D1 can be larger than the thickness of the second channel portion CL2 in the first direction D1.

[0097] Referring to ​ and ​ The diffusion metal layer DML can be removed. When the diffusion metal layer DML is removed, the first channel portion CL1 of the channel layer CL can be exposed, and the second protrusion PT2 of the fourth contact CT4 can be exposed. When the diffusion metal layer DML is removed, the first outer wall SW1 and the first upper surface TO1 of the first channel portion CL1 of the channel layer CL can be exposed. For example, the diffusion metal layer DML can be removed by a wet etching process.

[0098] Referring to ​ and ​ An initial conductor pCB can be formed on the laminate STA. The initial conductor pCB can cover the first laminate portion STA1 and the second laminate portion STA2 of the laminate STA. The initial conductor pCB can cover the first channel portion CL1 of the channel layer CL and the second protrusion PT2 of the fourth contact CT4. The initial conductor pCB can include a barrier layer BR covering the laminate STA and a conductive layer CO covering the barrier layer BR. The barrier layer BR of the initial conductor pCB can cover the first upper surface TO1 and the first outer wall SW1 of the first channel portion CL1 of the channel layer CL. The step of forming the initial conductor pCB can include forming the barrier layer BR on the laminate STA, and forming the conductive layer CO on the barrier layer BR.

[0099] Referring to ​ The fourth conductor CB4 and the fifth conductor CB5 can be formed. The initial conductor pCB can be separated, and thus the fourth conductor CB4 and the fifth conductor CB5 can be formed. The step of forming the fourth conductor CB4 and the fifth conductor CB5 can include forming a mask pattern MP including an opening on the initial conductor pCB, and etching the initial conductor pCB by using the mask pattern MP as an etching barrier. After the initial conductor pCB is etched, the remaining mask pattern MP can be removed.

[0100] Subsequently, a fifth insulating layer 150 covering the fourth conductor CB4 and the fifth conductor CB5 can be formed (refer to ​). Subsequently, a fifth contact CT5 (see FIG. 1C) connected to the fourth conductor CB4 (see FIG. 1C) and a sixth conductor CB6 (see FIG. 1C) can be formed in the fifth insulating layer 150, and a sixth contact CT6 (see FIG. 1C) connected to the fifth conductor CB5 (see FIG. 1C) and a seventh conductor CB7 (see FIG. 1C) can be formed. ​ ) and the sixth conductor CB6 (see ​ ), and the sixth contact CT6 (see ​ ) connected to the fifth conductor CB5 (see FIG. 1C) and the seventh conductor CB7 (see FIG. 1C) can be formed. ​

[0101] In the method for manufacturing a semiconductor device according to one embodiment of the present disclosure, since the first channel portion CL1 of the channel layer CL is formed of a metal silicide and the second channel portion CL2 is formed of polysilicon, an ohmic contact can be formed between the first channel portion CL1 and the second channel portion CL2. Thus, it is not necessary to form an ohmic contact between the first channel portion CL1 and the barrier layer BR of the fourth conductor CB4, and thus the barrier layer BR of the fourth conductor CB4 can be formed directly on the first channel portion CL1 without high-temperature heat treatment.

[0102] In the method for manufacturing a semiconductor device according to one embodiment of the present disclosure, since the first channel portion CL1 formed of a metal silicide can be formed without high-temperature heat treatment, a change in characteristics of the selection transistor due to deterioration of the selection transistor caused by high-temperature heat treatment can be prevented.

[0103] In the method for manufacturing a semiconductor device according to one embodiment of the present disclosure, the level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be adjusted by adjusting the formation conditions of the first channel portion CL1. The level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be adjusted by adjusting the temperature of heat treatment, adjusting the time for which heat treatment is performed, adjusting the composition of the material included in the diffusion metal layer DML, or adjusting the thickness of the diffusion metal layer DML. Since the first channel portion CL1 is formed of a metal silicide, the grain boundaries in the first channel portion CL1 can be relatively small compared to the grain boundaries in a channel layer formed of polysilicon. In addition, the first channel portion CL1 can be formed to have a uniform thickness. Thus, the level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be formed uniformly. The level of the boundary between the first channel portion CL1 and the second channel portion CL2 can be formed so that the boundary between the first channel portion CL1 and the second channel portion CL2 is adjacent to the selection line, and the boundary between the first channel portion CL1 and the second channel portion CL2 does not horizontally overlap with the selection line. Thus, since the distance between the selection line and the first channel portion CL1 can be uniform, a relatively uniform cell current can be generated, and the characteristics of the selection transistor can be uniform. ​

[0104] In the manufacturing method of a semiconductor device according to one embodiment of the present disclosure, the metal in the diffusion metal layer DML can be diffused into the channel layer CL and can be combined with silicon of the channel layer CL in a 1:1 manner. Since the metal and the silicon are combined in a 1:1 manner rather than a 1:2 or 1:3 manner, a phenomenon in which silicon is gathered around the metal can be prevented. In summary, silicon of the second channel portion CL2 formed of polysilicon can move to the first channel portion CL1 formed of metal silicide, and thus, a phenomenon in which the first channel portion CL1 and the second channel portion CL2 are separated from each other can be prevented.

[0105] ​ is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0106] Referring to ​ The memory system 1100 according to one embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110.

[0107] The memory device 1120 can include a semiconductor device according to one embodiment of the present disclosure. The memory device 1120 can be a multi-chip package constituted by a plurality of flash memory chips.

[0108] The memory controller 1110 can be configured to control the memory device 1120, and can include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of a host connected with the memory system 1100. In addition, the ECC circuit 1114 detects and corrects an error included in data read from the memory device 1120, and the memory interface 1115 performs an interface connection with the memory device 1120. In addition, the memory controller 1110 can further include a read only memory (ROM) or the like storing code data for connection with the host interface.

[0109] The memory system 1100 as described above can be a memory card or a solid state disk (SSD) in which the memory device 1120 and the memory controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) through one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect Express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0110] ​ is a block diagram illustrating a configuration of a computing system according to an embodiment of the disclosure.

[0111] Referring to ​ , the computing system 1200 according to one embodiment of the disclosure can include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. In addition, when the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 can be further included, and an application chip set, a camera image processor (CIS), and a mobile D-RAM, etc. can be further included.

[0112] The memory system 1210 can be constituted by a memory device 1212 and a memory controller 1211 similar to those described with reference to ​ .

[0113] Cross Reference to Related Applications

[0114] This application claims priority to Korean Patent Application No. 10-2020-0097015, filed on August 3, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A laminate comprising insulating and conductive patterns that are alternately stacked on top of each other; A channel layer, the channel layer including a first channel portion protruding from the laminate and a second channel portion in the laminate, and the channel layer passing through the laminate; as well as Conductive lines surrounding the first channel portion The first channel portion includes metal silicide. The first channel portion includes a first portion disposed in the laminate and a second portion disposed in the conductive line. The first part is in direct contact with the second channel part, and the second part is spaced apart from the second channel part.

2. The semiconductor device according to claim 1, wherein, The conductive line is in direct contact with the first channel portion.

3. The semiconductor device according to claim 1, wherein, The first channel portion includes nickel silicide.

4. The semiconductor device according to claim 1, wherein, The second channel portion comprises polycrystalline silicon.

5. The semiconductor device according to claim 1, wherein, The conductive lines cover the upper surface and outer wall of the first channel portion.

6. The semiconductor device according to claim 1, wherein, The conductive lines include materials different from those used in the first and second channel portions.

7. The semiconductor device according to claim 1, wherein, The conductive line includes a barrier layer in contact with the first channel portion and a conductive layer spaced apart from the first channel portion.

8. The semiconductor device according to claim 7, wherein, The barrier layer comprises titanium or tantalum, and The conductive layer comprises a metal different from the barrier layer.

9. A semiconductor device comprising: A laminate comprising insulating and conductive patterns that are alternately stacked on top of each other; A channel layer, the channel layer including a first channel portion protruding from the laminate and a second channel portion in the laminate, and the channel layer passing through the laminate; as well as Conductive lines surrounding the first channel portion The first channel portion, the second channel portion, and the conductive lines are made of different materials. The first channel portion includes metal silicide. The first channel portion includes a first portion disposed in the laminate and a second portion disposed in the conductive line. The first part is in direct contact with the second channel part, and the second part is spaced apart from the second channel part.

10. The semiconductor device of claim 9, further comprising: A filler layer that extends through the laminate. The filling layer includes a first filling portion surrounded by the first channel portion and a second filling portion surrounded by the second channel portion.

11. The semiconductor device according to claim 9, wherein, The conductive circuit includes a barrier layer and a conductive layer.

12. The semiconductor device according to claim 11, wherein, The barrier layer includes a knot portion surrounding the first channel portion, and The conductive layer surrounds the junction portion.

13. The semiconductor device according to claim 12, wherein, The conductive layer is in contact with the upper surface and outer wall of the junction portion.

14. The semiconductor device according to claim 12, wherein, The conductive layer includes a lower surface recessed to define the recess, and The knot portion and the first channel portion are disposed in the recess.

15. The semiconductor device according to claim 9, wherein, The first channel portion includes a metal silicide formed by combining metal and silicon at a temperature of 450°C or lower.

16. The semiconductor device according to claim 9, wherein, The first channel portion includes nickel silicide.

17. The semiconductor device according to claim 9, wherein, The thickness of the first channel portion is greater than the thickness of the second channel portion.

18. A method for manufacturing a semiconductor device, the method comprising the following steps: Form a supporting structure; A laminate is formed on the supporting structure; Forming a channel layer through the laminate; Remove the support structure to expose the first protrusion of the channel layer; A diffused metal layer is formed in contact with the first protrusion; Perform heat treatment to transform the first protrusion into a first channel portion; Remove the diffused metal layer; Flip the support structure; as well as The channel layer is electrically connected to the peripheral transistor.

19. The method according to claim 18, wherein, The step of changing the first protrusion into the first channel portion includes the following steps: diffusing a first element included in the diffused metal layer into the first protrusion.

20. The method according to claim 19, wherein, The first element is nickel.

21. The method according to claim 18, wherein, The first channel portion includes nickel silicide.

22. The method of claim 18, further comprising the step of: A conductive line is formed around the first channel portion.

23. The method of claim 18, further comprising the step of: Forming a contact portion through the laminated body, The diffused metal layer covers the second protrusion of the contact portion.

24. The method according to claim 18, wherein, The step of exposing the first protrusion includes the following steps: exposing the upper surface and outer wall of the first protrusion.

25. A method for manufacturing a semiconductor device, the method comprising the following steps: Form a supporting structure; A laminate is formed on the supporting structure; Forming a channel layer through the laminate; Remove the support structure to expose the upper surface and sidewalls of the first protrusion of the channel layer; A diffused metal layer is formed covering the upper surface and the sidewall of the first protrusion; Perform heat treatment to transform the first protrusion into a first channel portion. A memory layer is formed through the stack. The step of exposing the first protrusion includes the following steps: Remove the support structure to expose the second protrusion of the memory layer; and Remove the second protrusion to expose the first protrusion.

26. The method of claim 25, wherein, The diffused metal layer comprises nickel and platinum.

27. The method according to claim 25, wherein, The first channel portion and the diffused metal layer comprise nickel.

28. The method according to claim 25, wherein, The first channel portion includes nickel silicide.

29. The method of claim 25, further comprising the step of: After the first channel portion is formed, the diffused metal layer is removed.

30. The method of claim 29, further comprising the step of: After the diffused metal layer is removed, conductive lines are formed around the first channel portion.

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