Three-dimensional memory and preparation method thereof, and electronic device

Abstract

The present disclosure provides a three-dimensional memory and a preparation method thereof, and an electronic device, which relates to the field of semiconductor chip technology and aims to solve the problem of improving the structural stability of the three-dimensional memory. The three-dimensional memory includes a semiconductor layer, a stacked structure, a channel structure, a second dielectric layer, and a gate isolation structure. The stacked structure is arranged on the semiconductor layer, and includes a first dielectric layer and a gate layer alternately stacked. The channel structure runs through the stacked structure and the semiconductor layer. The second dielectric layer is at least partially arranged between the gate layer and the channel structure. The gate isolation structure runs through the stacked structure and the semiconductor layer. The gate isolation structure includes an insulating isolation portion, and the insulating isolation portion is in contact with the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and a preparation method thereof, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] How to improve the reliability of the three-dimensional memory preparation process and improve the structural stability of the three-dimensional memory are issues that need to be urgently addressed. Summary of the invention

[0005] Embodiments of the present disclosure provide a three-dimensional memory and a method for preparing the same, and an electronic device, aiming to solve the problem of improving the structural stability of the three-dimensional memory.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a three-dimensional memory is provided. The three-dimensional memory includes a first semiconductor structure. The first semiconductor structure includes a semiconductor layer, a stacked structure, a channel structure, a second dielectric layer, and a gate isolation structure. The stacked structure is arranged on the semiconductor layer, and includes a first dielectric layer and a gate layer alternately stacked. The channel structure runs through the stacked structure and the semiconductor layer. The second dielectric layer is at least partially arranged between the gate layer and the channel structure. The gate isolation structure runs through the stacked structure and the semiconductor layer, and the gate isolation structure includes an insulating isolation portion, and the insulating isolation portion is in contact with the semiconductor layer.

[0008] In some embodiments, the second dielectric layer is also partially disposed between the first dielectric layer and the gate layer.

[0009] In some embodiments, the insulating isolation portion contacts a side surface of the first dielectric layer.

[0010] In some embodiments, the semiconductor layer is a polysilicon layer; and / or the second dielectric layer includes a high dielectric constant material.

[0011] In some embodiments, the gate layer includes a metal compound layer and a conductor layer, and the metal compound layer is disposed between the conductor layer and the second dielectric layer.

[0012] In some embodiments, the three-dimensional memory further includes a source layer, the source layer is disposed on a side of the semiconductor layer away from the stacked structure, and the channel structure is coupled to the source layer.

[0013] In some embodiments, the channel structure includes a semiconductor channel and a functional layer, the functional layer is arranged between the semiconductor channel and the stacked structure, and the semiconductor channel is coupled to the source layer. The functional layer includes a tunneling layer and a charge storage layer, the tunneling layer is arranged between the second dielectric layer and the semiconductor channel, and the charge storage layer is arranged between the tunneling layer and the second dielectric layer. The charge storage layer is in contact with the second dielectric layer, or the functional layer further includes a barrier layer, and the barrier layer is arranged between the charge storage layer and the second dielectric layer.

[0014] In some embodiments, the gate line isolation structure further includes a conductive portion, the conductive portion is disposed in the insulating isolation portion and extends to the source layer, and the conductive portion is coupled to the source layer.

[0015] In some embodiments, the three-dimensional memory further includes a second semiconductor structure, which is disposed on a side of the first semiconductor structure away from the source layer, and is coupled to the first semiconductor structure.

[0016] In the three-dimensional memory provided by the embodiment of the present disclosure, the insulating isolation part of the gate line isolation structure is in contact with the semiconductor layer. That is, there is no second dielectric layer between the insulating isolation part and the semiconductor layer. Since the second dielectric layer and the semiconductor layer are poorly bonded, when the second dielectric layer is in contact with the semiconductor layer, and when there is a force at the interface between the second dielectric layer and the semiconductor layer, a gap may be formed near the interface between the second dielectric layer and the semiconductor layer, and the gap may reduce the stability of the three-dimensional memory. Compared with the second dielectric layer, the insulating isolation part and the semiconductor layer have better bonding. In the three-dimensional memory provided by the embodiment of the present disclosure, since the insulating isolation part is in contact with the semiconductor layer, there is no second dielectric layer between the two. Therefore, the three-dimensional memory in the embodiment of the present disclosure may have better structural stability.

[0017] On the other hand, a three-dimensional memory is provided. The three-dimensional memory includes a stacked structure, a channel structure, a second dielectric layer and a gate line isolation structure. The stacked structure includes a first dielectric layer and a gate layer alternately stacked. The channel structure runs through the stacked structure. The second dielectric layer is at least partially disposed between the gate layer and the channel structure. The gate line isolation structure runs through the stacked structure, and the gate line isolation structure includes an insulating isolation portion, and the insulating isolation portion contacts the side of the first dielectric layer.

[0018] In some embodiments, the channel structure includes a semiconductor channel and a functional layer, and the functional layer is disposed between the semiconductor channel and the stacked structure.

[0019] In some embodiments, the three-dimensional memory further includes a source layer, and the semiconductor channel is coupled to the source layer.

[0020] In some embodiments, the three-dimensional memory further includes a semiconductor layer and a source layer. The semiconductor layer is disposed between the source layer and the stacked structure, the insulating isolation portion is in contact with the semiconductor layer, and the semiconductor channel is coupled to the source layer.

[0021] In the three-dimensional memory provided by the embodiment of the present disclosure, the insulating isolation part of the gate line isolation structure contacts the side of the first dielectric layer. That is, there is no second dielectric layer between the insulating isolation part and the side of the first dielectric layer. Since the second dielectric layer is poorly bonded to the first dielectric layer, when the second dielectric layer contacts the side of the first dielectric layer, and when there is a force at the interface between the second dielectric layer and the side of the first dielectric layer, a gap may be formed between the second dielectric layer and the side of the first dielectric layer, and the gap may reduce the stability of the three-dimensional memory. Compared with the second dielectric layer, the insulating isolation part has better bonding with the first dielectric layer. In the three-dimensional memory provided by the embodiment of the present disclosure, since the insulating isolation part contacts the side of the first dielectric layer, there is no second dielectric layer between the two. Therefore, the three-dimensional memory in the embodiment of the present disclosure may have better structural stability.

[0022] On the other hand, an electronic device is provided, comprising the three-dimensional memory provided by any one of the above embodiments.

[0023] On the other hand, a method for preparing a three-dimensional memory is provided, comprising: forming a semiconductor layer on a substrate; forming alternately stacked first dielectric layers and gate sacrificial layers on a side of the semiconductor layer away from the substrate; forming a channel structure penetrating the alternately stacked first dielectric layers and gate sacrificial layers and the semiconductor layer and extending to the substrate; forming a gate line slit penetrating the alternately stacked first dielectric layers and gate sacrificial layers and the semiconductor layer and extending to the substrate; removing the gate sacrificial layer through the gate line slit to form a sacrificial gap; forming a second dielectric layer in the sacrificial gap and the gate line slit; removing at least a portion of the second dielectric layer in contact with the semiconductor layer; forming a gate layer in the sacrificial gap; and forming a gate line isolation structure in the gate line slit.

[0024] In some embodiments, removing at least the portion of the second dielectric layer in contact with the semiconductor layer includes removing the portion of the second dielectric layer in contact with the semiconductor layer and the portion in contact with the side surface of the first dielectric layer and / or the substrate.

[0025] In some embodiments, the method for preparing the three-dimensional memory further includes, before removing at least a portion of the second dielectric layer in contact with the semiconductor layer, performing an ion implantation process on the second dielectric layer through the gate line slits.

[0026] In some embodiments, removing at least the portion of the second dielectric layer in contact with the semiconductor layer comprises: performing dry etching on the second dielectric layer through the gate line slits to remove at least the portion of the second dielectric layer in contact with the semiconductor layer.

[0027] In some embodiments, the method for preparing the three-dimensional memory further includes removing the substrate.

[0028] In some embodiments, the method for preparing the three-dimensional memory further includes forming a third dielectric layer on the substrate before the step of forming a semiconductor on the substrate.

[0029] In some embodiments, the channel structure includes a semiconductor channel and a functional layer. Removing the substrate includes removing the substrate to expose the third dielectric layer and a portion of the functional layer. The method for preparing the three-dimensional memory further includes removing the third dielectric layer and a portion of the functional layer to expose the semiconductor channel.

[0030] In some embodiments, the gate line isolation structure includes an insulating isolation portion and a conductive portion. Removing the substrate includes removing the substrate to expose the third dielectric layer and a portion of the insulating isolation portion. The method for preparing the three-dimensional memory further includes removing the third dielectric layer and a portion of the insulating isolation portion to expose the conductive portion.

[0031] In some embodiments, the method for preparing the three-dimensional memory further includes, after the step of removing the substrate, forming a source layer on a side of the semiconductor layer away from the stacked structure, wherein the source layer is coupled to the semiconductor channel.

[0032] It can be understood that the electronic device provided by the above embodiments of the present disclosure may include a three-dimensional memory; the method for preparing the three-dimensional memory provided by the above embodiments of the present disclosure can prepare a three-dimensional memory, and the beneficial effects that can be achieved can refer to the beneficial effects of the three-dimensional memory mentioned above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 is a schematic diagram of a three-dimensional structure of a three-dimensional memory according to some embodiments;

[0035] Figure 2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

[0036] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0037] Figure 4 for Figure 1 An equivalent circuit diagram of a memory cell string in a three-dimensional memory shown;

[0038] Figure 5A is a top view of a three-dimensional memory according to some embodiments;

[0039] Figure 5B for Figure 5A A cross-sectional view of the three-dimensional memory shown along the section line BB';

[0040] Figure 6 for Figure 5B A partial enlarged view of the three-dimensional memory;

[0041] Figure 7 For preparation Figure 5B A structural diagram of an intermediate semiconductor structure of a three-dimensional memory shown;

[0042] Fig. 8A A structural diagram of a semiconductor structure in the related art;

[0043] Figure 8B to Figure 8D A process flow chart for preparing a three-dimensional memory according to a semiconductor structure in the related art;

[0044] Fig. 9 is a structural diagram of a three-dimensional memory according to some embodiments;

[0045] Fig.10 is a structural diagram of a three-dimensional memory according to some embodiments;

[0046] Fig.11is a structural diagram of a three-dimensional memory according to some embodiments;

[0047] Fig.12 is a structural diagram of a three-dimensional memory according to some embodiments;

[0048] Fig.13 is a flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0049] Figure 14A to Figure 14M is a process flow chart of a method for preparing a three-dimensional memory according to some embodiments. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0051] In the description of the present disclosure, it is necessary to understand that the orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "bottom", "inside", "outside", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0061] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0062] As used herein, the term "vertical / vertically" means nominally perpendicular to a major surface (ie, a lateral surface) of a substrate.

[0063] In the preparation process of a three-dimensional memory (such as 3D NAND), a channel structure with a storage function usually needs to form a channel hole in the stacked structure, form an oxide-nitride-oxide (ONO) stacked structure layer in the channel hole, and then remove at least a portion of the ONO stacked structure layer at the bottom of the channel hole by, for example, a deep hole etching process, so that the semiconductor channel subsequently formed in the channel hole can be coupled to the source.

[0064] As the number of layers of the three-dimensional memory stacked structure increases, the ONO stacked layer structure at the bottom of the etching channel hole also faces great challenges. For example, the etching process puts forward higher requirements on the process capability control such as the overlay accuracy of the channel hole, the consistency of key dimensions, and the minimum warping.

[0065] The deep hole etching-free structure can remove the ONO stacked structure layer in the channel hole by, for example, etching from the back of the substrate (i.e., the side away from the stacked structure), thereby avoiding the deep hole etching process challenges brought about by the increase in the number of layers of the three-dimensional memory. However, most of the existing deep hole etching-free structures require a large number of etching processes, such as wet etching processes, on the back of the wafer (i.e., the side of the substrate away from the stacked structure), which poses a great challenge to the structural stability of the three-dimensional memory, such as the bonding force between different layers and the bonding force between different structures.

[0066] In order to improve the reliability of the three-dimensional memory during the preparation process, enhance the structural stability of the three-dimensional memory, and provide a good foundation for the deep hole-free etching structure, the embodiments of the present disclosure provide a three-dimensional memory and a preparation method thereof, and an electronic device.

[0067] Figure 1 Schematic diagram of the three-dimensional structure of the three-dimensional memory. Figure 2 is a cross-sectional view of a three-dimensional memory. Figure 3 for Figure 1A cross-sectional view of a storage unit string of the three-dimensional memory along the section line AA', Figure 4 for Figure 3 Equivalent circuit diagram of the storage cell string in .

[0068] See also Figure 1 and Figure 2 , an embodiment of the present disclosure provides a three-dimensional memory. The three-dimensional memory 10 may include a first semiconductor structure 200. The three-dimensional memory 10 may also include a source layer SL coupled to the first semiconductor structure 200, and a second semiconductor structure 100 coupled to the first semiconductor structure 200. The second semiconductor structure 100 may be disposed on a side of the first semiconductor structure 200 away from the source layer SL.

[0069] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0070] The first semiconductor structure 200 may include memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400 .

[0071] Specifically, see Figure 3 and Figure 4 The memory cell string 400 may include a plurality of transistors T, one transistor T may be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) may be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor. It should be noted that Figure 1 to Figure 4 The number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided by the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0072] Further, along a first direction (roughly parallel to the extension direction of a semiconductor channel), the bottom gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, which is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400; the top gate line among the multiple gate lines G (e.g., the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, which is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400; the middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string can be completed.

[0073] Continue to see Figure 1 and Figure 2 In some embodiments, the first semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

[0074] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0075] The second semiconductor structure 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)), or storage circuits (e.g., static random access memories (SRAMs)).

[0076] Specifically, in some embodiments, the second semiconductor structure 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0077] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0078] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0079] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, so that the first semiconductor structure 200 and the second semiconductor structure 100 can be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the second semiconductor structure can be coupled to the storage cell string in the first semiconductor structure to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other through the bonding interface 500.

[0080] Figure 5A is a top view of the three-dimensional memory. Figure 5B yes Figure 5A A cross-sectional view of the three-dimensional memory along the BB' section line. It should be noted that: Figure 5A and Figure 5B Only the first semiconductor structure and the source layer in the three-dimensional memory are shown, while other structures are omitted, for example, the second semiconductor structure is omitted.

[0081] See also Figure 5A and Figure 5B , the first semiconductor structure 200 includes a stacked structure 230 and a semiconductor layer 222 .

[0082] The stacked structure 230 is located on the semiconductor layer 222. Specifically, the stacked structure 230 is located on one side of the semiconductor layer 222 along a first direction, and the first direction is, for example, perpendicular to the extension direction of the semiconductor layer 222. In some embodiments, the stacked structure 230 is in contact with the semiconductor layer 222; in other embodiments, other structures, such as other functional layers, are disposed between the stacked structure 230 and the semiconductor layer 222 in the first direction.

[0083] The stacked structure 230 includes alternately stacked first dielectric layers 231 and gate layers 232. Specifically, in the stacked structure 230, the first dielectric layers 231 and the gate layers 232 are alternately stacked along a first direction. In some embodiments, the stacked structure 230 includes a plurality of alternately stacked first dielectric layers 231 and a plurality of gate layers 232. Among the first dielectric layers 231 and the gate layers 232 of the stacked structure, the layer closest to the semiconductor layer 222 is the first dielectric layer 231, for example Figure 5B The first dielectric layer 231b in the embodiment of the present invention.

[0084] The embodiments of the present disclosure do not limit the number of layers of the stacked structure 230. For example, the number of layers of the stacked structure 230 may be 8, 64, 128, etc. It can be understood that the more layers the stacked structure 230 has, the higher the integration level is, and the more storage cells (e.g., transistors) are in the storage cell string formed by the stacked structure 230.

[0085] The material of the first dielectric layer 231 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and a combination of one or more of organic insulating materials. The materials of each first dielectric layer 231 may be the same or different. In some embodiments, the materials of each first dielectric layer 231 are the same.

[0086] The gate layer 232 may include at least one (e.g., multiple) gate lines (e.g., gate lines G1 and gate lines G2) for controlling the conduction state of transistors in the memory cell string. In some embodiments, based on the above, along the first direction, at least one (e.g., one; or multiple) gate layers located at the bottom of the multiple gate layers 232 (e.g., including the gate layer 232b closest to the semiconductor layer 222 among the multiple gate layers 232) is constructed as at least one (e.g., one; or multiple) source end selection gate; at least one (e.g., one; or multiple) gate layer located at the top of the multiple gate layers 232 (e.g., including the gate layer 232c farthest from the semiconductor layer 222 among the multiple gate layers 232) is constructed as at least one (e.g., one; or multiple) drain end selection gate; at least one (e.g., one; or multiple) gate layer located in the middle of the multiple gate layers 232, such as the gate layer 232a, is constructed as multiple word lines.

[0087] In order to more clearly illustrate the structure of the gate layer, a Figure 6 As Figure 5B Magnified view of area P in the middle. Figure 5B and Figure 6 , the gate layer 232 may include a conductor layer 2322. The material of the conductor layer 2322 may include a conductive material, and the conductive material is, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. In some embodiments, the material of the conductor layer 2322 may be tungsten. The materials of each conductor layer 2322 may be the same or different. In some embodiments, the material of the conductor layer 2322 in each gate layer 232 is the same, for example, tungsten.

[0088] In some embodiments, the gate layer 232 further includes a metal compound layer 2321, and the conductor layer 2322 can be separated from both the first dielectric layer 231 and the channel structure 240 by the metal compound layer 2321. The metal compound layer 2331 is configured as a barrier material layer, which can be used as a barrier layer to reduce the diffusion of impurity atoms or gases into the first dielectric layer 231 and the channel structure 240; the metal compound layer 2331 can also be configured as an adhesive layer, which can enhance the adhesion between the conductor layer 2332 and the first dielectric layer 231. It should be noted that when there is a second dielectric layer 260 between the gate layer 232 and the channel structure 240 (it can be said that the second dielectric layer 260 is partially disposed between the gate layer 232 and the channel structure 240), and / or when there is a second dielectric layer 260 between the gate layer 232 and the first dielectric layer 231 (it can be said that the second dielectric layer 260 is also partially disposed between the first dielectric layer 231 and the gate layer 232), the metal compound layer 2331 can be disposed between the conductor layer 2332 and the second dielectric layer 260, which can enhance the adhesion between the conductor layer 2332 and the second dielectric layer 260. The second dielectric layer 260 will be described in detail below.

[0089] The material of the metal compound layer 2331 may include a metal compound, such as a combination of one or more of titanium nitride, tantalum nitride, and tungsten carbide, or other suitable materials.

[0090] Continue to see Figure 5A and Figure 5B In some embodiments, the first semiconductor structure 200 may further include a gate line contact G-CNT. Figure 1 The gate line contact G-CNT may extend along the first direction. The gate line contact G-CNT is configured to be connected to the gate line G (included in Figure 5B The gate layer 232 is coupled to the array interconnect layer, so that the array interconnect layer transmits electrical signals to the gate line (eg, including the word line) through the gate line contact G-CNT. Figure 5A In the first semiconductor structure 200, the gate line contacts G-CNT may be distributed in an array, and the region where the gate line contacts G-CNT are disposed may be referred to as a contact region CA.

[0091] Continue to see Figure 5A and Figure 5B, the embodiments of the present disclosure do not impose any particular restrictions on the thickness of each layer in the stacked structure 232. In some embodiments, the thickness of each first dielectric layer 231 is the same, and the thickness of each gate layer 232 is the same. Exemplarily, in the stacked structure 230, the thickness of each first dielectric layer 231 and each gate layer 232 is the same. In other embodiments, in the stacked structure 230, the thickness of at least two first dielectric layers in each first dielectric layer 231 is different; and / or, the thickness of at least two gate layers in each gate layer 232 is different. Exemplarily, in the stacked structure 230, the thickness of at least one first dielectric layer (e.g., the first dielectric layer 231b and / or the first dielectric layer 231c) located at the outermost side along the first direction is different from the thickness of other first dielectric layers (e.g., the first dielectric layer 231a).

[0092] The material of the semiconductor layer 222 may include a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or single crystal silicon. In some embodiments, the material of the semiconductor layer 222 includes polycrystalline silicon. Exemplarily, the material of the semiconductor layer 222 may be doped polycrystalline silicon; and again exemplary, the material of the semiconductor layer 222 may be undoped polycrystalline silicon.

[0093] In order to explain the semiconductor layer 222 in detail, it is first necessary to explain that the three-dimensional memory provided by the embodiment of the present disclosure can be composed of Figure 7 The intermediate semiconductor structure shown is further processed to obtain. Specifically, see Figure 5B and Figure 7 The intermediate semiconductor structure 20 may include a substrate 210, a semiconductor layer 222, a third dielectric layer 221, a stacked structure 230, and a channel structure 240 located on the substrate 210. Figure 7 The substrate 210 of the intermediate semiconductor structure 20 is removed, and a source layer SL is formed, so that Figure 5B In other words, Figure 7 The specific structure of the intermediate semiconductor structure can be referred to below. Figure 5B Description of the corresponding structure in the three-dimensional memory.

[0094] Specifically, see Figure 7In the intermediate semiconductor structure 20, the substrate 210 may be a composite substrate having a multi-layer structure. Exemplarily, the substrate 210 may include a base 211, a first sacrificial layer 212, and a second sacrificial layer 213. The base 211 may include amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials; the base 211 may also be made of non-conductive materials such as glass, plastic, or sapphire wafers. The material of the first sacrificial layer 212 may be an insulating material, such as silicon oxide, silicon nitride, etc. The material of the second sacrificial layer 213 may be a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or single crystal silicon. In other embodiments, the substrate 210 may be a single-layer structure, in which case the substrate 210 may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.; the substrate 210 may also be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0095] The semiconductor layer 222 and the third dielectric layer 221 may be located on the substrate 210. In the etching process for removing the substrate 210, the semiconductor layer 222 and the third dielectric layer 221 may be configured as an etching stop layer. Specifically, the etching rate of the material of the third dielectric layer 221 may be different from the etching rate of the material of the semiconductor layer 222. Furthermore, the etching rate of the layer in the substrate 210 that contacts the third dielectric layer 221, such as the material of the second sacrificial layer 213, may be different from the etching rate of the material of the third dielectric layer 221. Exemplarily, the material of the third dielectric layer 221 includes silicon oxide, and the material of the semiconductor layer 222 and the second sacrificial layer 213 is the same, both being polysilicon. Based on the above, in Figure 7 In the intermediate semiconductor structure 20, when the substrate 210 is removed by an etching process and / or other materials having an etching rate close to that of the substrate 210 are removed in the future, the third dielectric layer 221 can be exposed without further etching the semiconductor layer 222; when the third dielectric layer 221 is removed by an etching process and / or other materials having an etching rate close to that of the third dielectric layer 221 are removed in the future, the semiconductor layer 222 can be exposed without further etching the film layer arranged on the side of the semiconductor layer 222 away from the substrate 210, such as the first dielectric layer 231b.

[0096] In addition, during the process of forming the source layer SL, a laser annealing process may be performed. At this time, after the laser annealing process, the semiconductor layer 222 may serve as an interface layer, which may strengthen the bonding between the source layer SL and the stacked structure 230 and improve the peeling problem between the source layer SL and the stacked structure 230 .

[0097] Continue to see Figure 5B, the first semiconductor structure 200 further includes a channel structure 240. The channel structure 240 penetrates the stacked structure 230 and the semiconductor layer 222. Specifically, the channel structure 240 penetrates the stacked structure 230 and the semiconductor layer 222 along the first direction. In some embodiments, the channel structure 240 may extend to the source layer SL, so that the channel structure 240 may be coupled to the source layer SL.

[0098] The channel structure 240 extending to the source layer SL may mean the following two situations:

[0099] First, the channel structure 240 can penetrate the stacked structure 230 and the semiconductor layer 222, and protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL to the source layer SL. Second, the channel structure 240 can penetrate the stacked structure 230 and the semiconductor layer 222, and the bottom surface 240' of the channel structure 240 (for example, the surface of the two surfaces of the channel structure 240 distributed along the first direction that is close to the source layer SL) is flush with the interface IF3.

[0100] Based on the above, in some possible implementations, since the channel structure 240 extends to the source layer SL, the channel structure 240 can contact the source layer SL, so that the channel structure 240 can be coupled to the source layer SL. In some other possible implementations, a conductive structure can be further provided on one side of the channel structure 240 close to the source layer SL, and the conductive structure can contact the channel structure 240 and the source layer SL, so that the channel structure 240 can be coupled to the source layer SL. The conductive structure can improve the electrical connection stability between the channel structure 240 and the source layer SL.

[0101] The channel structures 240 may be arranged in an array, and in the first semiconductor structure 200, the region where the channel structures 240 are disposed may be referred to as a storage array area SA. For example, a plurality of channel structures 240 are arranged into a plurality of channel rows sequentially distributed along the third direction, the channel structures 240 in each odd-numbered channel row may be arranged in an array, and the channel structures 240 in each even-numbered channel row may be arranged in an array.

[0102] To more clearly illustrate the channel structure, see Figure 5A , Figure 5B and Figure 6 , the channel structure 240 includes a semiconductor channel 241. The material of the semiconductor channel 241 may include a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or single crystal silicon. The semiconductor channel 241 may be used as a channel of each transistor in the memory cell string. In some embodiments, the semiconductor channel 241 may be coupled to the source layer SL.

[0103] The channel structure 240 further includes a functional layer 242. Specifically, the functional layer 242 is disposed between the semiconductor channel 241 and the stacked structure 230. The functional layer 242 may include a tunneling layer 242a and a charge storage layer 242b.

[0104] The tunneling layer 242a may be disposed between the gate layer 232 and the semiconductor channel 241. It should be noted that when there is a second dielectric layer 260 between the gate layer 232 and the channel structure 240 (it can also be said that the second dielectric layer 260 is partially disposed between the gate layer 232 and the channel structure 240), the tunneling layer 242a may be disposed between the second dielectric layer 260 and the semiconductor channel 241. The second dielectric layer 260 will be described in detail below. The material of the tunneling layer 242a may include an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the tunneling layer 242a is silicon oxide. Electrons or holes in the semiconductor channel 241 may tunnel through the tunneling layer 242a to the charge storage layer 242b of the memory cell string.

[0105] The charge storage layer 242b may be disposed between the tunneling layer 242a and the gate layer 232. It should be noted that when there is a second dielectric layer 260 between the gate layer 232 and the channel structure 240 (it can also be said that the second dielectric layer 260 is partially disposed between the gate layer 232 and the channel structure 240), the charge storage layer 242b may be disposed between the tunneling layer 242a and the second dielectric layer 260. The second dielectric layer 260 will be described in detail below. The material of the charge storage layer 242b may include a combination of one or more of silicon nitride, silicon oxynitride, and silicon. The charge storage layer 242b may be configured to store the charge of the storage cell in the storage cell string. When a certain voltage is applied to the semiconductor channel 241 through the gate layer 232, the storage or removal of the charge in the charge storage layer 242b may affect the conduction state of the semiconductor channel 241.

[0106] In some embodiments, the functional layer 242 may further include a barrier layer 242c. The barrier layer 242c may be disposed between the charge storage layer 242b and the gate layer 232. It should be noted that when a second dielectric layer 260 is present between the gate layer 232 and the channel structure 240 (it can also be said that the second dielectric layer 260 is partially disposed between the gate layer 232 and the channel structure 240), the barrier layer 242c may be disposed between the charge storage layer 242b and the second dielectric layer 260. The second dielectric layer 260 will be described in detail below. The material of the barrier layer 242c may include an insulating material, and the insulating material may include, for example, a combination of one or more of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the barrier layer 242a is silicon oxide.

[0107] Continue to see Figure 5B In some embodiments, the channel structure 240 further includes a filling portion 243. The material of the filling portion 243 may include an insulating material, for example, the material of the filling portion 243 is silicon nitride. The filling portion 243 may further include one or more air gaps 243', and the air gaps 243' may relieve structural stress.

[0108] The first semiconductor structure 200 further includes a second dielectric layer 260. In some embodiments, the second dielectric layer 260 includes a high dielectric constant material (i.e., a high-K material), and the high dielectric constant material is, for example, a combination of one or more of the following materials: aluminum oxide, hafnium dioxide, lanthanum oxide, yttrium oxide, tantalum oxide, a silicate of one of the above materials, and a nitrogen-doped compound of one of the above materials.

[0109] See also Figure 5B and Figure 6 The second dielectric layer 260 is at least partially disposed between the gate layer 232 and the channel structure 240. For example, the second dielectric layer 260 includes a first portion 260a. The first portion 260a of the second dielectric layer is disposed between the gate layer 232 and the channel structure 240.

[0110] In some embodiments, the functional layer 242 in the channel structure includes a barrier layer 242c, and the barrier layer 242c can be disposed between the charge storage layer 242b and the second dielectric layer 260. For example, the barrier layer 242c can be disposed between the charge storage layer 242b and the first portion 260a of the second dielectric layer. In this case, the second dielectric layer 260 (for example, the first portion 260a of the second dielectric layer) can be configured to control the work function between the gate layer 232 and the charge storage layer 242b in the functional layer. In other embodiments, the functional layer 242 in the channel structure does not have a barrier layer 242c, and in this case, the second dielectric layer 260 can be disposed between the gate layer 232 and the charge storage layer 242b, and the charge storage layer 242b is in contact with the second dielectric layer 260. The second dielectric layer 260 can be configured to prevent the charge stored in the charge storage layer 242b from leaking to the gate layer 232.

[0111] In the manufacturing process of the three-dimensional memory, before the gate layer 232 is made, a sacrificial gap can be formed between adjacent first dielectric layers 231, and then the gate layer 232 can be formed in the sacrificial gap. Exemplarily, the intermediate product of preparing the three-dimensional memory may include an initial stacked structure, which includes alternately stacked first dielectric layers 231 and gate sacrificial layers. In the subsequent process of processing the intermediate product to manufacture the three-dimensional memory, a gate line slit can be formed through the initial stacked structure, so that the gate sacrificial layer between the first dielectric layers 231 can be exposed through the gate line slit; the gate sacrificial layer can be removed through the gate line slit, and then a sacrificial gap is formed at the position where the gate sacrificial layer was originally set in the initial stacked structure; then, the gate layer 232 can be formed in the sacrificial gap. As described above, in the three-dimensional memory, in the first semiconductor structure 200, the second dielectric layer 260 can be located between the gate layer 232 and the channel structure 240. In order to arrange the second dielectric layer 260 between the gate layer 232 and the channel structure 240, the second dielectric layer 260 may be formed in the sacrificial gap before forming the gate layer 232, and then the gate layer 232 may be formed in the sacrificial gap with the second dielectric layer 260. Furthermore, the second dielectric layer 260 may be formed conformally, so that the second dielectric layer 260 may be formed on the surface exposed by the gate line slits.

[0112] Based on the above, in some embodiments, the second dielectric layer 260 is partially disposed between the first dielectric layer 231 and the gate layer 232. For example, the second dielectric layer 260 may further include a second portion 260b disposed between the first dielectric layer 231 and the gate layer 232.

[0113] The first semiconductor structure 200 further includes a gate line isolation structure 250. The gate line isolation structure 250 penetrates the stacked structure 230 and the semiconductor layer 222. The gate line isolation structure 250 may be configured to divide the stacked structure 230 into a plurality of memory blocks. Figure 5A Due to the provision of the gate line isolation structure 250 , the three-dimensional memory 10 can be divided into a plurality of memory blocks, for example, a memory block B1 , a memory block B2 , and a memory block B3 .

[0114] In some embodiments, the gate line isolation structure 250 penetrates the stacked structure 230 and the semiconductor layer 222. For example, the gate line isolation structure 250 may penetrate the stacked structure 230 and the semiconductor layer 222 along a first direction. In addition, the gate line isolation structure 250 may extend along a third direction (for example, perpendicular to the first direction). Exemplarily, the gate line isolation structure 250 may penetrate the stacked structure 230 and the semiconductor layer 222 and extend to the source layer SL. Similar to the channel structure 240, the gate line isolation structure 250 extending to the source layer SL may mean the following two situations:

[0115] First, the gate line isolation structure 250 can penetrate the stacked structure 230 and the semiconductor layer 222, and protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL and protrude into the source layer SL. Second, the gate line isolation structure 250 can penetrate the stacked structure 230 and the semiconductor layer 222, and the bottom surface 250' of the gate line isolation structure 250 (for example, the surface of the gate line isolation structure 250 that is close to the source layer SL among the two surfaces distributed along the first direction) can be flush with the interface IF3.

[0116] The gate line isolation structure 250 includes an insulating isolation portion 251. The insulating isolation portion 251 can be configured to electrically insulate and isolate two adjacent gate lines (e.g., gate line G1 and gate line G2) located in the same layer in the stacked structure 230, so that the two adjacent gate lines located in the same layer in the stacked structure 230 will not form a conductive path, thereby enabling addressing of the memory cell through the word line. It can be understood that the insulating isolation portion 251 can also be configured to electrically insulate and isolate two or more gate lines located in different layers in the stacked structure 230. The material of the insulating isolation portion 251 includes an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, metal oxide, and organic silicate glass. In some embodiments, the material of the insulating isolation portion 251 is silicon oxide.

[0117] The insulating isolation part 251 is in contact with the semiconductor layer 222. It can also be said that there is no other structure between the insulating isolation part 251 and the semiconductor layer 222, for example, there is no second dielectric layer 260. In some embodiments, as described above, in the process of making the second dielectric layer 260, the second dielectric layer 260 is also conformally formed in the gate line slit, so that in the intermediate product of the three-dimensional memory, the second dielectric layer 260 is also formed in the gate line slit. Exemplarily, in the intermediate product of the three-dimensional memory, in the gate line slit, the second dielectric layer 260 is also formed on the interface IF2 between the insulating isolation part 251 and the semiconductor layer 222. The bonding between the second dielectric layer 260 and the semiconductor layer 222 is poor. Exemplarily, the second dielectric layer 260 includes a high dielectric constant material (such as aluminum oxide), and the semiconductor layer 222 is a polysilicon layer, and the bonding between the high dielectric constant material and the polysilicon is poor. Since the second dielectric layer 260 is poorly bonded to the semiconductor layer 222 , when the second dielectric layer 260 is present between the insulating isolation portion 251 and the semiconductor layer 222 , defects such as voids may be formed near the interface IF2 between the second dielectric layer 260 and the semiconductor layer 222 .

[0118] For example, Fig. 8A A semiconductor structure in the related art is shown. Fig. 8AIn the semiconductor structure 30 in the related art, there is a second dielectric layer 260 between the insulating isolation part 251 and the semiconductor layer 222. At this time, the semiconductor layer 222 and other film layers including semiconductor materials can exert a force on the insulating isolation part 251, such as exerting a squeezing effect on the insulating isolation part 251. Because the second dielectric layer 260 and the semiconductor layer 222 are poorly bonded, a gap SM may be formed near the interface IF2 between the second dielectric layer 260 and the semiconductor layer 222 under the action of the above force, which affects the structural stability of the semiconductor structure 30. See more Figure 5B In the three-dimensional memory provided in the embodiment of the present disclosure, in the first semiconductor structure 200, the insulating isolation portion 251 is in contact with the semiconductor layer 222. In this way, there is no second dielectric layer 260 between the insulating isolation portion 251 and the semiconductor layer 222. Compared with the second dielectric layer 260, the insulating isolation portion 251 is better combined with the semiconductor layer 222, and when the insulating isolation portion 251 is in contact with the semiconductor layer 222, the above problem can be improved. Based on the above, since the insulating isolation portion 251 is in contact with the semiconductor layer 222, the structural stability of the first semiconductor structure 200 can be improved, and then the structural stability of the three-dimensional memory can be improved, and the yield of the product can also be improved.

[0119] Furthermore, in some embodiments, the insulating isolation portion 251 contacts the side surface SW of at least one (e.g., one; or more) first dielectric layer 231 in the stacked structure 230. The side surface SW of the first dielectric layer 231 is, for example, a surface of the first dielectric layer 231 distributed perpendicular to the first direction.

[0120] In some possible implementations, the insulating isolation portion 251 contacts the side of the first dielectric layer 231 (e.g., the first dielectric layer 231b) closest to the source layer SL in the stacked structure 230. In other possible implementations, the insulating isolation portion 251 contacts the side of each first dielectric layer 231 in the stacked structure.

[0121] Based on the same principle, in the intermediate product of the three-dimensional memory, a second dielectric layer 260 may also be formed on the side SW of the first dielectric layer 231. The bonding between the second dielectric layer 260 and the first dielectric layer 231 is also poor. For example, the second dielectric layer 260 includes a high dielectric constant material (such as aluminum oxide), and the first dielectric layer 231 includes silicon oxide, and the bonding between the high dielectric constant material and silicon oxide is poor. Similarly, since the bonding between the second dielectric layer 260 and the first dielectric layer 231 is poor, when the second dielectric layer 260 exists between the insulating isolation portion 251 and the first dielectric layer 231, defects such as gaps may be formed on the side SW of the first dielectric layer 231, which will affect the structural stability of the semiconductor structure 200. In the first semiconductor structure of the three-dimensional memory provided in the embodiment of the present disclosure, the insulating isolation portion 251 is in contact with the side surface SW of the first dielectric layer 231, that is, there is no second dielectric layer 260 between the insulating isolation portion 251 and the side surface SW of the first dielectric layer 231, which can improve the structural stability of the first semiconductor structure 200, and thus the structural stability of the three-dimensional memory can also be improved, thereby improving the yield of the product.

[0122] It can be understood that, since the insulating isolation part 251 is in contact with the semiconductor layer 222, there is no other film layer between the insulating isolation part 251 and the semiconductor layer 222 except the second dielectric layer 260. Since the insulating isolation part 251 is well combined with the semiconductor layer 222, when the insulating isolation part 251 is in direct contact with the semiconductor layer 222, the structural stability of the semiconductor structure can be improved. Similarly, the side contact of the insulating isolation part 251 with the first dielectric layer 231 can also have similar benefits.

[0123] Continue to see Figure 5B In some embodiments, the gate line isolation structure 250 further includes at least one (e.g., one; or more) conductive portion 252. The conductive portion 252 may include a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0124] The conductive portion 252 is disposed in the insulating isolation portion 251. Since the conductive portion 252 is disposed in the insulating isolation portion 251, the conductive portion 252 and the gate layer 232 may be electrically insulated.

[0125] In addition, the conductive portion 252 extends to the source layer SL. Similar to the channel structure 240, the conductive portion 252 extending to the source layer SL may refer to the following two situations:

[0126] First, the conductive portion 252 may protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL and into the source layer SL. Second, the bottom surface 252' of the conductive portion 252 (eg, the surface of the conductive portion 252 closer to the source layer SL in the two surfaces distributed along the first direction) may be flush with the interface IF3.

[0127] The conductive portion 252 can be coupled to the source layer SL. In this way, the conductive portion 252 can serve as a common source contact of the three-dimensional memory, that is, the electrical signal can be transmitted to the source layer SL of the three-dimensional memory through the conductive portion 252. Based on the above, in some possible implementations, since the conductive portion 252 extends to the source layer SL, the conductive portion 252 can contact the source layer SL, so that the conductive portion 252 can be coupled to the source layer SL. In some other possible implementations, a conductive structure may be further provided on one side of the conductive portion 252 close to the source layer SL. The conductive structure may contact the conductive portion 252 and the source layer SL, so that the conductive portion 252 can be coupled to the source layer SL. The conductive structure can improve the electrical connection stability between the conductive portion 252 and the source layer SL.

[0128] In some other embodiments, the gate line isolation structure 250 may further include at least one (e.g., one; or, for example, multiple) semiconductor filling portion. The semiconductor filling portion may be disposed within the insulating isolation portion 251 and extend to the source layer SL. The relative position of the semiconductor filling portion in the first semiconductor structure may be similar to that of the conductive portion 252, and reference may be made to the above description, which will not be repeated here.

[0129] The semiconductor filling part may include semiconductor material, such as polysilicon. The semiconductor filling part in the gate line isolation structure 250 may play a role in regulating stress, so that the stress distribution in the three-dimensional memory is uniform, which is conducive to improving the structural stability of the three-dimensional memory.

[0130] In yet other embodiments, the gate line isolation structure 250 may include only the insulating isolation portion 251. For example, the gate line slits may be filled with only insulating material.

[0131] In some embodiments, the first semiconductor structure 200 may further include a dummy channel structure 270. The dummy channel structure 270 may be located in the contact area CA. The dummy channel structure 270 is configured to provide mechanical support to the semiconductor structure 200. Exemplarily, the dummy channel structure 270 may penetrate the stacked structure 230 along the first direction, and may also penetrate the semiconductor layer 222 along the first direction. In some possible implementations, the dummy channel structure 270 may penetrate the stacked structure 230 and the semiconductor layer 222 along the first direction, and protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL and protrude into the source layer SL. The dummy channel structure 270 may include an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials. The dummy channel structure 270 may include one or more air gaps 271, and the air gaps 271 may reduce structural stress.

[0132] In some embodiments, the first semiconductor structure 200 may further include a capping layer 280. The capping layer 280 may cover the portion of the first semiconductor structure 200 located in the contact area CA, and may protect the first semiconductor structure 200. The capping layer 280 may include an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0133] The source layer SL may be located on a side of the semiconductor layer 222 away from the stacked structure 230. It can also be said that along the first direction, the source layer SL, the semiconductor layer 222, and the stacked structure 230 are arranged in sequence. In addition, the channel structure 240 in the first semiconductor structure is coupled to the source layer SL, so that the source layer SL can serve as the source of the three-dimensional storage string. Exemplarily, the semiconductor channel in the channel structure can be coupled to the source layer SL. In some embodiments, the gate line isolation structure 250 also includes a conductive portion 252, which can also be coupled to the source layer SL.

[0134] See also Figure 5B and Figure 7 , when passing Figure 7 When the three-dimensional memory provided by the present disclosure is manufactured using the intermediate semiconductor structure in the middle semiconductor structure, for example, when the three-dimensional memory is manufactured by removing the substrate 210 and setting the source layer SL, since the insulating isolation part 251 is in contact with the semiconductor layer 222, the structural integrity of the first dielectric layer 231c between the source selection gate (for example, including the gate layer 232b) and the semiconductor layer 222 can be improved when the substrate 210 is removed.

[0135] Specifically, compared Fig.8D In the related art shown in Fig. 8A Three-dimensional memory and semiconductor structure fabricated in Figure 5B Shown by Figure 7 The three-dimensional memory prepared by the intermediate semiconductor structure in Fig. 8A The semiconductor structure 30 is subsequently processed to manufacture Fig.8D When the three-dimensional memory 50 is formed, due to the presence of the gap SM in the semiconductor structure 30, when the film layer (such as the substrate, the first etch stop layer 221) on the side of the semiconductor layer 222 away from the stacked structure is removed by an etching process (such as a wet etching process), the stacked structure can also be etched.

[0136] For example, Figure 8B and Figure 8C Shown by Fig. 8A Semiconductor structure preparation in Fig.8D The process flow of the three-dimensional memory in . Figures 8A to 8D When the substrate (e.g., the second sacrificial layer 213) and the third dielectric layer 221 are removed, the stacked structure is destroyed, for example, the first dielectric layer 231b is destroyed, so that a gap SM' can be formed in the first dielectric layer 231b between the source select gate (e.g., including the gate layer 232b) and the semiconductor layer 222. In addition, in subsequent steps, the gap SM' can be filled with the source layer SL', thereby affecting the operating voltage of the transistor corresponding to the source select gate (e.g., the on-voltage and / or off-voltage of the transistor).

[0137] In the three-dimensional memory provided in the embodiment of the present disclosure, see Figure 5B The insulating isolation portion 251 is in contact with the semiconductor layer 222, that is, there is no second dielectric layer 260 between the insulating isolation portion 251 and the semiconductor layer 222, which can improve the above problems, thereby improving the structural stability of the three-dimensional memory and improving the operating voltage of the bottom selection gate.

[0138] In some embodiments, as described above, the semiconductor channel 241 of the channel structure 240 is coupled to the source layer SL. Figure 7 and Figure 5B , you can remove Figure 7 A portion of the functional layer 242 of the channel structure 240 in the intermediate semiconductor structure is removed, for example, a portion of the functional layer 242 protruding from the substrate 210 is removed to expose the semiconductor channel 241 in the channel structure, and then a source layer SL is set on the semiconductor channel 241, so that the source layer SL contacts the semiconductor channel 241 to achieve coupling between the source layer SL and the semiconductor channel 241, so that the source layer SL can serve as the source of the three-dimensional storage string.

[0139] Continue to see Figure 5B In some possible implementations, the gate line isolation structure 250 further includes a conductive portion 252. For example, see Figure 5B and Figure 7 , you can remove Figure 7 A portion of the insulating isolation portion 251 of the gate line isolation structure 250 in the intermediate semiconductor structure is removed, for example, a portion of the insulating isolation portion 251 protruding from the substrate 210 is removed to expose the conductive portion 252 in the gate line isolation structure 250, and then a source layer SL is set on the conductive portion 252, so that the source layer SL contacts the conductive portion 252 to achieve coupling between the source layer SL and the conductive portion 252.

[0140] In some embodiments, the material of the functional layer 242 of the channel structure 240 and the material of the insulating isolation portion 251 of the gate line isolation structure 250 may have similar etching rates in the etching process. Figure 7 A portion of the functional layer 242 of the channel structure 240 in the intermediate semiconductor structure 20 and a portion of the insulating isolation portion 251 of the gate line isolation structure 250 can be processed in the same process. For example, after removing the second sacrificial layer 213, the exposed functional layer 242 and the insulating isolation portion 251 can be removed by an etching process, so that the semiconductor channel 241 and the conductive portion 252 (for example, a common source contact) in the channel structure can be exposed by one etching, which can simplify the process flow.

[0141] In some embodiments, see Figure 5B The semiconductor channel 241 in the channel structure can penetrate the semiconductor layer 222 and protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL and protrude into the source layer SL. In this way, the contact area between the semiconductor channel 241 and the source layer SL can be increased, which is beneficial to improving the electrical connection stability between the semiconductor channel 241 and the source layer SL. Based on the same principle, the conductive portion 252 can also penetrate the semiconductor layer 222 and protrude from the interface IF3 between the semiconductor layer 222 and the source layer SL and protrude into the source layer SL. In this way, the contact area between the conductive portion 252 and the source layer SL can be increased, which is beneficial to improving the electrical connection stability between the conductive portion 252 and the source layer SL.

[0142] In other embodiments, see Fig. 9 , the semiconductor channel 241 in the channel structure can penetrate the semiconductor layer 222, and the bottom surface 241' of the semiconductor channel 241 in contact with the source layer SL is flush with the interface IF3. Figure 7In the process of manufacturing a three-dimensional memory using the semiconductor structure 20 in the embodiment, an etching process (such as chemical mechanical planarization) can be used to remove the structure located on the side of the semiconductor layer 222 away from the stacked structure 230 (i.e., the structure protruding from the semiconductor layer 222 in the direction in which the semiconductor layer 222 is away from the stacked structure 230), and then a source layer SL is formed on the side of the semiconductor layer 222 away from the stacked structure 230, so that the surface of the three-dimensional memory can be relatively flat. Based on the same principle, the conductive portion 252 can penetrate the semiconductor layer 222, and the bottom surface 252' of the conductive portion 252 in contact with the source layer SL is flush with the interface IF3, so that the surface of the three-dimensional memory can be more flat.

[0143] In some embodiments, see Figure 5B In the three-dimensional memory provided by the embodiment of the present disclosure, the semiconductor layer 222 can also be configured as a spacer layer between the source selection gate (for example, including the gate layer 232b) and the source layer SL. In addition, by controlling the thickness of the semiconductor layer 222, the distance between the source selection gate and the source layer SL can be effectively controlled, which is beneficial to controlling the operating voltage of the transistor corresponding to the source selection gate.

[0144] In some embodiments, as described above, see Figure 2 , the three-dimensional memory 10 also includes a second semiconductor structure 100. In the three-dimensional memory 10, the second semiconductor structure 100 can be arranged on a side of the first semiconductor structure 200 away from the source layer SL, or in other words, the second semiconductor structure 200 and the source layer SL are located on both sides of the first semiconductor structure 100. In this way, the device density of the three-dimensional memory 10 can be improved. In addition, when preparing such a three-dimensional memory, the first semiconductor structure and the second semiconductor structure can be manufactured separately. In this way, it is possible to avoid the two devices affecting each other's manufacturing process during manufacturing, and the performance of the three-dimensional memory can be improved.

[0145] In some embodiments, the three-dimensional memory may further include a back-end process interconnection layer (not shown in the figure). The back-end process interconnection layer may be disposed on a side of the source layer SL away from the first semiconductor structure 200, and is configured to transmit electrical signals between the three-dimensional memory and an external circuit. The back-end process interconnection layer may be coupled to a peripheral circuit in the second semiconductor structure, so that an electrical signal output by the external circuit may be transmitted to the peripheral circuit through the back-end process interconnection layer.

[0146] The embodiments of the present disclosure also provide a three-dimensional memory. Fig.10 A structural diagram of a three-dimensional memory. Fig.11 is a structural diagram of another three-dimensional memory. It should be noted that Fig.10 and Fig.11Only the first semiconductor structure and the source layer in the three-dimensional memory are shown, while other structures are omitted, for example, the second semiconductor structure is omitted. Figure 5B , Fig.10 and Fig.11 , Fig.10 and Fig.11 The three-dimensional memory 60 and Figure 5B The difference between the three-dimensional memory 10 is Fig.10 and Fig.11 The three-dimensional memory 60 in the embodiment does not include the semiconductor layer 222. The remaining structures can be the same as Figure 5B The corresponding structure in the three-dimensional memory 10 is the same, and reference may be made to the above description of the three-dimensional memory 10, which will not be repeated here.

[0147] See also Fig.10 The three-dimensional memory 60 includes a stacked structure 230. The stacked structure 230 includes first dielectric layers 231 and gate layers 232 that are alternately stacked.

[0148] The three-dimensional memory 60 further includes a channel structure 240 , and the channel structure 240 penetrates the stacked structure 230 .

[0149] In some embodiments, the channel structure 240 includes a semiconductor channel 241 and a functional layer 242. The functional layer 242 is disposed between the semiconductor channel 241 and the stacked structure 230.

[0150] The three-dimensional memory 60 further includes a second dielectric layer 260 . The second dielectric layer 260 is at least partially disposed between the gate layer 232 and the channel structure 240 .

[0151] The three-dimensional memory 60 further includes a gate line isolation structure 250. The gate line isolation structure 250 penetrates the stacked structure 230. The gate line isolation structure 250 includes an insulating isolation portion 251. The insulating isolation portion 251 contacts at least one (e.g., one; or more) side surfaces SW of the first dielectric layer 231. The side surfaces SW of the first dielectric layer 231 are, for example, surfaces of the first dielectric layer distributed perpendicular to the first direction.

[0152] In some possible implementations, the insulating isolation portion 251 contacts the side of the first dielectric layer 231 (e.g., the first dielectric layer 231b) closest to the source layer SL in the stacked structure 230. In other possible implementations, the insulating isolation portion 251 contacts the side of each first dielectric layer 231 in the stacked structure.

[0153] The beneficial effects that can be achieved by the insulating isolation portion 251 contacting the side surface SW of at least one first dielectric layer 231 can be referred to above and will not be described in detail here.

[0154] In some embodiments, the three-dimensional memory 60 further includes a source layer SL. The source layer SL may be disposed on the stacked structure 230. The channel structure 240 is coupled to the source layer SL. Exemplarily, a semiconductor channel 241 in the channel structure 240 is coupled to the source layer SL to achieve coupling of the channel structure 240 to the source layer SL.

[0155] Fig.10 and Fig.11 The three-dimensional memory 60 in the embodiment can also be composed of Figure 7 The intermediate semiconductor structure 20 is further processed to obtain.

[0156] Specifically, see Figure 7 and Fig.10 , the substrate 210, part of the functional layer 242 and part of the insulating isolation portion 251 can be removed by an etching process (such as a wet / dry etching process) to expose the semiconductor channel 241 and / or the conductive portion 252. Further, the semiconductor layer 222 can be removed by an etching process to obtain Fig.10 A three-dimensional memory 60 is shown.

[0157] See also Figure 7 and Fig.11 , a chemical mechanical planarization (CMP) can be used to remove the substrate 210 to expose the semiconductor channel 241 and / or the conductive portion 252. Further, the first dielectric layer 231 (for example, the first dielectric layer 231b) can be exposed to obtain Fig.11 The three-dimensional memory 60 shown. In this way, the surface of the three-dimensional memory 60 can be relatively flat.

[0158] Fig.12 is a structural diagram of another three-dimensional memory. It should be noted that Fig.12 Only the first semiconductor structure and the source layer in the three-dimensional memory are shown, while other structures are omitted, for example, the second semiconductor structure is omitted.

[0159] See also Fig.12 In some embodiments, the three-dimensional memory 60 further includes a semiconductor layer 222 ′ and a source layer SL.

[0160] It should be noted that see Figure 5B and Fig.12 , Fig.12 The three-dimensional memory 60 and Figure 5B The difference between the three-dimensional memory 10 is Fig.12 The semiconductor layer 222' in the three-dimensional memory 60 is Figure 5BThe semiconductor layer 222 in the three-dimensional memory 10 is different (the structure of the semiconductor layer 222' will be described in detail below), and the remaining structures can be the same as Figure 5B The corresponding structure in the three-dimensional memory 10 is the same, and reference may be made to the above description of the three-dimensional memory 10, which will not be repeated here.

[0161] See also Fig.12 In the three-dimensional memory 60, the semiconductor layer 222' is disposed between the source layer SL and the stacked structure 230. Exemplarily, the source layer SL, the semiconductor layer 222' and the stacked structure 230 may be sequentially distributed along the first direction.

[0162] In some possible implementations, one or more film layers may be disposed between the semiconductor layer 222 ′ and the insulating isolation portion 251 . For example, a second dielectric layer 260 may be disposed between the semiconductor layer 222 ′ and the insulating isolation portion 251 .

[0163] In some other possible implementations, the semiconductor layer 222 ′ is in contact with the insulating isolation portion 251 , that is, there is no other structure between the semiconductor layer 222 ′ and the insulating isolation portion 251 .

[0164] The material and other features of the semiconductor layer 222' may be Figure 5B The semiconductor layer 222 in the three-dimensional memory 10 is the same, and reference may be made to the above description, which will not be repeated here.

[0165] Continue to see Fig.12 In the three-dimensional memory 60, the channel structure 240 is coupled to the source layer SL. Exemplarily, the semiconductor channel 241 in the channel structure 240 is coupled to the source layer SL to achieve the coupling of the channel structure 240 to the source layer SL.

[0166] Some embodiments of the present disclosure further provide an electronic device. The electronic device may be any one of a mobile communication terminal, a tablet computer, a game console, a digital multimedia player, a smart wearable device (eg, a smart watch, a smart bracelet, smart glasses, etc.), and the like.

[0167] The electronic device may include the three-dimensional memory described above, and may also include at least one of a central processing unit (CPU), a cache, a controller, and the like.

[0168] Some embodiments of the present disclosure also provide a method for preparing a three-dimensional memory, which can be used to prepare the three-dimensional memory provided by any of the above embodiments. Fig.13 is a flow chart of a method for preparing a three-dimensional memory according to an embodiment of the present disclosure, Figure 14A to Figure 14MFIG. 1 is a process flow chart of a method for preparing a three-dimensional memory according to an embodiment of the present disclosure. Fig.13 and Figures 14A to 14M , a method for preparing a three-dimensional memory comprises:

[0169] S11. Form a semiconductor layer on a substrate.

[0170] See also Fig.14A In some embodiments, the substrate 210 may be a composite substrate having a multi-layer structure. Exemplarily, the substrate 210 may include a base 211, a first sacrificial layer 212, and a second sacrificial layer 213. The materials of each layer in the substrate 210 may refer to the above description and will not be repeated here. The first sacrificial layer 212 and the second sacrificial layer 213 may be formed on the substrate 211 by a thin film deposition process, and the thin film deposition process may be, for example, a combination of one or more of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or an atomic layer deposition method (ALD) and an electroplating process.

[0171] In some embodiments, before forming the semiconductor layer 222 on the substrate 210, the third dielectric layer 221 is formed on the substrate 210. That is, the third dielectric layer 221 and the semiconductor layer 222 may be sequentially formed on the substrate 210. In other embodiments, only the semiconductor layer 222 may be formed on the substrate 210 without forming the third dielectric layer 221.

[0172] The materials of the third dielectric layer 221 and the semiconductor layer 222 can refer to the above description and will not be described again.

[0173] The semiconductor layer 222 may be formed on the substrate by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of one or more of atomic layer deposition (ALD) and electroplating processes.

[0174] S12, forming alternately stacked first dielectric layers and gate sacrificial layers on a side of the semiconductor layer away from the substrate.

[0175] See also Fig. 14B Multiple first dielectric layers 231 and multiple gate sacrificial layers 610 stacked alternately may be formed on one side of the semiconductor layer 222 away from the substrate 210 along the first direction. For simplicity, the alternately stacked first dielectric layers 231 and gate sacrificial layers 610 are referred to as an initial stacked structure 600 herein.

[0176] In the initial stacked structure 600, the thicknesses of the plurality of first dielectric layers 231 may be the same or different, and the thicknesses of the plurality of gate sacrificial layers 610 may be the same or different, and may be set according to specific process requirements. In addition, the present disclosure does not limit the number of layers of the initial stacked structure, for example, the number of layers of the initial stacked structure may be 8, 64, 128, etc.

[0177] In some embodiments, among the first dielectric layers 231 and the gate sacrificial layers 610 of the initial stacked structure 600, the layer closest to the semiconductor layer 222 is the first dielectric layer 231. In other embodiments, among the first dielectric layers 231 and the gate sacrificial layers 610 of the initial stacked structure 600, the layer closest to the semiconductor layer 222 is the gate sacrificial layer 610.

[0178] The material of the first dielectric layer 231 can refer to the above description and will not be repeated here. The material of the gate sacrificial layer 610 can include a combination of one or more of silicon nitride, silicon oxide and silicon oxynitride. It should be noted that the material of the gate sacrificial layer 610 and the material of the first dielectric layer 231 can cooperate with each other, so that in the etching process, the etching rate of the material of the gate sacrificial layer 610 is different from the etching rate of the material of the first dielectric layer 231, and then in the etching process, the gate sacrificial layer 610 can be removed while the first dielectric layer 231 is retained.

[0179] A first dielectric layer 231 and a gate sacrificial layer 610 may be formed on the substrate 210 by a thin film deposition process, such as a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0180] In some embodiments, the edge of the initial stacked structure 610 may form a step-like structure. The step-like structure may be disposed in the contact region CA of the semiconductor structure. Exemplarily, the step-like structure may be formed by performing a plurality of “trim-etch” cycles on the plurality of first dielectric layers 231 and the gate sacrificial layer 610 of the initial stacked structure 600.

[0181] In some embodiments, a cover layer 280 may be formed on the stepped structure. The material of the cover layer 280 may refer to the above description and will not be described again. For example, the cover layer 280 may be formed by a thin film deposition process. In some possible implementations, a CMP process may be used to planarize the surface of the cover layer 280 away from the substrate 210.

[0182] S13, forming a channel structure penetrating the alternately stacked first dielectric layer, gate sacrificial layer and semiconductor layer and extending to the substrate

[0183] See also Fig. 14C , the channel structure 240 extending to the substrate 210 may mean the following two situations:

[0184] First, the channel structure 240 may protrude from the interface IF1 between the substrate 210 and the semiconductor layer 222 and protrude into the substrate 210. Second, the bottom surface 240' of the channel structure 240 (for example, the surface of the two surfaces of the channel structure 240 distributed along the first direction and close to the substrate 210) may be flush with the interface IF1. In the following, the description of "structure 1 extending to structure 2" may refer to the description of the channel structure 240 extending to the substrate 210, for example, the gate line slit extending to the substrate 210 may refer to the description of the channel structure 240 extending to the substrate 210, and will not be repeated one by one below.

[0185] In some embodiments, forming a channel structure 240 that penetrates the alternately stacked first dielectric layer 231 and the gate sacrificial layer 610 (i.e., the initial stacked structure 600) and the semiconductor layer 222 and extends to the substrate 210 includes forming a channel hole 240h. The channel hole 240h penetrates the alternately stacked first dielectric layer 231 and the gate sacrificial layer 610 (i.e., the initial stacked structure 600) and the semiconductor layer 222 and extends to the substrate 210. The channel hole 240h may penetrate the initial stacked structure 600 and the semiconductor layer 222 along a first direction. Exemplarily, the channel hole 240h may be formed in the initial stacked structure 600 and the semiconductor layer 222 by a dry / wet etching process. In some possible implementations, the substrate 210 may include a second sacrificial layer 213, and the second sacrificial layer 213 may be configured as an etch stop layer for etching to form the channel hole 240h. Exemplarily, the etching of the channel hole 240 h may be stopped by the second sacrificial layer 213 , so that the channel hole 240 h does not further extend to the first sacrificial layer 212 and the substrate 211 .

[0186] Forming a channel structure 240 that penetrates the alternately stacked first dielectric layer 231 and the gate sacrificial layer 610 (i.e., the initial stacked structure 600) and the semiconductor layer 222 and extends to the substrate also includes, after forming the channel hole 240h, sequentially forming a functional layer 242 and a semiconductor channel layer 241 on the inner wall of the channel hole 240h. The materials of the functional layer 242 and the semiconductor channel layer 241 can be as described above, and will not be repeated here. In some embodiments, forming the functional layer 242 on the inner wall of the channel hole 240h may include sequentially forming a charge storage layer 242b and a tunneling layer 242a on the inner wall of the channel hole 240h. In some embodiments, forming the functional layer 242 on the inner wall of the channel hole 240h also includes forming a barrier layer 242c on the inner wall of the channel hole 240h before forming the charge storage layer 242b and the tunneling layer 242a. That is, based on the above, forming the channel structure 240 may include sequentially forming a blocking layer 242 c , a charge storage layer 242 b , a tunneling layer 242 a , and a semiconductor channel layer 241 in the channel hole 240 h .

[0187] Exemplarily, a thin film deposition process can be used to form a barrier layer 242c, a charge storage layer 242b, a tunneling layer 242a and a semiconductor channel layer 241 on the inner wall of the channel hole 240h. The thin film deposition process is, for example, a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0188] In some possible implementations, after the functional layer 242 and the semiconductor channel 241 are sequentially formed on the inner wall of the channel hole 240h, a filling portion 243 may be formed in the channel hole 240h. The filling portion 243 may be formed by a thin film deposition process. For example, the thin film deposition process may be controlled so that one or more air gaps 243' are formed in the filling portion 243.

[0189] In some embodiments, step S13 may further include forming a dummy channel structure 270 in the contact area CA of the semiconductor structure. For example, in the step of forming the channel hole 240h, a channel hole 240h' may also be formed in the contact area CA of the semiconductor structure, and the channel hole 240h' may be referred to as a channel hole 240h' in which a dummy channel structure 270 is to be formed. An insulating material, such as silicon oxide, may be formed in the channel hole 240h' in which a dummy channel structure is to be formed by a thin film deposition process, so as to form the dummy channel structure 270. Similarly, one or more air gaps 271 may be formed in the dummy channel structure 270 by controlling the thin film deposition process.

[0190] S14, forming a gate line slit that penetrates the alternately stacked first dielectric layer, the gate sacrificial layer, and the semiconductor layer and extends to the substrate.

[0191] Similar to the formation of the channel hole 240h, a dry / wet etching process can be used to form the gate line slit St in the initial stacked structure 600. The specific process of forming the gate line slit St can refer to the above description of the process of forming the channel hole 240h, which will not be repeated here.

[0192] The gate line slit St may penetrate the initial stacked structure 600 and the semiconductor layer 222 along the first direction, and the gate line slit St may extend along a third direction (eg, perpendicular to the first direction).

[0193] It should be noted that, in some embodiments, the step of forming the channel hole 240h penetrating the initial stacked structure 600 and the semiconductor layer 222 and extending to the substrate 210 in step S13 and the step of forming the gate line slit St penetrating the initial stacked structure 600 and the semiconductor layer 222 and extending to the substrate 210 in step S14 can be performed in the same process, for example, the channel hole 240h and the gate line slit St are formed by one etching process. In other embodiments, the step of forming the channel hole 240h penetrating the initial stacked structure 600 and the semiconductor layer 222 and extending to the substrate 210 in step S13 and the step of forming the gate line slit St penetrating the initial stacked structure 600 and the semiconductor layer 222 and extending to the substrate 210 in step S14 can also be performed in different processes, for example, the channel hole 240h is formed by one etching process, and the gate line slit St is formed by another etching process. The embodiments of the present disclosure do not limit the order of performing the above two steps.

[0194] S15, removing the gate sacrificial layer through the gate line slits to form a sacrificial gap.

[0195] See also Fig.14D In some embodiments, a dry / wet etching process can be used to utilize the gate line slit St as a channel for the etchant, so that the gate sacrificial layer can contact the etchant through the gate line slit St, thereby removing the gate sacrificial layer in the initial stacked structure 600, and forming a sacrificial gap 610' at the position where the gate sacrificial layer was originally set in the initial stacked structure 600.

[0196] S16, forming a second dielectric layer in the sacrificial gap and the gate line slit.

[0197] See also Fig.14E The second dielectric layer 260 may be formed in the sacrificial gap 160' by a thin film deposition process. In some possible implementations, the second dielectric layer 260 may be conformally formed in the sacrificial gap 160' and the gate line slit St by a thin film deposition process.

[0198] In some embodiments, when the second dielectric layer 260 is formed in the sacrificial gap 610' by a thin film deposition process, the surface 600a (ie, the surface 600a of the initial stacked structure 600 away from the semiconductor layer 222) may be formed. Fig.14E A second dielectric layer 260 is conformally formed on the upper surface 600 a of the initial stacked structure 600 .

[0199] S17, removing at least the portion of the second dielectric layer that contacts the semiconductor layer.

[0200] See also Fig.14F , step S17 includes removing the portion of the second dielectric layer 260 in contact with the semiconductor layer 222. Further, in some embodiments, step S17 includes removing the portion of the second dielectric layer 260 in contact with the semiconductor layer 222, and the portion in contact with the side SW of the first dielectric layer 231 and / or the substrate 210. In some embodiments, step S17 may also include removing the portion of the second dielectric layer 260 in contact with the third dielectric layer 221. The side SW of the first dielectric layer 231 may be a surface of the first dielectric layer 231 exposed by the gate line slit St, and specifically, the side SW may be a side of the first dielectric layer 231 perpendicular to the first direction. In some possible implementations, step S17 may also include removing the second dielectric layer 260 located on the surface 600a of the initial stacked structure 600 away from the semiconductor layer 222. Based on the above, after completing step S17, in the semiconductor structure, the second dielectric layer 260 may not exist on the surface of the semiconductor layer 222 exposed by the gate line slit St; further, in the semiconductor structure, the second dielectric layer 260 may not exist on the side surface SW of the first dielectric layer 231 exposed by the gate line slit St and on the surface of the substrate 210 exposed by the gate line slit St; in addition, the second dielectric layer 260 may not exist on the surface 600a of the initial stacked structure 600 away from the semiconductor layer 222.

[0201] In some embodiments, before performing step S17, see Figure 14G, the second dielectric layer 260 can be subjected to ion implantation through the gate line slit St. Exemplarily, the second dielectric layer 260 located in the gate line slit St can be subjected to ion implantation through the gate line slit St. The second dielectric layer 260 located in the gate line slit St can include the second dielectric layer 260 located in the gate line slit St and in contact with the side SW of the first dielectric layer 231, the semiconductor layer 222, and the substrate 210, and can also include the second dielectric layer 260 located in the gate line slit St and in contact with the third dielectric layer 221. The above-mentioned second dielectric layer 260 can be subjected to ion implantation. Exemplarily again, the second dielectric layer 260 located on the surface of the initial stacked structure 600 away from the semiconductor layer 222 can also be subjected to ion implantation. Through the ion implantation treatment, the second dielectric layer 260 located in the gate line slit St can be modified, so that in the subsequent etching process, the etching rate of the second dielectric layer 260 is accelerated and it is easier to be removed.

[0202] Further, see Fig.14H After the second dielectric layer 260 is ion-implanted through the gate line slits St, step S17 may be performed. For example, a portion or all of the second dielectric layer 260 that has been ion-implanted may be removed by an etching process (e.g., a wet etching process). In some embodiments, after the second dielectric layer 260 is ion-implanted through the gate line slits St, a portion of the second dielectric layer 260 that has been ion-implanted may be removed by an etching process (e.g., a wet etching process).

[0203] In some embodiments, step S17 may include sub-step S171, which includes dry etching the second dielectric layer 260 through the gate line slit St to remove at least the portion of the second dielectric layer 260 in contact with the semiconductor layer 222. Exemplarily, the entire second dielectric layer 260 in the gate line slit St may be removed by dry etching.

[0204] In some embodiments, the second dielectric layer 260 may be firstly subjected to ion implantation through the gate line slits St, and a portion of the second dielectric layer 260 subjected to ion implantation may be removed by an etching process (e.g., a wet etching process), and then sub-step S171 may be performed. As described above, after the second dielectric layer 260 is subjected to ion implantation through the gate line slits St and an etching process (e.g., a wet etching process) is performed, the second dielectric layer 260 located in the gate line slits St may not be completely removed. For example, see Fig.14H, the second dielectric layer 260 may remain at the bottom of the gate line slit St. The bottom of the gate line slit St may be an end of the gate line slit St close to the substrate 210, and the semiconductor layer 222 and / or the substrate 210 may be exposed through the bottom of the gate line slit St. The bottom of the gate line slit St may be processed by the dry etching process in sub-step S171, and the second dielectric layer 260 remaining in the gate line slit St may be further removed.

[0205] In addition, see Figure 14G In some embodiments, the gate line slit St may further include other interface layers. Exemplarily, the materials of the semiconductor layer 222 and the second sacrificial layer 213 may be polysilicon. Before the second dielectric layer 260 is formed, the surface of the semiconductor layer 222 and / or the substrate 210 exposed by the gate line slit St may be oxidized, so that an oxide layer OI is formed on the surface of the semiconductor layer 222 and / or the substrate 210 exposed by the gate line slit St, that is, an oxide layer OI is formed at the bottom of the gate line slit St. The oxide layer OI may protect the semiconductor layer 222 and / or the second sacrificial layer 213.

[0206] Based on this, see Fig.14F and Figure 14G When executing sub-step S171, while the second dielectric layer 260 is dry-etched through the gate line slit St, other interface layers located in the gate line slit St, such as the oxide layer OI, may also be dry-etched to remove other interface layers located in the gate line slit St.

[0207] Based on the above, see Fig.14F In some embodiments, after step S17, the sacrificial gap 610' may be provided with a second dielectric layer 260 (it can also be said that the sacrificial gap 610' has a second dielectric layer 260). Specifically, the second dielectric layer 260 may be provided on the inner wall IW1 of the sacrificial gap 610' perpendicular to the first direction, and may also be provided on the inner wall IW2 of the sacrificial gap 610' along the first direction.

[0208] S18. Form a gate layer in the sacrificial gap.

[0209] See also Fig.14H and Fig.14I In some embodiments, the gate layer 232 may include a conductor layer 2322. The material and position of the conductor layer 2322 may refer to the above description and will not be described again. The conductor layer 2322 may be formed in the sacrificial gap 610' by a thin film deposition process, such as a combination of one or more of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), an atomic layer deposition method (ALD) and an electroplating process.

[0210] In some embodiments, the gate layer 232 may further include a metal compound layer 2321. The material and position of the metal compound layer 2321 may refer to the above description and will not be repeated here. At this time, step S18 may include: sequentially forming a metal compound layer 2321 and a conductor layer 2322 in the sacrificial gap 610', that is, forming a metal compound layer 2321 in the sacrificial gap 610', and then forming a conductor layer 2322 in the sacrificial gap 610' with the metal compound layer 2321. Exemplarily, the metal compound layer 2321 may be formed in the sacrificial gap 610' by a thin film deposition process, and the thin film deposition process is, for example, a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating processes.

[0211] In some embodiments, in the process of forming the gate layer 232, a conformal thin film deposition process may be used, so that the material of the gate layer 232 may also be conformally formed in the gate line slit St. At this time, step S18 may include a sub-step S181, and sub-step S181 includes removing the gate layer 232 material located in the gate line slit St, for example, an etching process, such as a wet etching process, may be used to remove the gate layer 232 material in the gate line slit St. Sub-step 181 may also include removing a portion of the gate layer 232 material located in the sacrificial gap 610', for example, a portion of the gate layer 232 material located in the sacrificial gap 610' and close to the gate line slit St may be removed.

[0212] In some possible implementations, sub-step S181 and the step of removing the second dielectric layer 260 in step S17 can be performed in the same process. Exemplarily, before step S17, the second dielectric layer 260 can be subjected to ion implantation through the gate line slit St, and then the gate layer 232 is formed in the sacrificial gap, and at the same time, the material of the gate layer 232 is conformally deposited in the gate line slit St to form a material layer. Afterwards, sub-step S181 and step S17 can be performed in the same process, for example, the process of removing the gate layer 232 material in the gate line slit St in sub-step S181 and the process of removing the second dielectric layer 260 after ion implantation in step S17 are completed by a single etching process (e.g., a wet etching process). For example, the etching rate of the material of the second dielectric layer 260 after ion implantation is similar to the etching rate of the material of the gate layer 232, and both can be removed by a single etching process.

[0213] Based on the above, a stacked structure 230 may be formed. The stacked structure 230 includes first dielectric layers 231 and gate layers 232 that are alternately stacked.

[0214] S19, forming a gate line isolation structure in the gate line slit.

[0215] See also Fig.14J In some embodiments, the gate line isolation structure 250 may include an insulating isolation portion 251. The material of the insulating isolation portion 251 may refer to the above description and will not be described again here. The insulating isolation portion 251 may be formed in the gate line slit St to form the gate line isolation structure 250. In some embodiments, the insulating isolation portion 251 may be formed in the gate line slit St and a portion of the sacrificial gap. Exemplarily, after sub-step S181, a portion of the gate layer 232 material near the gate line slit St in the sacrificial gap is removed, and the insulating isolation portion 251 may be conformally formed in the gate line slit St and the above-mentioned portion of the sacrificial gap.

[0216] The insulating isolation portion 251 may be formed by a thin film deposition process, such as a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0217] As described above, after step S17, in the semiconductor structure, the second dielectric layer 260 may not exist on the surface of the semiconductor layer 222 exposed by the gate line slit St; further, in the semiconductor structure, the second dielectric layer 260 may not exist on the side surface SW of the first dielectric layer 231 exposed by the gate line slit St and the surface of the substrate 210 exposed by the gate line slit St. Therefore, the insulating isolation portion 251 formed in step S19 may contact the semiconductor layer 222 and may also contact the side surface SW of the first dielectric layer 231. In this way, the structural stability of the semiconductor structure can be improved. For specific descriptions, please refer to the relevant descriptions above, which will not be repeated here.

[0218] In some embodiments, the gate line isolation structure 250 may further include a conductive portion 252, and the material of the conductive portion 252 may refer to the above description, which will not be repeated here. At this time, step S19 may include: sequentially forming an insulating isolation portion 251 and a conductive portion 252 in the gate line slit St, so that the conductive portion 252 is arranged in the insulating isolation portion 251. The conductive portion 252 may be formed by a thin film deposition process, such as a combination of one or more of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or an atomic layer deposition method (ALD) and an electroplating process.

[0219] S20 (optional): removing the substrate.

[0220] See also Fig.14J and Figure 14KIn some embodiments, the substrate 210 may be processed from the back side (i.e., the side of the substrate 210 away from the semiconductor layer 222), and the substrate 210 may be removed by chemical mechanical planarization (CMP) and dry / wet etching processes. For example, the base 211 may be removed by chemical mechanical planarization (CMP) and / or etching processes (e.g., including dry etching processes and / or wet etching processes); for another example, the first sacrificial layer 212 may be removed by a wet etching process, and the second sacrificial layer 213 may be used as an etching stop layer in the process of removing the first sacrificial layer 212 by a wet etching process; for another example, the second sacrificial layer 213 may be removed by a wet etching process, and the third dielectric layer 221 may be used as an etching stop layer in the process of removing the second sacrificial layer 213 by a wet etching process.

[0221] In some embodiments, see Fig.14J and Figure 14K , the channel structure 240 includes a semiconductor channel 241 and a functional layer 242. The method for preparing a three-dimensional memory further includes forming a third dielectric layer 221 on the substrate before the step of forming the semiconductor layer 222 on the substrate. At this time, step S20 may include a sub-step S201, and sub-step S201 includes removing the substrate 210 to expose the third dielectric layer 221 and a portion of the functional layer 242, such as a portion of the functional layer 242 extending to the substrate 210. Exemplarily, as described above, the substrate 210 may be removed by an etching process, and the third dielectric layer 221 may be used as an etching stop layer in the process of removing the substrate 210 by a wet etching process. For example, a predetermined etchant may be selected so that the etching may stop at the third dielectric layer 221 without further etching the semiconductor layer 222. Further, the etching rate of the material of the functional layer 242 (for example, the barrier layer 242c) can be close to the etching rate of the material of the third dielectric layer 221. For example, the material of the barrier layer 242c is the same as that of the third dielectric layer 221, both of which are silicon oxide. Based on this, the etching can be stopped at the third dielectric layer 221 and the functional layer 242. By adding the third dielectric layer 221, it is helpful to control the process uniformity during the removal of the substrate 210.

[0222] Further, see Figure 14K and Figure 14L The method for preparing a three-dimensional memory may further include: removing the third dielectric layer 221 and a portion of the functional layer 242 to expose the semiconductor channel 241. For example, a portion of the semiconductor channel 241 extending to the substrate 210 may be exposed.

[0223] For example, the third dielectric layer 221 and part of the functional layer 242 can be removed by an etching process (e.g., a wet etching process), and by selecting a predetermined etchant, the etching stops at the semiconductor layer 222 without further etching the first dielectric layer 231. Furthermore, the etching rate of the material of the semiconductor channel 241 can be similar to the etching rate of the material of the semiconductor layer 222. For example, the material of the semiconductor channel 241 is the same as that of the semiconductor layer 222, both of which are polycrystalline silicon. Based on this, the etching can stop at the semiconductor layer 222 and the semiconductor channel 241. By adding the semiconductor layer 222, it is beneficial to control the process uniformity during the substrate removal process.

[0224] For example, the portion of the functional layer 242 of the channel structure 240 extending to the third dielectric layer 221 or the semiconductor layer 222 may be further removed by controlling the etching time, so that the semiconductor channel 241 has a larger exposed area.

[0225] Continue to see Fig.14J and Figure 14K In some embodiments, the gate line isolation structure 250 includes an insulating isolation portion 251 and a conductive portion 252. At this time, based on the same principle, step S20 may include a sub-step S202, and sub-step S202 includes removing the substrate 210 to expose the third dielectric layer 221 and a portion of the insulating isolation portion 251, such as a portion of the insulating isolation portion 251 extending to the substrate 210. Exemplarily, as described above, the substrate 210 may be removed by an etching process. Similarly, the etching rate of the material of the insulating isolation portion 251 may be similar to the etching rate of the material of the third dielectric layer 221, for example, the material of the insulating isolation portion 251 is the same as the material of the third dielectric layer 221, both of which are silicon oxide. Based on this, etching can be stopped at the third dielectric layer 221 and the insulating isolation portion 251.

[0226] Further, in some embodiments, see Figure 14K and Figure 14L The method for preparing a three-dimensional memory may further include removing the third dielectric layer 221 and a portion of the insulating isolation portion 251 to expose the conductive portion 252 . For example, a portion of the conductive portion 252 extending to the substrate 210 may be exposed.

[0227] For example, the third dielectric layer 221 and part of the insulating isolation portion 252 can be removed by an etching process (e.g., a wet etching process), and a predetermined etchant is selected so that the etching stops at the semiconductor layer 222 without further etching the first dielectric layer 231. Furthermore, the etching rate of the material of the conductive portion 252 can be similar to the etching rate of the material of the semiconductor layer 222. For example, the material of the conductive portion 252 is the same as that of the semiconductor layer 222, both of which are polysilicon. Based on this, the etching can stop at the semiconductor layer 222 and the conductive portion 252.

[0228] For example, the portion of the insulating isolation portion 251 of the gate line isolation structure extending to the third dielectric layer 221 or the semiconductor layer 222 may be further removed by controlling the etching time, so that the conductive portion 252 has a larger exposed area.

[0229] In some embodiments, sub-step S201 and sub-step S202 can be performed in the same process. On this basis, the step of removing the third dielectric layer 221 and a portion of the functional layer 242 to expose the semiconductor channel 241 and the step of removing the third dielectric layer 221 and a portion of the insulating isolation portion 251 to expose the conductive portion 252 can be performed in the same process. Exemplarily, the etching rate of the material of the insulating isolation portion 251, the etching rate of the material of the functional layer 242, and the etching rate of the material of the third dielectric layer 221 are similar, and the third dielectric layer 221, a portion of the insulating isolation portion 251, and a portion of the functional layer 242 can be removed by a single etching process (e.g., a wet etching process) to expose the semiconductor channel 241, the conductive portion 252, and the semiconductor layer 222.

[0230] In some embodiments, since the etching rate of the material of the virtual channel structure 270 can be close to the etching rate of the material of the insulating isolation portion 251 and / or the functional layer 242, in the step of removing part of the insulating isolation portion 251 and / or removing part of the functional layer 242, the portion of the virtual channel structure 270 extending to the substrate can also be partially removed.

[0231] Step S21 (optional): after removing the substrate, a source layer is formed on a side of the semiconductor layer away from the stacked structure.

[0232] See also Figure 14M The material of the source layer SL can refer to the above description and will not be described again. For example, the source layer SL can be formed by a thin film deposition process, such as a combination of one or more of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or an atomic layer deposition method (ALD) and an electroplating process.

[0233] As described above, after the substrate is removed in step S20 and a step of removing a portion of the functional layer 242 is performed, the semiconductor channel 241 in the semiconductor structure can be exposed. Therefore, the formed source layer SL can contact the exposed semiconductor channel 241 to achieve coupling between the source layer SL and the semiconductor channel 241.

[0234] In some embodiments, as described above, after step S20 and performing the step of removing part of the insulating isolation part 251, the conductive part 252 may also be exposed. Therefore, the formed source layer SL may also contact the exposed conductive part 252 to achieve coupling between the conductive part 252 and the source layer SL.

[0235] In some possible implementations, the source layer SL may be doped with P-type or N-type dopants by, for example, an ion implantation process, and the lattice damage of the material caused by the ion implantation process may be repaired and the implanted dopants may be activated by a laser annealing process.

[0236] In some embodiments, the method for preparing a three-dimensional memory may further include step S22: before removing the substrate, coupling the first semiconductor structure with the second semiconductor structure, wherein the second semiconductor structure is located on a side of the first semiconductor structure away from the substrate.

[0237] The first semiconductor structure and the second semiconductor structure may refer to the above description and will not be described in detail here.

[0238] In some embodiments, the array device and the peripheral device can be bonded by setting a bonding interface between the array interconnect layer and the peripheral interconnect layer, thereby achieving the coupling of the first semiconductor structure and the second semiconductor structure. Then, the first semiconductor structure and the second semiconductor structure bonded together can be turned 180° as a whole, and then the step of removing the substrate can be performed from the back of the substrate (i.e., the side of the substrate away from the stacked structure). In this way, the second semiconductor structure including the peripheral circuit and the first semiconductor structure can be manufactured separately. For example, the peripheral circuit can be manufactured on one substrate, and the semiconductor structure can be manufactured on another substrate. In this way, it is possible to avoid the two devices affecting each other's manufacturing process during manufacturing, and the performance of the three-dimensional memory can be improved. In addition, in the step of removing the substrate, since the first semiconductor structure is coupled to the second semiconductor structure first, and then the step of removing the substrate is performed, therefore, in the step of removing the substrate, the second semiconductor structure can provide support for the first semiconductor structure, which can improve the structural stability of the three-dimensional memory and improve the yield of the product.

[0239] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: A first semiconductor structure, the first semiconductor structure comprising: Semiconductor layer; A stacked structure, arranged on the semiconductor layer, comprising alternately stacked first dielectric layers and gate layers; A source layer, arranged on a side of the semiconductor layer away from the stacked structure; A channel structure, penetrating the stacked structure and the semiconductor layer, the channel structure being coupled to the source layer; a second dielectric layer, at least partially disposed between the gate layer and the channel structure; A gate line isolation structure runs through the stacked structure and the semiconductor layer, the gate line isolation structure includes an insulating isolation portion and a conductive portion, the insulating isolation portion is in contact with the semiconductor layer, the conductive portion is arranged in the insulating isolation portion and extends to the source layer, and the conductive portion is coupled to the source layer.

2. The three-dimensional memory according to claim 1, characterized in that: The second dielectric layer is also partially disposed between the first dielectric layer and the gate layer.

3. The three-dimensional memory according to claim 1 or 2, characterized in that: The insulating isolation portion contacts a side surface of the first dielectric layer.

4. The three-dimensional memory according to claim 1, characterized in that: The semiconductor layer is a polysilicon layer; and / or The second dielectric layer includes a high dielectric constant material.

5. The three-dimensional memory according to claim 2, characterized in that: The gate layer includes a metal compound layer and a conductor layer, and the metal compound layer is arranged between the conductor layer and the second dielectric layer.

6. The three-dimensional memory according to claim 1, characterized in that: The channel structure comprises: a semiconductor channel and a functional layer, wherein the functional layer is arranged between the semiconductor channel and the stacked structure, and the semiconductor channel is coupled to the source layer; The functional layer comprises: a tunneling layer and a charge storage layer, wherein the tunneling layer is arranged between the second dielectric layer and the semiconductor channel, and the charge storage layer is arranged between the tunneling layer and the second dielectric layer; The charge storage layer is in contact with the second dielectric layer, or the functional layer further includes a barrier layer, and the barrier layer is disposed between the charge storage layer and the second dielectric layer.

7. The three-dimensional memory according to claim 1, characterized in that: Also includes: A second semiconductor structure is disposed on a side of the first semiconductor structure away from the source layer; The second semiconductor structure is coupled to the first semiconductor structure.

8. A three-dimensional memory, characterized in that: include: source layer; A stacked structure, arranged on the source layer, comprising alternately stacked first dielectric layers and gate layers; A channel structure, penetrating the stacked structure, wherein the channel structure is coupled to the source layer; A second dielectric layer, at least partially disposed between the gate layer and the channel structure; a gate line isolation structure, which penetrates the stacked structure, the gate line isolation structure comprising an insulating isolation portion and a conductive portion, the conductive portion being arranged in the insulating isolation portion and extending to the source layer, the conductive portion being coupled to the source layer; The insulating isolation portion contacts a side surface of the first dielectric layer.

9. The three-dimensional memory according to claim 8, characterized in that: The channel structure includes: a semiconductor channel and a functional layer, wherein the functional layer is arranged between the semiconductor channel and the stacked structure.

10. The three-dimensional memory according to claim 9, characterized in that: Also includes: A semiconductor layer is provided between the source layer and the stacked structure, the insulating isolation portion is in contact with the semiconductor layer, and the semiconductor channel is coupled to the source layer.

11. An electronic device, characterized in that: A three-dimensional memory comprising the three-dimensional memory according to any one of claims 1 to 10.

12. A method for preparing a three-dimensional memory, characterized in that: include: forming a semiconductor layer on a substrate; Forming alternately stacked first dielectric layers and gate sacrificial layers on a side of the semiconductor layer away from the substrate; forming a channel structure penetrating the alternately stacked first dielectric layer and gate sacrificial layer and the semiconductor layer and extending to the substrate; Forming a source layer on a side of the semiconductor layer away from the alternately stacked first dielectric layers and gate sacrificial layers, wherein the source layer is coupled to the channel structure; forming a gate line slit penetrating the alternately stacked first dielectric layer, gate sacrificial layer and semiconductor layer and extending to the substrate; Removing the gate sacrificial layer through the gate line slits to form a sacrificial gap; forming a second dielectric layer in the sacrificial gap and the gate line slit; removing at least a portion of the second dielectric layer in contact with the semiconductor layer; forming a gate layer in the sacrificial gap; A gate line isolation structure is formed in the gate line slit, the gate line isolation structure includes an insulating isolation part and a conductive part, the insulating isolation part is in contact with the semiconductor layer, the conductive part is arranged in the insulating isolation part and extends to the source layer, and the conductive part is coupled to the source layer.

13. The method for preparing a three-dimensional memory according to claim 12, characterized in that: Removing at least a portion of the second dielectric layer in contact with the semiconductor layer comprises: The portion of the second dielectric layer in contact with the semiconductor layer and the portion in contact with the side surface of the first dielectric layer and / or the substrate are removed.

14. The method for preparing a three-dimensional memory according to claim 12, characterized in that: Also includes: Before at least removing the portion of the second dielectric layer in contact with the semiconductor layer, an ion implantation process is performed on the second dielectric layer through the gate line slits.

15. The method for preparing a three-dimensional memory according to claim 12, characterized in that: Removing at least a portion of the second dielectric layer in contact with the semiconductor layer comprises: The second dielectric layer is dry-etched through the gate line slits to remove at least a portion of the second dielectric layer that is in contact with the semiconductor layer.

16. The method for preparing a three-dimensional memory according to claim 12, characterized in that: Before the step of forming a source layer on a side of the semiconductor layer away from the alternately stacked first dielectric layers and gate sacrificial layers, the method further includes: The substrate is removed.

17. The method for preparing a three-dimensional memory according to claim 16, characterized in that: Also includes: Before the step of forming a semiconductor layer on the substrate, a third dielectric layer is formed on the substrate.

18. The method for preparing a three-dimensional memory according to claim 17, characterized in that: The channel structure includes a semiconductor channel and a functional layer; Removing the substrate comprises: removing the substrate to expose the third dielectric layer and a portion of the functional layer; The method for preparing the three-dimensional memory further includes: removing the third dielectric layer and a portion of the functional layer to expose the semiconductor channel.

19. The method for preparing a three-dimensional memory according to claim 18, characterized in that: Removing the substrate comprises: removing the substrate to expose the third dielectric layer and a portion of the insulating isolation portion; The method for preparing the three-dimensional memory further includes: The third dielectric layer and a portion of the insulating isolation portion are removed to expose the conductive portion.

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