Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a substrate; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the light-emitting element including a light-emitting region, the pixel circuit being connected to the light-emitting element and configured to drive the light-emitting element, the pixel circuit including a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate, the first electrode plate being closer to the substrate than the second electrode plate, the second electrode plate of the storage capacitor including a body portion and a first opening in the body portion, the orthographic projection of the first opening on the substrate at least partially overlapping the orthographic projection of the first electrode plate on the substrate; the pixel unit includes a first pixel unit and a second pixel unit, the first electrode plate of the pixel unit including a first arcuate edge, the average curvature of the first arcuate edge of the first pixel unit being greater than the average curvature of the first arcuate edge of the second pixel unit.

Description

[0001] This patent application is a divisional application of application number 202111028193.8, filed on September 2, 2021. Technical Field

[0002] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0003] With the continuous development of display technology, people have increasingly higher requirements for the uniformity of display and the quality of the picture. Due to their advantages such as high display quality, high-resolution display devices are being used in a wider range of applications. Summary of the Invention

[0004] At least one embodiment of this disclosure relates to a display panel and a display device.

[0005] At least one embodiment of this disclosure provides a display panel, including: a substrate; and a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the light-emitting element including a light-emitting region; the pixel circuit is connected to the light-emitting element and configured to drive the light-emitting element, the pixel circuit including a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate, the first electrode plate being closer to the substrate than the second electrode plate, the second electrode plate of the storage capacitor including a body portion and a first opening in the body portion, the orthographic projection of the first opening on the substrate at least partially overlapping the orthographic projection of the first electrode plate on the substrate; the pixel unit including a first pixel unit and a second pixel unit, the first electrode plate of the pixel unit including a first arcuate edge, the average curvature of the first arcuate edge of the first pixel unit being greater than the average curvature of the first arcuate edge of the second pixel unit.

[0006] For example, the maximum curvature of the first arcuate edge of the first pixel unit is less than the maximum curvature of the first arcuate edge of the second pixel unit.

[0007] For example, the curvature at the midpoint of the first arcuate edge of the first pixel unit is greater than the curvature at the midpoint of the first arcuate edge of the second pixel unit.

[0008] For example, the maximum curvature of the first arc-shaped edge of the first pixel unit is less than the maximum curvature of the first opening of the first pixel unit, and the maximum curvature of the first arc-shaped edge of the second pixel unit is less than the maximum curvature of the first opening of the second pixel unit.

[0009] For example, the area of ​​the first electrode plate and the second electrode plate of the first pixel unit facing each other is smaller than the area of ​​the first electrode plate and the second electrode plate of the second pixel unit facing each other.

[0010] For example, the first electrode plate of the first pixel unit and the first electrode plate of the second pixel unit are arranged in a first direction; the maximum size of the first electrode plate of the first pixel unit in a second direction is smaller than the maximum size of the first electrode plate of the second pixel unit in the second direction, and the first direction intersects with the second direction.

[0011] For example, the area of ​​the first electrode plate of the first pixel unit is smaller than the area of ​​the first electrode plate of the second pixel unit.

[0012] For example, the area of ​​the first opening of the first pixel unit is larger than the area of ​​the first opening of the second pixel unit.

[0013] For example, the orthographic projection of the light-emitting element of the second pixel unit onto the substrate does not overlap with the orthographic projection of the storage capacitor of the first pixel unit onto the substrate, and the orthographic projection of the storage capacitor of the second pixel unit onto the substrate does not overlap with the orthographic projection of the light-emitting region of the second pixel unit onto the substrate.

[0014] For example, the display panel further includes a third pixel unit, wherein the first electrode plate of the third pixel unit, the first electrode plate of the first pixel unit, and the first electrode plate of the second pixel unit are arranged in the first direction.

[0015] For example, the average curvature of the first arcuate edge of the first pixel unit is greater than the average curvature of the first arcuate edge of the third pixel unit.

[0016] For example, the maximum size of the first electrode plate of the first pixel unit in the second direction is smaller than the maximum size of the first electrode plate of the second pixel unit in the second direction, and smaller than the maximum size of the first electrode plate of the third pixel unit in the second direction, wherein the second direction intersects the first direction.

[0017] For example, the area of ​​the first opening of the first pixel unit is larger than the area of ​​the first opening of the second pixel unit, and is also larger than the area of ​​the first opening of the third pixel unit.

[0018] For example, the orthographic projection of the light-emitting region of the third pixel unit onto the substrate does not overlap with the orthographic projection of the storage capacitor of the first pixel unit onto the substrate, and does not overlap with the orthographic projection of the storage capacitor of the second pixel unit onto the substrate; the orthographic projection of the light-emitting element of the second pixel unit onto the substrate does not overlap with the orthographic projection of the storage capacitor of the first pixel unit onto the substrate, and does not overlap with the orthographic projection of the storage capacitor of the third pixel unit onto the substrate.

[0019] For example, the orthographic projection of the light-emitting region of the second pixel unit onto the substrate does not overlap with the orthographic projection of the storage capacitor of the first pixel unit onto the substrate, and also does not overlap with the orthographic projection of the storage capacitor of the third pixel unit onto the substrate.

[0020] For example, the area of ​​the storage capacitor is equal to the difference between the area of ​​the first plate and the area of ​​the first opening.

[0021] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising a total of n rows and m columns, wherein at least one of the n rows and m columns, i.e., the pixel circuit in the i-th row and j-th column, satisfies the following formula:

[0022]

[0023] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; B represents the area of ​​the first plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor; d represents the vertical distance between the first plate and the second plate of the storage capacitor; where 0 <K<1。

[0024] For example, 0.3≤K≤0.8.

[0025] For example, 0.5≤K≤0.7.

[0026] For example, 0.1 ≤ K < 0.3 or 0.8 <K≤0.9。

[0027] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising a total of n rows and m columns, wherein at least one of the n rows and m columns, i.e., the pixel circuit in the i-th row and j-th column, satisfies the following formula:

[0028]

[0029] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate of the storage capacitor; B represents the area of ​​the first plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0030] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns, wherein the pixel circuit in the i-th row and j-th column is the pixel circuit of the first pixel unit; the pixel circuit of the first pixel unit satisfies the following formula:

[0031]

[0032] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; A represents the area of ​​the second plate of the storage capacitor; B represents the area of ​​the first plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0033] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns, the pixel circuit in the i-th row and j-th column being the pixel circuit of the first pixel unit, and the pixel circuit in the (i+x)-th row and (j+2y+1)-th column being the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit satisfies the following formula:

[0034]

[0035] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate of the storage capacitor; B represents the area of ​​the first plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0036] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns, the pixel circuit in the i-th row and j-th column being the pixel circuit of the first pixel unit, the pixel circuit in the (i+x)-th row and (j+2y+1)-th column being the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; satisfying the following formula:

[0037] Hij×B(i+x)(j+2y+1)-H(i+x)(j+2y+1)×Bij>0, where n is an integer ≥2; m is an integer ≥2; i is a natural number satisfying 1≤i≤n; j is a natural number satisfying 1≤j≤m; and i+x≤n; j+2y+1≤m; x is an integer satisfying 0≤x≤n; y is an integer satisfying 0≤y≤m; B represents the area of ​​the first plate of the storage capacitor, and H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0038] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns, the pixel circuit in the i-th row and j-th column being the pixel circuit of the first pixel unit, and the pixel circuit in the (i+x)-th row and (j+2y+1)-th column being the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; satisfying the following formula:

[0039]

[0040] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n, j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0041] For example, the first electrode plate of the first pixel unit and the first electrode plate of the second pixel unit are arranged in a first direction; the maximum size of the first electrode plate of the first pixel unit in the first direction is smaller than the maximum size of the first electrode plate of the second pixel unit in the first direction.

[0042] For example, the first electrode plate includes a second edge opposite to the first arc-shaped edge, the first electrode plate of the first pixel unit and the first electrode plate of the second pixel unit are arranged in a first direction; along the second direction, the minimum distance from the first opening of the first pixel unit to the second edge of the first electrode plate is D1, the minimum distance from the first opening of the second pixel unit to the second edge of the first electrode plate is D2, the first direction intersects the second direction, and D1 is less than D2.

[0043] For example,

[0044] For example,

[0045] For example,

[0046] For example, the second electrode plate includes a first edge and a second edge disposed opposite to each other. The first arcuate edge of the first electrode plate and the first edge of the second electrode plate are located on the same side of the first opening. The second edge of the first electrode plate and the second edge of the second electrode plate are located on the same side of the first opening. In the first pixel unit, the shortest distance between the second edge of the first electrode plate and the second edge of the second electrode plate is E1. In the second pixel unit, the shortest distance between the second edge of the first electrode plate and the second edge of the second electrode plate is E2. E1 is greater than E2.

[0047] For example,

[0048] For example,

[0049] For example, the first electrode plate further includes a third edge and a fourth edge, and the second electrode plate further includes a third edge and a fourth edge. The third edge of the first electrode plate and the third edge of the second electrode plate are located on the same side of the first opening, and the fourth edge of the first electrode plate and the fourth edge of the second electrode plate are located on the same side of the first opening. In the first pixel unit, the distance between the third edge of the first electrode plate and the third edge of the second electrode plate is F1, and in the second pixel unit, the distance between the third edge of the first electrode plate and the third edge of the second electrode plate is F2, where F1 is greater than F2.

[0050] For example, in the first pixel unit, the minimum distance between the first opening and the third edge of the second electrode plate is G1, and in the second pixel unit, the minimum distance between the first opening and the third edge of the second electrode plate is G2, where G1 is less than G2.

[0051] For example,

[0052] For example, in the first pixel unit, the ratio of the maximum size of the first electrode plate in the second direction to the maximum size of the second electrode plate in the second direction is R11; in the second pixel unit, the ratio of the maximum size of the first electrode plate in the second direction to the maximum size of the second electrode plate in the second direction is R12; and in the third pixel unit, the ratio of the maximum size of the first electrode plate in the second direction to the maximum size of the second electrode plate in the second direction is R13. The second direction intersects the first direction, and R11 is less than R12 and R13.

[0053] For example, in the first pixel unit, the ratio of the maximum size of the first opening in the second direction to the maximum size of the first electrode plate in the second direction is R21; in the second pixel unit, the ratio of the maximum size of the first opening in the second direction to the maximum size of the first electrode plate in the second direction is R22; and in the third pixel unit, the ratio of the maximum size of the first opening in the second direction to the maximum size of the first electrode plate in the second direction is R23. The second direction intersects the first direction, and R21 is greater than R22 and R23.

[0054] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns, wherein at least one of the n rows and m columns, i.e., the i-th row and j-th column, is the pixel circuit of the first pixel unit, and the (i+x)(j+2y+1)-th column is the pixel circuit of the second pixel unit or the third pixel unit, and the area of ​​the first electrode plate of the first pixel unit and the area of ​​the first electrode plate of the second pixel unit or the third pixel unit satisfy the following formula:

[0055]

[0056] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; B represents the area of ​​the first plate of the storage capacitor.

[0057] For example,

[0058] For example, the display panel also includes a light emission control signal line extending along a first direction, the first electrode plate including a second edge opposite to the first arcuate edge, the first electrode plate and the light emission control signal line being arranged along a second direction, in the first pixel unit, the distance from the second edge of the first electrode plate to the light emission control signal line is Q1, and in the second pixel unit, the distance from the second edge of the first electrode plate to the light emission control signal line is Q2, where Q1 is greater than Q2.

[0059] For example,

[0060] For example, the display panel also includes a transition electrode, through which the pixel circuit is connected to the light-emitting element.

[0061] For example, in the first pixel unit, the shortest distance between the first electrode plate and the transfer electrode is P1, and in the second pixel unit or the third pixel unit, the shortest distance between the first electrode plate and the transfer electrode is P2, where P1 is greater than P2.

[0062] For example,

[0063] For example, the pixel circuit further includes a driving transistor, the gate of which is connected to the first plate of the storage capacitor.

[0064] For example, in the first pixel unit, the ratio of the area of ​​the portion of the semiconductor layer of the driving transistor located in the first opening to the sum of the areas of the second electrode and the first opening is R31; in the second pixel unit, the ratio of the area of ​​the portion of the semiconductor layer of the driving transistor located in the first opening to the sum of the areas of the second electrode and the first opening is R32; and in the third pixel unit, the ratio of the area of ​​the portion of the semiconductor layer of the driving transistor located in the first opening to the sum of the areas of the second electrode and the first opening is R33. R31 is greater than R32, and R31 is greater than R33.

[0065] For example, multiple pixel units and multiple pixel circuits are provided, the multiple pixel circuits comprising n rows and m columns. Let the i-th row and j-th column be the pixel circuit of the first pixel unit, let the i-th row and (j-1)-th column be the pixel circuit of the second pixel unit, and let the i-th row and (j+1)-th column be the pixel circuit of the third pixel unit, satisfying the following formula:

[0066]

[0067] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate of the storage capacitor; B represents the area of ​​the first plate of the storage capacitor; H represents the area of ​​the first opening in the second plate of the storage capacitor.

[0068] For example, the light-emitting element includes a first electrode, and the ratio of the overlapping area of ​​the first electrode of the first pixel unit and the first plate of the first pixel unit to the area of ​​the first electrode of the first pixel unit is less than the ratio of the overlapping area of ​​the first electrode of the first pixel unit and the first plate of the second pixel unit to the area of ​​the first electrode of the first pixel unit.

[0069] For example, the overlap area between the first electrode of the first pixel unit and the second electrode plate of the first pixel unit is smaller than the overlap area between the first electrode of the first pixel unit and the second electrode plate of the second pixel unit.

[0070] For example, the display panel further includes a fourth pixel unit, wherein the pixel circuit of the fourth pixel unit, the pixel circuit of the third pixel unit, the pixel circuit of the first pixel unit, and the pixel circuit of the second pixel unit are arranged sequentially along the first direction, and the facing areas of the first electrode plate and the second electrode plate of the fourth pixel unit are not equal to the facing areas of the first electrode plate and the second electrode plate of the second pixel unit.

[0071] For example, the light-emitting element includes a light-emitting functional layer, with the light-emitting functional layers of two first pixel units and two fourth pixel units surrounding a second pixel unit or a third pixel unit, and the center line connecting the two first pixel units and the center line connecting the light-emitting functional layers of the two fourth pixel units passing through the light-emitting functional layer of the second pixel unit or the third pixel unit.

[0072] For example, the first electrode of the light-emitting element of the fourth pixel unit has a notch, and the orthographic projection of the notch on the substrate does not overlap with the orthographic projection of the storage capacitor of the fourth pixel unit on the substrate.

[0073] For example, the pixel circuit further includes a threshold compensation transistor, the first electrode of which is connected to the second electrode of the driving transistor, and the second electrode of which is connected to the gate of the driving transistor; the threshold compensation transistor includes a first channel, a second channel, and a conductive connection portion connecting the first channel and the second channel, and the orthographic projection of the first electrode of the light-emitting element on the substrate covers the orthographic projection of the conductive connection portion on the substrate.

[0074] For example, the display panel further includes a pixel defining layer, the pixel defining layer including a second opening defining the light-emitting area, wherein the ratio of the overlapping area of ​​the second opening of the first pixel unit and the first electrode of the first pixel unit to the area of ​​the second opening of the first pixel unit is greater than 0 and less than 3%.

[0075] For example, the overlap area between the second opening of the first pixel unit and the first electrode plate of the first pixel unit is equal to the overlap area between the second opening of the first pixel unit and the first electrode plate of the second pixel unit.

[0076] For example, the display panel also includes multiple touch electrodes, each touch electrode being in a grid shape. Each touch electrode includes multiple conductive lines, which intersect to form multiple mesh areas. The ratio of the overlapping area of ​​the opposite portion of the storage capacitor of the first pixel unit with the multiple conductive lines to the area of ​​the mesh area is less than the ratio of the overlapping area of ​​the opposite portion of the storage capacitor of the second pixel unit with the multiple conductive lines to the area of ​​the mesh area.

[0077] For example, the ratio of the area of ​​the second opening of at least one of the first pixel unit and the second pixel unit to the area of ​​the mesh region is greater than one-half and less than three-quarters.

[0078] For example, the orthographic projection of the transfer electrode on the substrate overlaps with the orthographic projection of the plurality of conductive lines on the substrate.

[0079] For example, the display panel also includes a spacer located between the light-emitting area of ​​the first pixel unit and the light-emitting area of ​​the fourth pixel unit.

[0080] For example, the slope angle of the portion of the pixel defining layer that forms the second opening of the first pixel unit is smaller than the slope angle of the portion of the pixel defining layer that forms the second opening of the third pixel unit, and the slope angle of the portion of the pixel defining layer that forms the second opening of the third pixel unit is smaller than the slope angle of the portion of the pixel defining layer that forms the second opening of the second pixel unit.

[0081] For example, the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit constitute a repeating unit, and the light-emitting area of ​​the first pixel unit and the light-emitting area of ​​the fourth pixel unit are located between the light-emitting area of ​​the second pixel unit and the light-emitting area of ​​the third pixel unit.

[0082] For example, the orthographic projection of the light-emitting region of the first pixel unit onto the substrate overlaps with the orthographic projection of at least one of the storage capacitors of the first pixel unit or the second pixel unit onto the substrate, and the opposing areas of the storage capacitors of the first pixel unit and the opposing areas of the storage capacitors of the second pixel unit are not equal.

[0083] At least one embodiment of this disclosure also provides a display device, including any of the above-described display panels. Attached Figure Description

[0084] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0085] Figure 1A This is a schematic diagram of the pixel arrangement of a display panel.

[0086] Figure 1B This is a schematic diagram of the pixel arrangement for another type of display panel.

[0087] Figure 1C This is a schematic diagram of the pixel arrangement for another type of display panel.

[0088] Figure 2 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light in a display panel.

[0089] Figure 3 This is a schematic diagram showing the arrangement of the light-emitting area of ​​a light-emitting element that stores a capacitor in a display panel.

[0090] Figure 4 This is a schematic diagram of a display panel.

[0091] Figure 5A This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0092] Figure 5B This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0093] Figure 6 for Figure 5A A cross-sectional view of the UV line along the center.

[0094] Figure 7 for Figure 5A or Figure 5B A plan view of the first plate of the storage capacitor.

[0095] Figure 8 for Figure 5A or Figure 5B A plan view of the second plate of the storage capacitor.

[0096] Figure 9 This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0097] Figure 10 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0098] Figure 11A This is a comparative schematic diagram of a first pixel unit and a first electrode plate in a second pixel unit of a display panel provided in an embodiment of the present disclosure.

[0099] Figure 11B for Figure 11A A comparative schematic diagram of the first edge of the first electrode plate in the diagram.

[0100] Figure 12 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0101] Figure 13 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0102] Figure 14 This is a schematic diagram of a pixel circuit.

[0103] Figure 15 It is a layout diagram of a pixel circuit.

[0104] Figure 16A It is a cross-sectional view of a display panel.

[0105] Figure 16B yes Figure 15 A sectional view along line JK.

[0106] Figure 17 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0107] Figure 18 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0108] Figure 19 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0109] Figure 20This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0110] Figure 21 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0111] Figure 22 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0112] Figures 23 to 27 This is a schematic diagram of a display panel provided in some embodiments of this disclosure. Detailed Implementation

[0113] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0114] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0115] Figure 1A This is a schematic diagram of the pixel arrangement of a display panel. Figure 1B This is a schematic diagram of the pixel arrangement for another type of display panel. Figure 1C This is a schematic diagram of the pixel arrangement for another type of display panel. Figure 2 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light in a display panel.

[0116] like Figures 1A to 1C As shown, the display device includes multiple pixel units 100. Figure 2 As shown, each pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. Figures 1A to 1CThe pixel arrangement shown refers to the setting position of the light-emitting area of ​​the light-emitting element 100b in the pixel unit 100.

[0117] like Figures 1A to 1C As shown, the plurality of pixel units 100 include a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104. For example, as Figures 1A to 1C As shown, the first pixel unit 101, the second pixel unit 102, the third pixel unit 103, and the fourth pixel unit 104 can constitute a repeating unit RP. Of course, in other embodiments, the number of pixel units included in a repeating unit RP can also be other values. For example, a repeating unit RP can include three pixel units, four pixel units, or more than four pixel units, depending on the needs. Figures 1A to 1C The pixel arrangements shown in this disclosure are only illustrative examples, and the pixel arrangements in the display panels provided in the embodiments are not limited to those shown in this disclosure. Figures 1A to 1C As shown.

[0118] Figure 3 This is a schematic diagram showing the arrangement of the light-emitting area of ​​a light-emitting element that stores a capacitor in a display panel. For example... Figure 3 As shown, the pixel circuit 100a includes a storage capacitor Cst. When arranging the pixel units, in order to improve the flatness of the light-emitting area LMR of the light-emitting element 100b and avoid display defects, the light-emitting area LMR of the light-emitting element 100b will try to avoid the position of the storage capacitor Cst. Considering that the light-emitting areas of the second pixel unit 102 and the third pixel unit 103 are relatively large, the light-emitting areas of the second pixel unit 102 and the third pixel unit 103 are prioritized to avoid the position of the storage capacitor Cst during the arrangement. However, due to the limited arrangement space, the light-emitting areas of the first pixel unit 101 and the fourth pixel unit 104 will inevitably overlap with the storage capacitor Cst, resulting in inconsistent electrical environments of each pixel unit and causing uneven display.

[0119] Figure 4 This is a schematic diagram of a display panel. (Example) Figure 4 As shown, the storage capacitors in the first pixel unit 101, the second pixel unit 102, the third pixel unit 103, and the fourth pixel unit 104 are all the same.

[0120] Figure 5A This is a plan view of a display panel provided in one embodiment of the present disclosure. Figure 5B This is a plan view of a display panel provided in one embodiment of the present disclosure. Figure 6 for Figure 5A A cross-sectional view of the UV line along the center. Figure 7 for Figure 5A or Figure 5B A plan view of the first plate of the storage capacitor. Figure 8 for Figure 5A or Figure 5B A plan view of the second plate of the storage capacitor. Figure 9 This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0121] like Figures 2 to 6 As shown, the display panel includes a substrate BS and pixel units 100 located on the substrate BS. Figure 2 As shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. Figure 5A , Figure 5B and Figure 9 As shown, the light-emitting element 100b includes a light-emitting region LMR.

[0122] like Figure 5A and Figure 5B As shown, the pixel circuit 100a includes a storage capacitor Cst. (As...) Figures 5A to 8 As shown, the storage capacitor Cst includes a first plate Ca and a second plate Cb. Figure 6 As shown, the first electrode Ca is closer to the substrate BS than the second electrode Cb. Figure 6 and Figure 8 As shown, the second electrode Cb of the storage capacitor Cst includes a body portion Bd and a first opening OPN1 in the body portion Bd. For example, the orthographic projection of the first opening OPN1 on the substrate BS at least partially overlaps with the orthographic projection of the first electrode Ca on the substrate BS. The embodiments of this disclosure are illustrated by taking as an example where the orthographic projection of the first opening OPN1 on the substrate BS completely falls within the orthographic projection of the first electrode Ca on the substrate BS.

[0123] For example, such as Figure 5A As shown, the area opposite the storage capacitor Cst is the difference between the area of ​​the first plate Ca and the area of ​​the first opening OPN1. In some embodiments, the second plates Cb in a row of pixel units are electrically connected to each other. In this case, the second plates Cb can be divided according to the pixel units. For example, Figure 8 The second electrode Cb of two pixel units is shown. For example, in some embodiments, the second electrode Cb of different pixel units have the same shape and size.

[0124] like Figure 6As shown, an insulating layer 402 is provided between the first electrode Ca and the second electrode Cb, with the first electrode Ca located on the insulating layer 401. The insulating layer 402 is the dielectric layer of the storage capacitor Cst.

[0125] Figure 5A and Figure 5B The first direction X and the second direction Y are shown. Figure 6 The third direction Z is shown. For example, in embodiments of this disclosure, the first direction X and the second direction Y are parallel to the main surface of the substrate, and the third direction Z is perpendicular to the main surface of the substrate. The main surface of the substrate is the surface on which various components are fabricated. Figure 6 The upper surface of the substrate is its main surface. For example, the first direction X and the second direction Y intersect. Further, for example, the first direction X is perpendicular to the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0126] like Figure 5A and Figure 9 As shown, pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. For example, the first pixel unit 101 and the second pixel unit 102 emit different colors.

[0127] like Figure 5A and Figure 9 As shown, the orthographic projection of the light-emitting region LMR of the first pixel unit 101 onto the substrate BS overlaps with the orthographic projection of at least one of the storage capacitor Cst of the first pixel unit 101 or the storage capacitor Cst of the second pixel unit 102 onto the substrate BS.

[0128] For example, such as Figure 5A As shown, the area directly opposite the storage capacitor Cst of the first pixel unit 101 and the area directly opposite the storage capacitor Cst of the second pixel unit 102 are not equal. For example, as... Figure 5A As shown, the area directly opposite the storage capacitor Cst of the first pixel unit 101 is smaller than the area directly opposite the storage capacitor Cst of the second pixel unit 102. For example, as Figure 5A As shown, the storage capacitance Cst of the first pixel unit 101 is smaller than the storage capacitance Cst of the second pixel unit 102.

[0129] The display panel provided in the embodiments of this disclosure has an unequal area between the storage capacitor Cst of the first pixel unit 101 and the storage capacitor Cst of the second pixel unit 102, which reduces the overlap area between the light-emitting area of ​​the first pixel unit 101 and the storage capacitor Cst. This reduces the difference in electrical environment between the light-emitting area of ​​the first pixel unit 101 and the light-emitting areas of other pixel units, improves the consistency of the electrical environment of the light-emitting areas of different pixel units, enhances display uniformity, and improves display quality.

[0130] For example, the first pixel unit 101 is a green pixel unit. The green pixel unit has a higher turn-off voltage. By reducing the storage capacitor, the green pixel unit can be charged faster, which reduces its data voltage (Vdata), making it easier to turn off, reducing the risk of crosstalk, and improving the low grayscale display effect.

[0131] For example, such as Figure 5A As shown, the area of ​​the storage capacitor Cst of the first pixel unit 101 is smaller than the area of ​​the storage capacitor Cst of the second pixel unit 102.

[0132] Figure 5A and Figure 5B Data line DT is also shown. Data line DT is configured to provide data signals to pixel circuit 100a. Data line DT, first electrode Ca, and second electrode Cb are located on three different layers.

[0133] For example, such as Figure 7 As shown, the first electrode plate Ca of pixel unit 100 includes a first edge e1, which includes an arcuate portion. The first edge e1 can be referred to as the first arcuate edge e1. Figure 7 As shown, the first electrode Ca also includes a second edge e2, a third edge e3, and a fourth edge e4. (As...) Figure 7 As shown, for the first electrode plate Ca, the first arcuate edge e1 and the second edge e2 are arranged opposite to each other, and the third edge e3 and the fourth edge e4 are arranged opposite to each other. For example, in an embodiment of this disclosure, a pixel unit 100 includes a pixel circuit, and the pixel circuit of a pixel unit 100 includes a first electrode plate Ca and a second electrode plate Cb. Figure 7 The first plate Ca of two pixel units 100 is shown.

[0134] Figure 11A This is a comparative schematic diagram of a first pixel unit and a first electrode plate in a second pixel unit of a display panel provided in an embodiment of the present disclosure. Figure 11B for Figure 11A A comparative schematic diagram of the first edge of the first electrode plate in the diagram. Figure 11A In the diagram, the dashed line represents the first electrode plate Ca of the first pixel unit, and the solid line represents the first electrode plate Ca of the second pixel unit. Figure 11B In the diagram, the dashed line represents the first arcuate edge e1 of the first electrode plate Ca of the first pixel unit 101, and the solid line represents the first arcuate edge e1 of the first electrode plate Ca of the second pixel unit 102. For example... Figure 11A and Figure 11B As shown, the average curvature of the first arcuate edge e1 of the first pixel unit 101 is greater than the average curvature of the first arcuate edge e1 of the second pixel unit 102. For curvature comparison, the first electrode plate Ca of the first pixel unit and the first electrode plate Ca of the second pixel unit are arranged overlappingly. However, in the display panel, the orthographic projection of the first electrode plate Ca of the first pixel unit onto the substrate and the orthographic projection of the first electrode plate Ca of the second pixel unit onto the substrate do not overlap. For example, the first electrode plate Ca of the first pixel unit and the first electrode plate Ca of the second pixel unit are arranged side-by-side in a plane parallel to the main surface of the substrate.

[0135] For example, such as Figure 11A and Figure 11B As shown, the curvature of the first arcuate edge e1 of the first pixel unit 101 is greater than that of the first arcuate edge e1 of the second pixel unit 102. For example, as Figure 11A and Figure 11B As shown, the average radius of curvature of the first arcuate edge e1 of the first pixel unit 101 is smaller than the average radius of curvature of the first arcuate edge e1 of the second pixel unit 102. For example, the reciprocal of curvature is the radius of curvature. The smaller the radius of curvature, the greater the curvature. The greater the curvature of the arc, the smaller the radius of curvature. For the first arcuate edge e1 of the first pixel unit 101 and the first arcuate edge e1 of the second pixel unit 102, when the first arcuate edge e1 is a segment of the same circle, the radius of curvature of this segment of the arc is a constant value. In this case, the radius of curvature of the first arcuate edge e1 of the first pixel unit 101 is smaller than the radius of curvature of the first arcuate edge e1 of the second pixel unit 102. When the first arc edge e1 is not a circular arc as a whole, different positions may have different radii of curvature. Thus, the first arc edge e1 has an average radius of curvature, the maximum radius of curvature is the arc segment with the least curvature of the first arc edge e1, and the minimum radius of curvature is the arc segment with the greatest curvature of the first arc edge e1. For example, the average radius of curvature can be the average of the radii of curvature of each arc segment of the first arc edge e1.

[0136] For example, such as Figure 11A and Figure 11B As shown, the maximum radius of curvature of the first arc-shaped edge e1 of the first pixel unit 101 is smaller than the maximum radius of curvature of the first arc-shaped edge e1 of the second pixel unit 102.

[0137] For example, such as Figure 11A and Figure 11B As shown, the maximum curvature of the first arcuate edge e1 of the first pixel unit 101 is less than the maximum curvature of the first arcuate edge e1 of the second pixel unit 102. For example, Figure 11A and Figure 11B The first arc-shaped edge e1 can be a part of a circle or a part of an ellipse, but is not limited to these. For example, the location of the maximum curvature of the first arc-shaped edge e1 is the connection point between the first arc-shaped edge e1 and the third edge e3, or the connection point between the first arc-shaped edge e1 and the fourth edge e4, but is not limited to these.

[0138] For example, such as Figure 11A and Figure 11B As shown, the curvature at the midpoint of the first arcuate edge e1 of the first pixel unit 101 is greater than the curvature at the midpoint of the first arcuate edge e1 of the second pixel unit 102. For example, as... Figure 11A and Figure 11B As shown, the midpoint of the first arc-shaped edge e1 is the highest point of the first arc-shaped edge e1.

[0139] For example, such as Figure 5A As shown, the maximum curvature of the first arc-shaped edge e1 of the first pixel unit 101 is less than the maximum curvature of the first opening OPN1 of the first pixel unit e1, and the maximum curvature of the first arc-shaped edge e1 of the second pixel unit 102 is less than the maximum curvature of the first opening OPN1 of the second pixel unit 102.

[0140] For example, in the embodiments of this disclosure, the shape of the first opening OPN1 can be set as needed. The embodiments of this disclosure are illustrated using a circular hole as an example. For example, the location of the maximum curvature of the arc can be the curvature at the midpoint of the arc.

[0141] In some embodiments of the present disclosure, the curvature of the first arc-shaped edge e1 of the first electrode plate Ca is adjusted so that the average curvature of the first arc-shaped edge e1 of the first pixel unit 101 is greater than the average curvature of the first arc-shaped edge e1 of the second pixel unit 102, thereby reducing the overlap area between the light-emitting area of ​​the pixel unit and the storage capacitor Cst.

[0142] Mean curvature is defined as the average degree of curvature of a curve. For example... Figure 11A and Figure 11B As shown, the arc length of the first arc-shaped edge e1 of the first electrode plate Ca of the first pixel unit 101 is S1, and the arc length of the first arc-shaped edge e1 of the first electrode plate Ca of the second pixel unit 102 is S2. Then, the average curvature is the ratio of the angle of change of the upper tangent of the arc length to the arc length.

[0143] For example, for the first pixel unit 101, the average curvature K(G) of the first arcuate edge e1 is Δα / S1, and for the second pixel unit 102, the average curvature K(R) of the first arcuate edge e1 is Δβ / S2. Figure 11B As shown, when the chord length ODS corresponding to the arc length of the first arc edge e1 is fixed, the greater the height H, the greater the average curvature K; when the height H is fixed, the greater the chord length ODS, the smaller the average curvature K. Figure 11A The height H1 and chord length ODS01 of the first arcuate edge e1 of the first electrode Ca of the first pixel unit 101 are shown. Figure 11A The height H2 and chord length ODS02 of the first arcuate edge e1 of the first electrode Ca of the first pixel unit 101 are shown.

[0144] like Figure 9 As shown, the display panel also includes a third pixel unit 103 and a fourth pixel unit 104. The third pixel unit 103 and the fourth pixel unit 104 emit different colors. The first pixel unit 101 and the fourth pixel unit 104 can emit the same color, or they can be different colors.

[0145] For example, the first pixel unit 101 and the fourth pixel unit 104 can both be green pixel units. One of the third pixel unit 103 and the fourth pixel unit 104 can be a red pixel unit, and the other of the third pixel unit 103 and the fourth pixel unit 104 can be a blue pixel unit. The embodiments of this disclosure are illustrated using the example of the first pixel unit 101 being a green pixel unit, the second pixel unit 102 being a red pixel unit, the third pixel unit 103 being a blue pixel unit, and the fourth pixel unit 104 being a green pixel unit. Of course, the emission colors of the first pixel unit 101, the second pixel unit 102, the third pixel unit 103, and the fourth pixel unit 104 can be determined as needed and are not limited to the cases given in the above examples.

[0146] Figure 11A and Figure 11B The first electrode plate Ca of the first pixel unit 101 can also be replaced with the first electrode plate Ca of the fourth pixel unit 104. In this case... Figure 11A and Figure 11B The first electrode Ca of the second pixel unit 102 is replaced by the first electrode Ca of the third pixel unit 103. That is, the average curvature of the first arc-shaped edge e1 of the fourth pixel unit 104 is greater than the average curvature of the first arc-shaped edge e1 of the third pixel unit 103.

[0147] For example, in some embodiments, the shape and size of the first electrode plate Ca of the first pixel unit 101 are the same as the shape and size of the first electrode plate Ca of the fourth pixel unit 104, and the shape and size of the first electrode plate Ca of the second pixel unit 102 are the same as the shape and size of the first electrode plate Ca of the third pixel unit 103, but not limited thereto.

[0148] For example, in some embodiments, the shape and size of the second electrode plate Cb of the first pixel unit 101 are the same as the shape and size of the second electrode plate Cb of the fourth pixel unit 104, and the shape and size of the second electrode plate Cb of the second pixel unit 102 are the same as the shape and size of the second electrode plate Cb of the third pixel unit 103, but not limited thereto.

[0149] For example, in some embodiments, the average curvature of the first arcuate edge e1 of the first electrode plate Ca of the green pixel unit is greater than the average curvature of the first arcuate edge e1 of the first electrode plate Ca of the red pixel unit, and is also greater than the average curvature of the first arcuate edge e1 of the first electrode plate Ca of the blue pixel unit. For example, in some embodiments, the average curvature of the first arcuate edge e1 of the first electrode plate Ca of the red pixel unit is equal to the average curvature of the first arcuate edge e1 of the first electrode plate Ca of the blue pixel unit.

[0150] Of course, the embodiments of this disclosure are not limited to increasing the average curvature of the first arc-shaped edge e1 of the first electrode plate Ca of the green pixel unit. When the first arc-shaped edge e1 of the first electrode plate Ca of the red or blue pixel unit overlaps with the light-emitting area of ​​the light-emitting unit, the average curvature of the first arc-shaped edge e1 of the first electrode plate Ca of at least one of the red or blue pixel units is increased accordingly.

[0151] Of course, in the embodiments of this disclosure, the average curvature of the first arc-shaped edge e1 of the first electrode plate Ca of each pixel unit may be the same, and the storage capacitor may be adjusted in other ways to reduce the overlap area between the storage capacitor and the light-emitting area of ​​the light-emitting element.

[0152] The display panel provided in the embodiments of this disclosure can reduce the overlap area between the storage capacitor and the light-emitting area of ​​the light-emitting element by reducing the area of ​​the first plate of the storage capacitor of the first pixel unit or the fourth pixel unit.

[0153] For example, such as Figure 5A and Figure 7 As shown, the first electrode plate Ca of the first pixel unit 101 and the first electrode plate Ca of the second pixel unit 102 are arranged in the first direction X. The maximum size of the first electrode plate Ca of the first pixel unit 101 in the second direction Y is smaller than the maximum size of the first electrode plate Ca of the second pixel unit 102 in the second direction Y. The first direction X intersects with the second direction Y.

[0154] For example, such as Figure 5A and Figure 7 As shown, the area of ​​the first electrode plate Ca of the first pixel unit 101 is smaller than the area of ​​the first electrode plate Ca of the second pixel unit 102.

[0155] In some embodiments, the area of ​​the storage capacitor can be different by adjusting the size of the first opening OPN1. For example, the area of ​​the first opening OPN1 of the first pixel unit 101 is larger than the area of ​​the first opening OPN1 of the second pixel unit 102.

[0156] like Figure 5B As shown, the first electrode plate Ca of the fourth pixel unit 104 and the first electrode plate Ca of the third pixel unit 103 are arranged in the first direction X. The maximum size of the first electrode plate Ca of the fourth pixel unit 104 in the second direction Y is smaller than the maximum size of the first electrode plate Ca of the third pixel unit 103 in the second direction Y.

[0157] For example, such as Figure 5B and Figure 7 As shown, the area of ​​the first plate Ca of the fourth pixel unit 104 is smaller than the area of ​​the first plate Ca of the third pixel unit 103.

[0158] For example, in some embodiments, the area of ​​the first opening OPN1 of the fourth pixel unit 104 is larger than the area of ​​the first opening OPN1 of the third pixel unit 103.

[0159] For example, such as Figure 9 As shown, the orthographic projection of the light-emitting element 100b of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor of the first pixel unit 101 onto the substrate BS. For example, as... Figure 9 As shown, the orthographic projection of the light-emitting element 100b of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor of the fourth pixel unit 104 onto the substrate BS.

[0160] Figure 9 The storage capacitor Csta of the first pixel unit 101, the storage capacitor Cstb of the second pixel unit 102, the storage capacitor Cstc of the third pixel unit 103, and the storage capacitor Cstd of the fourth pixel unit 104 are shown.

[0161] For example, such as Figure 9 As shown, the orthographic projection of the storage capacitor Cst of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the light-emitting region LMR of the second pixel unit 102 onto the substrate BS.

[0162] like Figure 5B and Figure 9As shown, the orthographic projection of the light-emitting region LMR of the fourth pixel unit 104 onto the substrate BS overlaps with the orthographic projection of at least one of the storage capacitor Cstd of the fourth pixel unit 104 or the storage capacitor Cstc of the third pixel unit 103 onto the substrate BS.

[0163] like Figure 5B As shown, the area facing the storage capacitor Cstd of the fourth pixel unit 104 is not equal to the area facing the storage capacitor Cstc of the third pixel unit 103. Figure 5B As shown, the area of ​​the storage capacitor Cstd of the fourth pixel unit 104 is smaller than the area of ​​the storage capacitor Cstc of the third pixel unit 103.

[0164] The display panel provided in the embodiments of this disclosure has an area opposite to the storage capacitor Cstd of the fourth pixel unit 104 and an area opposite to the storage capacitor Cstc of the third pixel unit 103 that is not equal. This reduces the overlap area between the light-emitting area of ​​the fourth pixel unit 104 and the storage capacitor Cstd, thereby reducing the difference in electrical environment between the light-emitting area of ​​the fourth pixel unit 104 and the light-emitting areas of other pixel units. This improves the consistency of the electrical environment of the light-emitting areas of different pixel units, enhances display uniformity, and improves display quality.

[0165] like Figure 9 As shown, the orthographic projection of the light-emitting region LMR of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor Cstb onto the substrate BS, and the orthographic projection of the light-emitting region LMR of the third pixel unit 103 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor Cstc onto the substrate BS.

[0166] For example, such as Figure 9 As shown, the first electrode plate Ca of the third pixel unit 103, the first electrode plate Ca of the first pixel unit 101, and the first electrode plate Ca of the second pixel unit 102 are arranged in the first direction X.

[0167] For example, such as Figure 5A and Figure 5B As shown, the first plate Ca of pixel unit 100 includes a first arc-shaped edge e1. The average curvature of the first arc-shaped edge e1 of the first pixel unit 101 is greater than the average curvature of the first arc-shaped edge e1 of the second pixel unit 102, and is also greater than the average curvature of the first arc-shaped edge e1 of the third pixel unit 103.

[0168] For example, such as Figure 5A and Figure 5BAs shown, the maximum size of the first electrode plate Ca of the first pixel unit 101 in the second direction Y is smaller than the maximum size of the first electrode plate Ca of the second pixel unit 102 in the second direction Y, and smaller than the maximum size of the first electrode plate Ca of the third pixel unit 103 in the second direction Y.

[0169] For example, such as Figure 5A and Figure 5B As shown, the area of ​​the first opening OPN1 of the first pixel unit 101 is larger than the area of ​​the first opening OPN1 of the second pixel unit 102, and is also larger than the area of ​​the first opening OPN1 of the third pixel unit 103.

[0170] For example, such as Figure 5A , Figure 5B and Figure 9 As shown, the orthographic projection of the light-emitting region LMR of the third pixel unit 103 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor Csta of the first pixel unit 101 onto the substrate BS, and also does not overlap with the orthographic projection of the storage capacitor Cstb of the second pixel unit 102 onto the substrate BS; the orthographic projection of the light-emitting element 100b of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor of the first pixel unit 101 onto the substrate BS, and also does not overlap with the orthographic projection of the storage capacitor of the third pixel unit 103 onto the substrate BS.

[0171] For example, such as Figure 5A , Figure 5B and Figure 9 As shown, the orthographic projection of the light-emitting region LMR of the second pixel unit 102 onto the substrate BS does not overlap with the orthographic projection of the storage capacitor Cst of the first pixel unit 101 onto the substrate BS, and also does not overlap with the orthographic projection of the storage capacitor Cst of the third pixel unit 103 onto the substrate BS.

[0172] In the display panel provided in the embodiments of this disclosure, when adjusting the storage capacitor, at least one of the following can be adjusted: the area of ​​the first electrode plate Ca, the average curvature of the first arcuate edge e1 of the first electrode plate Ca, and the area of ​​the first opening OPN1.

[0173] For example, compared to a display panel where all pixel units have the same storage capacitance, some embodiments of this disclosure provide a display panel that meets at least one of the following conditions: (1) The average curvature of the first arcuate edge e1 of the first electrode plate Ca of the first pixel unit 101 increases. (2) The area B1 of the first electrode plate Ca of the first pixel unit 101 decreases. (3) The area of ​​the first opening OPN1 of the first pixel unit 101 increases.

[0174] Figure 10This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 10 As shown, in some embodiments, compared with a display panel where the storage capacitance of each pixel unit is the same, the average curvature of the first arcuate edge e1 of the first electrode plate B1 of the first pixel unit 101 of the display panel provided in some embodiments of this disclosure is increased, while the rest remains unchanged.

[0175] For example, in some embodiments, compared to a display panel where all pixel units have the same storage capacitance, the area B1 of the first electrode plate Ca of the first pixel unit 101 of the display panel provided in some embodiments of this disclosure is smaller, while the rest remains unchanged.

[0176] For example, in some embodiments, compared to a display panel where all pixel units have the same storage capacitance, the area H1 of the first opening OPN1 of the first pixel unit 101 of the display panel provided in some embodiments of this disclosure is larger, while the rest remains unchanged.

[0177] For example, in some embodiments, compared to a display panel where all pixel units have the same storage capacitance, the average curvature of the first arcuate edge e1 of the first electrode plate B1 of the first pixel unit 101 of the display panel provided in some embodiments of this disclosure is increased, the area B1 of the first electrode plate Ca of the first pixel unit 101 is decreased, and the area H1 of the first opening OPN1 of the first pixel unit 101 is increased, while the area A1 of the second electrode plate Cb of the first pixel unit 101 remains unchanged, and the storage capacitance of the second pixel unit 102 remains unchanged.

[0178] In some embodiments of this disclosure, the storage capacitor of the third pixel unit 103 remains unchanged, and the change in the storage capacitor of the fourth pixel unit 104 can be referred to the change in the storage capacitor of the first pixel unit 101.

[0179] For example, in some embodiments, such as Figure 5A As shown, taking the first pixel unit 101 and the second pixel unit 102 as examples, the storage capacitor of the pixel circuit of the first pixel unit 101 is C1, the area of ​​the first plate Ca is A1, the area of ​​the first opening OPN1 is H1, and the area of ​​the second plate Cb is B1; the storage capacitor of the pixel circuit of the second pixel unit 102 is C2, the area of ​​the first plate Ca is A2, the area of ​​the first opening OPN1 is H2, and the area of ​​the second plate Cb is B2; according to the capacitance formula: C=εS / 4πkd, C1=εS1 / 4πkd1=ε(B1-H1) / 4πkd1, C2=εS2 / d2=ε(B2-H2) / 4πkd2, d1 is the vertical distance between the first plate Ca and the second plate Cb of the first pixel unit 101, and d2 is the vertical distance between the first plate Ca and the second plate Cb of the second pixel unit 102.

[0180] For example, multiple pixel units 100 are provided, and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a include n rows and m columns in total. The ratio of at least one pixel circuit in the i-th row and j-th column (which is a set) to at least one pixel circuit in the (i + x)-th row and (j + 2y + 1)-th column (which is a set) is K, and it satisfies the following formula:

[0181]

[0182] Where n is an integer greater than or equal to 2; m is an integer greater than or equal to 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; B represents the area of the first electrode plate Ca of the storage capacitor Cst; H represents the area of the first opening OPN1 in the second electrode plate Cb of the storage capacitor Cst; d represents the vertical distance between the first electrode plate Ca and the second electrode plate Cb of the storage capacitor Cst; 0 < K < 1. For example, 0.3 ≤ K ≤ 0.8. Further for example, K satisfies one of the following: 0.6 ≤ K ≤ 0.9, 0.5 ≤ K ≤ 0.7, 0.1 ≤ K ≤ 0.7.

[0183] For example, in Formula 1, d(i + x)(j + 2y + 1) represents the vertical distance between the first electrode plate Ca and the second electrode plate Cb of the storage capacitor Cst of the pixel circuit in the (i + x)-th row and (j + 2y + 1)-th column. For example, B(i + x)(j + 2y + 1) represents the area of the first electrode plate Ca of the storage capacitor Cst of the pixel circuit in the (i + x)-th row and (j + 2y + 1)-th column. H(i + x)(j + 2y + 1) represents the area of the first opening OPN1 in the second electrode plate Cb of the storage capacitor Cst of the pixel circuit in the (i + x)-th row and (j + 2y + 1)-th column.

[0184] For example, the applicable conditions of Formula 1 include: the outer contour of the second electrode plate Cb covers the outer contour of the first electrode plate Ca.

[0185] For example, Formula 1 is not limited to the case where the facing area of the storage capacitor of the pixel circuit of the green pixel unit becomes smaller, and it can also include the case where the facing area of the storage capacitor of the pixel circuit of at least one of the red pixel unit and the blue pixel unit becomes smaller; that is, as long as the storage capacitor of one of the red pixel unit, the green pixel unit, and the blue pixel unit becomes smaller, it is covered within the scope of this formula; that is, one of the pixel circuits of the first pixel unit and the fourth pixel unit can also be the pixel circuit of the red pixel unit, and the other of the pixel circuits of the first pixel unit and the fourth pixel unit can be the pixel circuit of the blue pixel unit.

[0186] Similarly, the curvature described earlier is not limited to the case where the first pixel unit is a green pixel unit. The first pixel unit can also be a pixel unit of any color other than green.

[0187] Table 1. GGRB Pixel Circuit Layout

[0188]

[0189]

[0190] Based on the pixel arrangement in Table 1, we can determine the storage capacitance of the pixel circuits in the i-th row and j-th column and the pixel circuits of each adjacent pixel unit. If K satisfies the above formula, we can reduce the overlap area between the light-emitting area of ​​the light-emitting element of the first or fourth pixel unit and the pixel circuit, thereby improving the display quality.

[0191] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a comprise n rows and m columns, and at least one of the multiple pixel circuits 100a satisfies the following formula:

[0192]

[0193] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; B represents the area of ​​the first plate Ca of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst.

[0194] For example, in Formula 2, Bij represents the area of ​​the first plate Ca of the storage capacitor Cst in the i-th row and j-th column of the pixel circuit, Aij represents the area of ​​the second plate Cb of the storage capacitor Cst in the i-th row and j-th column of the pixel circuit, Hij represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst in the i-th row and j-th column of the pixel circuit, B(i+x)(j+2y+1) represents the area of ​​the first plate Ca of the storage capacitor Cst in the (i+x)-th row and (j+2y+1)-th column of the pixel circuit, A(i+x)(j+2y+1) represents the area of ​​the second plate Cb of the storage capacitor Cst in the (i+x)-th row and (j+2y+1)-th column of the pixel circuit, and H(i+x)(j+2y+1) represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst in the (i+x)-th row and (j+2y+1)-th column of the pixel circuit.

[0195] For example, the applicable conditions of Formula 2 include: 1) the outer contour of the second electrode Cb covers the outer contour of the first electrode Ca; 2) the outer contour of the second electrode of the storage capacitor of all pixel circuits remains unchanged, but the area of ​​the first opening OPN1 of the first pixel unit 101 increases or the area B1 of the first electrode Ca of the first pixel unit 101 decreases; 3) the area of ​​the first opening OPN1 of the first pixel unit 101 increases and the area B1 of the first electrode Ca of the first pixel unit 101 decreases.

[0196] Formula 2 compares the ratio of the area of ​​the storage capacitor Cst of different pixel units to the sum of the area of ​​the second plate and the area of ​​the first opening. When Formula 2 is satisfied, the overlap area between the light-emitting area of ​​the light-emitting element of the first or fourth pixel unit and the pixel circuit can be reduced, improving display quality. For example, in Formula 2, the first and fourth pixel units are green pixel units, one of the second and third pixel units is a red pixel unit, and the other of the second and third pixel units is a blue pixel unit. However, this is not the only possibility. Formula 2 can also be applied to cases where one of the first and fourth pixel units is a red pixel unit, and the other of the first and fourth pixel units is a blue pixel unit.

[0197] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a comprise n rows and m columns. The pixel unit 100 in the i-th row and j-th column is the pixel circuit of the first pixel unit 101, and the pixel circuit of the second pixel unit 102 or the third pixel unit 103 is the pixel circuit of the (i+x)-th row and (j+2y+1)-th column. The pixel circuit of the first pixel unit 101 satisfies the following formula:

[0198]

[0199] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; B represents the area of ​​the first plate Ca of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst.

[0200] For example, in some embodiments,

[0201] For example, the meanings of Bij, Aij, and Hij in Formula 3 can be found in the description in Formula 2, and will not be repeated here.

[0202] Formula 3 represents the condition that the ratio of the area of ​​the storage capacitor Cst of the first pixel unit to the sum of the area of ​​the second plate and the area of ​​the first opening must meet. When Formula 3 is met, the overlap area between the light-emitting area of ​​the light-emitting element of the first pixel unit and the pixel circuit can be reduced, thereby improving the display quality.

[0203] For example, in some embodiments,

[0204] For example, at least one of the pixel circuits of the second pixel unit 102 or the pixel circuit of the third pixel unit 103 satisfies the following formula:

[0205]

[0206] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; B represents the area of ​​the first plate Ca of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst. For example, in some embodiments, at least one of the pixel circuits of the second pixel unit 102 or the pixel circuit of the third pixel unit 103 satisfies

[0207] For example, the meanings of B(i+x)(j+2y+1), A(i+x)(j+2y+1), and H(i+x)(j+2y+1) in Formula 4 can be referred to the description in Formula 2, and will not be repeated here. Formula 4 represents the condition that the ratio of the area of ​​the storage capacitor Cst of the second pixel unit 102 or the third pixel unit 103 facing each other to the sum of the area of ​​the second electrode plate and the area of ​​the first opening must satisfy. When Formula 4 is satisfied, the driving capability of at least one of the pixel circuits in the second pixel unit 102 or the third pixel unit 103 can be improved, thereby improving the display quality.

[0208] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a comprise n rows and m columns. The pixel circuit in the i-th row and j-th column is the pixel circuit of the first pixel unit 101, and the pixel circuit in the (i+x)-th row and (j+2y+1)-th column is the pixel circuit of the second pixel unit 102 or the pixel circuit of the third pixel unit 103; satisfying the following formula:

[0209] Hij×B(i+x)(j+2y+1)-H(i+x)(j+2y+1)×Bij>0 (Formula 5) where n is an integer ≥2; m is an integer ≥2; i is a natural number satisfying 1≤i≤n; j is a natural number satisfying 1≤j≤m; and i+x≤n; j+2y+1≤m; x is an integer satisfying 0≤x≤n; y is an integer satisfying 0≤y≤m; B represents the area of ​​the first plate Ca of the storage capacitor Cst, and H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst.

[0210] Formula 5 above indicates that the ratio of the area of ​​the first opening of the first pixel unit 101 to the area of ​​the first electrode plate is greater than the ratio of the area of ​​the first opening of the second pixel unit 102 or the third pixel unit 103 to the area of ​​the first electrode plate. When Formula 5 is satisfied, the storage capacitance of the first pixel unit 101 can be made smaller than the storage capacitance of the second pixel unit 102 or the third pixel unit 103.

[0211] For example, the applicable conditions for Formula 5 include: the outer contour of the second plate Cb covers the outer contour of the first plate Ca.

[0212] For example, the meanings of Hij, B(i+x)(j+2y+1), H(i+x)(j+2y+1), and Bij in Formula 5 above can be referred to the description in Formula 2, and will not be repeated here.

[0213] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a comprise n rows and m columns. The pixel circuit in the i-th row and j-th column is the pixel circuit of the first pixel unit 101, and the pixel circuit in the (i+x)-th row and (j+2y+1)-th column is the pixel circuit of the second pixel unit 102 or the pixel circuit of the third pixel unit 103; satisfying the following formula:

[0214]

[0215] Where n is an integer ≥ 2; m is an integer ≥ 2; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n, j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst.

[0216] Formula 6 above indicates that the ratio of the area of ​​the first opening of the first pixel unit 101 to the sum of the areas of the first opening and the second electrode plate is greater than the ratio of the area of ​​the first opening of the second pixel unit 102 or the third pixel unit 103 to the sum of the areas of the first opening and the second electrode plate. When Formula 6 is satisfied, the storage capacitance of the first pixel unit 101 can be made smaller than the storage capacitance of the second pixel unit 102 or the third pixel unit 103.

[0217] For example, the meanings of Hij, Aij, H(i+x)(j+2y+1), Bij, and A(i+x)(j+2y+1) in Formula 6 above can be referred to the description in Formula 2, and will not be repeated here.

[0218] For example, the first electrode plate Ca of the first pixel unit 101 and the first electrode plate Ca of the second pixel unit 102 are arranged in the first direction X; the maximum size of the first electrode plate Ca of the first pixel unit 101 in the first direction X is smaller than the maximum size of the first electrode plate Ca of the second pixel unit 102 in the first direction X. In the display panel provided in some embodiments of this disclosure, the storage capacitance of the first pixel unit 101 is reduced by reducing the size of the first electrode plate Ca of the first pixel unit 101 in the first direction X.

[0219] Figure 12 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 12 As shown, the first electrode plate Ca includes a second edge e2 opposite to the first arcuate edge e1. The first electrode plate Ca of the first pixel unit 101 and the first electrode plate Ca of the second pixel unit 102 are arranged in the first direction X. Along the second direction Y, the minimum distance from the first opening OPN1 of the first pixel unit 101 to the second edge e2 of the first electrode plate Ca is D1, and the minimum distance from the first opening OPN1 of the second pixel unit 102 to the second edge e2 of the first electrode plate Ca is D2. D1 is less than D2, which helps to reduce the storage capacitance of the first pixel unit 101. For example, For example, For example, For example, the smaller the ratio of D1 to D2, the greater the difference in storage capacitance between the first pixel unit 101 and the second pixel unit 102.

[0220] For example, such as Figure 8 and Figure 12As shown, the second electrode Cb includes a first edge e11 and a second edge e22 disposed opposite to each other. The first arcuate edge e1 of the first electrode Ca and the first edge e11 of the second electrode Cb are located on the same side of the first opening OPN1, and the second edge e2 of the first electrode Ca and the second edge e22 of the second electrode Cb are located on the same side of the first opening OPN1; in the first pixel unit 101, as Figure 12 As shown, the shortest distance between the second edge e2 of the first electrode plate Ca and the second edge e22 of the second electrode plate Cb is E1; in the second pixel unit 102, the shortest distance between the second edge e2 of the first electrode plate Ca and the second edge e22 of the second electrode plate Cb is E2; E1 is greater than E2, which helps to reduce the storage capacitance of the first pixel unit 101 and the overlapping area of ​​the light-emitting area of ​​the light-emitting element and the storage capacitance.

[0221] For example, in some embodiments, Furthermore, for example, in some embodiments,

[0222] For example, in some embodiments,

[0223] Figure 13 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 7 , Figure 8 and Figure 13 As shown, the first electrode Ca includes a third edge e3 and a fourth edge e4, and the second electrode Cb includes a third edge e33 and a fourth edge e44. The third edge e3 of the first electrode Ca and the third edge e33 of the second electrode Cb are located on the same side of the first opening OPN1, and the fourth edge e4 of the first electrode Ca and the fourth edge e44 of the second electrode Cb are located on the same side of the first opening OPN1. Figure 13 As shown, in the first pixel unit 101, the distance between the third edge e3 of the first plate Ca and the third edge e33 of the second plate Cb is F1; in the second pixel unit 102, the distance between the third edge e3 of the first plate Ca and the third edge e33 of the second plate Cb is F2, and F1 is greater than F2. Figure 13 The display panel shown reduces the storage capacitance of the first pixel unit 101 by reducing the size of the first electrode Ca of the first pixel unit 101 in the first direction X. For example, the minimum value of F1 is 1.66 μm, and the minimum value of F2 is 0.

[0224] For example, such as Figure 13As shown, in the first pixel unit 101, the minimum distance between the first opening OPN1 and the third edge e33 of the second electrode Cb is G1; in the second pixel unit 102, the minimum distance between the first opening OPN1 and the third edge e33 of the second electrode Cb is G2; G1 is less than G2, that is, the size of the first opening OPN1 of the first pixel unit 101 is greater than the size of the first opening OPN1 of the second pixel unit 102. Figure 13 The display panel provided in the embodiment of this disclosure, as shown, reduces the storage capacitance by increasing the area of ​​the first opening OPN1 of the first pixel unit 101. For example,

[0225] For example, such as Figure 5A , Figure 5B , Figure 10 , Figure 12 and Figure 13 As shown, in the first pixel unit 101, the ratio of the maximum size of the first electrode plate Ca in the second direction Y to the maximum size of the second electrode plate Cb in the second direction Y is R11; in the second pixel unit 102, the ratio of the maximum size of the first electrode plate Ca in the second direction Y to the maximum size of the second electrode plate Cb in the second direction Y is R12; in the third pixel unit 103, the ratio of the maximum size of the first electrode plate Ca in the second direction Y to the maximum size of the second electrode plate Cb in the second direction Y is R13; R11 is less than R12 and R11 is less than R13, thereby reducing the storage capacitance of the first pixel unit 101 by reducing the maximum size of the first electrode plate Ca in the second direction Y of the first pixel unit 101.

[0226] For example, such as Figure 13 As shown, in the first pixel unit 101, the ratio of the maximum size of the first opening OPN1 in the second direction Y to the maximum size of the first electrode Ca in the second direction Y is R21; in the second pixel unit 102, the ratio of the maximum size of the first opening OPN1 in the second direction Y to the maximum size of the first electrode Ca in the second direction Y is R22; in the third pixel unit 103, the ratio of the maximum size of the first opening OPN1 in the second direction Y to the maximum size of the first electrode Ca in the second direction Y is R23; R21 is greater than R22 and R21 is greater than R23, thereby reducing the storage capacitance of the first pixel unit 101 by decreasing the maximum size of the first electrode Ca in the second direction Y or increasing the size of the first opening OPN1.

[0227] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a include n rows and m columns. At least one of the areas of the first electrode plate Ca of the first pixel unit 101 and the first electrode plate Ca of the second pixel unit 102, or the areas of the first electrode plate Ca of the first pixel unit 101 and the first electrode plate Ca of the third pixel unit 103, satisfies the following formula:

[0228]

[0229] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number that satisfies 1 ≤ i ≤ n; j is a natural number that satisfies 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer that satisfies 0 ≤ x ≤ n; y is an integer that satisfies 0 ≤ y ≤ m; B represents the area of ​​the first plate Ca of the storage capacitor Cst.

[0230] For example, in some embodiments, For example,

[0231] For example, in some embodiments, For example,

[0232] For example, the meanings of Bij and B(i+x)(j+2y+1) in Formula 7 above can be found in the description in Formula 2, and will not be repeated here.

[0233] Formula 7 represents the ratio of the area of ​​the first electrode plate Ca of the first pixel unit 101 to the area of ​​the first electrode plate Ca of the second pixel unit 102 or the third pixel unit 103. In a display panel that satisfies Formula 7, the storage capacitance of the first pixel unit 101 is less than the storage capacitance of the second pixel unit 102 or the third pixel unit 103.

[0234] For example, such as Figure 12 and Figure 13 As shown, in order to further reduce the overlap area between the light-emitting area and the storage capacitor, in a pixel unit 100, the maximum curvature of the first arc-shaped edge e1 of the first electrode plate Ca is greater than the maximum curvature of the first arc-shaped edge e11 of the second electrode plate Cb.

[0235] Figure 14 This is a schematic diagram of a pixel circuit. Figure 15 It is a layout diagram of a pixel circuit. Figure 16A It is a cross-sectional view of a display panel. Figure 16B yes Figure 15 A sectional view along line JK. The following is combined with... Figures 14 to 16B Please provide an explanation.

[0236] Figure 14 The pixel circuit of a pixel unit of the display panel is shown, such as Figure 14 As shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1, and a storage capacitor Cst. The six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 100b includes a first electrode 201, a second electrode 202, and a light-emitting functional layer 203 located between the first electrode 201 and the second electrode 202. For example, the light-emitting functional layer 203 includes a light-emitting layer. For example, the light-emitting functional layer 203 also includes at least one of an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer. For example, the first electrode 201 is an anode, and the second electrode 202 is a cathode. Typically, the threshold compensation transistor T3 and the first reset transistor T6 employ a dual-gate thin-film transistor (TFT) to reduce leakage current.

[0237] like Figure 14As shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light emission control signal line EML, an initialization signal line INT, and a reset control signal line RST. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light emission control signal line EML is configured to provide a light emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, the magnitude of which may be between the first voltage signal VDD and the second voltage signal VSS, but is not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 may both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are connected and both are configured to provide the initialization signal Vinit to the pixel unit 100. That is, the first initialization signal line INT1 and the second initialization signal line INT2 are both called initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both being Vinit.

[0238] like Figure 14 As shown, the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0239] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit 100a. For example, a pixel includes multiple pixel units. A pixel may include multiple pixel units that emit different colors of light. For example, a pixel may include pixel units that emit red light, pixel units that emit green light, and pixel units that emit blue light, but is not limited to these. The number of pixel units included in a pixel and the light emission characteristics of each pixel unit can be determined as needed.

[0240] For example, such as Figure 14 As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first terminal T21 of the data writing transistor T2 is connected to the data line DT, and the second terminal T22 of the data writing transistor T2 is connected to the first terminal T11 of the driving transistor T1.

[0241] For example, such as Figure 14 As shown, the pixel circuit 100a also includes a threshold compensation transistor T3. The gate T30 of the threshold compensation transistor T3 is connected to the gate line GT. The first terminal T31 of the threshold compensation transistor T3 is connected to the second terminal T12 of the driving transistor T1. The second terminal T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0242] For example, such as Figure 14 As shown, the display panel also includes a light emission control signal line EML, and the pixel circuit 100a also includes a first light emission control transistor T4 and a second light emission control transistor T5. The gate T40 of the first light emission control transistor T4 is connected to the light emission control signal line EML, the first electrode T41 of the first light emission control transistor T4 is connected to the first power supply line PL1, and the second electrode T42 of the first light emission control transistor T4 is connected to the first electrode T11 of the driving transistor T1. The gate T50 of the second light emission control transistor T5 is connected to the light emission control signal line EML, the first electrode T51 of the second light emission control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light emission control transistor T5 is connected to the first electrode 201 of the light-emitting element 100b.

[0243] like Figure 14As shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first electrode 201 of the light-emitting element 100b and is configured to reset the first electrode 201 of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first electrode 201 of the light-emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected so that they can be input with the same initialization signal, but this is not a limitation. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be isolated from each other and configured to input signals separately.

[0244] For example, such as Figure 14 As shown, the first terminal T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, and the second terminal T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1. The first terminal T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second terminal T72 of the second reset transistor T7 is connected to the first electrode 201 of the light-emitting element 100b. For example, as... Figure 14 As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0245] like Figure 14 As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, the first plate Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second plate Cb of the storage capacitor Cst is connected to the first power line PL1.

[0246] For example, such as Figure 14 As shown, the display panel also includes a second power line PL2, which is connected to the second electrode 201 of the light-emitting element 100b. Figure 14 The first node N1, the second node N2, the third node N3, and the fourth node N4 are shown.

[0247] Figure 16A Can be Figure 15 A sectional view along line J1-K1. (See attached image.) Figure 16A As shown, the display panel includes pixel circuitry 100a located on a substrate. Figure 16A The pixel circuit 100a is shown with the second terminal T52 of the second light-emitting control transistor T5 as an example, but the complete structure of the pixel circuit 100a is not shown. Figure 15 and Figure 16A As shown, the transition electrode 801 is connected to the pixel circuit 100a (the second electrode T52 of the second light-emitting control transistor T5) through a via VH2 penetrating the insulating layer 410 and the insulating layer 411. The first electrode 201 of the light-emitting element 100b is connected to the transition electrode 801 through a via VH1 penetrating the insulating layer 412.

[0248] like Figure 16A As shown, the display panel also includes a pixel defining layer PDL, which includes a second opening OPN2 that defines the light-emitting region LMR of the light-emitting element.

[0249] Figure 16B Can be Figure 15 A sectional view along line J2-K2. (See attached image.) Figure 16B As shown, the second plate Cb of the storage capacitor Cst has an opening OPN1. One end of the transition electrode 802 passes through the opening OPN1 and is connected to the gate T10 of the driving transistor T1 through the via VH3. The other end of the transition electrode 802 is connected to the second electrode T62 of the first reset transistor T6 (the second electrode of the threshold compensation transistor T3) through the via VH4. Figure 16B As shown, via VH3 penetrates insulating layers 423 and 422, and via VH4 penetrates insulating layers 423, 422, and 421. Insulating layer 424 is located on the adapter electrode 802.

[0250] like Figure 15 As shown, the active layer 140 includes a semiconductor layer of a transistor, a first electrode, and a second electrode. The first conductive layer LY1 includes the first electrode Ca of the storage capacitor Cst, a first reset control signal line RST1, a second reset control signal line RST2, a gate line GT, and a light emission control signal line EML. The second conductive layer LY2 includes the second electrode Cb of the storage capacitor Cst, a first initialization signal line INT1, and a second initialization signal line INT2. The third conductive layer LY3 includes a data line DT, a first power supply line PL1, and various transition electrodes. Figure 15 Transition electrode 801, transition electrode 802, and transition electrode 803 are shown.

[0251] Figure 15 Vias VH5 to VH9 are also shown. Each via penetrates at least one insulating layer to connect two conductive elements at the via location. Figure 15As shown, the data line DT is connected to the first terminal T21 of the data writing transistor T2 through via VH5, the first power line PL1 is connected to the second terminal Cb of the storage capacitor Cst through via VH6, the first power line PL1 is connected to the first terminal T41 of the first light-emitting control transistor T4 through via VH7, one end of the adapter electrode 803 is connected to the second initialization signal line INT2 through via VH8, and the other end of the adapter electrode 803 is connected to the first terminal T71 of the second reset transistor T7 through via VH9.

[0252] The embodiments of this disclosure use a 7T1C pixel circuit as an example for illustration, but the embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and the embodiments of this disclosure do not limit this. Of course, the display panel may also include a pixel circuit with fewer than 7 transistors.

[0253] Figure 17 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 17 As shown, the display panel also includes a light-emitting control signal line EML, which extends along a first direction X. A first electrode plate Ca includes a second edge e2 opposite to a first arcuate edge e1. The first electrode plate Ca and the light-emitting control signal line EML are arranged along a second direction Y. In the first pixel unit 101, the distance from the second edge e2 of the first electrode plate Ca to the light-emitting control signal line EML is Q1. In the second pixel unit 102, the distance from the second edge e2 of the first electrode plate Ca to the light-emitting control signal line EML is Q2. Q1 is greater than Q2. Therefore, by reducing the size of the first electrode plate Ca of the first pixel unit 101 in the second direction, the storage capacitance of the first pixel unit 101 is reduced, thereby reducing the overlap area between the light-emitting area of ​​the light-emitting element and the storage capacitance. For example, to improve display quality... For example,

[0254] Figure 18 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 15 and Figure 18 As shown, the display panel also includes a transition electrode 801, and the pixel circuit 100a is connected to the light-emitting element 100b through the transition electrode 801.

[0255] For example, in the first pixel unit 101, the shortest distance between the first electrode plate Ca and the transfer electrode 801 is P1; in the second pixel unit 102 or the third pixel unit 103, the shortest distance between the first electrode plate Ca and the transfer electrode 801 is P2; P1 is greater than P2, thus, by reducing the size of the first electrode plate Ca in the second direction Y of the first pixel unit 101, the storage capacitance of the first pixel unit 101 is reduced. For example, For example, For example,

[0256] For example, such as Figure 14 and Figure 15 As shown, the pixel circuit 100a also includes a driving transistor T1, the gate T10 of which is connected to the first plate Ca of the storage capacitor Cst. The first plate Ca of the storage capacitor Cst and the gate T10 of the driving transistor T1 are integrally formed, forming a single structure. Figure 15 As shown, the gate T10 of the driving transistor T1 is connected to the first reset transistor T6 through the transfer electrode 802.

[0257] Figure 19 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 19 As shown, in the first pixel unit 101, the ratio of the area of ​​the portion of the semiconductor layer T14 of the driving transistor T1 located in the first opening OPN1 to the sum of the areas of the second electrode Cb and the first opening OPN1 is R31; in the second pixel unit 102, the ratio of the area of ​​the portion of the semiconductor layer T14 of the driving transistor T1 located in the first opening OPN1 to the sum of the areas of the second electrode Cb and the first opening OPN1 is R32; in the third pixel unit 103, the ratio of the area of ​​the portion of the semiconductor layer of the driving transistor T1 located in the first opening OPN1 to the sum of the areas of the second electrode Cb and the first opening OPN1 is R33; R31 is greater than R32, and R31 is greater than R33.

[0258] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a include n rows and m columns. Let the pixel circuit in the i-th row and j-th column be the pixel circuit of the first pixel unit 101, let the pixel circuit in the i-th row and (j-1)-th column be the pixel circuit of the second pixel unit 102, and let the pixel circuit in the i-th row and (j+1)-th column be the pixel circuit of the third pixel unit 103, satisfying the following formula:

[0259]

[0260] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; B represents the area of ​​the first plate Ca of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst. Therefore, by reducing the size of the first plate Ca of the first pixel unit 101, the storage capacitance of the first pixel unit 101 is reduced.

[0261] For example, the meanings of Bij, Hij, and Aij in Formula 8 above can be found in the description in Formula 2, and will not be repeated here. For example, in Formula 8 above, Bi(j-1) represents the area of ​​the first plate Ca of the storage capacitor Cst in the i-th row and (j-1)-th column of the pixel circuit, Ai(j-1) represents the area of ​​the second plate Cb of the storage capacitor Cst in the i-th row and (j-1)-th column of the pixel circuit, Hi(j-1) represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst in the i-th row and (j-1)-th column of the pixel circuit, Bi(j+1) represents the area of ​​the first plate Ca of the storage capacitor Cst in the i-th row and (j+1)-th column of the pixel circuit, Ai(j+1) represents the area of ​​the second plate Cb of the storage capacitor Cst in the i-th row and (j+1)-th column of the pixel circuit, and Hi(j+1) represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst in the i-th row and (j+1)-th column of the pixel circuit.

[0262] Figure 20 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 20 As shown, the light-emitting element 100b includes a light-emitting functional layer. The light-emitting functional layers of two first pixel units 101 and two fourth pixel units 104 surround a second pixel unit 102 or a third pixel unit 103. The center line 001 of the two first pixel units 101 and the center line 002 of the light-emitting functional layers of the two fourth pixel units 104 pass through the light-emitting functional layers of the second pixel unit 102 or the third pixel unit 103.

[0263] For example, such as Figure 5A , 5B , Figure 9As shown, the light-emitting element 100b includes a first electrode 201. The ratio of the overlapping area of ​​the first electrode 201 of the first pixel unit 101 and the first plate Ca of the first pixel unit 101 to the area of ​​the first electrode 201 of the first pixel unit 101 is less than the ratio of the overlapping area of ​​the first electrode 201 of the first pixel unit 101 and the first plate Ca of the second pixel unit 102 to the area of ​​the first electrode 201 of the first pixel unit 101. Therefore, by reducing the size of the first plate Ca of the first pixel unit 101, the storage capacitance of the first pixel unit 101 is reduced.

[0264] For example, such as Figure 5A As shown, the overlap area between the first electrode 201 of the first pixel unit 101 and the second electrode plate Cb of the first pixel unit 101 is smaller than the overlap area between the first electrode 201 of the first pixel unit 101 and the second electrode plate Cb of the second pixel unit 102.

[0265] For example, such as Figure 5B , Figure 9 and Figure 10 As shown, the pixel circuits 100a of the fourth pixel unit 104, the third pixel unit 103, the first pixel unit 101, and the second pixel unit 102 are arranged sequentially along the first direction X. The area of ​​the storage capacitor Cst of the fourth pixel unit 104 and the area of ​​the storage capacitor Cst of the second pixel unit 102 are not equal.

[0266] For example, such as Figure 5B and Figure 15 As shown, the first electrode 201 of the light-emitting element 100b of the fourth pixel unit 104 has a notch 01. Figure 15 As shown, the orthographic projection of the notch 01 on the substrate BS does not overlap with the orthographic projection of the storage capacitor Cst of the fourth pixel unit 104 on the substrate BS. For example, the notch 01 refers to the inwardly recessed portion of the first electrode 201, where no material of the first electrode 201 is disposed.

[0267] For example, such as Figure 14 and Figure 15 As shown, the pixel circuit 100a also includes a threshold compensation transistor T3. The first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1. The threshold compensation transistor T3 includes a first channel 301, a second channel 302, and a conductive connection portion CP connecting the first channel 301 and the second channel 302. The orthographic projection of the first electrode 201 of the light-emitting element 100b on the substrate BS covers the orthographic projection of the conductive connection portion CP on the substrate BS.

[0268] For example, such as Figure 15 and Figure 16A As shown, the display panel also includes a pixel-defining layer (PDL), which includes a second opening (OPN2) that defines a light-emitting region (LMR). Figure 5A As shown, the ratio of the overlapping area of ​​the second opening OPN2 of the first pixel unit 101 and the first plate Ca of the first pixel unit 101 to the area of ​​the second opening OPN2 of the first pixel unit 101 is greater than 0 and less than 3%.

[0269] For example, the overlap area between the second opening OPN2 of the first pixel unit 101 and the first electrode plate Ca of the first pixel unit 101 is equal to the overlap area between the second opening OPN2 of the first pixel unit 101 and the first electrode plate Ca of the second pixel unit 102.

[0270] Figure 21 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 21 As shown, the display panel also includes a spacer PS, which is located between the light-emitting area LMR of the first pixel unit 101 and the light-emitting area LMR of the fourth pixel unit 104.

[0271] For example, the slope angle of the portion of the pixel limiting layer PDL of the second opening OPN2 forming the first pixel unit 101 is smaller than the slope angle of the portion of the pixel limiting layer PDL of the second opening OPN2 forming the third pixel unit 103, and the slope angle of the portion of the pixel limiting layer PDL of the second opening OPN2 forming the third pixel unit 103 is smaller than the slope angle of the portion of the pixel limiting layer PDL of the second opening OPN2 forming the second pixel unit 102.

[0272] For example, the slope angle of the green pixel unit is smaller than that of the blue pixel unit, and the slope angle of the blue pixel unit is smaller than that of the red pixel unit. For example, in some embodiments, the slope angle of the green pixel unit is 25.1°, the slope angle of the blue pixel unit is 25.8°, and the slope angle of the red pixel unit is 29.5°.

[0273] For example, such as Figure 21 As shown, the first pixel unit 101, the second pixel unit 102, the third pixel unit 103, and the fourth pixel unit 104 constitute a repeating unit RP. The light-emitting area LMR of the first pixel unit 101 and the light-emitting area LMR of the fourth pixel unit 104 are located between the light-emitting area LMR of the second pixel unit 102 and the light-emitting area LMR of the third pixel unit 103.

[0274] Figure 22This is a schematic diagram of a display panel provided in one embodiment of the present disclosure. For example, the display panel further includes multiple touch electrodes TE, each touch electrode TE being in a grid shape. Each touch electrode TE includes multiple conductive lines CDT, which intersect to form multiple mesh areas MH. The ratio of the overlapping area of ​​the storage capacitor Cst of the first pixel unit 101 with the multiple conductive lines CDT to the area of ​​the mesh area MH is less than the ratio of the overlapping area of ​​the storage capacitor Cst of the second pixel unit 102 with the multiple conductive lines CDT to the area of ​​the mesh area MH. That is, the overlapping area of ​​the storage capacitor Cst of the second pixel unit 102 with the multiple conductive lines CDT is greater than the overlapping area of ​​the storage capacitor Cst of the first pixel unit 101 with the multiple conductive lines CDT. Figure 22 Only one touch electrode TE is shown. For example, multiple touch electrodes TE are arranged insulated from each other.

[0275] For example, the ratio of the area of ​​the second opening OPN2 of at least one of the first pixel unit 101 and the second pixel unit 102 to the area of ​​the mesh region MH is greater than one-half and less than three-quarters.

[0276] For example, such as Figure 22 As shown, the orthographic projection of the adapter electrode 801 on the substrate BS overlaps with the orthographic projection of the multiple conductive lines CDT on the substrate BS. The multiple conductive lines CDT act as a shield to prevent the adapter electrode 801 from reflecting light.

[0277] Figures 23 to 26 This is a schematic diagram of a display panel provided in some embodiments of this disclosure. Figures 23 to 26 The pixel circuitry for each pixel unit is shown using the storage capacitor Cst.

[0278] Figure 23 The display panel shown is Figure 10 Compared to the display panel shown, in the second pixel unit 102, the first electrode Ca extends beyond the outline of the second electrode Cb in the second pixel unit 102; in the third pixel unit 103, the first electrode Ca extends beyond the outline of the second electrode Cb in the third pixel unit 103; while in the first pixel unit 101, the first electrode Ca does not extend beyond the outline of the second electrode Cb in the first pixel unit 101; and in the fourth pixel unit 104, the first electrode Ca does not extend beyond the outline of the second electrode Cb in the fourth pixel unit 104. It should be noted that in... Figure 23 Based on the display panel shown, the first electrode plate Ca in the first pixel unit 101 can extend beyond the outline of the second electrode plate Cb in the first pixel unit 101, and the first electrode plate Ca in the fourth pixel unit 104 can extend beyond the outline of the second electrode plate Cb in the fourth pixel unit 104.

[0279] Figure 24The display panel shown is Figure 10 Compared to the display panel shown, the first electrode plate Ca is rotated 180°. The first arc-shaped edge e1 of the first electrode plate Ca is located below the first opening OPN1.

[0280] Figure 25 The display panel shown is Figure 10 Compared to the display panel shown, the first electrode plate Ca is rotated 270°. The first arc-shaped edge e1 of the first electrode plate Ca is located to the left of the first opening OPN1.

[0281] Figure 26 The display panel shown is Figure 10 Compared to the display panel shown, the first electrode plate Ca is rotated 90°. The first arc-shaped edge e1 of the first electrode plate Ca is located to the right of the first opening OPN1.

[0282] Figure 27 The display panel shown is Figure 4 Compared to the display panel shown, the outer contour of the second electrode Cb does not cover the outer contour of the first electrode Ca, and at least a portion of the first electrode Ca extends beyond the second electrode Cb. For example... Figure 27 As shown, the first plate Ca in different pixel units has the same shape and size, while the second plate Cb in different pixel units may have different sizes.

[0283] For example, such as Figure 27 As shown, the first electrode plate Ca in the first pixel unit 101 and the fourth pixel unit 104 have the same shape and size, and the first electrode plate Ca in the second pixel unit 102 and the third pixel unit 103 have the same shape and size. The size of the first electrode plate Ca in the first pixel unit 101 or the fourth pixel unit 104 in the second direction Y is smaller than the size of the first electrode plate Ca in the second pixel unit 102 or the third pixel unit 103 in the second direction Y.

[0284] Figure 27 Taking the example that the size of the first electrode plate Ca in the first pixel unit 101 or the fourth pixel unit 104 in the first direction X is smaller than the size of the first electrode plate Ca in the second pixel unit 102 or the third pixel unit 103 in the first direction X, the explanation is as follows: However, in other embodiments, the size of the first electrode plate Ca in the first pixel unit 101 or the fourth pixel unit 104 in the first direction X may also be equal to the size of the first electrode plate Ca in the second pixel unit 102 or the third pixel unit 103 in the first direction X.

[0285] exist Figure 27In the display panel shown, the first electrode plate Ca is closer to the substrate than the second electrode plate Cb, and the average curvature of the first edge e11 of the second electrode plate Cb of the first pixel unit 101 or the fourth pixel unit 104 is greater than the average curvature of the first edge e11 of the second electrode plate Cb of the second pixel unit 102 or the third pixel unit 103.

[0286] For example, in Figure 27 In the display panel shown, the size of the first opening OPN1 of different pixel units is equal.

[0287] For example, in Figure 27 In the display panel shown, the area of ​​the storage capacitor in the first pixel unit 101 or the fourth pixel unit 104 is smaller than the area of ​​the storage capacitor in the second pixel unit 102 or the third pixel unit 103.

[0288] For example, multiple pixel units 100 and multiple pixel circuits 100a are provided. The multiple pixel circuits 100a include n rows and m columns. Let the pixel circuit in the i-th row and j-th column be the pixel circuit of the first pixel unit 101, let the pixel circuit in the i-th row and (j-1)-th column be the pixel circuit of the second pixel unit 102, and let the pixel circuit in the i-th row and (j+1)-th column be the pixel circuit of the third pixel unit 103, satisfying the following formula:

[0289]

[0290] Where n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1 ≤ i ≤ n; j is a natural number satisfying 1 ≤ j ≤ m; and i + x ≤ n; j + 2y + 1 ≤ m; x is an integer satisfying 0 ≤ x ≤ n; y is an integer satisfying 0 ≤ y ≤ m; A represents the area of ​​the second plate Cb of the storage capacitor Cst; B represents the area of ​​the first plate Ca of the storage capacitor Cst; H represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst. Therefore, by reducing the size of the first plate Ca of the first pixel unit 101, the storage capacitance of the first pixel unit 101 is reduced.

[0291] For example, the meanings of Bij, Hij, and Aij in Formula 9 above can be referred to the description in Formula 2, and will not be repeated here. For example, in Formula 9 above, B(i+x)(j+2y+1) represents the area of ​​the first plate Ca of the storage capacitor Cst of the pixel circuit in the i+x row and (j+2y+1) column, A(i+x)(j+2y+1) represents the area of ​​the second plate Cb of the storage capacitor Cst of the pixel circuit in the (i+x) row and (j+2y+1) column, and H(i+x)(j+2y+1) represents the area of ​​the first opening OPN1 in the second plate Cb of the storage capacitor Cst of the pixel circuit in the (i+x) row and (j+2y+1) column.

[0292] For example, refer to Figure 27 According to Formula 9, the ratio of the area of ​​the storage capacitor of the first pixel unit 101 to the area of ​​the first electrode plate Ca is less than the ratio of the area of ​​the storage capacitor of the second pixel unit 102 to the area of ​​the first electrode plate Ca.

[0293] For example, refer to Figure 27 According to Formula 9, the ratio of the area of ​​the storage capacitor of the first pixel unit 101 to the area of ​​the first electrode plate Ca is less than the ratio of the area of ​​the storage capacitor of the third pixel unit 103 to the area of ​​the first electrode plate Ca.

[0294] For example, refer to Figure 27 According to Formula 9, the ratio of the area of ​​the storage capacitor of the fourth pixel unit 104 to the area of ​​the first electrode plate Ca is less than the ratio of the area of ​​the storage capacitor of the second pixel unit 102 to the area of ​​the first electrode plate Ca.

[0295] For example, refer to Figure 27 According to Formula 9, the ratio of the area of ​​the storage capacitor of the fourth pixel unit 104 to the area of ​​the first electrode plate Ca is less than the ratio of the area of ​​the storage capacitor of the third pixel unit 103 to the area of ​​the first electrode plate Ca.

[0296] This disclosure provides at least one embodiment of a display device, including any of the above-described display panels.

[0297] For example, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any product or component with a display function, including televisions, digital cameras, mobile phones, watches, tablets, laptops, navigators, etc., which include OLED display devices.

[0298] It should be noted that, for clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements present.

[0299] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0300] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: a substrate; and a pixel unit on the substrate, comprising a pixel circuit and a light emitting element, the light emitting element comprising a light emitting region, wherein the pixel circuit is connected to the light emitting element, the pixel circuit is configured to drive the light emitting element, the pixel circuit comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, the first plate is closer to the substrate than the second plate, the second plate of the storage capacitor comprises a body portion and a first opening in the body portion, a projection of the first opening on the substrate at least partially overlaps with a projection of the first plate on the substrate; the pixel unit comprises a first pixel unit and a second pixel unit, the first plate of the pixel unit comprises a first arc-shaped edge and a second edge opposite to the first arc-shaped edge, the second plate comprises a first edge and a second edge opposite to each other, the first arc-shaped edge of the first plate and the first edge of the second plate are on the same side of the first opening, the second edge of the first plate and the second edge of the second plate are on the same side of the first opening, the first plate further comprises a third edge and a fourth edge, the second plate further comprises a third edge and a fourth edge, the third edge of the first plate and the third edge of the second plate are on the same side of the first opening, the fourth edge of the first plate and the fourth edge of the second plate are on the same side of the first opening, in the first pixel unit, a minimum distance between the third edge of the first plate and the third edge of the second plate is F1, in the second pixel unit, a minimum distance between the third edge of the first plate and the third edge of the second plate is F2, wherein F1 is greater than F2. An opposite area of the first plate and the second plate of the first pixel unit is less than an opposite area of the first plate and the second plate of the second pixel unit.

2. The display panel of claim 1, wherein, The first plate of the first pixel unit and the first plate of the second pixel unit are arranged in a first direction; a maximum dimension of the first plate of the first pixel unit in a second direction is less than a maximum dimension of the first plate of the second pixel unit in the second direction, the first direction intersects the second direction.

3. The display panel of claim 1, wherein, An area of the first plate of the first pixel unit is less than an area of the first plate of the second pixel unit.

4. The display panel of claim 1, wherein, The first plate of the third pixel unit, the first plate of the first pixel unit and the first plate of the second pixel unit are arranged in a first direction. 5.The display panel of claim 1, further comprising a third pixel unit, wherein, A maximum curvature of the first arc-shaped edge of the first pixel unit is less than a maximum curvature of the first arc-shaped edge of the second pixel unit.

6. The display panel of claim 1, wherein, A curvature at a midpoint position of the first arc-shaped edge of the first pixel unit is greater than a curvature at a midpoint position of the first arc-shaped edge of the second pixel unit.

7. The display panel of claim 1, wherein, ​ 8. The display panel of claim 1, wherein, A maximum curvature of the first arc-shaped edge of the first pixel unit is less than a maximum curvature of the first opening of the first pixel unit, and a maximum curvature of the first arc-shaped edge of the second pixel unit is less than a maximum curvature of the first opening of the second pixel unit.

9. The display panel of claim 1, wherein, An area of the first opening of the first pixel unit is greater than an area of the first opening of the second pixel unit.

10. The display panel of claim 1, wherein, A normal projection of the light emitting element of the second pixel unit on the substrate is not overlapped with a normal projection of the storage capacitor of the first pixel unit on the substrate, and a normal projection of the storage capacitor of the second pixel unit on the substrate is not overlapped with a normal projection of the light emitting region of the second pixel unit on the substrate.

11. The display panel of claim 5, wherein, An average curvature of the first arc-shaped edge of the first pixel unit is greater than an average curvature of the first arc-shaped edge of the third pixel unit.

12. The display panel of claim 5, wherein, A maximum dimension of the first plate of the first pixel unit in a second direction is less than a maximum dimension of the first plate of the second pixel unit in the second direction, and less than a maximum dimension of the first plate of the third pixel unit in the second direction, the second direction intersecting the first direction.

13. The display panel of claim 5, wherein, An area of the first opening of the first pixel unit is greater than an area of the first opening of the second pixel unit, and greater than an area of the first opening of the third pixel unit.

14. The display panel of claim 5, wherein, A normal projection of the light emitting region of the third pixel unit on the substrate is not overlapped with a normal projection of the storage capacitor of the first pixel unit on the substrate, and not overlapped with a normal projection of the storage capacitor of the second pixel unit on the substrate; A normal projection of the light emitting element of the second pixel unit on the substrate is not overlapped with a normal projection of the storage capacitor of the first pixel unit on the substrate, and not overlapped with a normal projection of the storage capacitor of the third pixel unit on the substrate.

15. The display panel of claim 5, wherein, A normal projection of the light emitting region of the second pixel unit on the substrate is not overlapped with a normal projection of the storage capacitor of the first pixel unit on the substrate, and not overlapped with a normal projection of the storage capacitor of the third pixel unit on the substrate.

16. The display panel of claim 1, wherein, A normal projection of the light emitting element of the second pixel unit on the substrate is not overlapped with a normal projection of the storage capacitor of the first pixel unit on the substrate, and not overlapped with a normal projection of the storage capacitor of the third pixel unit on the substrate.

17. The display panel of any of claims 1-16, wherein, The normal projection area of the storage capacitor is equal to the difference between the area of the first plate and the area of the first opening. A plurality of pixel units are provided, and a plurality of pixel circuits are provided, the plurality of pixel circuits including n rows and m columns, at least one of the n rows and m columns, i.e. the pixel circuit of the i-th row and the j-th column, satisfying the following formula: , Wherein, n is an integer ≥2; m is an integer ≥2; i represents the i-th row; j represents the j-th column; i satisfies the natural number 1≤i≤n; j satisfies the natural number 1≤j≤m; and i+x≤n; j+2y+1≤m; x satisfies the integer 0≤x≤n; y satisfies the integer 0≤y≤m; B represents the area of the first plate of the storage capacitor; H represents the area of the first opening in the second plate of the storage capacitor; and d represents the vertical distance between the first plate and the second plate of the storage capacitor. Wherein, 0<K<1.

18. The display panel of claim 17, wherein, 0.3≤K≤0.8。 19. The display panel of claim 17, wherein, 0.5≤K≤0.7。 20. The display panel of claim 17, wherein, 0.1≤K<0.3 or 0.8<K≤0.

9.

21. The display panel of any of claims 1-16, wherein, A plurality of pixel units are provided, and a plurality of pixel circuits are provided, which collectively comprise n rows and m columns, at least one of the n rows and m columns, i.e., the pixel circuit of the i-th row and the j-th column, satisfies the following formula: , Wherein, n is an integer ≥2; m is an integer ≥2; i represents the i-th row; j represents the j-th column; i satisfies the natural number 1≤i≤n; j satisfies the natural number 1≤j≤m; and i+x≤n; j+2y+1≤m; x satisfies the integer 0≤x≤n; y satisfies the integer 0≤y≤m; A represents the area of the second plate of the storage capacitor; B represents the area of the first plate of the storage capacitor; and H represents the area of the first opening in the second plate of the storage capacitor.

22. The display panel of any one of claims 1-16, wherein, A plurality of pixel units are provided, and a plurality of pixel circuits are provided, which collectively comprise n rows and m columns, The pixel circuit of the i-th row and the j-th column is the pixel circuit of the first pixel unit; The pixel circuit of the first pixel unit satisfies the following formula: ， Wherein, n is an integer ≥2; m is an integer ≥2; i satisfies the natural number 1≤i≤n; j satisfies the natural number 1≤j≤m; A represents the area of the second plate of the storage capacitor; B represents the area of the first plate of the storage capacitor; and H represents the area of the first opening in the second plate of the storage capacitor.

23. The display panel of any of claims 5, 11-15, wherein, A plurality of pixel units are provided, and a plurality of pixel circuits are provided, which collectively comprise n rows and m columns, the pixel circuit of the i-th row and the j-th column is the pixel circuit of the first pixel unit, and the pixel circuit of the (i+x)-th row and the (j+2y+1)-th column is the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; The pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit satisfies the following formula: ， Wherein, n is an integer ≥2; m is an integer ≥2; i satisfies the natural number 1≤i≤n; j satisfies the natural number 1≤j≤m; and i+x≤n; j+2y+1≤m; x satisfies the integer 0≤x≤n; y satisfies the integer 0≤y≤m; A represents the area of the second plate of the storage capacitor; B represents the area of the first plate of the storage capacitor; and H represents the area of the first opening in the second plate of the storage capacitor.

24. The display panel of any of claims 5, 11-15, wherein, The display panel comprises a plurality of pixel units and a plurality of pixel circuits, the plurality of pixel circuits comprises n rows and m columns in total, The pixel circuit in the i-th row and the j-th column is the pixel circuit of the first pixel unit, and the pixel circuit in the (i+x)-th row and the (j+2y+1)-th column is the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; the following formula is satisfied: ， wherein n is an integer greater than or equal to 2; m is an integer greater than or equal to 2; i is a natural number satisfying 1≤i≤n; j is a natural number satisfying 1≤j≤m; i+x≤n, j+2y+1≤m; x is an integer satisfying 0≤x≤n; y is an integer satisfying 0≤y≤m; B represents the area of the first plate of the storage capacitor, and H represents the area of the first opening in the second plate of the storage capacitor.

25. The display panel of any one of claims 5, 11-15, wherein, The display panel comprises a plurality of pixel units and a plurality of pixel circuits, the plurality of pixel circuits comprises n rows and m columns in total, The pixel circuit in the i-th row and the j-th column is the pixel circuit of the first pixel unit, and the pixel circuit in the (i+x)-th row and the (j+2y+1)-th column is the pixel circuit of the second pixel unit or the pixel circuit of the third pixel unit; the following formula is satisfied: , wherein n is an integer greater than or equal to 2; m is an integer greater than or equal to 2; i is a natural number satisfying 1≤i≤n; j is a natural number satisfying 1≤j≤m; i+x≤n, j+2y+1≤m; x is an integer satisfying 0≤x≤n; y is an integer satisfying 0≤y≤m; A represents the area of the second plate of the storage capacitor; and H represents the area of the first opening in the second plate of the storage capacitor.

26. The display panel of any of claims 1-16, wherein, The first plate of the first pixel unit and the first plate of the second pixel unit are arranged in a first direction; and a maximum dimension of the first plate of the first pixel unit in the first direction is smaller than a maximum dimension of the first plate of the second pixel unit in the first direction.

27. The display panel of any one of claims 1-16, wherein, The first plate of the first pixel unit and the first plate of the second pixel unit are arranged in a first direction; In a second direction, a minimum distance from an edge of the first opening of the first pixel unit to the second edge of the first plate is D1, and a minimum distance from an edge of the first opening of the second pixel unit to the second edge of the first plate is D2, the first direction intersects the second direction, wherein D1 is smaller than D2.

28. The display panel of claim 27, wherein, 。 29. The display panel of claim 27, wherein, 。 30. The display panel of claim 27, wherein, 。 31. The display panel of any one of claims 1-16, wherein, In the first pixel unit, a shortest distance between the second edge of the first plate and the second edge of the second plate is E1, In the second pixel unit, a shortest distance between the second edge of the first plate and the second edge of the second plate is E2, wherein E1 is greater than E2.

32. The display panel of claim 31, wherein, 。 33. The display panel of claim 31, wherein, 。 34. The display panel of claim 1, wherein, An average curvature of the first arc-shaped edge of the first pixel unit is greater than an average curvature of the first arc-shaped edge of the second pixel unit.

35. The display panel of claim 1, wherein, In the first pixel unit, a minimum distance between an edge of the first opening and the third edge of the second plate is G1, In the second pixel unit, a minimum distance between an edge of the first opening and the third edge of the second plate is G2, wherein G1 is less than G2.

36. The display panel of claim 35, wherein, 。 37. The display panel of claim 5, wherein, In the first pixel unit, a ratio of a maximum dimension of the first plate in a second direction to a maximum dimension of the second plate in the second direction is R11, In the second pixel unit, a ratio of a maximum dimension of the first plate in the second direction to a maximum dimension of the second plate in the second direction is R12, In the third pixel unit, a ratio of a maximum dimension of the first plate in the second direction to a maximum dimension of the second plate in the second direction is R13, wherein the second direction intersects the first direction, R11 is less than R12, and R11 is less than R13.

38. The display panel of claim 5, wherein, In the first pixel unit, a ratio of a maximum dimension of the first opening in a second direction to a maximum dimension of the first plate in the second direction is R21, In the second pixel unit, a ratio of a maximum dimension of the first opening in the second direction to a maximum dimension of the first plate in the second direction is R22, In the third pixel unit, a ratio of a maximum dimension of the first opening in the second direction to a maximum dimension of the first plate in the second direction is R23, wherein the second direction intersects the first direction, R21 is greater than R22, and R21 is greater than R23.

39. The display panel of claim 5, wherein, A plurality of pixel units are provided, and a plurality of pixel circuits are provided, the plurality of pixel circuits collectively comprising n rows and m columns, at least one of the n rows and m columns, i.e., the i-th row and the j-th column, being a pixel circuit of the first pixel unit, and the (i+x)(j+2y+1)-th being a pixel circuit of the second pixel unit or the third pixel unit, an area of the first plate of the first pixel unit and an area of the first plate of the second pixel unit or the third pixel unit satisfy the following formula: ， wherein n is an integer ≥ 2; m is an integer ≥ 2; i represents the i-th row; j represents the j-th column; i satisfies a natural number of 1≤i≤n; j satisfies a natural number of 1≤j≤m; and i+x≤n; j+2y+1≤m; x satisfies an integer of 0≤x≤n; y satisfies an integer of 0≤y≤m; and B represents an area of the first plate of the storage capacitor.

40. The display panel of claim 39, wherein, 。 41. The display panel according to any one of claims 1-16, further comprising a light emission control signal line, wherein, The light-emitting control signal line extends along a first direction, The first plate comprises a second edge opposite to the first arc-shaped edge, The first plate and the light-emitting control signal line are arranged along a second direction, In the first pixel unit, a minimum distance between the second edge of the first plate and the light-emitting control signal line is Q1, In the second pixel unit, a minimum distance between the second edge of the first plate and the light-emitting control signal line is Q2, wherein Q1 is greater than Q2.

42. The display panel of claim 41, wherein, 。 43. The display panel of any of claims 5, 11-15, further comprising a transfer electrode, wherein, The pixel circuit is connected with the light emitting element through the transfer electrode.

44. The display panel of claim 43, wherein, In the first pixel unit, a shortest distance between the first plate and the transfer electrode is P1, In the second pixel unit or the third pixel unit, a shortest distance between the first plate and the transfer electrode is P2, Wherein, P1 is greater than P2.

45. The display panel of claim 44, wherein, 。 46. The display panel of any of claims 5, 11-15, wherein, The pixel circuit further comprises a driving transistor, The gate of the driving transistor is connected with the first plate of the storage capacitor.

47. The display panel of claim 46, wherein, In the first pixel unit, a ratio of an area of a part of the semiconductor layer of the driving transistor located in the first opening to a sum of areas of the second plate and the first opening is R31, In the second pixel unit, a ratio of an area of a part of the semiconductor layer of the driving transistor located in the first opening to a sum of areas of the second plate and the first opening is R32, In the third pixel unit, a ratio of an area of a part of the semiconductor layer of the driving transistor located in the first opening to a sum of areas of the second plate and the first opening is R33, Wherein, R31 is greater than R32, and R31 is greater than R33.

48. The display panel of any one of claims 1-16, wherein, A plurality of pixel units are provided, and a plurality of pixel circuits are provided, the plurality of pixel circuits comprising n rows and m columns in total, Supposing that the i-th row and the j-th column are the pixel circuit of the first pixel unit, the i-th row and the (j-1)-th column are the pixel circuit of the second pixel unit, and the i-th row and the (j+1)-th column are the pixel circuit of the third pixel unit, the following formula is satisfied: ， Wherein, n is an integer greater than or equal to 2; m is an integer greater than or equal to 2; i represents the i-th row; j represents the j-th column; i is a natural number satisfying 1≤i≤n; j is a natural number satisfying 1≤j≤m; i+x≤n; j+2y+1≤m; x is an integer satisfying 0≤x≤n; y is an integer satisfying 0≤y≤m; A represents an area of the second plate of the storage capacitor; B represents an area of the first plate of the storage capacitor; and H represents an area of the first opening in the second plate of the storage capacitor.

49. The display panel of any one of claims 1-16, wherein, The light emitting element comprises a first electrode, and a ratio of an overlapping area of the first electrode of the first pixel unit and the first plate of the first pixel unit to an area of the first electrode of the first pixel unit is less than a ratio of an overlapping area of the first electrode of the first pixel unit and the first plate of the second pixel unit to the area of the first electrode of the first pixel unit.

50. The display panel of claim 49, wherein, An overlapping area of the first electrode of the first pixel unit and the second plate of the first pixel unit is less than an overlapping area of the first electrode of the first pixel unit and the second plate of the second pixel unit. 51.The display panel of claim 5, further comprising a fourth pixel unit, wherein, The pixel circuit of the fourth pixel unit, the pixel circuit of the third pixel unit, the pixel circuit of the first pixel unit, and the pixel circuit of the second pixel unit are arranged in the first direction in sequence, The facing area of the first and second plates of the fourth pixel unit and the facing area of the first and second plates of the second pixel unit are not equal.

52. The display panel of claim 51, wherein, The light emitting element comprises a light emitting functional layer, the light emitting functional layers of the two first pixel units and the two fourth pixel units surround one second pixel unit or one third pixel unit, and the center line of the two first pixel units and the center line of the light emitting functional layers of the two fourth pixel units pass through the light emitting functional layer of the second pixel unit or the third pixel unit.

53. The display panel of claim 52, wherein, The first electrode of the light emitting element of the fourth pixel unit has a notch, and the orthographic projection of the notch on the substrate substrate does not overlap with the orthographic projection of the storage capacitor of the fourth pixel unit on the substrate substrate.

54. The display panel of claim 46, wherein, The pixel circuit further comprises a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected with a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is connected with a gate electrode of the driving transistor; the threshold compensation transistor comprises a first channel, a second channel, and a conductive connection part connecting the first channel and the second channel, The orthographic projection of the first electrode of the light emitting element on the substrate substrate covers the orthographic projection of the conductive connection part on the substrate substrate.

55. The display panel of claim 43, further comprising a pixel definition layer, wherein, The pixel defining layer comprises a second opening, the second opening defines the light emitting region, and the overlapping area of the second opening of the first pixel unit and the first plate of the first pixel unit is greater than 0 and less than 3% of the area of the second opening of the first pixel unit.

56. The display panel of claim 55, wherein, The overlapping area of the second opening of the first pixel unit and the first plate of the first pixel unit is equal to the overlapping area of the second opening of the first pixel unit and the first plate of the second pixel unit.

57. The display panel of claim 55, further comprising a plurality of touch electrodes, wherein, Each touch electrode is in a grid shape, the touch electrode comprises a plurality of conductive lines, and the plurality of conductive lines cross to form a plurality of mesh regions, The ratio of the overlapping area of the facing part of the storage capacitor of the first pixel unit and the plurality of conductive lines to the area of the mesh region is less than the ratio of the overlapping area of the facing part of the storage capacitor of the second pixel unit and the plurality of conductive lines to the area of the mesh region.

58. The display panel of claim 57, wherein, The ratio of the area of the second opening of at least one of the first pixel unit and the second pixel unit to the area of the mesh region is greater than one half and less than three quarters.

59. The display panel of claim 57, wherein, The orthographic projection of the transfer electrode on the substrate substrate partially overlaps with the orthographic projection of the plurality of conductive lines on the substrate substrate.

60. The display panel of claim 52, further comprising a spacer, wherein, The spacer is located between the light emitting region of the first pixel unit and the light emitting region of the fourth pixel unit.

61. The display panel of claim 55, wherein, The slope angle of the part of the pixel defining layer forming the second opening of the first pixel unit is less than the slope angle of the part of the pixel defining layer forming the second opening of the third pixel unit, and the slope angle of the part of the pixel defining layer forming the second opening of the third pixel unit is less than the slope angle of the part of the pixel defining layer forming the second opening of the second pixel unit.

62. The display panel of claim 51, wherein, The first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit constitute a repeating unit, and the light emitting area of the first pixel unit and the light emitting area of the fourth pixel unit are located between the light emitting area of the second pixel unit and the light emitting area of the third pixel unit.

63. The display panel of any of claims 1-16, wherein, A normal projection of the light emitting area of the first pixel unit on the substrate substrate partially overlaps with a normal projection of at least one of the storage capacitor of the first pixel unit or the storage capacitor of the second pixel unit on the substrate substrate, The normal facing area of the storage capacitor of the first pixel unit and the normal facing area of the storage capacitor of the second pixel unit are not equal.

64. A display device comprising the display panel according to any one of claims 1-63.

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