Composite circuit protection device

Abstract

A composite circuit protection device includes a positive temperature coefficient (PTC) element, a varistor, a first conductive lead and a second conductive lead. The PTC element includes a PTC layer having two opposite PTC surfaces, a first electrode layer and a second electrode layer having surface areas smaller than those of the respective PTC surfaces. The first conductive lead and the second conductive lead are connected to the PTC element and the varistor, respectively. The varistor includes a varistor layer having two opposite varistor surfaces, a third electrode layer and a fourth electrode layer having surface areas smaller than those of the respective varistor surfaces. The composite circuit protection device has excellent resistance, and the PTC element can protect the varistor from burning out in the presence of overcurrent and overvoltage.

Description

Technical Field

[0001] This invention relates to a composite circuit protection device, and more particularly to a composite circuit protection device comprising a positive temperature coefficient (PTC) element and a voltage-dependent resistor (VDR), wherein at least one of the elements has an electrode with a reduced surface area. Background Technology

[0002] See Figure 1 An existing composite circuit protection device includes a positive temperature coefficient (PTC) element 12, a varistor (VDR) 13, a first conductive lead 14, and a second conductive lead 15. The PTC element 12 includes a PTC layer 121, a first electrode layer 122, and a second electrode layer 123. The first electrode layer 122 and the second electrode layer 123 each have an electrode surface connected to one of two opposite surfaces of the PTC layer 121, and the area of ​​the electrode surface is equal to the area of ​​the two opposite surfaces of the PTC layer 121. The VDR 13 includes a varistor layer 131, a third electrode layer 132, and a fourth electrode layer 133. The third electrode layer 132 and the fourth electrode layer 133 each have an electrode surface connected to one of two opposite surfaces of the varistor layer 131, and the area of ​​the electrode surface is equal to the area of ​​the two opposite surfaces of the varistor layer 131. The first conductive lead 14 and the second conductive lead 15 are respectively connected to the first electrode layer 122 and the third electrode layer 132.

[0003] Electrical characteristics [such as operating current and high-voltage surge endurance] are important factors affecting the occurrence of power surges in composite circuit protection devices. Increasing the operating current of the composite circuit protection device by increasing the thickness or area of ​​the PTC element 12 makes it more susceptible to power surge damage. Conversely, increasing the high-voltage endurance of the overcurrent protection device by reducing the thickness or area of ​​the PTC element 12 does not necessarily make it less susceptible to power surge damage.

[0004] Although the combination of PTC element 12 and VDR 13 provides overcurrent and overvoltage protection for the resulting composite circuit protection device, VDR 13 can only withstand power surges briefly (e.g., 0.001 seconds). In other words, if the surge duration exceeds the cutoff time interval, VDR 13 will burn out or be damaged due to overcurrent or overvoltage, causing the composite circuit protection device to permanently lose its function. Summary of the Invention

[0005] The purpose of this invention is to provide a composite circuit protection device that can overcome at least one of the disadvantages of the above-mentioned background technology.

[0006] The composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element, a varistor, a first conductive lead, and a second conductive lead. The PTC element includes a PTC layer, a first electrode layer, and a second electrode layer. The PTC layer has two opposite PTC surfaces. The first and second electrode layers each have an electrode surface connected to one of the two opposite PTC surfaces of the PTC layer. The varistor includes a varistor layer, a third electrode layer, and a fourth electrode layer. The varistor layer has two opposite resistor surfaces. The third electrode layer has an electrode surface connected to one of the two opposite resistor surfaces of the varistor layer and disposed between one of the two opposite resistor surfaces of the varistor layer and the second electrode layer of the PTC element. The fourth electrode layer has an electrode surface connected to the other of the two opposite resistor surfaces of the varistor layer. The first conductive lead is connected to the first electrode layer, and the second conductive lead is connected to one of the third and fourth electrode layers of the varistor. The area of ​​the electrode surface of the first electrode layer and the second electrode layer is smaller than the area of ​​their respective PTC surface, or the area of ​​the electrode surface of the third electrode layer and the fourth electrode layer is smaller than the area of ​​their respective resistor surface.

[0007] In the composite circuit protection device of the present invention, the area of ​​the electrode surface of the first electrode layer and the second electrode layer is 70% to 90% of the area of ​​the respective PTC surface.

[0008] In the composite circuit protection device of the present invention, the area of ​​the electrode surfaces of the third electrode layer and the fourth electrode layer is 70% to 90% of the area of ​​the respective resistor surface.

[0009] The composite circuit protection device of the present invention has a PTC element whose rated voltage is 45% to 200% of the varistor voltage measured at 1mA.

[0010] The composite circuit protection device of the present invention has a PTC element whose rated voltage is 45% to 100% of the varistor voltage measured at 1mA.

[0011] The composite circuit protection device of the present invention has a PTC element whose rated voltage is 45% to 70% of the varistor voltage measured at 1mA.

[0012] The composite circuit protection device of the present invention allows the PTC element to trip before the varistor burns out when subjected to overcurrent and a voltage greater than the varistor's varistor voltage.

[0013] The composite circuit protection device of the present invention trips within 1μs to 100s when the PTC element is subjected to an overcurrent greater than 0.1A and a voltage greater than the varistor voltage.

[0014] The composite circuit protection device of the present invention trips within 1ms to 10s when the PTC element is subjected to an overcurrent greater than 0.5A and a voltage greater than the varistor voltage.

[0015] The composite circuit protection device of the present invention allows the PTC element to trip within 1ms to 1s when subjected to an overcurrent greater than 10A and a voltage greater than the varistor voltage.

[0016] The composite circuit protection device of the present invention has a first hole formed in the PTC layer of the PTC element.

[0017] The composite circuit protection device of the present invention has a PTC layer of the PTC element having a periphery that defines the boundary of the PTC layer and interconnects with two opposite PTC surfaces of the PTC layer, and the first hole is spaced apart from the periphery of the PTC layer.

[0018] The composite circuit protection device of the present invention has a first hole penetrating at least one of two opposite PTC surfaces of the PTC layer.

[0019] In the composite circuit protection device of the present invention, the first hole also penetrates at least one of the first electrode layer and the second electrode layer.

[0020] The composite circuit protection device of the present invention has a second hole formed in the varistor.

[0021] The composite circuit protection device of the present invention further includes a third conductive lead, the second conductive lead being connected to the fourth electrode layer, and the third conductive lead being connected to and disposed between the second electrode layer and the third electrode layer.

[0022] The composite circuit protection device of the present invention has a second hole formed in the varistor layer.

[0023] The composite circuit protection device of the present invention has a varistor layer with a periphery that defines the boundary of the varistor layer and interconnects with two opposite resistor surfaces of the varistor layer, and the second hole is spaced apart from the periphery of the varistor layer.

[0024] The composite circuit protection device of the present invention has a second hole that penetrates at least one of the two opposite resistor surfaces of the varistor layer.

[0025] In the composite circuit protection device of the present invention, the second hole also penetrates at least one of the third electrode layer and the fourth electrode layer.

[0026] The composite circuit protection device of the present invention has a polymer PTC element and a PTC polymer layer.

[0027] The composite circuit protection device of the present invention further includes a packaging material that encapsulates the PTC element, the varistor, a portion of the first conductive lead, and a portion of the second conductive lead.

[0028] The beneficial effects of the present invention are as follows: the composite circuit protection device of the present invention has excellent tolerance and reliability. Under the presence of overcurrent and overvoltage, the PTC element can protect the varistor from burning out. Attached Figure Description

[0029] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0030] Figure 1 This is a schematic diagram of an existing composite circuit protection device;

[0031] Figure 2 This is a schematic diagram of the first specific embodiment of the composite circuit protection device of the present invention;

[0032] Figure 3 This is a cross-sectional schematic diagram of the first specific embodiment;

[0033] Figure 4 This is a schematic diagram of a second specific embodiment of the composite circuit protection device of the present invention;

[0034] Figure 5 This is a cross-sectional schematic diagram of the second specific embodiment;

[0035] Figure 6 This is a cross-sectional schematic diagram of the third specific embodiment of the composite circuit protection device of the present invention. Detailed Implementation

[0036] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0037] See Figure 2 and Figure 3 The first embodiment of the composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element 2, a varistor 3, a first conductive lead 4 and a second conductive lead 5.

[0038] The PTC element 2 includes a PTC layer 21, a first electrode layer 22 and a second electrode layer 23. The PTC layer 21 has two opposite PTC surfaces 211. The first electrode layer 22 and the second electrode layer 23 each have electrode surfaces 221 and 231 that are connected to one of the two opposite PTC surfaces 211 of the PTC layer 21.

[0039] The varistor 3 includes a varistor layer 31, a third electrode layer 32 and a fourth electrode layer 33. The varistor layer 31 has two opposite resistor surfaces 311.

[0040] The third electrode layer 32 has an electrode surface 321 that is connected to one of the two opposite resistor surfaces 311 of the varistor layer 31 by solder and is disposed between the one of the two opposite resistor surfaces 311 of the varistor layer 31 and the second electrode layer 23 of the PTC element 2. The fourth electrode layer 33 has an electrode surface 331 that is connected to the other of the two opposite resistor surfaces 311 of the varistor layer 31 by solder.

[0041] The first conductive lead 4 is connected to the first electrode layer 22. The second conductive lead 5 is connected to either the third electrode layer 32 or the fourth electrode layer 33 of the varistor 3. In this embodiment, the second conductive lead 5 is connected to and disposed between the second electrode layer 23 and the third electrode layer 32.

[0042] The areas of the electrode surfaces 221 and 231 of the first electrode layer 22 and the second electrode layer 23 are smaller than the area of ​​their respective PTC surface 211. The areas of the electrode surfaces 321 and 331 of the third electrode layer 32 and the fourth electrode layer 33 are smaller than the area of ​​their respective resistor surface 311.

[0043] In some specific embodiments of the present invention, the area of ​​the electrode surfaces 221 and 231 of the first electrode layer 22 and the second electrode layer 23 is 70% to 90% of the area of ​​the respective PTC surface 211.

[0044] In some specific embodiments of the present invention, the area of ​​the electrode surfaces 321 and 331 of the third electrode layer 32 and the fourth electrode layer 33 is 70% to 90% of the area of ​​the respective resistor surface 311.

[0045] The PTC element 2 has a rated voltage that is 40% to 200% of the varistor voltage of the varistor 3 measured at 1 mA. In some embodiments of the invention, the rated voltage of the PTC element 2 is 45% to 100% of the varistor voltage of the varistor 3 measured at 1 mA. In some embodiments of the invention, the rated voltage of the PTC element 2 is 45% to 70% of the varistor voltage of the varistor 3 measured at 1 mA.

[0046] According to the present invention, the PTC element 2 trips before the varistor 3 burns out when subjected to overcurrent and a voltage greater than the varistor voltage of the varistor 3. In other words, under the presence of overcurrent and a voltage greater than the varistor voltage of the varistor 3, the PTC element 2 quickly trips to a high-resistance state, thereby limiting the overcurrent from flowing through the varistor 3, thus protecting the varistor 3 from burnout, and the composite circuit protection device can thus be reused.

[0047] In this article, the terms “burn out,” “spark,” and “on fire” are used interchangeably and refer to the varistor losing its function, typically at temperatures above 180°C.

[0048] In some specific embodiments of the present invention, the PTC element 2 trips within 1 μs to 100 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 trips within 10 μs to 10 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 trips within 0.1 ms to 1 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3.

[0049] In some specific embodiments of the present invention, the PTC element 2 trips within 1 ms to 10 s under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage of the varistor 3.

[0050] In some specific embodiments of the present invention, the PTC element 2 trips within 1 ms to 1 s under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 trips within 1 ms to 0.1 s under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3.

[0051] The PTC element 2 may have a first hole 210 formed therein. In this embodiment, the first hole 210 is formed in the PTC layer 21. The PTC layer 21 of the PTC element 2 has a periphery 212 that defines the boundary of the PTC layer 21 and interconnects with two opposite PTC surfaces 211 of the PTC layer 21. The first hole 210 is spaced apart from the periphery 212 of the PTC layer 21 and has an effective volume to accommodate the thermal expansion of the PTC layer 21 when the temperature rises, so as to avoid undesirable structural deformation of the PTC layer 21.

[0052] In some embodiments of the present invention, the first hole 210 penetrates at least one of the two opposite PTC surfaces 211 of the PTC layer 21. In some embodiments of the present invention, the first hole 210 also penetrates at least one of the first electrode layer 22 and the second electrode layer 23. In this embodiment, the first hole 210 penetrates the two opposite PTC surfaces 211 of the PTC layer 21 and the first electrode layer 22 and the second electrode layer 23 to form a perforation. In some embodiments of the present invention, the first hole 210 is located at the geometric center of the PTC layer 21 and penetrates the two opposite PTC surfaces 211. The first hole 210 is defined by a hole defining wall having a cross-section parallel to the PTC surface 211 of the PTC layer 21. The cross-section of the hole defining wall can be circular, square, elliptical, triangular, cross-shaped, etc.

[0053] According to the present invention, the PTC element 2 may be a polymer PTC (PPTC) element, and the PTC layer 21 may be a PTC polymer layer. The PTC polymer layer includes a polymer substrate and a conductive filler dispersed in the polymer substrate. The varistor layer 31 may be made of a metal oxide material. The polymer substrate may be made of a polymer composition containing a non-grafted olefin-based polymer. In some embodiments of the present invention, the non-grafted olefin-based polymer is high-density polyethylene (HDPE). In some embodiments of the present invention, the polymer composition further includes a grafted olefin-based polymer. In some embodiments of the present invention, the grafted olefin-based polymer is an olefin-based polymer grafted with carboxylic anhydride. The conductive filler applicable to the present invention is selected from carbon black powder, metal powder, conductive ceramic powder, or combinations thereof, but is not limited thereto.

[0054] The varistor 3 may have a second hole 310 formed in the varistor layer 31. In this embodiment, the varistor layer 31 of the varistor 3 has a periphery 312, which defines the boundary of the varistor layer 31 and interconnects with two opposite resistor surfaces 311 of the varistor layer 31. The second hole 310 is spaced apart from the periphery 312 of the varistor layer 31.

[0055] In some embodiments of the present invention, the second hole 310 penetrates at least one of the two opposite resistor surfaces 311 of the varistor layer 31. In some embodiments of the present invention, the second hole 310 also penetrates at least one of the third electrode layer 32 and the fourth electrode layer 33. In this embodiment, the second hole 310 penetrates the two opposite resistor surfaces 311 of the varistor layer 31 and the third electrode layer 32 and the fourth electrode layer 33 to form a through hole.

[0056] According to the present invention, the first conductive lead 4 has a connecting portion 41 and a free portion 42, while the second conductive lead 5 has a connecting portion 51 and a free portion 52. The connecting portion 41 of the first conductive lead 4 is connected to the outer surface of the first electrode layer 22 by solder, and the free portion 42 of the first conductive lead 4 extends from the connecting portion 41 out of the first electrode layer 22 for insertion into the pin holes (not shown) of a circuit board or circuit device. In this embodiment, the connecting portion 51 of the second conductive lead 5 is connected by solder and disposed between the second electrode layer 23 and the third electrode layer 32, and the free portion 52 of the second conductive lead 5 extends from the connecting portion 51 out of the second electrode layer 23 and the third electrode layer 32 for insertion into the pin holes (not shown) of a circuit board or circuit device.

[0057] See Figure 4 and Figure 5 The second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, except that in the second embodiment, the connecting portion 51 of the second conductive lead 5 is connected to the outer surface of the fourth electrode layer 33 by solder, and the free portion 52 of the second conductive lead 5 extends from the connecting portion 51 out of the fourth electrode layer 33 for insertion into the pin holes (not shown) of a circuit board or circuit device. Furthermore, the second embodiment also includes a package 7 that encapsulates the PTC element 2, the varistor 3, a portion of the first conductive lead 4, and a portion of the second conductive lead 5. The free portions 42 of the first conductive lead 4 and the free portions 52 of the second conductive lead 5 are exposed outside the package 7. In some specific embodiments of the present invention, the package 7 is made of epoxy resin.

[0058] See Figure 6 The third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, except that the third embodiment further includes a third conductive lead 6, which is connected to and disposed between the second electrode layer 23 and the third electrode layer 32. The third conductive lead 6 has a connecting portion 61 and a free portion 62. The connecting portion 61 of the third conductive lead 6 is connected to the second electrode layer 23 and the third electrode layer 32, and the free portion 62 of the third conductive lead 6 extends from the connecting portion 61 out of the second electrode layer 23 and the third electrode layer 32 for insertion into the pin holes (not shown) of a circuit board or circuit device.

[0059] In this embodiment, the encapsulation material 7 encapsulates the PTC element 2, the varistor 3, a portion of the first conductive lead 4, a portion of the second conductive lead 5, and a portion of the third conductive lead 6. The free portions 42 of the first conductive lead 4, 52 of the second conductive lead 5, and 62 of the third conductive lead 6 are exposed outside the encapsulation material 7.

[0060] The present invention will be further described with reference to the following embodiments, but it should be understood that the embodiments are for illustrative purposes only and should not be construed as limiting the implementation of the present invention.

[0061] Example

[0062] <Example 1 (E1)>

[0063] 10g HDPE (purchased from Taiwan Plastics Industries Co., Ltd., product model: HDPE9002) as a non-grafted olefin polymer, 10g maleic anhydride-grafted HDPE (purchased from DuPont, product model: MB100D) as a carboxylic anhydride-grafted olefin polymer, 15g carbon black powder (purchased from Columbia Chemicals, product model: Raven 430UB) as a conductive filler, 15g magnesium hydroxide (purchased from Martin Marietta, product model: ... MH 10).

[0064] The above ingredients were mixed in a mixer (Brabender) at a temperature of 200°C and a stirring speed of 30 rpm for 10 minutes.

[0065] The above-obtained mixture is placed in a mold and hot-pressed at a temperature of 200°C and a pressure of 80 kg / cm². 2 The PTC polymer layer sheet was hot-pressed for 4 minutes under the specified conditions to form a thin sheet. The sheet was then removed from the mold, and its two opposite PTC surfaces were brought into contact with two copper foils (serving as the first electrode layer 22 and the second electrode layer 23, respectively), and hot-pressed at 200°C and a pressure of 80 kg / cm². 2 Under these conditions, the PPTC element is hot-pressed for 4 minutes to form a PPTC element with a thickness of 2.2 mm. This PPTC element is then cut into multiple circles with a diameter of 14.5 mm (approximately 165.1 mm²). 2 After the chip (hereinafter referred to as PPTC chip) is made, each PPTC chip is irradiated with Co-60 gamma rays at a total radiation dose of 150 kGy.

[0066] The circular metal-oxide varistor (MOV, purchased from Ceramate Technical, product model: 20D361K, hereinafter referred to as MOV) includes a varistor layer 31 and two electrode layers (serving as the third electrode layer 32 and the fourth electrode layer 33, respectively). The varistor layer 31 has two opposite resistive surfaces 311 (each with a diameter of 20.0 mm and an area of ​​approximately 314.2 mm²). 2The third electrode layer 32 and the fourth electrode layer 33 are respectively connected to two opposite resistor surfaces 311 of the varistor layer. The MOV is etched to remove a portion of the periphery of the electrode layers, so that each third electrode layer 32 and each fourth electrode layer 33 has a diameter of 18.9 mm (area approximately 280.6 mm²). 2 The circular electrode layers, i.e., the etched MOV electrode coverage, are approximately 89%, meaning the area of ​​each third electrode layer 32 and each fourth electrode layer 33 is 280.6 mm². 2 () is approximately the area of ​​the surface 311 of each resistor (314.2 mm²). 2 89% of ).

[0067] The first conductive lead 4 and the second conductive lead 5 are respectively soldered to the two copper foils of each PPTC chip. Then, the etched MOV is soldered to one of the two copper foils to form the composite circuit protection device of E1.

[0068] According to Underwriter Laboratories' UL 1434 safety standard for thermistor-type devices, the holding current (maximum current during normal operation), trip current (minimum current required for the PPTC element to reach a high-resistance state), rated voltage (the voltage applicable to the PPTC element during operation), and withstand voltage (the maximum voltage that will not cause malfunction or damage to the PPTC element) of the PPTC chip were measured. Furthermore, prior to etching, according to Underwriter Laboratories' UL 1449 safety standard for transient voltage surge suppressors, the varistor voltage (the voltage at which the MOV is triggered to operate) and clamping voltage (the maximum voltage that the MOV can provide for limiting operation) of the MOV element were measured. The measurement results for the properties of the PPTC chip and MOV are shown in Table 1.

[0069] Table 1

[0070]

[0071] a: Measured at 1mA.

[0072] b: In the pulse waveform (t) p )8 / 20μs and pulse current (I p Measurement at 2.5A.

[0073] <Examples 2 and 3 (E2 and E3)>

[0074] The process conditions for the composite circuit protection devices of E2 and E3 are similar to those of E1. The difference lies in that, before irradiating the PPTC wafer with gamma rays, the PPTC wafers of E2 and E3 are etched to remove part of the periphery of the first electrode layer 22 and the second electrode layer 23, so that each first electrode layer 22 and each second electrode layer 23 has a diameter of 13.7 mm (area of ​​approximately 147.4 mm²). 2 The circular electrode layers, i.e., the electrode coverage of the etched PPTC wafers, are approximately 89%, meaning the area of ​​each first electrode layer 22 and each second electrode layer 23 is 147.4 mm². 2 () is approximately the area of ​​the respective PTC surface 211 (165.1 mm²) 2 89% of the total. Furthermore, the MOVs in E2 were not etched, meaning their electrode coverage is 100%.

[0075] <Examples 4 to 12 (E4-E12)>

[0076] The process conditions for composite circuit protection devices of E4-E6, E7-E9, and E10-E12 are similar to those of E1-E3, with the difference being that the PPTC chip forms the first through-hole 210 and / or the MOV forms the second through-hole 310 (as shown in Table 2). Each first through-hole 210 and each second through-hole 310 is formed by a circular cross-section (diameter of 1.5 mm and circular area of ​​1.77 mm²). 2 The hole definition is defined by the wall.

[0077] In E4-E6, after gamma-ray irradiation, a first perforation 210 is drilled in the center of the PPTC chip. In E7-E9, before soldering copper foil, a second perforation 310 is drilled in the center of the MOV. In E10-E12, a first perforation 210 is drilled in the center of the PPTC chip and a second perforation 310 is drilled in the center of the MOV (as shown in the image). Figure 3 (As shown).

[0078] <Comparative Examples 1 to 4 (CE1-CE4)>

[0079] The process conditions for the circuit protection devices of CE1-CE4 are similar to those of E2, E3, E8 and E9, respectively. The difference is that none of CE1-CE4 contain PPTC chips.

[0080] <Comparative Examples 5 to 8 (CE5-CE8)>

[0081] The process conditions for the circuit protection devices of CE5-CE8 are similar to those of E1, E3, E4 and E6, respectively. The difference is that CE5-CE8 does not contain MOV.

[0082] <Comparative Examples 9 to 12 (CE9-CE12)>

[0083] The process conditions of the composite circuit protection device of CE9-CE12 are similar to those of E1, E4, E7 and E10, respectively. The difference is that the electrode coverage of MOV of CE9-CE12 is 100%.

[0084] The structural summary of the (composite) circuit protection devices E1-E12 and CE1-CE12 is shown in Table 2.

[0085] Table 2

[0086]

[0087]

[0088] "--" indicates that the component does not exist.

[0089] Performance testing

[0090] [Surge immunity test]

[0091] Ten of each of the E1-E12 and CE1-CE12 (composite) circuit protection devices were taken as test samples for surge immune testing.

[0092] The surge immunoassay for each test sample was performed at a voltage greater than the MOV (600V). ac Or 700V ac The test was conducted under a current of 0.5A or an overcurrent (i.e., 10A) on the PPTC chip, with the first conductive lead 4 and the second conductive lead 5 connected for 60 seconds and then turned off. If neither the PPTC chip nor the MOV was burned or damaged, the test sample passed the surge immunoassay test, and the average time for the PPTC chip to trip was recorded (if tripping occurred). If either the PPTC chip or the MOV was burned, the test sample was considered burned, and the average time for the burnout was recorded. The results are shown in Table 3.

[0093] Table 3

[0094]

[0095]

[0096] Table 3 shows that the test samples CE1-CE4 containing only MOV burned out within 5.2 seconds under an overcurrent of 0.5A and a voltage of at least 1.6 times the varistor voltage of the MOV (generally, MOVs can withstand a voltage of 1.2 times their varistor voltage), or burned out within 1.0 seconds under an overcurrent and overvoltage of 10A, and the damage was irreparable. Furthermore, the test samples CE5-CE8 containing only PPTC chips burned out under an overcurrent of 0.5A or 10A.

[0097] Although the CE9-CE12 test samples contained PPTC chips and MOVs, the electrode coverage of both PPTC chips and MOVs was 100%, and both PPTC chips and MOVs burned out under overcurrent and overvoltage conditions of 0.5A and 10A respectively.

[0098] Conversely, all test samples in E1-E12 containing combinations of PPTC chips and MOVs (where the electrode coverage of PPTC chips and / or MOVs was less than 90%) passed the surge immunoassay test without burning out, indicating that the reduction in the area of ​​the electrode layer of PPTC chips and / or MOVs can effectively prevent damage to the circuit protection device.

[0099] Furthermore, compared to E1-E3, the perforated test samples of the PPTC chip and / or MOV in E4-E12 improve heat transfer, further shortening the tripping time of the PPTC chip and preventing overcurrent from flowing through the MOV, thus protecting the MOV from burnout. In other words, in the E1-E12 test samples, the PPTC chip trips before the MOV burns out under overcurrent and voltages greater than the MOV's varistor voltage.

[0100] In summary, by controlling the area of ​​each electrode layer of the PTC element 2 to be smaller than the area of ​​its respective PTC surface 211, and / or controlling the area of ​​each electrode layer of the varistor 3 to be smaller than the area of ​​its respective resistor surface 311, the PTC element quickly jumps to a high resistance state under the presence of overcurrent and overvoltage, thereby protecting the varistor from burning out due to unwanted arcing. The composite circuit protection device of this invention can thus be reused, exhibiting excellent tolerance and reliability, and thus effectively achieves the purpose of this invention.

[0101] The above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and description of the present invention shall still fall within the scope of the present invention.

Claims

1. A composite circuit protection device, characterized in that: Include: PTC components include: The PTC layer has two opposite PTC surfaces, and The first electrode layer and the second electrode layer each have an electrode surface that is connected to one of the two opposite PTC surfaces of the PTC layer; Varistors, including: The varistor layer has two opposite resistor surfaces. The third electrode layer has an electrode surface that connects one of the two opposite resistor surfaces of the varistor layer and is disposed between the one of the two opposite resistor surfaces of the varistor layer and the second electrode layer of the PTC element. The fourth electrode layer has an electrode surface that connects to the other of the two opposite resistor surfaces of the varistor layer. A first conductive lead is connected to the first electrode layer; and The second conductive lead is connected to one of the third and fourth electrode layers of the varistor. The area of ​​the electrode surface of the first electrode layer and the second electrode layer is 70% to 90% of the area of ​​the PTC surface, and the area of ​​the electrode surface of the third electrode layer and the fourth electrode layer is 70% to 90% of the area of ​​the resistor surface.

2. The composite circuit protection device according to claim 1, characterized in that: The rated voltage of the PTC element is 45% to 200% of the varistor voltage measured at 1mA.

3. The composite circuit protection device according to claim 1, characterized in that: The rated voltage of the PTC element is 45% to 100% of the varistor voltage measured at 1mA.

4. The composite circuit protection device according to claim 1, characterized in that: The rated voltage of the PTC element is 45% to 70% of the varistor voltage measured at 1mA.

5. The composite circuit protection device according to claim 1, characterized in that: The PTC element trips before the varistor burns out when subjected to overcurrent and a voltage greater than the varistor's varistor voltage.

6. The composite circuit protection device according to claim 5, characterized in that: The PTC element trips within 1μs to 100s when subjected to an overcurrent greater than 0.1A and a voltage greater than the varistor voltage.

7. The composite circuit protection device according to claim 5, characterized in that: The PTC element trips within 1ms to 10s when subjected to an overcurrent greater than 0.5A and a voltage greater than the varistor voltage.

8. The composite circuit protection device according to claim 5, characterized in that: The PTC element trips within 1ms to 1s when subjected to an overcurrent greater than 10A and a voltage greater than the varistor voltage.

9. The composite circuit protection device according to claim 1, characterized in that: The PTC element has a first hole formed in the PTC layer.

10. The composite circuit protection device according to claim 9, characterized in that: The PTC layer of the PTC element has a periphery that defines the boundary of the PTC layer and interconnects with two opposite PTC surfaces of the PTC layer, and the first hole is spaced apart from the periphery of the PTC layer.

11. The composite circuit protection device according to claim 9, characterized in that: The first hole penetrates at least one of the two opposite PTC surfaces of the PTC layer.

12. The composite circuit protection device according to claim 11, characterized in that: The first hole also penetrates at least one of the first electrode layer and the second electrode layer.

13. The composite circuit protection device according to claim 1, characterized in that: The varistor has a second hole.

14. The composite circuit protection device according to claim 1, characterized in that: The composite circuit protection device further includes a third conductive lead, the second conductive lead being connected to the fourth electrode layer, and the third conductive lead being connected to and disposed between the second electrode layer and the third electrode layer.

15. The composite circuit protection device according to claim 1, characterized in that: The varistor has a second hole formed in the varistor layer.

16. The composite circuit protection device according to claim 15, characterized in that: The varistor layer of the varistor has a periphery that defines the boundary of the varistor layer and interconnects with two opposite resistor surfaces of the varistor layer, and the second hole is spaced apart from the periphery of the varistor layer.

17. The composite circuit protection device according to claim 15, characterized in that: The second hole penetrates at least one of the two opposite resistor surfaces of the varistor layer.

18. The composite circuit protection device according to claim 17, characterized in that: The second hole also penetrates at least one of the third electrode layer and the fourth electrode layer.

19. The composite circuit protection device according to claim 1, characterized in that: The PTC element is a polymer PTC element, and the PTC layer is a PTC polymer layer.

20. The composite circuit protection device according to claim 1, characterized in that: The composite circuit protection device further includes an encapsulation material that encapsulates the PTC element, the varistor, a portion of the first conductive lead, and a portion of the second conductive lead.

Images