Phase synchronization update without sync signal transmission

Abstract

The present disclosure relates to phase synchronization updates without synchronization signal transmission. Embodiments of the present disclosure provide systems and methods for implementing phase synchronization updates based on an input system reference signal SYSREF without the need for synchronous distribution of the SYSREF signal on a high-speed domain. In particular, the phase synchronization mechanism of the present invention is based on maintaining a first phase accumulator in a device clock domain and asynchronously transmitting phase updates to a final digital clock domain using a second phase accumulator in a final digital clock domain. The arrival of a new SYSREF pulse can be detected based on a count value of the first phase accumulator, which is asynchronously transmitted and scaled to a second phase delay adder downstream. In this way, even if the SYSREF signal itself is not synchronously transmitted to the second phase delay adder, the phase update of the SYSREF signal can be transmitted downstream, so that the final phase can be deterministically generated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 63 / 062,561, filed on August 7, 2020, entitled “PHASE SYNC UPDATE WITHOUT SYNC SIGNAL TRANSMISSION,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to systems and methods for synchronizing clock signals between multiple electronic components using phase synchronization updates. Background Art

[0004] The competitive nature and market forces of the integrated circuit (IC) industry tend to encourage the production of digital logic in the most advanced process nodes with the highest available clock speeds. The clock is typically driven by a phase-locked loop (PLL) that is configured to output a clock signal (often referred to as the "PLL reference clock signal" or simply "PLL clock" or "PLL output") that is based on a lower-speed device clock signal, where the device clock signal is a reference clock signal from the master IC input. A variety of applications, whether precision instrumentation or wireless communications, often require synchronization of digital components between multiple ICs (or within a single IC). This is sometimes referred to as multi-chip synchronization / synchronization (MCS). These components often rely on digital counters (often called "phase accumulators" or "phase accumulators"), where the arrival of a system reference (SYSREF) signal pulse resets the phase of the counter-based component (hence, the SYSREF signal is sometimes also called the "reset signal"). An example is a numerically controlled oscillator (NCO), which is based on the use of such a phase-accumulating counter.

[0005] Typically, the process of MCS involves distributing a synchronous SYSREF signal along with a PLL reference clock signal to multiple chips in a system. It is difficult to synchronously distribute the SYSREF signal throughout the IC when the PLL is running at a leading-edge frequency. To address this requirement, the high-speed clock output of the PLL is sometimes gated (i.e., prevented from being further distributed, beyond a large amount) so that downstream logic can be gated in a "clock-off" mode before the SYSREF reset signal triggers synchronous non-gating of the clock signal to be distributed. Unfortunately, this approach prevents further SYSREF-based phase updates by changing the clock and / or reset signals without disturbing the downstream logic. Summary of the invention

[0006] According to one aspect of the present disclosure, a system for generating phase updates for synchronous integrated circuit (IC) components is provided, the system comprising: a phase-locked loop (PLL) circuit configured to receive a device clock signal and generate a PLL clock signal having a frequency greater than the device clock signal; a clock divider circuit configured to generate a final digital clock signal based on the PLL clock signal; a first phase accumulator configured to generate a first phase update based on the final digital clock signal; a second phase accumulator configured to generate a second phase update based on the device clock signal, wherein each of the first phase update and the second phase update indicates the arrival of a pulse of a system reference (SYSREF) signal; and a combiner configured to generate a phase update based on the first phase update and the second phase update.

[0007] According to another aspect of the present disclosure, a timing arrangement for synchronizing one or more integrated circuit (IC) components is provided, comprising: a first counter configured to count the number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a phase-locked loop (PLL) clock signal, the PLL clock signal is based on a device clock signal, and the frequency of the final digital clock signal is greater than the frequency of the device clock signal; a second counter configured to count the number of cycles of the device clock signal; and a phase update circuit configured to generate a phase update indicating the arrival of a pulse of a system reference (SYSREF) signal based on outputs of the first counter and the second counter.

[0008] According to another aspect of the present disclosure, a method for synchronizing one or more integrated circuit (IC) components is provided, the method comprising: counting the number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a phase-locked loop (PLL) clock signal, the PLL clock signal is based on a device clock signal, and the frequency of the final digital clock signal is greater than the frequency of the device clock signal; counting the number of cycles of the device clock signal; and generating a phase update indicating the arrival of a pulse of a system reference (SYSREF) signal based on the counted number of cycles of the final digital clock signal and the counted number of cycles of the device clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0010] FIG. 1 provides a schematic diagram of a conventional system for providing phase synchronization updates.

[0011] Figure 2Provided is a schematic diagram of a system configured to provide phase synchronization updates without synchronization signal transmission according to some embodiments of the present disclosure;

[0012] Figure 3 A timing diagram illustrating how multiple phase accumulators may be synchronized during an MCS process according to some embodiments of the present disclosure is provided;

[0013] Figure 4 A timing diagram is provided that illustrates how the arrival of a new SYSREF pulse starts the process of transmitting a new phase offset to generate a final phase without synchronization signal transmission according to some embodiments of the present disclosure;

[0014] Figure 5 Provided is a schematic diagram of an electronic device that can implement phase synchronization update without synchronization signal transmission according to some embodiments of the present disclosure;

[0015] Figure 6 is a block diagram of an example system according to some embodiments of the present disclosure, which example system may include one or more systems configured to provide phase synchronization updates without synchronization signal transmission;

[0016] Figure 7 is a block diagram of an example radio frequency (RF) device according to some embodiments of the present disclosure, which may include one or more systems configured to provide phase synchronization updates in the absence of synchronization signal transmission;

[0017] Figure 8 A block diagram is provided illustrating an example data processing system according to some embodiments of the present disclosure that may be configured to control operation of one or more systems configured to provide phase synchronization updates without synchronization signal transmissions. DETAILED DESCRIPTION

[0018] Overview

[0019] Embodiments of the present disclosure provide systems and methods for implementing phase synchronous updates based on an input SYSREF signal without the need for synchronous distribution of the SYSREF signal. In the context of the present disclosure, a SYSREF signal can be described as being distributed "synchronously" if it is distributed to various IC components in a manner that substantially maintains a predefined delay between the arrival of a pulse in the SYSREF signal and a final digital clock signal generated based on a PLL clock in the high-speed domain (e.g., when the SYSREF signal is clocked with a high-speed clock). Synchronously distributing SYSREF signals in a high-speed domain is often difficult due to the strict setup and hold constraints of ultra-high-speed digital signal transmission. In addition, providing phase synchronous updates without synchronous signal transmission can advantageously reduce or eliminate the need to synchronously transmit SYSREF signals over long conductive traces within an IC. In particular, the phase synchronization mechanism of the present disclosure is based on maintaining a first phase accumulator in the final digital clock domain (i.e., clocked with a final digital clock generated based on a PLL output clock) and using a second phase accumulator in the device clock domain (i.e., clocked with a device clock, which is typically much slower than the PLL output clock) to asynchronously transmit phase updates to IC components operating in the final digital clock domain. As used herein, the term "phase update" (which may be used interchangeably with the term "phase synchronization update") refers to information indicating the arrival time of a new pulse of the SYSREF signal, which indicates a new phase (thus, it is an update) that needs to be distributed to other devices. In some embodiments, the first phase accumulator may be a local multi-frame clock (LMFC) counter for JESD operations, and is therefore referred to as a "LMFC phase counter" or simply "LMFC counter" hereinafter. The second phase accumulator may be another phase counter and may be referred to as a "shadow phase accumulator" or "shadow counter" hereinafter. In some embodiments, the shadow counter may have a programmable reset period to allow an integer or power-of-two phase relationship with the LMFC counter. The LMFC counter may be configured to generate a first phase update based on (e.g., by being clocked) a final digital clock signal. To this end, the LMFC counter may be configured to count clock cycles of the final digital clock signal. The shadow counter may be configured to generate a second phase update based on (e.g., by being clocked) a device clock signal. To this end, the shadow counter may be configured to count clock cycles of the device clock signal. Each of the first phase update and the second phase update indicates the arrival of a pulse of the SYSREF signal. The arrival of a new SYSREF phase (i.e., a new pulse of the SYSREF signal arriving at an unexpected device clock cycle) can then be detected based on the counter value of the shadow counter, whose value can be asynchronously transferred (i.e., transferred in a manner that does not require a fixed transfer delay relative to the final digital clock) to the final digital clock domain and scaled to the count of the LMFC counter to provide a final phase update (denoted as "Final Phase" in this figure).In other words, a final phase update indicating the arrival of a new SYSREF pulse may be generated based on a phase update provided by the value of the shadow counter in addition to a phase update provided by the value of the LMFC counter. In this manner, even though the SYSREF signal itself is not synchronously transmitted to the LMFC counter as is done in conventional implementations, the phase update from the SYSREF signal may be deterministically transmitted downstream (i.e., toward the LMFC counter and other IC components that are clocked with the final digital clock signal) so that the system may generate and use the final phase update to synchronize the various IC components to the SYSREF signal. For example, in some embodiments, different components of a JESD system may use the final phase update to determine when to begin a new multi-frame boundary within the framing operation described in the JESD 204 specification.

[0020] Although the embodiments described herein may involve an MCS via an input SYSREF signal, the systems and methods described herein for providing phase synchronous updates without synchronization signal transmission may be used to transmit phase updates between any type of phase accumulators within an IC, particularly if the phase accumulators are separated in a manner that may make it difficult to synchronously transmit phase update signals (e.g., due to high speed PLLs).

[0021] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and drawings.

[0022] As will be appreciated by those skilled in the art, aspects of the present disclosure, in particular aspects of providing phase synchronization updates without synchronization signal transmission as proposed herein, can be embodied in various ways—for example, as a method, a system, a computer program product, or a computer-readable storage medium. Therefore, aspects of the present disclosure can take the form of a full hardware embodiment, a full software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which can be collectively referred to herein as a "circuit", "module" or "system". The functions described in the present disclosure can be implemented as an algorithm executed by one or more hardware processing units (for example, one or more microprocessors of one or more computers). In various embodiments, different steps and parts of steps of each method described herein can be performed by different processing units. In addition, aspects of the present disclosure can take the form of a computer program product contained in one or more computer-readable media, preferably non-transitory, with computer-readable program code embodied (for example, stored) thereon. In various embodiments, such a computer program can, for example, be downloaded (updated) to existing devices and systems (for example, existing transceivers, such as RF transceivers, receivers, transmitters and / or their controllers, etc.), or stored when these devices and systems are manufactured.

[0023] The following detailed description presents various descriptions of certain embodiments. However, the innovation described herein can be embodied in many different ways, for example, as defined and covered by the selected examples.

[0024] In the following description, reference is made to the accompanying drawings in which like reference numerals may represent identical or functionally similar elements. It should be understood that the elements shown in the accompanying drawings are not necessarily drawn to scale. In addition, some embodiments may incorporate any suitable combination of features from two or more of the accompanying drawings. In addition, it should be understood that certain embodiments may include more elements than a subset of the elements shown in the accompanying drawings and / or the accompanying drawings. In general, although some of the drawings provided herein illustrate various aspects of providing phase synchronization updates in the absence of synchronization signal transmissions, and systems in which such circuits may be implemented, the details of these systems may differ in different embodiments. For example, various components of the systems presented herein for providing phase synchronization updates in the absence of synchronization signal transmissions may have additional components contained therein or coupled thereto that are not specifically shown in the figures, such as logic, storage, passive elements (e.g., resistors, capacitors, inductors, etc.) or other elements (e.g., transistors, etc.). In another example, the details shown in some of the drawings (e.g., by Figure 2), for example, specific arrangements and example implementation details of various components of a system for providing phase synchronization updates without synchronization signal transmission, and / or specific arrangements of coupling connections (e.g., using Figure 2 The coupling connection of the multiplexer shown in the figure, etc.) may be different in different embodiments, and the illustration of this figure only provides some examples of how these components can be used together to provide phase synchronization updates without synchronization signal transmission. In another example, although some embodiments shown in this figure illustrate a certain number of components (for example, Figure 2 ), it should be understood that, based on the description provided herein, these embodiments may be implemented with any number of these components. In addition, although certain elements of various elements of the system for providing phase synchronization updates without synchronization signal transmission, such as Figure 2 The systems shown in may be depicted in the figures as being communicatively coupled using a single depicted line, but in some embodiments, any of these elements may be coupled via multiple conductors, such as may be present in a bus, or when differential signals are involved.

[0025] The description may use the phrase "in one embodiment" or "in an embodiment", each of which may refer to one or more identical or different embodiments. Unless otherwise indicated, the use of ordinal adjectives "first", "second" and "third" etc. to describe a common object only indicates that different instances of the same object are referred to, and does not mean to imply that the objects described in this manner must be arranged in a given order in time, space, ranking or in any other way. In addition, for the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" refers to (A), (B) or (A and B), while the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). As used herein, the symbol "A / B / C" refers to (A, B and / or C). The term "between", when used for a measurement range, includes the end of the measurement range.

[0026] Various aspects of the illustrative embodiments are described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" refers to a direct electrical connection between connected things without any intermediate devices / components, while the term "coupled" refers to a direct electrical connection between connected things, or an indirect electrical connection through one or more passive or active intermediate devices / components. In another example, the term "circuit" refers to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. Sometimes, in this description, the term "circuit" may be omitted (e.g., a PLL circuit may be referred to as "PLL", etc.). Similarly, sometimes, in this description, the term "signal" may be omitted (e.g., a SYSREF signal may be referred to as "SYSREF", etc.). If used, the terms "substantially", "approximately", "roughly", "approximately", etc. may be used to generally refer to within + / -20% of a target value, such as within + / -10% of a target value, based on the context of a specific value as described herein or known in the art.

[0027] Provides a general implementation of phase-synchronous updates

[0028] FIG1 provides a schematic diagram of a conventional system 100 for providing phase synchronization updates. As shown in FIG1 , the SYSREF signal 101 may pass through a series of digital flip-flops (DFFs) or registers (shown as DFF 102, DFF 104, and DFF 106 in FIG1 , although there may be more flip-flops in the path of the SYSREF signal 101 in other embodiments) to avoid ambiguity and be synchronously transmitted to the LMFC counter 110, which is configured to generate / output a final phase 111 used by the JESD system to determine when to start a new multi-frame boundary in the framing operation described in the JESD 204 specification. In particular, from the last flip-flop (DFF 106 in the example shown in FIG1 ), the SYSREF signal 101 is provided to the multiplexer 108. Multiplexer 108 is configured to reset the count of LMFC counter 110 when it detects a new pulse in the SYSREF signal provided to multiplexer 108 (this is why the signal provided to multiplexer 108 from the last flip-flop 106 is labeled "Phase Reset" in FIG. 1 ). A final phase 111 is then output by LMFC counter 110 (which may include logic to produce such an output), which is a phase update indicating the arrival of a pulse in SYSREF signal 101.

[0029] The system 100 also shows the various clock signals that the different components of the system 100 are running on (i.e., the clock signals that the different components are clocked by), as well as the clock inputs of these components (the clock inputs of the components are shown in FIG. 1 and subsequent figures as small triangles on the periphery of the box illustrating the component, with arrows with the corresponding clock signals pointing to the box). For example, the device clock signal 111 is illustrated in FIG. 1 as the clock signal of the flip-flop 102 because the arrow with the device clock signal 111 points to the triangle illustrating the clock input of the flip-flop 102. The device clock signal 111 can be a relatively low-speed clock. The device clock signal 111 is also provided to the PLL 112, which is configured to generate a PLL clock signal 113 having a frequency greater than the frequency of the device clock signal 101. The flip-flop 104 is clocked with the PLL clock signal 113. FIG. 1 further shows a clock divider 114, which is configured to generate a final digital clock signal 115 based on the PLL clock signal 113 provided thereto. Each of the flip-flop 106 , the multiplexer 108 , and the LMFC counter 110 is clocked with the final digital clock signal 115 .

[0030] 1 , first, the SYSREF signal 101 is clocked with a relatively low-speed device clock 111 at the flip-flop 102. However, the SYSREF signal 101 is then passed to the peripheral PLL flip-flop, i.e., flip-flop 104, where it is clocked with a relatively high-speed PLL clock signal 113 generated by the PLL 112. From the flip-flop 104, it may become very difficult to synchronously transfer the SYSREF signal 101 to the LMFC counter 110 to generate the final phase signal 111 based on the phase update of the SYSREF signal 101.

[0031] Provides phase-synchronous updates without sync signal transmission

[0032] Embodiments of the present disclosure propose systems and methods for providing a phase update of a SYSREF signal without distributing the SYSREF signal to a LMFC counter in the high-speed domain of a final digital clock signal.

[0033] Figure 2 A schematic diagram of a system 200 configured to provide phase synchronization updates without synchronization signal transmission according to some embodiments of the present disclosure is provided. Compared to conventional implementations, as shown in FIG1 , the system 200 includes components 202-214, which can be viewed as part of a shaded block 230, Figure 2200 has a dashed rectangular outline. Together with the state machine 218, the synchronization component 220, and the gate 224, the components of the dashed box 230 are used to provide a phase update of the SYSREF signal without synchronously transmitting the SYSREF signal to the LMFC counter 228. In some embodiments, for example, the components of the system 200 other than the shadow counter 202 and the LMFC counter 228 can be considered as the "phase update circuit" of the system 200.

[0034] In the following, the coupling between various components is first described, followed by the Figure 3 and 4 The timing diagram shown in is used to further illustrate the functions of the various components of system 200.

[0035] like Figure 2 As shown, the SYSREF signal may first be received by a flip-flop 216, similar to the flip-flop 102 shown in FIG. 1, clocked by the device clock 111. The device clock 111 is provided to a PLL 222, similar to the PLL 112, configured to generate a higher speed PLL output clock 113 based on the lower speed device clock 111. Figure 2 As shown, the PLL output clock is provided to a first input of a gate 224. A second input of the gate 224 is coupled to the output of the state machine 218, and the output of the gate 224 is coupled to a clock divider 226. The clock divider 226 may be similar to a conventional clock divider, such as the clock divider 114 shown in FIG. 1 , configured to generate a final digital clock signal 227 based on the PLL clock signal 113 provided thereto, except that the PLL clock signal 113 is now provided to the clock divider 226 via the gate 224. In some embodiments, the gate 224 may be an AND gate (or may include a plurality of logic elements configured to implement the AND gate functionality).

[0036] Turning to the details of block 230, similar to flip-flop 216, shadow counter 202 can also be configured to operate under device clock signal 111, such as Figure 2 As shown, the arrow goes from the device clock signal 111 to the clock input of the shadow counter 202. To this end, when the system 200 is initialized and receives one of the first pulses of the SYSREF signal (e.g., when the system 200 receives the first pulse or the first pulse of the SYSREF signal), the system 200 can be configured to reset the shadow counter 202, which can be done in a variety of ways. This is done in Figure 2 This is shown in FIG. 1 by a dashed arrow from SYSREF to the shadow counter 202, although in a particular implementation it need not be done directly and may be done, for example, by a state machine 218 coupled to the shadow counter 202, such as Figure 2208. The shadow counter 202 may be configured to count cycles of the device clock signal 111 and provide its output 203 to the multiplexer 204. The output of the multiplexer 204 may be provided to a transmit replica component / circuit 206, wherein an output 207 of the transmit replica component 206 may be provided as a second input to the multiplexer 204 and an optional scaling component / circuit 208. The transmit replica component 206 may also be configured to operate with the device clock 111, as shown. Figure 2 206. The output 209 of the scaling component 208 may be provided to a multiplexer 210. If the scaling component 208 is not implemented, the transmit replica component output 207 may be provided as an input to the multiplexer 210. The multiplexer 210 may be configured to receive the output 221 of the synchronization component 220, as shown in FIG. Figure 2 As indicated by the arrow from the synchronization component 220 to the multiplexer 210. The output of the multiplexer 210 may be provided to a receive replica component / circuit 212, wherein the output 213 of the receive replica component 212 may be provided as a second input to the multiplexer 210 and a combiner 214 (e.g., an adder), the combiner 214 (e.g., an adder) being configured to generate a final phase 215 228 based on the receive replica component output 213 and the output 229 of the LMFC counter (e.g., by adding the outputs 213 and 229). The receive replica component 212 may be configured to operate on a final digital clock 227 generated by a clock divider 226, as shown. Figure 2 This is shown by the arrow from the final digital clock signal 227 to the clock input of the receiving replica component 212.

[0037] Returning to flip-flop 216, the output of flip-flop 216 indicates a phase update in the SYSREF signal, such as Figure 2 As shown, the output of flip-flop 216 is labeled "Phase Update". Figure 2 As shown, the output can be provided to each of the state machine 218, the synchronization component 220 and the multiplexer 204. The synchronization component 220 can be configured to operate under the final digital clock 227 generated by the clock divider 226, such as Figure 2216, which is shown by an arrow from the final digital clock to the clock input of the synchronization component 220. In some embodiments, the synchronization component 220 may be implemented as a series of two flip-flops or registers one after the other, although in other embodiments, the synchronization component 220 may be implemented in any other manner that allows the synchronization component 220 to transmit an asynchronous input (in this case, the phase-updated output of the flip-flop 216) to the output 221 of the synchronization component 220, which may be clocked synchronously with the final digital clock 227. In this case, the phase-updated output of the flip-flop 216 will be captured by the receiving replica component 212, through the path of the multiplexer 210, as shown. Figure 2 As shown, it runs synchronously on the final digital clock 227.

[0038] like Figure 2 As shown, the output 219 of the state machine 218 may be provided to each of the shadow counter 202, the gate 224, the clock divider 226, and the LMFC counter 228. The state machine 218 may be configured to receive the SYSREF signal 101 and the state machine output 219 may indicate a phase update of the SYSREF signal. The state machine 218 may be viewed as logic configured to control the operation of the shadow counter 202, the gate 224, the clock divider 226, and the LMFC counter 228 for a portion of an MCS program that is run at startup of the system 200. In particular, the state machine 218 may be viewed as logic configured to control the reset of the shadow counter 202, the clock divider 226, and the LMFC counter 228 based on the receipt of the initial phase (i.e., initial pulse) of the SYSREF signal 101. With respect to gate 224, state machine 218 may be configured to control when gate circuit 224 transmits PLL clock 113 to clock divider 226 to generate final digital clock 227 based on receipt of an initial pulse of SYSREF signal 101. LMFC counter 228 may be configured to operate at final digital clock 227 generated by clock divider 226, as shown in FIG. Figure 2 228. Thus, the LMFC counter 228 can be configured to count the cycles of the final digital clock 227 provided to it from the clock divider 226 and be reset when required by the state machine 218. The output 229 of the LMFC counter 228 can be provided to the combiner 214, as shown in FIG. Figure 2 This is indicated by the arrow from LMFC counter 228 to combiner 214.

[0039] Figure 3A timing diagram 300 is provided that illustrates how multiple phase accumulators (including clock dividers) in a chip according to some embodiments of the present disclosure may be synchronized during an MCS process. The various signals shown in the timing diagram 300 are labeled on the left side of the diagram, with reference to the above and Figure 2 . Thus, timing diagram 300 illustrates, from top to bottom, SYSREF signal 101, device clock signal 111, PLL clock signal 113, final digital clock signal 227, state machine output 219, flip-flop output 217, shadow counter output 203, and LMFC counter output 229. As is conventional with timing diagrams, time is measured along the horizontal axis of timing diagram 300. Timing diagram 300 illustrates how LMFC counter 228 and shadow counter 202 (i.e., two different phase accumulators of system 200) may be synchronized when system 200 is first initialized / started / activated. Thereafter, system 200 may distribute phase updates for subsequent SYSREF pulses, such as Figure 4 As shown in the timing diagram.

[0040] Figure 3 An embodiment is illustrated in which the initial synchronization between the LMFC counter 228 and the shadow counter 202 is performed based on an MCS procedure, as is conventionally used to synchronize the LMFC counter 228 to the SYSREF signal 101, although in other embodiments, any other procedure for synchronizing the initial counts of the LMFC counter 228 and the shadow counter 202 may be implemented and is within the scope of the present disclosure. Figure 3 The difference from the conventional MCS initial synchronization process lies in the synchronization of the shadow counter 202 with the SYSREF signal 101 and the LMFC counter 228, and the function of the state machine 218 with respect to the synchronization.

[0041] like Figure 3 As shown, the arrival of pulse 302 in SYSREF signal 101 causes the change of output 217 of flip-flop 216, that is, pulse 304 ( Figure 3 and Figure 4 The causal relationship is represented by the dashed arrows in the timing diagram of FIG. 1 , such as shown in this case between the start of pulse 302 and the start of pulse 304). Flip-flop output 217 is synchronized with SYSREF signal 101 because both are clocked with device clock 111. Therefore, Figure 3 As shown, the last edge of pulse 302 can be substantially aligned with the end of the cycle of device clock 111, and can also be aligned with the starting edge of pulse 304 (so that when pulse 302 ends, the starting edge of pulse 304 can be aligned with the end of the cycle of device clock 111), and similarly as Figure 3 shown.

[0042] In turn, the pulse 304 in the flip-flop output 217 causes the state of the state machine 218 to change, so that the output 219 of the state machine 218 changes from "ready" to "stop". Figure 3 As shown, such a change may occur after one clock cycle of the device clock 111, although in other embodiments, the change of the state of the state machine 218 from "ready" to "stopped" may take more than one device clock cycle 111. Figure 3 As shown, in some embodiments, the state machine 218 can be run on the device clock 111. In some embodiments, the state machine 218 can be a state machine with at least 4 states. Figure 3 226 and the clock divider 226 do not generate the final digital clock 227. This is in the state machine 218. Figure 3 , where the final digital clock 227 stops after the output 219 of the state machine 218 switches to indicate that the state machine 218 is in the "stop" state. Figure 3 As shown, the state machine 218 may remain in the “stopped” state for the duration of one clock cycle of the device clock 111 , although in other embodiments, the state machine 218 may remain in the “stopped” state for the duration of more than one cycle of the device clock 111 .

[0043] At the end of the "Stop" state, the state machine 218 switches to the "Reset" state. As a result, an output 219 indicating a reset is provided from the state machine 218 to each of the shadow counter 202 and the LMFC counter 228 (eg, Figure 2 As shown, the respective arrows are marked "reset"), which causes the output 203 of the shadow counter 202 and the output 229 of the LMFC counter 228 to be reset to some initial values. The initial values ​​of both are Figure 3 202 and LMFC counter 228 may be any other value (e.g., any other integer value), and, in general, the initial values ​​of the shadow counter 202 and the LMFC counter 228 may be, but need not be, the same. When the state machine 218 is in the "reset" state, the final digital clock 227 generated by the clock divider 226 may remain off, such as Figure 3 As shown. Figure 3As shown, state machine 218 may remain in the “reset” state for the duration of one clock cycle of device clock 111 , although in other embodiments, state machine 218 may remain in the “reset” state for the duration of more than one cycle of device clock 111 .

[0044] At the end of the "Reset" state, the state machine 218 switches to the "Complete" state. When the state machine 218 switches to the "Complete" state, it starts generating the final digital clock again by providing an output signal 219 to the gate 224 indicating that the state machine 218 is in the "Complete" state. The gate 224 then passes the PLL clock 113 to the clock divider 226 and the clock divider 226 generates the final digital clock 227. This Figure 3 , where the final digital clock signal 227 starts again after the state machine 218 switches to the "Complete" state. Since the final digital clock is running again, the LMFC counter 228 starts counting the cycles of the final digital clock 227 from the initial value. This is shown in FIG. Figure 3 The restart of the final digital clock 227 and the output value 229 of the LMFC counter 228 are incremented by 1 from the initial value after the state machine 218 switches to the "Complete" state (i.e., for Figure 3 2, where the initial value of LMFC counter 228 is 0 and the value of 1 is shown by an arrow between them. Similarly, after state machine 218 switches to the "Complete" state, shadow counter 202 also starts counting cycles of device clock 111 (because shadow counter 202 runs on device clock 111), starting from the initial value. Figure 3 The first cycle of the device clock 111 ends after the state machine 218 switches to the "Complete" state and the output value 203 of the shadow counter 202 is incremented by 1 from the initial value (i.e., for Figure 3 In the example shown, an arrow between the initial value of shadow counter 202 is 0 and the value of 1 is shown.

[0045] Figure 4 A timing diagram 400 is provided that illustrates how the arrival of a new SYSREF pulse 402 of the SYSREF signal 101 begins the process of transmitting a new phase offset to generate the final phase 215 without synchronization signal transmission according to some embodiments of the present disclosure. Figure 3 Similarly, the various signals shown in timing diagram 400 are labeled Figure 4 On the left side of the figure, refer to the above and Figure 2Thus, timing diagram 400 shows, from top to bottom, SYSREF signal 101, device clock signal 111, final digital clock signal 227, flip-flop output 217, shadow counter output 203, LMFC counter output 229, transmit replica component output 207, sync component output 221, receive replica component output 213, and final phase 215 (i.e., output 215 of combiner 214).

[0046] The new SYSREF pulse 402 may be, for example, the next pulse in the SYSREF signal 101 after the system 200 has been initialized and the shadow counter 202 and the LMFC counter 228 begin counting simultaneously, for example, as Figure 3 Consider Figure 4 , where just before pulse 402 arrives, the value of shadow counter 202 is 0 and the value of the LMFC counter is also 0, although in other embodiments these values ​​may be different and need not be the same.

[0047] like Figure 4 As shown, the arrival of pulse 402 in SYSREF signal 101 causes a change in the output of flip-flop 216, resulting in pulse 404 in flip-flop output 217. Figure 4 404. In turn, pulse 404 in trigger output 217 causes multiple actions in system 200. One action is that pulse 404 in trigger output 217 causes pulse 406 in output 221 of synchronization component 220 because trigger output 217 is provided to synchronization component 220 as a phase update. Figure 4 406. Pulses 404 and 406 are not aligned because flip-flop 216 and sync component 220 are not synchronized (the former is clocked on device clock 111 and the latter is clocked on final digital clock 227). Another action caused by pulse 404 in flip-flop output 217 is a change in output 207 of send replica component 206 because flip-flop output 217 is provided to multiplexer 204 associated with send replica component 206. This is shown in FIG. Figure 4 This is illustrated in FIG. 4 by the dashed arrow from the beginning of pulse 404 to the change in the output 207 of the send replica component. The change in the output 207 of the send replica component is aligned with the end of pulse 404 because the flip-flop 216 and the send replica component 206 are synchronized (i.e., both are clocked on the device clock 111). Because, for Figure 4 For example, at the end of pulse 404, the value of shadow counter 202 is 2, so the sending replica component output 207 is changed from any previous output it may have (e.g., the value 0, for Figure 4) is changed to the value of the shadow counter 202, i.e., to 2. Thus, the combination of the transmit replica component 206 and the multiplexer 204 can be viewed as the multiplexer 204 holding the output 207 of the transmit replica component 206 at whatever the last output was or at some predefined initial value (e.g., 0) for the duration until a new SYSREF pulse (e.g., pulse 402) of the SYSREF signal 101 arrives, as the shadow counter 202 continues to count, and only loading the latest value of the output 203 of the shadow counter 202 to the transmit replica component 206 when a new SYSREF pulse arrives.

[0048] Shadow counter 202 continues to count in the sequence of values ​​that shadow counter 202 is configured to pass. Such a sequence is Figure 4 In the example of , the shadow counter 202 is shown as 0, 1, 2, 3, and then the sequence repeats, although in other embodiments the shadow counter 202 can count to more than 3 or less than 3. Similarly, Figure 4 LMFC counter 228 is shown counting through a sequence of 0, 1, 2, 3, 4, 5, 6, 7 and then repeating the sequence, although in other embodiments LMFC counter 228 may count to greater than 7 or less than 7. Thus, at a given time, output 203 of shadow counter 202 is one of the values ​​of the sequence of values ​​that shadow counter 202 is configured to count through before restarting the sequence again (e.g., 0, 1, 2, 3, 4), and output 229 of LMFC counter 228 is one of the values ​​of the sequence of values ​​that LMFC counter 228 is configured to count through before restarting the sequence again (e.g., the sequence 0, 1, 2, 3, 4, 5, 6, 7).

[0049] Another action indirectly caused by pulse 404 is a change in the value of output 213 of receiving replica 212. Figure 4 4 is shown by the dashed arrow from the start of pulse 406 (caused by pulse 404) to the change in receiving the replica output 213. The scaling component 208 can be a component configured to change the value of the output 207 of the sending replica component 206 (i.e., the latest value of the shadow counter 202), counted on the device clock 111, to reflect the difference between the period of the device clock 111 and the period of the final digital clock 227 used by the LMFC counter 228. Figure 3 and 4 In the example shown, the final digital clock 227 is twice the device clock 111 (even if the two clock signals are not synchronized, it can be Figure 3 and 4406 ). Thus, as a result of pulse 406, output 209 of scaling component 208 becomes 4 (i.e., twice as much output 207 of replica component 206 was sent at the start of pulse 406). Output 209 of scaling component 208 is provided to multiplexer 210. In addition, output 221 of synchronization component 220 is provided to multiplexer 210. Multiplexer 210 is configured to pass the value of output 209 of scaling component 208 to receiving replica component 212 after the start of pulse 406 in the output of synchronization component 220. Receiving replica component 212 is configured to output the value of output 209 of scaling component 208 that has been loaded thereto after the start of pulse 406. In other words, receiving replica component 212 is configured to pass its input received from scaling component 208 to its output.

[0050] The output 213 of the receiving replication component 212 is provided to the combiner 214, which generates an output 215 as the final phase. The final phase 215 (i.e., the output of the combiner 214) is shown at Figure 4 In the last line of Figure 4 As shown, the final phase 215 first passes through the sequence 1, 2, 3, 4, 5, and 6, corresponding to the counter value of the LMFC counter 228, because the received replica input and thus the received replica output is 0. When the output 209 of the scaling component 208 changes to a value of 4 as described above, and because it is assumed in this example that the combiner 214 adds the values ​​received from the LMFC counter 228 and the received replica 212, the final phase 215 does not change from 6 to 7 as it would without the pulse 406, but rather from 6 to 3, where 3 is the result of adding the values ​​of 7 and 4 in the order in which the LMFC counter 228 counts (i.e., 7+4=11, but for Figure 4 In the example shown, LMFC counter 228 only counts to 7 and then starts the counting sequence again from 0, so 7 plus another 4 counts means a value of 3). Thereafter, final phase 215 continues to change as LMFC counter 228 counts (i.e., output 229) until a new SYSREF pulse 412 arrives and the phase update process begins from the beginning as described with respect to pulse 402.

[0051] Example Systems and Devices

[0052] System 200 may be implemented in any electronic device or system in which a distribution of phase updates of SYSREF signal 101 may be required. Some examples of such devices / systems are described in Figure 5-7 Shown in.

[0053] In some embodiments, system 200 can be implemented in a radio system. A radio system is a system that sends and receives signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems can be used in countless different applications, such as aircraft, automotive and industrial radars, cellular technology, Wi-Fi and other short-range communication technologies, and military applications. Figure 5 An example is shown in , which provides a schematic diagram of an electronic device 500 including an RF transceiver 510 and a baseband IC (BBIC) 520 coupled to the RF transceiver 510 using a high-speed serial interface 535 supported by, for example, JESD.

[0054] like Figure 5 As shown, RF transceiver 510 may include device clock circuit components 512 and PLL and clock divider circuits 514. Figure 5 As shown, the RF transceiver 510 may also include a digital component 530. The component 530 may include a JESD component 534, a digital core 536, and one or more digital data paths 538. The RF transceiver 510 may also include one or more receive (RX) paths 540 (in Figure 2 2 ), and one or more transmit (TX) paths 550 (shown in FIG. Figure 2 2214, RX path mixer 2216, and RX path post-mix filter 2218, as shown in FIG. 2215 . Each RX path 540 may include an RX mixer and filter circuit 542 and an RX converter circuit 544. Each TX path 550 may include a TX mixer and filter circuit 552 and a TX converter circuit 554. In some embodiments, the RX mixer and filter circuit 542 may include an RX path amplifier 2212, an RX path pre-mix filter 2214, an RX path mixer 2216, and an RX path post-mix filter 2218, as shown in FIG. Figure 7 As described above, the RX converter circuit 544 may include an analog-to-digital converter (ADC) 2220, also as described in reference Figure 7 In some embodiments, the TX mixer and filter circuit 552 may include a TX path amplifier 2222, a TX path post-mix filter 2224, a TX path mixer 2226, and a TX path pre-mix filter 2228, as described in reference Figure 7 As described, the TX converter circuit 554 may include a digital-to-analog converter (DAC) 2230, also as described in reference Figure 7 RX converter circuit 544 can be coupled to digital component 530 and RX mixer and filter circuit 542, and RX mixer and filter circuit 542 can be further coupled to one or more antennas ( Figure 5Not shown, but such an antenna can be implemented as a reference Figure 7 2202) described above, which are configured to wirelessly receive RF signals, such as those described in reference Figure 7 TX converter circuit 554 can be coupled to digital component 530 and TX mixer and filter circuit 552, and TX mixer and filter circuit 552 can be further coupled to one or more antennas configured to wirelessly transmit RF signals, as described in reference Figure 7 More detailed description. Digital component 530 may include digital processing unit 2208, control logic 2236 and Figure 7 One or more of the various other digital components of the RF device 2200.

[0055] In various embodiments, multiple components of system 200 may be implemented in different portions of RF transceiver 510. For example, shadow counter 202 may be implemented in device clock circuit component 512, while LMFC counter 228 may be implemented in JESD component 534. PLL 222, gate 224, and clock divider 226 may be implemented in PLL and clock divider circuit 514. Various other portions of system 200 may be included in other portions of RF transceiver 510.

[0056] The PLL and clock divider circuit 514 can be configured to provide the final digital clock 227 to various components of the RF transceiver 510, such as the digital component 530, and the RX path 540 and the TX path 550. These components can also receive phase updates in the manner described herein for receiving the final phase. The components can then use the final phase 215 to time their operations relative to the SYSREF signal 101, thereby synchronizing with the SYSREF signal 101 and therefore with each other. In some embodiments, such synchronization using the final phase 215 can be performed as known in the art based on the final phase provided by a conventional LMFC counter (e.g., such as the counter described with reference to FIG. 1). In some embodiments, synchronization between various IC components of the system can be performed as follows. For example, consider that each of IC components 1 and 2 is configured to operate under the final digital clock 227 and is configured to receive the final phase 215. The final phase 215 goes through a series of counts at the rate of the final digital clock 227 (i.e., at each cycle of the final digital clock 227, the final phase 215 switches to the next counter value in the sequence, where the sequence can be, for example, 0, 1, 2, 3, 4, 5, 6, 7, as in the example described above). The system can be configured so that when the final phase provided to IC components 1 and 2 is at a specific count (e.g., at a count of 2), IC components 1 and 2 should take a specific action. For example, the action can be that a specific state of IC components 1 and 2 is reset when the final phase 215 is at a specific count. In some embodiments, the state reset in this manner can be a multiframe boundary, which determines which frame or set of samples is the first in the sequence. This is important for the framer of the system because it needs to start the multiframe boundary at a deterministic time so that when the deframer queues its samples and releases the start of the multiframe on its LMFC, there is a deterministic delay between the framer sending the first sample in the multiframe and the deframer releasing it to the data path. Both the framer and deframer chips need to have their LMFC counters deterministically aligned with the SYSREF signal in order for them to work. Once all of this is in place, the overall latency on the JESD link is deterministic, despite asynchronous crossings and undefined routing delays in the traces on the board.

[0057] Figure 6 is a block diagram of an example system 2100 according to any embodiment disclosed herein, which may include one or more systems configured to provide phase synchronization updates without synchronization signal transmission. For example, any suitable components of the system 2100 may include one or more of the systems 200 and / or devices 500 as disclosed herein. Figure 62100, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in system 2100 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system on chip (SOC) die.

[0058] Additionally, in various embodiments, the system 2100 may not include Figure 6 , but the system 2100 may include interface circuitry for coupling to one or more components. For example, the system 2100 may not include the display device 2106, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2106 may be coupled. In another set of examples, the system 2100 may not include the audio input device 2118 or the audio output device 2108, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 2118 or the audio output device 2108 may be coupled.

[0059] The system 2100 may include a processing device 2102 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2102 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The system 2100 may include a memory 2104, which itself may include one or more storage devices, such as volatile memory (e.g., dynamic random access memory (RAM) (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk. In some embodiments, the memory 2104 may include a memory that shares a die with the processing device 2102. The memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0060] In some embodiments, the system 2100 may include a communication chip 2112 (e.g., one or more communication chips). For example, the communication chip 2112 may be configured to manage wireless communications to transmit data to and from the system 2100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0061] The communication chip 2112 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 2112 can be based on the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 2112 can operate according to GSM Evolution Enhanced Data (EDGE), GSM Evolution Enhanced Data Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2112 can operate according to code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), evolution data optimized (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2112 can operate according to other wireless protocols. The system 2100 may include an antenna 2122 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0062] In some embodiments, the communication chip 2112 can manage wired communication, such as electricity, light or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2112 can include multiple communication chips. For example, the first communication chip 2112 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 2112 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication chip 2112 can be dedicated to wireless communications, and the second communication chip 2112 can be dedicated to wired communications.

[0063] System 2100 may include battery / power circuitry 2114. Battery / power circuitry 2114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of system 2100 to an energy source separate from system 2100 (e.g., AC line power).

[0064] System 2100 may include a display device 2106 (or corresponding interface circuitry, as described above). Display device 2106 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0065] System 2100 may include an audio output device 2108 (or corresponding interface circuitry, as described above). Audio output device 2108 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0066] System 2100 may include an audio input device 2118 (or corresponding interface circuitry, as described above). Audio input device 2118 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0067] The system 2100 may include a GPS device 2116 (or corresponding interface circuitry, as described above). The GPS device 2116 may communicate with a satellite-based system and may receive the location of the system 2100, as is known in the art.

[0068] System 2100 may include other output devices 2110 (or corresponding interface circuitry, as described above). Examples of other output devices 2110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0069] The system 2100 may include other input devices 2120 (or corresponding interface circuitry, as described above). Examples of other input devices 2120 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0070] The system 2100 can have any desired form factor, such as a handheld or mobile electronic device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some embodiments, the system 2100 can be any other electronic device that processes data.

[0071] Figure 7 is a block diagram of an example RF device 2200 according to any of the embodiments disclosed herein, which RF device 2200 may include one or more components having one or more systems configured to provide phase synchronization updates without synchronization signal transmission. For example, any suitable component of the RF device 2200 may include a die including at least one system or a portion thereof configured to provide phase synchronization updates without synchronization signal transmission according to any of the embodiments disclosed herein. In some embodiments, the RF device 2200 may be included within any component of the system 2100, as described with reference to Figure 6 The RF device 2200 may also include a reference 2102, or may be coupled to any component of the system 2100, such as the memory 2104 and / or the processing device 2102 of the system 2100. Figure 6 Any components described, such as but not limited to battery / power circuit 2114, memory 2104, and various input and output devices, such as Figure 6 shown.

[0072] In general, the RF device 2200 can be any device or system that can support wireless transmission and / or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). In some embodiments, the RF device 2200 can be used for wireless communications, for example, in a base station (BS) or user equipment (UE) device of any suitable cellular wireless communication technology (e.g., GSM, WCDMA, or LTE). In a further example, the RF device 2200 can be used as or in a BS or UE device of, for example, a millimeter wave wireless technology such as fifth generation (5G) wireless (i.e., a high frequency / short wavelength spectrum, for example, a frequency in the range of about 20 to 60 GHz, corresponding to a wavelength in the range of about 5 to 15 mm). In yet another example, the RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., 2.4 GHz frequency band, corresponding to about 12 cm wavelength, or 5.8 GHz frequency band, spectrum, corresponding to about 5 cm wavelength), for example, in devices such as desktops, laptops, video game consoles, smart phones, tablets, smart TVs, digital audio players, cars, printers, etc. that support Wi-Fi. In some embodiments, a Wi-Fi-enabled device can be, for example, a node in a smart system that is configured to communicate data with other nodes (e.g., smart sensors). In another example, the RF device 2200 can be used for wireless communication using Bluetooth technology (e.g., a frequency band of about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 centimeters). In other embodiments, the RF device 2200 can be used to transmit and / or receive RF signals for purposes other than communication, such as in automotive radar systems, or in medical applications such as magnetic resonance imaging (MRI).

[0073] In various embodiments, the RF device 2200 may be included in a frequency division duplex (FDD) or time domain duplex (TDD) variant of the frequency allocation that may be used in a cellular network. In an FDD system, the uplink (i.e., the RF signal sent from the UE device to the BS) and the downlink (i.e., the RF signal transmitted from the BS to the US device) may use different frequency bands simultaneously. In a TDD system, the uplink and downlink may use the same frequency but at different times.

[0074] Multiple components in Figure 72200, but any one or more of these components may be omitted or duplicated as appropriate for the application. For example, in some embodiments, the RF device 2200 may be an RF device that supports both wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include components referred to herein as a transmit (TX) path and components referred to herein as a receive (RX) path. However, in other embodiments, the RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path; or the RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0075] In some embodiments, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single chip, for example, on a single SOC chip.

[0076] Additionally, in various embodiments, the RF device 2200 may not include Figure 7 2200, but the RF device 2200 may include interface circuits for coupling to one or more components. For example, the RF device 2200 may not include the antenna 2202, but may include antenna interface circuits (e.g., matching circuits, connectors, and driver circuits) to which the antenna 2202 may be coupled. In another set of examples, the RF device 2200 may not include the digital processing unit 2208 or the local oscillator 2206, but may include device interface circuits (e.g., connectors and supporting circuits) to which the digital processing unit 2208 or the local oscillator 2206 may be coupled.

[0077] like Figure 7 As shown, the RF device 2200 may include an antenna 2202, a duplexer 2204, a local oscillator 2206, and a digital processing unit 2208. Figure 7 As shown, the RF device 2200 may include an RX path, which may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an ADC 2220. Figure 7As further shown, the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a TX path post-mix filter 2224, a TX path mixer 2226, a TX path pre-mix filter 2228, and a DAC 2230. In addition, the RF device 2200 may also include an impedance tuner 2232, an RF switch 2234, and a control logic 2236. In various embodiments, the RF device 2200 may include Figure 7 2200. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form or be part of the RF front end (FE) of RF device 2200. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form or be part of the RFFE of RF device 2200. In some embodiments, RX path mixer 2216 and TX path mixer 2226 (possibly with Figure 7 ) may be considered to form or be part of an RF transceiver (or RF receiver or RF transmitter if only RX path or TX path components, respectively, are included in the RF device 2200) of the RF device 2200. In some embodiments, the RF device 2200 may also include one or more control logic elements / circuits, such as Figure 7 Shown is control logic 2236, such as an RFFE control interface. In some embodiments, control logic 2236 can be configured to control operation of at least a portion of any system configured to provide phase synchronization updates in the absence of synchronization signal transmission, as described herein, within any component of the RF device. In some embodiments, control logic 2236 can be used to perform other functions within control RF device 2200, such as enhancing control of complex RF system environments, supporting implementation of envelope tracking techniques, reducing dissipated power, etc.

[0078] Antenna 2202 can be configured to wirelessly transmit and / or receive radio frequency signals according to any wireless standard or protocol (e.g., Wi-Fi, LTE, or GSM) and any other wireless protocol designated as 3G, 4G, 5G and higher versions. If RF device 2200 is an FDD transceiver, antenna 2202 can be configured to simultaneously receive and transmit communication signals in separate, i.e., non-overlapping and non-contiguous frequency bands, for example, in frequency bands having intervals of, for example, 20 MHz from each other. If RF device 2200 is a TDD transceiver, antenna 2202 can be configured to sequentially receive and transmit communication signals in frequency bands where TX and RX paths may be the same or overlapping. In some embodiments, RF device 2200 may be a multi-band RF device, in which case antenna 2202 may be configured to simultaneously receive signals having multiple RF components in separate frequency bands and / or to simultaneously transmit signals having multiple RF components in separate frequency bands. In such an embodiment, antenna 2202 can be a single broadband antenna or multiple band-specific antennas (i.e., multiple antennas, each configured to receive and / or transmit signals in a specific frequency band). In various embodiments, antenna 2202 can include multiple antenna elements, for example, multiple antenna elements forming a phased antenna array (i.e., a communication system or antenna array that can use multiple antenna elements and phase shifts to send and receive RF signals). Compared to a single antenna system, a phased antenna array can provide advantages such as increased gain, directional control capabilities, and simultaneous communication. In some embodiments, RF device 2200 can include more than one antenna 2202 to achieve antenna diversity. In some such embodiments, an RF switch 2234 can be deployed to switch between different antennas.

[0079] The output of antenna 2202 may be coupled to the input of duplexer 2204. Duplexer 2204 may be any suitable component configured to filter multiple signals to allow bidirectional communication through a single path between duplexer 2204 and antenna 2202. 2204 may be configured to provide RX signals to the RX path of RF device 2200 and to receive TX signals from the TX path of RF device 2200.

[0080] The RF device 2200 may include one or more local oscillators 2206 configured to provide a local oscillator signal that may be used for down-conversion of RF signals received by the antenna 2202 and / or up-conversion of signals to be transmitted by the antenna 2202 .

[0081] RF device 2200 may include a digital processing unit 2208, which may include one or more processing devices. In some embodiments, digital processing unit 2208 may be implemented as Figure 6, the description of which is provided above (when used as a digital processing unit 2208, the processing device 2102 can, but need not, implement any system configured to provide phase synchronization updates without the need for synchronization signal transmission as described herein). The digital processing unit 2208 can be configured to perform various functions related to digital processing of RX and / or TX signals. Examples of such functions include, but are not limited to, decimation / downsampling, error correction, digital down-conversion or up-conversion, DC offset cancellation, automatic gain control, etc. Although not shown in Figure 7 However, in some embodiments, the RF device 2200 may further include a storage device, for example, a reference Figure 6 The depicted memory device 2104 is configured to cooperate with the digital processing unit 2208. When used within or coupled to the RF device 2200, the memory device 2104 may, but need not, implement any system configured to provide phase synchronization updates without synchronization signal transmission as described herein.

[0082] The steering may include details of the RX path in the RF device 2200, and the RX path amplifier 2212 may include a low noise amplifier (LNA). The input of the RX path amplifier 2212 may be coupled to an antenna port (not shown) of the antenna 2202, for example, via the duplexer 2204. The RX path amplifier 2212 may amplify the RF signal received by the antenna 2202.

[0083] The output of the RX path amplifier 2212 may be coupled to the input of an RX path premix filter 2214 , which may be a harmonic or bandpass (eg, lowpass) filter configured to filter the received RF signal that has been amplified by the RX path amplifier 2212 .

[0084] The output of the RX path premix filter 2214 can be coupled to the input of the RX path mixer 2216, also referred to as a down converter. The RX path mixer 2216 can include two inputs and one output. The first input can be configured to receive an RX signal, which can be a current signal indicating a signal received by the antenna 2202 (e.g., the first input can receive the output of the RX path premix filter 2214). The second input can be configured to receive a local oscillator signal from one of the local oscillators 2206. The RX path mixer 2216 can then mix the signals received at its two inputs to generate a down-converted RX signal provided at the output of the RX path mixer 2216. As used herein, down conversion refers to the process of mixing a received RF signal with a local oscillator signal to produce a lower frequency signal. In particular, the TX path mixer (e.g., down converter) 2216 can be configured to generate a sum and / or difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2200 can implement a direct conversion receiver (DCR), also known as a homodyne, synchronous or zero intermediate frequency receiver, in which case the RX path mixer 2216 can be configured to demodulate the incoming radio signal using a local oscillator signal having a frequency that is the same as or close to the carrier frequency of the radio signal. In other embodiments, the RF device 2200 can utilize down-conversion to an intermediate frequency (IF). The IF can be used in a superheterodyne radio receiver, where the received RF signal is converted to an IF before the final detection of the information in the received signal is completed. Converting to an IF can be useful for a variety of reasons. For example, when using multiple filters, they can all be set to fixed frequencies, which makes them easier to build and adjust. In some embodiments, the RX path mixer 2216 can include several such IF conversion stages.

[0085] Despite Figure 7A single RX path mixer 2216 is shown in the RX path of the RX path. In some embodiments, the RX path mixer 2216 can be implemented as an orthogonal down converter, in which case it will include a first RX path mixer and a second RX path mixer. The first RX path mixer can be configured to perform down conversion by mixing the RX signal received by the antenna 2202 and the in-phase component of the local oscillator signal provided by the local oscillator 2206 to generate an in-phase (I) down-converted RX signal. The second RX path mixer can be configured to perform down conversion by mixing the RX signal received by the antenna 2202 and the orthogonal component of the local oscillator signal provided by the local oscillator 2206 (the orthogonal component is a component that is 90 degrees in phase with the in-phase component of the local oscillator signal) to generate an orthogonal (Q) down-converted RX signal. The output of the first RX path mixer can be provided to the I signal path, and the output of the second RX path mixer can be provided to the Q signal path, which can be 90 degrees different from the I signal path.

[0086] The output of the RX path mixer 2216 can optionally be coupled to an RX path post-mixing filter 2218, which can be a low pass filter. If the RX path mixer 2216 is a quadrature mixer implementing the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers, respectively, can be coupled to respective individual first and second RX path post-mixing filters included in the filter 2218.

[0087] ADC 2220 may be configured to convert the mixed RX signal from RX path mixer 2216 from the analog domain to the digital domain. ADC 2220 may be a quadrature ADC, which, similar to RX path quadrature mixer 2216, may include two ADCs configured to digitize the down-converted RX path signal separated in in-phase and quadrature components. The output of ADC 2220 may be provided to digital processing unit 2208, which may be configured to perform various functions associated with digital processing of the RX signal, thereby extracting information encoded in the RX signal.

[0088] Turning to the details of the TX path that may be included in the RF device 2200, a digital signal (TX signal) to be later transmitted by the antenna 2202 may be provided from the digital processing unit 2208 to the DAC 2230. Similar to the ADC 2220, the DAC 2230 may include two DACs configured to convert digital I- and Q-path TX signal components into analog form, respectively.

[0089] Optionally, the output of the DAC 2230 can be coupled to a TX path premix filter 2228, which can be a bandpass (e.g., low-pass) filter (or a pair of bandpass filters, such as low-pass filters, in the case of orthogonal processing), configured to filter out signal components outside the desired frequency band from the analog TX signal output by the DAC 2230. The digital TX signal can then be provided to the TX path mixer 2226, which can also be referred to as an upconverter. Similar to the RX path mixer 2216, the TX path mixer 2226 can include a pair of TX path mixers for mixing in-phase and quadrature components. Similar to the first and second RX path mixers that can be included in the RX path, each TX path mixer of the TX path mixer 2226 can include two inputs and one output. The first input can receive the TX signal components converted to analog form by the corresponding DAC 2230, which will be upconverted to generate the RF signal to be transmitted. The first TX path mixer can generate an in-phase (I) up-converted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2206 (in various embodiments, the local oscillator 2206 can include multiple different local oscillators, or be configured to provide different local oscillator frequencies for the mixer 2216 in the RX path and the mixer 2226 in the TX path). The second TX path mixer can generate an orthogonal phase (Q) up-converted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the orthogonal component of the TX path local oscillator signal. The output of the second TX path mixer can be added to the output of the first TX path mixer to create a real RF signal. The second input of each TX path mixer can be coupled to the local oscillator 2206.

[0090] Optionally, the RF device 2200 may include a TX path post-mix filter 2224 configured to filter the output of the TX path mixer 2226 .

[0091] The TX path amplifier 2222 may be a power amplifier (PA) configured to amplify the up-converted RF signal before providing it to the antenna 2202 for transmission.

[0092] In various embodiments, any one of the RX path premix filter 2214, the RX path postmix filter 2218, the TX postmix filter 2224, and the TX premix filter 2228 can be implemented as an RF filter. In some embodiments, the RF filter can be implemented as a plurality of RF filters or filter banks. The filter bank can include a plurality of RF filters that can be coupled to a switch (e.g., an RF switch 2234), and the switch is configured to selectively open and close any one of the plurality of RF filters (e.g., activate any one of the plurality of RF filters) to achieve the desired filtering characteristics of the filter bank (i.e., so as to program the filter bank). For example, when the RF device 2200 is or is included in a BS or UE device, such a filter bank can be used to switch between different RF frequency ranges. In another example, such a filter bank can be programmable to suppress TX leakage on different duplex distances.

[0093] The impedance tuner 2232 may include any suitable circuit configured to match the input and output impedances of different RF circuits to minimize signal loss in the RF device 2200. For example, the impedance tuner 2232 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2202 may be particularly advantageous because the impedance of the antenna is a function of the environment in which the RF device 2200 is located, for example, the impedance of the antenna changes depending on whether the antenna is held in a hand, placed on the roof of a car, etc.

[0094] As described above, the RF switch 2234 can be a device configured to route high frequency signals through a transmission path, for example, in order to Figure 7 2200, for example, to achieve desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch can be used to switch between different antennas 2202. In other embodiments, the RF switch can be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively turning the RF filters on and off). Typically, the RF system will include multiple such RF switches.

[0095] RF device 2200 provides a simplified version, and in further embodiments, may include Figure 72200 and 2210. For example, the RX path of the RF device 2200 may include a current-to-voltage amplifier between the RX path mixer 2216 and the ADC 2220, which may be configured to amplify the down-converted signal and convert it to a voltage signal. In another example, the RX path of the RF device 2200 may include a balanced-unbalanced transformer for producing a balanced signal. In yet another example, the RF device 2200 may also include a clock generator, which may, for example, include a suitable PLL configured to receive a reference clock signal and use it to generate a different clock signal, which may then be used to time the operation of the ADC 2220, the DAC 2230, and / or may also be used by the local oscillator 2206 to generate a local oscillator signal to be used in the RX path or the TX path. One or more systems configured to provide phase synchronization updates in the absence of synchronization signal transmission, as described herein, to provide phase updates for the operation of one or more of these components.

[0096] Example Data Processing System

[0097] Figure 8 A block diagram is provided illustrating an example data processing system 2300 that can be configured to control the operation of one or more systems configured to provide phase synchronization updates without synchronization signal transmissions in accordance with some embodiments of the present disclosure. For example, the data processing system 2300 can be configured to implement or control portions of the system 200 and / or device 500 as described herein. In some embodiments, the data processing system 2300 can be configured to implement Figure 7 Control logic 2236 is shown.

[0098] like Figure 8 As shown, data processing system 2300 may include at least one processor 2302, such as a hardware processor 2302, coupled to a memory element 2304 via a system bus 2306. Therefore, the data processing system may store program codes in the memory element 2304. In addition, processor 2302 may execute program codes accessed from the memory element 2304 via the system bus 2306. In one aspect, the data processing system may be implemented as a computer suitable for storing and / or executing program codes. However, it should be understood that the data processing system 2300 may be implemented in the form of any system including a processor and a memory capable of performing the functions described in the present disclosure.

[0099] In some embodiments, the processor 2302 may execute software or algorithms to perform the activities discussed in the present disclosure, particularly activities related to providing phase synchronization updates in the absence of synchronization signal transmission, as described herein. The processor 2302 may include any combination of hardware, software, or firmware that provides programmable logic, including as non-limiting examples a microprocessor, a DSP, a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific IC (ASIC), or a virtual machine processor. The processor 2302 may be communicatively coupled to the memory element 2304, such as in a direct memory access (DMA) configuration, so that the processor 2302 can read from or write to the memory element 2304.

[0100] Typically, memory element 2304 can include any suitable volatile or non-volatile memory technology, including double data rate (DDR) RAM, synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, ROM, optical media, virtual memory area, magnetic or tape storage, or any other suitable technology. Unless otherwise specified, any memory element discussed herein should be interpreted as being included in the broad term "memory". Information that is measured, processed, tracked or sent to any component of data processing system 2300 or sent from any component of data processing system 2300 can be provided in any database, register, control list, cache or storage structure, all of which can be referenced in any suitable time range. Any such storage option can be included in the broad term "memory" used here. Similarly, any potential processing element, module and machine described herein should be interpreted as being included in the broad term "processor". Each element shown in this figure, such as any element of system 200 and / or device 500, may also include appropriate interfaces for receiving, transmitting and / or otherwise communicating data or information in a network environment so that they can communicate with, for example, data processing system 2300.

[0101] In certain example implementations, the mechanisms for implementing phase synchronization updates without the synchronization signal transmissions outlined herein may be implemented by logic encoded in one or more tangible media, which may include non-transitory media, such as embedded logic provided in an ASIC, DSP instructions, software (which may include object code and source code) executed by a processor or other similar machine, etc. In some of these instances, such as Figure 8Memory elements such as the memory element 2304 shown in the figure can store data or information used for the operations described herein. This includes memory elements that can store software, logic, code, or processor instructions that are executed to perform the activities described herein. The processor can execute any type of instructions associated with the data or information to implement the operations detailed herein. In one example, such as Figure 8 A processor such as processor 2302 shown in can transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or ASIC including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0102] Memory element 2304 may include one or more physical memory devices, such as local memory 2308 and one or more mass storage devices 2310. Local memory may refer to a RAM or other non-persistent memory device commonly used during the actual execution of the program code. The mass storage device may be implemented as a hard drive or other persistent data storage device. The processing system 2300 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code to reduce the number of times that the program code must be retrieved from the mass storage device 2310 during execution.

[0103] like Figure 8 As shown, memory element 2304 can store application programs 2318. In various embodiments, application programs 2318 can be stored in local memory 2308, one or more mass storage devices 2310, or separate from local memory and mass storage devices. It should be understood that data processing system 2300 can also execute an operating system (OS) capable of facilitating the execution of application programs 2318. Figure 8 23). The application program 2318 implemented in the form of executable program code can be executed by the data processing system 2300, for example, by the processor 2302. In response to the execution of the application, the data processing system 2300 can be configured to perform one or more operations or method steps described herein.

[0104] The input / output (I / O) devices described as input devices 2312 and output devices 2314 may optionally be coupled to a data processing system. Examples of input devices may include, but are not limited to, keyboards, pointing devices such as mice, etc. Examples of output devices may include, but are not limited to, monitors or displays, speakers, etc. In some embodiments, output device 2314 may be any type of screen display, such as a plasma display, LCD, organic light emitting diode (OLED) display, electroluminescent (EL) display, or any other indicator, such as a dial, barometer, or LED. In some embodiments, the system may include a driver (not shown) for output device 2314. Input and / or output devices 2312, 2314 may be coupled to a data processing system directly or through an intermediate I / O controller.

[0105] In an embodiment, the input and output devices may be implemented as a combined input / output device (in Figure 8 2312 and output device 2314). An example of such a combination device is a touch-sensitive display, sometimes also referred to as a "touch screen display" or simply a "touch screen." In such an embodiment, input to the device can be provided by movement of a physical object, such as a stylus or finger of a user, on or near the touch screen display.

[0106] Network adapter 2316 may also be optionally coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter may include a data receiver for receiving data sent by the system, device, and / or network to the data processing system 2300, and a data transmitter for sending data from the data processing system 2300 to the system, device, and / or network. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that may be used with the data processing system 2300.

[0107] Selected from examples

[0108] The following paragraphs provide various examples of the embodiments disclosed herein.

[0109] Example 1 provides a system for generating phase updates for synchronizing IC components. The system includes: a PLL circuit configured to receive a device clock signal and generate a PLL clock signal having a frequency greater than the device clock signal; a clock divider circuit; configured to generate a final digital clock signal based on the PLL clock signal; a first phase accumulator configured to generate a first phase update based on the final digital clock signal (e.g., by clocking); a second phase accumulator configured to generate a second phase update based on the device clock signal (e.g., by clocking), wherein each of the first phase update and the second phase update indicates the arrival of a pulse of a SYSREF signal; and a combiner configured to generate a phase update based on the first phase update and the second phase update.

[0110] Example 2 provides the system according to Example 1, further comprising an input component configured to receive a SYSREF signal and provide an output signal including pulses indicative of pulses of the SYSREF signal.

[0111] Example 3 provides a system according to Example 2, wherein the input component is a delay flip-flop (DFF0).

[0112] Example 4 provides the system according to Example 2 or 3, further comprising a transmit replica component configured to generate a transmit replica output indicating the second phase updated value at a falling edge of a pulse of the output signal of the input component.

[0113] Example 5 provides a system according to Example 4, wherein the send replication component includes a multiplexer and one or more DFFs.

[0114] Example 6 provides the system of Example 4 or 5, further comprising a state machine configured to control the operation of the transmit replica component based on the arrival of a pulse of the SYSREF signal.

[0115] Example 7 provides a system according to any of Examples 2-6, further comprising a scaling component configured to generate a scaling component output indicating a scaling value of the second phase update at a falling edge of a pulse of the output signal of the input component, wherein the scaling value is based on a difference between the final digital clock signal and the device clock signal.

[0116] Example 8 provides a system according to any of Examples 2-7, further comprising a synchronization component configured to generate a pulse based on a pulse of the output signal of the input component, wherein the pulse generated by the synchronization component is configured to trigger providing a second phase update to the combiner.

[0117] Example 9 provides a system according to Example 2, further comprising a scaling component configured to generate a scaling component output indicating a scaling value of the second phase update at a falling edge of a pulse of the output signal of the input component, wherein the scaling value is based on a difference between the final digital clock signal and the device clock signal; and a synchronization component configured to trigger provision of the scaling value to the combiner.

[0118] Example 10 provides a system according to Example 2, further including a sending replica component configured to generate a sending replica output indicating a value of the second phase update at a falling edge of a pulse of the output signal of the input component; and a synchronization component configured to trigger a value indicating a value of the second phase update to be provided to a combiner at a falling edge of a pulse of the output signal of the input component.

[0119] Example 11 provides a system according to any of the preceding examples, further comprising a state machine configured to control operation of one or more of the first phase accumulator, the second phase accumulator, and the clock divider circuit based on arrival of a pulse of the SYSREF signal.

[0120] Example 12 provides a system according to any of the preceding examples, further comprising: a gate coupled between the PLL and the clock divider circuit and configured to provide the PLL clock signal to the clock divider circuit; and a state machine configured to trigger the gate to provide the PLL clock signal to the clock divider circuit (triggering the clock divider circuit to generate a final digital clock signal) based on the arrival of a pulse of the SYSREF signal.

[0121] Example 13 provides a system according to any of the preceding examples, wherein at a given time, the combiner is configured to generate a phase update by adding a value of the first phase update and a value of the second phase update.

[0122] Example 14 provides a system according to any of the preceding examples, wherein the first phase accumulator is a LMFC.

[0123] Example 15 provides a system according to any of the preceding examples, wherein the SYSREF signal is a SYSREF signal of the JESD standard.

[0124] Example 16 provides a system according to any of the preceding examples, wherein the system is an RF transceiver.

[0125] Example 17 provides a system according to Example 16, wherein the RF transceiver further includes an IC component, the IC component including at least one of a mixer, an ADC, a DAC, an analog filter, and a digital filter, and the RF transceiver is configured to synchronize one or more IC components based on a phase update generated by the combiner.

[0126] Example 18 provides a timing arrangement for synchronizing one or more IC components. The timing arrangement includes: a first counter configured to count the number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a PLL clock signal, the PLL clock signal is based on a device clock signal, and the frequency of the final digital clock signal is greater than the frequency of the device clock signal; a second counter configured to count the number of cycles of the device clock signal; and a phase update circuit configured to generate a phase update indicating the arrival of a pulse of a SYSREF signal based on the outputs of the first counter and the second counter.

[0127] Example 19 provides a timing arrangement according to Example 18, wherein the phase update circuit is configured to generate a phase update in the absence of providing a SYSREF signal to the first counter.

[0128] Example 20 provides a timing arrangement according to Example 18 or 19, wherein the first counter is configured to count the number of cycles of the final digital clock signal by repeating a first count value sequence; and the second counter is configured to count the number of cycles of the device clock signal by repeating a second count value sequence, the second sequence being different from the first sequence.

[0129] Changes and implementation

[0130] Although the above reference Figure 2-8 The exemplary embodiments shown in FIG. 1 describe embodiments of the present disclosure, but those skilled in the art will appreciate that the various teachings above are applicable to a variety of other embodiments.

[0131] In the discussion of the above embodiments, components of the system, such as combiners / adders, flip-flops, multiplexers, and / or other components, can be easily replaced, substituted, or otherwise modified to accommodate specific circuit needs. In addition, it should be noted that the use of complementary electronic devices, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure related to providing phase synchronization updates without the need for synchronization signal transmission.

[0132] Parts of various systems for implementing phase synchronization updates in the absence of synchronization signal transmission proposed herein may include electronic circuits to perform the functions described herein. In some cases, one or more parts of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include a programmable logic gate configured to perform the functions described herein. The circuit may operate in an analog domain, a digital domain, or a mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-temporary computer-readable storage medium.

[0133] In some embodiments, any number of circuits in this figure can be implemented on the board of the relevant electronic device. The board can be a general circuit board, which can accommodate various components of the electronic system inside the electronic device, and further provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection, and other components of the system can communicate electrically through the electrical connection. Any suitable processor (including DSP, microprocessor, support chipset, etc.), computer-readable non-temporary memory element, etc. can be appropriately coupled to the board according to specific configuration requirements, processing requirements, computer design, etc. Other components such as external memory, additional sensors, audio / video display controllers and peripherals can be used as plug-in cards, connected to the board via cables, or integrated into the board itself. In various embodiments, the functions described herein can be implemented in a simulated form as software or firmware running in one or more configurable (e.g., programmable) elements, which are arranged in a structure that supports these functions. The software or firmware providing simulation can be provided on a non-temporary computer-readable storage medium, which includes instructions that allow the processor to perform those functions.

[0134] In some embodiments, the circuits in this figure can be implemented as stand-alone modules (e.g., devices having related components and circuits configured to perform specific applications or functions) or as plug-in modules inserted into application-specific hardware of an electronic device. Note that specific embodiments of the present disclosure can be easily included in a SOC package in part or in whole. SOC represents an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal, and typically RF functions: all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0135] All specifications, dimensions, and relationships outlined herein (e.g., the number of components of various devices and systems for providing phase synchronization updates in the absence of synchronization signal transmissions, or portions of such devices and systems, shown in this figure, etc.) are for exemplary and didactic purposes only. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. The specifications apply only to one non-limiting example, and therefore, they should be interpreted as such. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

[0136] Note that, through the numerous examples provided here, interactions can be described based on two, three, four or more electrical components. However, this is done only for clarity and example. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any illustrated components, modules and elements of this figure can be combined in various possible configurations, all of which are obviously within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by referring only to a limited number of electrical components. It should be understood that the circuits of this figure and its teachings are easy to expand and can accommodate a large number of components and more complex or more sophisticated arrangements and configurations. Therefore, the examples provided should not limit the scope or suppress the broad teachings of circuits that may be applied to countless other architectures.

[0137] In addition, the functions related to providing phase synchronization updates in the absence of synchronization signal transmission as presented herein illustrate only some of the possible functions that may be performed by or within the system illustrated in the present figure. Some of these operations may be appropriately deleted or removed, or may be significantly modified or changed without departing from the scope of the present disclosure. In addition, the timing of these operations may vary significantly. The foregoing operational flows are provided for purposes of example and discussion. The embodiments described herein provide substantial flexibility in that any suitable arrangements, timings, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

[0138] Note that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

[0139] Numerous other changes, substitutions, variations, and modifications may be ascertained by those skilled in the art, and the disclosure is intended to embrace all such changes, substitutions, variations, variations, and modifications that fall within the scope of the appended claims.

Claims

1. A system for generating a phase update for synchronizing an integrated circuit IC component, the phase update indicating the arrival of a pulse of a system reference SYSREF signal, the system comprising: a phase-locked loop (PLL) circuit configured to receive a device clock signal and generate a PLL clock signal based on the device clock signal, wherein a frequency of the PLL clock signal is greater than a frequency of the device clock signal; a clock divider circuit configured to generate a final digital clock signal based on the PLL clock signal; a first phase accumulator configured to generate a first accumulator output by counting cycles of the final digital clock signal; a second phase accumulator configured to generate a second accumulator output by counting cycles of the device clock signal; an input component configured to receive a SYSREF signal and provide an output signal including pulses indicative of pulses of the SYSREF signal; a transmit replica component configured to generate a transmit replica output indicating a value of the second accumulator output at a falling edge of a pulse of the output signal of the input component; and A combiner is configured to generate the phase update by adding the first accumulator output and a value based on the transmitted replica output.

2. The system of claim 1, wherein the input component is a trigger.

3. The system of claim 1, wherein the send replication component comprises a multiplexer and one or more flip-flops. 4 . The system of claim 1 , further comprising a state machine configured to control operation of the transmit replica component based on arrival of a pulse of the SYSREF signal.

5. The system according to claim 1 or 2 further includes a scaling component, which is configured to generate a scaling component output indicating a scaling value of the second accumulator output at a falling edge of a pulse of the output signal of the input component, wherein the scaling value is based on a difference between a period of the final digital clock signal and a period of the device clock signal.

6. The system of claim 5, further comprising a synchronization component configured to generate a pulse based on a pulse of an output signal of the input component, wherein the pulse generated by the synchronization component is configured to trigger provision of the scaling component output to the combiner.

7. The system according to claim 1, further comprising: a scaling component configured to generate a scaling component output indicative of a scaled value of the second accumulator output at a falling edge of a pulse of the output signal of the input component, wherein the scaled value is based on a difference between a period of the final digital clock signal and a period of the device clock signal; and A synchronization component is configured to trigger providing the scaled value to the combiner.

8. The system of claim 1, further comprising: A synchronization component is configured to trigger the provision of the transmission replica output to the combiner at the falling edge of a pulse of the output signal of the input component.

9. The system of claim 1 or 2, further comprising a state machine configured to control operation of one or more of the first phase accumulator, the second phase accumulator, and the clock divider circuit based on arrival of a pulse of the SYSREF signal.

10. The system according to claim 1 or 2, further comprising: a gate configured to provide the PLL clock signal to the clock divider circuit; and A state machine is configured to trigger the gate to provide the PLL clock signal to the clock divider circuit based on the arrival of a pulse of the SYSREF signal.

11. The system of claim 1 or 2, wherein the first phase accumulator is a local multi-frame clock.

12. The system of claim 1 or 2, wherein the SYSREF signal is a SYSREF signal of the JESD standard.

13. The system according to claim 1 or 2, wherein the system is a radio frequency (RF) transceiver.

14. The system of claim 13, wherein: The RF transceiver also includes an IC component, The IC component includes at least one of a mixer, an analog-to-digital converter, a digital-to-analog converter, an analog filter, and a digital filter, and The RF transceiver is configured to synchronize one or more of the IC components based on the phase updates generated by the combiner.

15. A timing arrangement for synchronizing one or more integrated circuit (IC) components, comprising: a first counter configured to generate a first counter output by counting the number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a phase-locked loop (PLL) clock signal, the PLL clock signal is based on a device clock signal, and a frequency of the final digital clock signal is greater than a frequency of the device clock signal; a second counter configured to generate a second counter output by counting a number of cycles of the device clock signal; an input component configured to receive a system reference SYSREF signal and provide an output signal including pulses indicative of pulses of the SYSREF signal; a transmission replica component configured to generate a transmission replica output indicating a value output by the second counter at a falling edge of a pulse of the output signal of the input component; and A phase update circuit is configured to generate a phase update indicating the arrival of a pulse of the SYSREF signal by adding the first counter output and a value based on the transmitted replica output.

16. A timing arrangement as claimed in claim 15, wherein the phase update circuit is configured to generate a phase update in the absence of providing a SYSREF signal to the first counter.

17. A timing arrangement according to claim 15 or 16, wherein: The first counter is configured to count the number of cycles of the final digital clock signal by repeating a first count value sequence, The second counter is configured to count the number of cycles of the device clock signal by repeating a second sequence of count values, the second sequence of count values ​​being different from the first sequence of count values.

18. A method of generating a phase update for synchronizing one or more integrated circuit (IC) components, the phase update indicating the arrival of a pulse of a system reference SYSREF signal, the method comprising: Counting the number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a phase-locked loop (PLL) clock signal, the PLL clock signal is based on a device clock signal, and a frequency of the final digital clock signal is greater than a frequency of the device clock signal; Counting the number of cycles of the device clock signal; generating a transmit replica output indicating a counted number of cycles of the device clock signal on a falling edge of a pulse, the pulse being indicative of a pulse of the SYSREF signal; and The phase update is generated by adding a counted number of cycles of the final digital clock signal and a value based on the transmitted replica output.

19. The method of claim 18, wherein the phase update occurs in the absence of providing a SYSREF signal to a counter for counting the number of cycles of the final digital clock signal.

20. The method of claim 18, wherein: Counting the number of cycles of the final digital clock signal includes repeating a first sequence of count values; and Counting the number of cycles of the device clock signal includes repeating a second sequence of count values, the second sequence of count values ​​being different from the first sequence of count values.

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