A method for compressing and decompressing FPGA code stream data

By segmenting and characteristic analysis of behavior units of FPGA code stream data, compressing using the method of skipping the entire line or skipping the segment, the problems of low compression rate and long configuration time in the prior art are solved, and higher compression rate and faster configuration speed are achieved.

CN114070327BActive Publication Date: 2025-05-13EHIWAY MICROELECTRONIC SCI & TECH (SUZHOU) CO LTD
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Patent Information

Application Number
CN202111373243.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-11-19
Publication Date
2025-05-13
Estimated Expiration
2041-11-19

AI Technical Summary

Technical Problem

When compressing FPGA code stream data in the prior art, there is a problem that the compression rate is low when repeated contents and the inability to effectively reduce the FPGA configuration time.

Method used

The code stream data to be compressed is divided into multiple data blocks in behavior units and compressed using a whole row skip or segment skip according to the characteristics of each row of data.

Benefits of technology

A higher compression rate for code stream data with high repetition rate is achieved, reducing FPGA configuration time and occupies less resources.

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Abstract

The present invention discloses a compression and decompression method for FPGA code stream data, and the compression method includes the following steps: 1. obtaining the position of the code stream data to be compressed in the device; 2. analyzing the position of the entire code stream data to be compressed in the device, and dividing the code stream data to be compressed into multiple data blocks in line units according to the position; 3. compressing the data blocks according to two situations: all the data in each line is the same and some data in each line is different; the decompression method is: analyzing whether full compression or segmented partial compression is enabled in the code stream data, and when full compression is enabled, using a partial decompression method for decompression; when segmented partial compression is enabled, using a segmented partial decompression method for decompression. The present invention has a higher compression rate for code stream data with a high repetition rate, can occupy less resources, greatly improves configuration efficiency, and can further keep user circuits confidential.
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Description

Technical Field

[0001] The invention belongs to the technical field of FPGA application, and in particular relates to a method for compressing and decompressing FPGA code stream data. Background Art

[0002] In recent years, with the emergence of large-scale, high-performance FPGAs, and the improvement of software and hardware design processes and design methods, FPGA-based reconfigurable systems have gradually become a new hotspot in the field of computer system research. The hardware information in FPGA-based reconfigurable systems, that is, the configuration information of the FPGA, can be modified or dynamically called like software using advanced EDA tools, so that the system has the high performance of hardware computing while also having the high flexibility of software.

[0003] The use of a reconfigurable system to implement a computing logic has two operating costs: the first is the computing time, which is the time used for actual computing; the second is the configuration time, which is the delay caused by configuring the internal programmable device. However, as the scale of FPGA continues to expand and the internal resources continue to enrich, the configuration time will become longer and longer, which seriously restricts the application of reconfigurable computing. A major part of the FPGA configuration time is consumed in the process of transferring the configuration file from the off-chip memory to the FPGA. Reducing the size of the configuration file can shorten the FPGA configuration time; in addition, it can also reduce the size of the off-chip memory, thereby saving system costs.

[0004] The compression process of FPGA code stream data is as follows: Figure 1 As shown, the configuration file generated by the EDA tool is first compressed, and then the compressed configuration file is stored in an off-chip non-volatile memory (such as a memory based on a Flash process).

[0005] The decompression process of FPGA code stream data is as follows Figure 2 As shown, when the FPGA system needs to configure this file, the system will immediately read the data of the configuration file from the non-volatile memory outside the chip, and then decompress it on the chip to obtain the original configuration data stream, which is directly sent to the FPGA for configuration.

[0006] In the prior art, dictionary-based compression methods are often used for FPGA code stream data. When a character or a string in the input data stream matches a character or a string in the dictionary, the compressor outputs the identifier of the matching position in the dictionary. As long as the number of bits of the codeword used to represent the corresponding matching position is less than the number of bits of the corresponding matching string in the input data stream, the purpose of compression can be achieved. If a careful design is carried out, a fairly good compression effect can be achieved. Depending on whether the dictionary can be updated during the compression process, it can be divided into static dictionary compression and dynamic dictionary compression.

[0007] A static dictionary is a basically fixed dictionary that sometimes allows strings to be added, but not deleted. A dynamic dictionary generally starts with an empty dictionary, and during the compression process, the content and size of the dictionary are variable.

[0008] However, the general dictionary compression and decompression method has the following two defects:

[0009] (1) When there is a large amount of repeated content in the code stream, it is necessary to generate compression codes every fixed number of bytes, which reduces the compression rate.

[0010] (2) It can only reduce storage size and data transfer time, but cannot reduce configuration time. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a method for compressing FPGA code stream data in view of the deficiencies in the above-mentioned prior art, which has a higher compression rate for code stream data with a high repetition rate and can occupy less resources.

[0012] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for compressing FPGA code stream data, the method comprising the following steps:

[0013] Step 1: Obtain the location of the code stream data to be compressed in the device;

[0014] Step 2: Analyze the position of the entire code stream data to be compressed in the device, and divide the code stream data to be compressed into multiple data blocks in units of lines according to the position;

[0015] Step 3: compress the data blocks according to two situations: when all the data in each row are the same and when some data in each row are different.

[0016] In the above-mentioned FPGA code stream data compression method, the specific method of compressing the data block in step 3 according to the two situations where all the data in each row are the same and some data in each row are different is:

[0017] Analyze whether the data of each row of data blocks are all the same. When the data of each row of data blocks are all the same, the data blocks are compressed by skipping the entire row; when the data of each row of data blocks have individual data that are different, the data blocks are compressed by skipping the segmentation.

[0018] The method of compressing data blocks by skipping the entire row is as follows: when the data of each row of data blocks are all the same, the entire data is replaced at the end of the previous data block with a keyword representing skipping a row of data blocks; when the data of several consecutive rows of data blocks are all the same, the keywords representing several rows of data blocks are used to replace several rows of data blocks;

[0019] The method of compressing data blocks by using the segmented skipping method is as follows: analyzing the data of each row of data blocks, grouping the data of each row of data blocks into a certain number, and when the data exceeding a certain number of groups are the same, replacing the previous groups of data with some special keywords.

[0020] The present invention also discloses a method for decompressing FPGA code stream data that greatly improves configuration efficiency and can further keep user circuits confidential. The method comprises: analyzing whether full compression or segmented partial compression is enabled in the code stream data, and when full compression is enabled, using a partial decompression method for decompression; when segmented partial compression is enabled, using a segmented partial decompression method for decompression;

[0021] The method of decompressing by using the partial decompression method is: parsing the keywords representing a row data block and the keywords representing several row data blocks in the code stream data, and controlling the addresses and data to be skipped during configuration according to the keywords and the decompression protocol;

[0022] The method of decompressing by using the segmented partial decompression method is: parsing some special keywords in the code stream data, and configuring corresponding data and addresses according to some special keywords and the decompression protocol.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] 1. The present invention provides a method for compressing and decompressing FPGA code stream data. Compared with the traditional method, the code stream with a high repetition rate can be compressed at a higher compression rate, and less time is consumed when configuring the FPGA, thereby improving the configuration speed.

[0025] 2. The FPGA code stream data compression method of the present invention replaces the data representing the same data value in the uncompressed and unencrypted code stream with the keywords of the relevant protocol, thereby achieving the purpose of compression; the code stream file size with a high repetition rate can be compressed to a smaller size, so the compressed code stream can be placed in an off-chip storage device, which can occupy less resources.

[0026] 3. In the FPGA code stream data compression method of the present invention, the length of the code stream compressed each time is determined by the same number of data, and there is no need to compress data of a fixed length according to a dictionary. Therefore, the compression rate for code stream data with a high repetition rate is higher.

[0027] 4. The FPGA code stream data decompression method of the present invention does not require the data to be decompressed before configuration. The data configuration can be directly skipped according to the decompression method. The segmented partial decompression method decompresses a certain part of the segmented compressed data and configures it at one time, thereby greatly improving the configuration efficiency.

[0028] 5. In the FPGA code stream data decompression method of the present invention, some contents do not need to be completely decompressed, which reduces the possibility of the user circuit being cracked, and thus the user circuit can be further kept confidential.

[0029] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the compression process of FPGA bit stream data.

[0031] Figure 2 Schematic diagram of the decompression process of FPGA code stream data.

[0032] Figure 3 The figure is a flow chart of the FPGA code stream data compression method of the present invention.

[0033] Figure 4 The figure is a flow chart of the decompression method of FPGA code stream data of the present invention. DETAILED DESCRIPTION

[0034] The following is an example 1 to illustrate the FPGA code stream data compression method of the present invention, and an example 2 to illustrate the FPGA code stream data decompression method of the present invention. Example 1

[0035] like Figure 3 As shown, the FPGA code stream data compression method of this embodiment includes the following steps:

[0036] Step 1: Obtain the location of the code stream data to be compressed in the device;

[0037] Step 2: Analyze the position of the entire code stream data to be compressed in the device, and divide the code stream data to be compressed into multiple data blocks in units of lines according to the position;

[0038] Step 3: compress the data blocks according to two situations: when all the data in each row are the same and when some data in each row are different.

[0039] In this embodiment, the specific method of compressing the data block in step 3 according to the two situations where all the data in each row are the same and some data in each row are different is:

[0040] Analyze whether the data of each row of data blocks are all the same. When the data of each row of data blocks are all the same, the data blocks are compressed by skipping the entire row; when the data of each row of data blocks have individual data that are different, the data blocks are compressed by skipping the segmentation.

[0041] The method of compressing data blocks by skipping the entire row is as follows: when the data of each row of data blocks are all the same, the entire data is replaced at the end of the previous data block with a keyword representing skipping a row of data blocks; when the data of several consecutive rows of data blocks are all the same, the keywords representing several rows of data blocks are used to replace several rows of data blocks;

[0042] The method of compressing data blocks by using the segmented skipping method is as follows: analyzing the data of each row of data blocks, grouping the data of each row of data blocks into a certain number, and when the data exceeding a certain number of groups are the same, replacing the previous groups of data with some special keywords.

[0043] The compression of FPGA code stream data is implemented at the software level, and is divided into two methods: full compression and segmented partial compression. When the data block is compressed by the full compression method, the data of the entire data block is directly skipped, and the address can be directly skipped, that is, skip configuration is performed; when the data block is compressed by the segmented partial compression method, since some data in the data block are different, the entire part cannot be skipped, and a method of segmented partial compression of this part of the data is adopted, and a group of completely identical data in the data block is replaced by some special keywords for compression. The FPGA code stream data compression method of the present invention replaces the data with the same numerical value in the non-compressed non-encrypted code stream with the keywords of the relevant protocol, thereby achieving the purpose of compression; the code stream file size with a high repetition rate can be compressed to a smaller size, so the compressed code stream is placed in an off-chip storage device, which can occupy less resources.

[0044] The FPGA code stream data compression method of the present invention does not require a dictionary and can compress a large amount of data with fewer keywords; moreover, the code stream length compressed each time by the compression method of the present invention is determined by the same number of data, and there is no need to compress data of a fixed length according to a dictionary, so the compression rate for code stream data with a high repetition rate is higher; the present invention not only reduces the configuration time from the file size and data transmission, but also reduces the configuration time from the internal configuration efficiency. Example 2

[0045] like Figure 4As shown, the decompression method of FPGA code stream data of this embodiment is as follows: parsing whether full compression or segmented partial compression is enabled in the code stream data, and when full compression is enabled, using a partial decompression method for decompression; when segmented partial compression is enabled, using a segmented partial decompression method for decompression;

[0046] The method of decompressing by using the partial decompression method is: parsing the keywords representing a row data block and the keywords representing several row data blocks in the code stream data, and controlling the addresses and data to be skipped during configuration according to the keywords and the decompression protocol;

[0047] The method of decompressing by using the segmented partial decompression method is: parsing some special keywords in the code stream data, and configuring corresponding data and addresses according to the keywords and the decompression protocol.

[0048] The decompression of FPGA code stream data is implemented at the software level. Corresponding to the compression method, decompression is performed according to two situations: full compression and segmented partial compression. The partial decompression method does not require the data to be decompressed before configuration, and data configuration can be skipped directly according to the decompression method. The segmented partial decompression method decompresses a certain part of the segmented compressed data and configures it at one time, thus greatly improving the configuration efficiency.

[0049] Part of the content of the decompression method of the present invention does not need to be completely decompressed, which reduces the possibility of the user circuit being cracked, and thus the user circuit can be further kept confidential.

[0050] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0051] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0052] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0053] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0054] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A method for compressing FPGA code stream data, characterized in that: The method comprises the following steps: Step 1: Obtain the location of the code stream data to be compressed in the device; Step 2: Analyze the position of the entire code stream data to be compressed in the device, and divide the code stream data to be compressed into multiple data blocks in units of lines according to the position; Step 3: compress the data blocks according to two situations: all the data in each row are the same and some data in each row are different; The specific method for compressing the data block in step 3 according to the two situations that all the data in each row are the same and some data in each row are different is: Analyze whether the data of each row of data blocks are all the same. When the data of each row of data blocks are all the same, the data blocks are compressed by skipping the entire row; when the data of each row of data blocks have individual data that are different, the data blocks are compressed by skipping the segmentation. The method of compressing data blocks by skipping the entire row is as follows: when the data of each row of data blocks are all the same, the entire data is replaced at the end of the previous data block with a keyword representing skipping a row of data blocks; when the data of several consecutive rows of data blocks are all the same, the keywords representing several rows of data blocks are used to replace several rows of data blocks; The method of compressing data blocks by using the segmented skipping method is as follows: analyzing the data of each row of data blocks, grouping the data of each row of data blocks into a certain number, and when the data exceeding a certain number of groups are the same, replacing the previous groups of data with some special keywords.

2. A method for decompressing FPGA code stream data using the compression method as claimed in claim 1, characterized in that: The method comprises: analyzing whether full compression or segmented partial compression is enabled in the code stream data, and when full compression is enabled, using a partial decompression method for decompression; when segmented partial compression is enabled, using a segmented partial decompression method for decompression; The method of decompressing by using the partial decompression method is: parsing the keywords representing a row data block and the keywords representing several row data blocks in the code stream data, and controlling the addresses and data to be skipped during configuration according to the keywords and the decompression protocol; The method of decompressing by using the segmented partial decompression method is: parsing some special keywords in the code stream data, and configuring corresponding data and addresses according to some special keywords and the decompression protocol.

Citation Information

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