Semiconductor device and method of manufacturing a semiconductor device

Abstract

A semiconductor device comprising a substrate base (2) having a surface (3), a conductor (5) comprising a conductor material (5a) covering at least part of the surface (3), and a dielectric (4) provided on the part of the surface (3) not covered by the conductor (5). Wherein the conductor (5) is in contact with the substrate base (2), the conductor (5) forms a layer with the dielectric (4), and a bonding surface (6) of the layer has a surface topography of less than 10 nm, wherein the bonding surface (6) faces away from the substrate base (2). Furthermore, the semiconductor device (1) has no diffusion barrier.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a bonding surface, a hybrid bonded semiconductor device including the semiconductor device having the bonding surface, and a method of manufacturing the semiconductor device. Background Technology

[0002] In various applications, semiconductor components are implemented as hybrid structures in which individual elements are assembled face-to-face at the end of the manufacturing process, for example, using wafer bonding technology. A typical example of such a hybrid structure is an electronic component comprising two chips or integrated circuit wafers. These two elements could be a CMOS element and a sensor element, such as a MEMS sensor element. For the two elements to couple to each other without adhesive to form a hybrid device, the planarized bonding surfaces of the individual elements are crucial for effective bonding. However, the limitations of planarization methods often lead to complex manufacturing processes with large bills of materials.

[0003] Therefore, wafer bonding techniques are commonly used to integrate sensors with CMOS electronics. These techniques include eutectic bonding, anodic bonding, fused bonding, and thermocompression bonding. This disclosure focuses on direct bonding structures and their fabrication methods. Summary of the Invention

[0004] The goal is to provide a concept for improving the semiconductor device with a planarized surface and the method for manufacturing such a semiconductor device.

[0005] Typically, a dual damascene fabrication process is performed to manufacture integrated circuit semiconductor devices, in which copper is used as the back-end process (BEOL) metal interconnect. However, due to the tendency of copper to diffuse into the surrounding materials, a barrier material must be placed between them to chemically isolate the surrounding semiconductor materials from the copper while maintaining their electrical connection. Furthermore, to planarize and thus achieve the desired atomically flat bonding surface, a chemical mechanical polishing (CMP) step is performed using a highly selective polishing slurry to prevent over-polishing of the copper. Typical polishing slurries used in this process contain cerium dioxide, thus introducing a significant amount of contamination that must be removed by additional cleaning steps.

[0006] Another drawback of the described dual damascene process is its availability in 300 mm wafer CMOS manufacturing processes. For CMOS-compatible processing of 200 mm wafers, which typically have non-copper BEOL metallization (e.g., aluminum), existing bonding fabrication methods employing dual damascene technology cannot be applied. Instead, more conventional bonding fabrication methods involving metal deposition, photolithography, and etching are required.

[0007] The improved concept aims to achieve hybrid bonding without using this dual damascene metallization technique, and this hybrid bonding can also be used in 200 mm wafer fabrication processes. The concept is based on the idea of ​​providing a semiconductor device fabricated using a novel method for hybrid bonding layers. This new method, without diffusion blocking, employs a new CMP process to improve the flatness of subsequent hybrid bonding pads. The hybrid bonding pads are achieved through metal deposition, photolithography, and etching. Subsequent oxide deposition and chemical mechanical polishing make this surface suitable for hybrid bonding.

[0008] Specifically, the semiconductor device according to the improved concept includes a substrate having a surface and a conductor comprising a conductive material covering at least a portion of the surface. The semiconductor device also includes a dielectric disposed on a portion of the surface not covered by the conductor. The conductor is in contact with the substrate, the conductor and the dielectric form a layer, and the bonding surface of this layer has a surface morphology of less than 10 nm, wherein the bonding surface faces away from the substrate. Furthermore, the device has no diffusion barriers.

[0009] For example, the substrate may include a substrate of a semiconductor material such as silicon, and may include active circuitry, such as an application-specific integrated circuit (ASIC) for readout purposes, disposed on the surface of the substrate or partially or entirely within the substrate. The surface of the substrate may be a top surface or a bottom surface, depending on the manufacturing process.

[0010] The conductor material forming the conductor is conductive and is disposed on and in contact with the surface of the semiconductor substrate. For example, the conductor is formed by patterning and structuring the conductor material. The dielectric, for example, is an oxide and is disposed on portions of the surface not covered by the conductor, such that the surface is completely or substantially covered by the conductor and the dielectric. A dielectric and conductor layer is formed; in other words, the thickness of the conductor corresponds to the thickness of the dielectric, wherein the thicknesses of both elements are determined along a direction perpendicular to the surface, which, for example, corresponds to the normal vector of the principal extending plane of the substrate.

[0011] A bonding surface is the surface of a layer that faces away from the substrate. Because bonding surfaces are planarized—that is, atomically flat with a surface morphology less than 10 nm—they are suitable for use as bonding surfaces in standard wafer bonding techniques. In particular, bonding surfaces are suitable for binderless bonding techniques, such as direct bonding.

[0012] This semiconductor device lacks diffusion barriers. In other words, no barrier metal is placed between the substrate and the conductor, or between the dielectric and the conductor. Introducing diffusion barriers by means of, for example, titanium-based metallization, is incompatible with certain manufacturing processes (e.g., 200 mm CMOS-compatible wafer fabrication). In contrast, the semiconductor device according to the improved concept follows a simplified manufacturing process that is not limited to specific processes (e.g., dual damascene processes) that are only compatible with, for example, certain wafer sizes.

[0013] In some embodiments, the conductor material includes one of aluminum, titanium, tungsten, silicon, nitride, or any combination thereof.

[0014] Depending on the desired conductor specifications, such as conductivity and / or manufacturing process compatibility, suitable conductor materials can be selected from a variety of materials compatible with CMOS processes, not limited to copper, which is the basis of traditional dual damascene processes. The listed materials all exhibit suitable conductivity but do not show properties that diffuse into other materials (e.g., substrate materials), particularly those that diffuse into dielectric materials such as oxides.

[0015] In some embodiments, the oxide material includes one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium dioxide, tantalum pentoxide, SiCN, SiCOH, or any combination thereof.

[0016] In some embodiments, the conductor includes a sacrificial material disposed on a surface of the conductor material away from the substrate, and includes a conductive material different from the conductor material, such as titanium nitride.

[0017] Residual layers of material (e.g., sacrificial layers not completely removed during the manufacturing process) can be disposed on the surface of the conductive material facing away from the substrate. In these embodiments, the bonding surface includes both the surface of the dielectric and the surface of the sacrificial material disposed on the conductive material. Since it also includes a conductive material (e.g., titanium nitride), the sacrificial material can be used to facilitate bonding with another semiconductor device.

[0018] Additionally or alternatively, in some applications, the remaining layer of sacrificial material can be beneficial because it can lead to a significant reduction in resistance. For example, the remaining TiN sacrificial layer prevents the formation of an oxygen-rich Ti layer at the Ti-SiO2 interface, which would otherwise result in an undesirable high resistance.

[0019] In another embodiment, the sacrificial material can be completely removed, such that the bonding surface comprises the surface of the conductor material.

[0020] In some embodiments, the substrate includes an insulating layer, such as an oxide layer, disposed on a substrate such as a silicon substrate. The surface is the surface of the insulating layer that faces away from the substrate.

[0021] Following CMOS-compatible processing, the substrate may include an insulating layer, such as an oxide layer, disposed on the substrate serving as a support. For example, the substrate is a silicon substrate. In these embodiments, the surface is the surface of the insulating layer, on which, according to an improved concept, both dielectrics and conductors are disposed, respectively.

[0022] The above objective is also achieved by a semiconductor hybrid device comprising a semiconductor device according to one of the above embodiments and another semiconductor device having another bonding surface, wherein the semiconductor device is bonded to the other semiconductor device.

[0023] Hybrid devices are, for example, devices comprising two chips or two wafers combined via standard wafer bonding techniques. In these hybrid devices, the two components can be fabricated independently and bonded near the end of the manufacturing process. Specifically, the surface of one semiconductor device (e.g., a planarized surface) is bonded to the process surface of the semiconductor device according to an improved concept. This strategy can be employed, for example, if the fabrication process of one semiconductor device is incompatible with the fabrication process of the other semiconductor device in the hybrid device. Examples of such hybrid devices include, for instance, imaging sensors, environmental sensors, MEMS CMOS sensors, chemical sensors, and general optoelectronic devices.

[0024] In some embodiments, the semiconductor device is a CMOS device and another semiconductor device is a MEMS and / or CMOS device.

[0025] Specifically, the aforementioned sensor types typically include active circuitry in an ASIC for the characteristics of the sensor portion of the electrically readout hybrid device. However, due to the use of incompatible materials (e.g., certain metals), CMOS-compatible fabrication of the active circuitry is not necessarily compatible with the fabrication of the MEMS structure. Therefore, in some embodiments, MEMS devices also include MEMS-compatible CMOS structures that can be fabricated independently of the readout ASIC and bonded to it near the end of the fabrication process.

[0026] In some embodiments, the other semiconductor device is a semiconductor device according to one of the above embodiments.

[0027] To keep the fabrication process of the entire hybrid device as simple and cost-effective as possible, both semiconductor devices can be embodiments of semiconductor devices based on an improved concept. Furthermore, the inclusion of bonding surfaces with surface morphology less than 10 nm in both semiconductor devices allows for efficient bonding of the two components.

[0028] The above objective is also achieved by a method for manufacturing a semiconductor device. This method includes providing a substrate having a surface, depositing a conductor on the surface, and patterning and structuring the conductor. The method further includes depositing a dielectric on the conductor (particularly on the structured conductor) and on exposed portions of the surface, and forming a bonding surface of the semiconductor device by removing portions of the dielectric using multiple chemical mechanical polishing (CMP) steps. The bonding surface has a surface morphology of less than 10 nm.

[0029] For example, providing a substrate means providing a substrate and depositing an insulating layer on the substrate such that the surface of the insulating layer is the surface facing away from the substrate. The substrate is a silicon substrate, such as a wafer or chip, and the insulating layer is, for example, an oxide layer. The substrate may include active circuitry such as an ASIC. The surface of the substrate may be a top or bottom surface relative to the fabrication process of the substrate.

[0030] Deposited conductors refer to the deposition of a conductive material, such as a metal, on the surface of a substrate. For example, conductor materials include deposited aluminum, titanium, tungsten, silicon, nitrides, or any combination thereof.

[0031] Patterning and structuring conductors can be performed using photolithography (e.g., beam or electron beam lithography) combined with wet or dry etching steps. Thus, patterning and structuring expose a portion of the substrate surface, while the remaining structured conductors form a conductor stack on the surface, wherein the conductor stack is in contact with the substrate.

[0032] Dielectric deposition refers to depositing dielectric material onto the exposed portions of a surface and onto a conductor, such that the conductor is embedded within the dielectric. In other words, the thickness of the dielectric, measured from the surface of the substrate in a direction perpendicular to the main extension plane of the substrate, is at least as large as the thickness of the conductor.

[0033] For example, multiple CMP steps include a first CMP step and a second CMP step. In such an embodiment, forming a bonding surface means first applying a first CMP step to remove the dielectric, at least until the thickness of the dielectric corresponds to the thickness of the conductor. The conductor material can serve as a stop layer for the first CMP step. After the first CMP step, in the second CMP step, other dielectrics and possibly portions of the conductor are removed. In other words, the thicknesses of both the dielectric and the conductor are reduced simultaneously, such that after the second CMP step, the bonding surface, including the surfaces of the dielectric and the conductor facing away from the substrate, is atomically flat, i.e., its surface morphology is less than 10 nm.

[0034] In particular, this method does not involve applying diffusion barriers. Therefore, the method based on the improved concept is compatible with a wide range of manufacturing processes such as 100 mm, 200 mm, and 300 mm CMOS-compatible processes.

[0035] In some embodiments, the method further includes bonding another semiconductor device, particularly via wafer-to-wafer or die-to-wafer hybrid bonding, to the bonding surface.

[0036] In some embodiments, depositing a conductor includes depositing a conductor material on a surface and depositing a sacrificial material on the conductor material. In these embodiments, forming a bonding surface includes removing at least a portion of the sacrificial material.

[0037] Depositing a sacrificial material means depositing a material (which may be a conductive material) onto a conductive material. The thickness of the sacrificial material can be less than or equal to the thickness of the conductive material. However, in some embodiments, the thickness of the sacrificial material can extend beyond the thickness of the conductive material.

[0038] In such embodiments, the sacrificial material of the conductor can serve as a stop layer for the first CMP step. Furthermore, in the second CMP step, other dielectrics and at least a portion of the sacrificial material are removed. In other words, the thicknesses of both the dielectric and the sacrificial material are simultaneously reduced such that, after the second CMP step, the bonded surface comprising the surfaces of the dielectric and the sacrificial material facing away from the substrate is atomically flat, i.e., its surface morphology is less than 10 nm.

[0039] In some other embodiments, the deposition of the sacrificial material includes depositing a conductive material (particularly titanium nitride) that is different from the conductor material. Alternatively, the deposition of the sacrificial material includes depositing a dielectric material that is different from the dielectric.

[0040] In some other embodiments, the sacrificial material is not completely removed during the second CMP step, leaving it on the final device. In these embodiments, the sacrificial material is conductive to provide conductivity for the conductors formed by the conductor stack. For example, the sacrificial material is titanium nitride, which has sufficient conductivity and good bonding properties. Alternatively, the sacrificial material is a dielectric material different from the dielectric, enabling the achievement of the desired atomically smooth bonding surface.

[0041] Additionally or alternatively, in some applications, the remaining layer of sacrificial material may be beneficial because when bonding surfaces to the bonding surfaces of another semiconductor device, the remaining layer of sacrificial material may result in a significant reduction in bonding resistance.

[0042] In some other embodiments, the sacrificial material is completely removed during the second CMP step.

[0043] In some cases, it may be desirable to keep the conductor thickness as small as possible. To achieve this, a second CMP step can be performed, in which the entire sacrificial material is removed and the conductor is defined solely by the structured conductor material.

[0044] In some embodiments of the method, multiple CMP steps are performed sequentially, particularly in the absence of intermediate metal deposition.

[0045] Performing CMP steps directly back-to-back means the entire manufacturing process remains reasonable while keeping the bill of materials short, resulting in a significant reduction in manufacturing costs compared to dual-insertion formulations.

[0046] In some embodiments, at least one of the plurality of CMP steps is a timed CMP step.

[0047] To facilitate fabrication and / or when the conductor material and / or sacrificial material do not serve as a CMP stop layer, timed CMP steps can be employed to achieve the desired thickness and surface roughness of the bonding surface. For example, a first CMP step is timed to terminate when the dielectric has been removed to the extent that the sacrificial material of the conductor is exposed, while a second CMP step is timed to terminate when the sacrificial material reaches a certain thickness or is completely removed.

[0048] In some embodiments, the multiple CMP steps differ from each other in terms of slurry composition and / or material selectivity.

[0049] The polishing slurry used during the first CMP step can be designed to remove the dielectric. For example, it could be a standard silica polishing slurry. During the second step, a different polishing slurry can be used, which removes both the dielectric and sacrificial material at similar (if not equidistant) rates. For example, the second CMP step reduces the dielectric thickness at a lower rate than the first CMP step, but therefore exhibits nearly uniform selectivity for both the dielectric and sacrificial material. Alternatively, the second polishing slurry may also exhibit uniform selectivity for both the conductor and dielectric materials. For example, both the first and second polishing slurries could be standard non-cerium dioxide-based polishing slurries that do not introduce contaminants, thus eliminating the need for subsequent cleaning steps to remove contaminants from the polished surface.

[0050] In other embodiments, the second abrasive slurry may have a different selectivity with respect to the dielectric and sacrificial material than the uniform selectivity. For example, the selectivity may be from 0.9 to 1.1 to optimize the microstructure of the bonding surface, thereby achieving improved bonding results.

[0051] In some embodiments, the bonding surface will be bonded to another bonding surface of another semiconductor device. Attached Figure Description

[0052] The following description of the figures of exemplary embodiments further illustrates and explains various aspects of the improved concept. Components and parts of semiconductor devices having the same structure and function are denoted by the same reference numerals. Since the components and parts of the semiconductor devices in the different figures correspond to each other functionally, the following figures will not repeat the description of these components and parts.

[0053] Figures 1A to 1E A cross-section of an intermediate step in an exemplary embodiment of an improved semiconductor device manufacturing method is shown;

[0054] Figure 2 A cross-section of an alternative embodiment of a semiconductor device manufactured according to an alternative embodiment of the manufacturing method is shown;

[0055] Figure 3 A cross-section of an exemplary embodiment of a semiconductor device is shown;

[0056] Figure 4 A cross-section of an exemplary embodiment of a hybrid semiconductor device is shown;

[0057] Figure 5 A cross-section of another exemplary embodiment of a semiconductor device is shown; and

[0058] Figure 6 A cross-section of another exemplary embodiment of a hybrid semiconductor device is shown. Detailed Implementation

[0059] Figures 1A to 1E A cross-section of an intermediate step in an exemplary manufacturing method of a semiconductor device 1 according to an improved concept is shown. In this embodiment, a second chemical mechanical planarization (CMP) step completely removes the sacrificial material 5b deposited on the conductor material 5a.

[0060] Figure 1A A cross-section of an intermediate product of a semiconductor device 1 is shown after a layer of conductive material 5a is deposited on surface 3 of substrate 2 and a layer of sacrificial material 5b is deposited on the surface of the conductive material 5a layer facing away from substrate 2. Substrate 2 comprises a substrate material, which may be silicon. Substrate 2 may also include an integrated circuit, which may in particular be a CMOS circuit having active and / or passive circuitry. Such integrated circuits are known in themselves and are not shown in the figure. For example, substrate 2 at this stage may be a wafer or a chip diced from a wafer. Surface 3 of substrate 2 is, for example, a surface parallel to the main extending plane of substrate 2 and may be referred to as the top surface without loss of generality.

[0061] The layer deposited on surface 3 is a conductive material 5a, such as aluminum, titanium, tungsten, silicon, nitride, or any combination thereof. The thickness of the layer is typically 300 nm to 3 μm, but can also be smaller or larger, depending on the specific requirements of the conductor 5 ultimately determined for the semiconductor device 1.

[0062] A sacrificial material 5b layer is deposited on the surface of the conductor material 5a layer, facing away from the substrate 2. The sacrificial material 5b can be a conductive material (e.g., titanium nitride) different from the conductor material 5a, or it can be a dielectric material (e.g., an oxide). The thickness of this layer can be less than or greater than the thickness of the conductor material 5a layer, or equal to its thickness, depending on the requirements of subsequent steps in the manufacturing process. Typically, the sacrificial material 5b is deposited at a thickness of 100 nm to 1 μm.

[0063] Figure 1B It shows that according to Figure 1A The intermediate product is a cross-section after patterning and structuring the conductor material 5a and the sacrificial material 5b. Patterning and structuring can be performed by means of photolithography (e.g., beam or electron beam lithography) combined with wet or dry etching steps. Thus, patterning and structuring expose a portion of the surface 3 of the substrate, while the remaining structured conductor material 5a and sacrificial material 5b form a conductor stack on the surface 3, wherein the conductor stack is in contact with the substrate 2.

[0064] Figure 1C It shows that according to Figure 1B The intermediate product is shown in cross-section after the deposition of dielectric 4. Depositing dielectric 4 means depositing dielectric material on the conductor stack and on the surface 3 of the substrate. Thus, the dielectric material is different from the sacrificial material. For example, the dielectric material is an oxide such as silicon dioxide. The deposition of dielectric 4 is performed such that the conductor stack is embedded in dielectric 4. In other words, the thickness of dielectric 4, measured from the surface 3 of the substrate 2 in a direction perpendicular to the main extension plane of the substrate 2, is at least as large as the thickness of the conductor stack.

[0065] Figure 1D It shows that according to Figure 1C The cross-section of the intermediate product after the first CMP step. During this first step, a portion of the dielectric 4 is removed, reducing the thickness of the dielectric 4, at least until the sacrificial material 5b is exposed. In some cases, the first CMP step may be performed to the point that the thickness of the sacrificial material 5b is also reduced. However, the sacrificial material 5b is not completely removed during the first CMP step. For example, a first polishing slurry configured to remove the dielectric material is used to perform the first CMP step. For example, the first polishing slurry is a standard silica polishing slurry.

[0066] Figure 1E It shows that according to Figure 1EThe cross-section of the semiconductor device 1 after the second CMP step. The second step, also known as the polishing step, involves the removal of the dielectric 4 and sacrificial material 5b until the conductor material 5a is exposed to form the final conductor 5. After this step, the conductor 5 and dielectric 4 form a layer, meaning the thickness of the conductor 5 corresponds to the thickness of the dielectric 4. Therefore, the bonding surface 6 is the surface of the layer. The second CMP step differs from the first CMP step in, for example, in terms of the polishing slurry composition and / or material selectivity. For example, the selectivity of the polishing slurry between the dielectric 4 and the sacrificial material 5b is uniform, such that both materials are uniformly removed. In some cases, the second polishing slurry may have a non-uniform selectivity with respect to the dielectric 4 and the sacrificial material 5b. For example, the selectivity may be from 0.9 to 1.1 to optimize the microstructure and achieve improved results.

[0067] For example, the second polishing fluid does not contain contaminants such as cerium dioxide that would leave residues on any planarized surface and thus require further cleaning steps.

[0068] Therefore, the second CMP step achieves planarization of the bonding surface 6 of the semiconductor device 1, characterized by a surface morphology with a size of less than 10 nm, which can therefore be considered atomically smooth.

[0069] Figure 2 It shows the relationship with Figures 1A to 1E Compared to the manufacturing method of semiconductor device 1, the cross-section of an alternative embodiment of a semiconductor device manufactured following an alternative embodiment of the manufacturing method of semiconductor device 1 is shown. In this embodiment, during the second CMP step, the sacrificial material 5b is not completely removed and is therefore retained as part of the conductor 5 on the final semiconductor device 1, as... Figure 2 As shown.

[0070] In this embodiment, the sacrificial material 5b is a conductive material and, together with the conductive material 5a, forms the final conductor 5 of the semiconductor device 1. Leaving a layer of sacrificial material 5b on the final semiconductor device 1 has the advantage that the sacrificial material 5b promotes bonding with another semiconductor device. The thickness of the sacrificial material 5b on the final product can reach 50 nm. In this case, a suitable choice of sacrificial material is, for example, titanium nitride.

[0071] Figure 3 An embodiment of a semiconductor device 1 comprising a plurality of conductors 5 on the surface 3 of a semiconductor substrate is shown. The manufacturing method is similar to... Figures 1A to 1E The manufacturing method shown may require multiple conductors 5 to provide connections to multiple points of the integrated circuit included in the substrate 2.

[0072] Another difference is that, in this embodiment, the substrate 2 includes an insulating layer 2b in addition to the substrate 2a, to provide electrical insulation to, for example, active circuitry on the substrate 2. The insulating material can be the same as the dielectric 4, such as silicon dioxide.

[0073] Figure 4 A cross-section of an exemplary embodiment of a hybrid semiconductor device 10 including two semiconductor devices 1 and 1a according to an improved concept is shown. For example, the bonding surfaces 6 of the semiconductor devices 1 and 1a are bonded to each other by means of direct wafer bonding. For example, the first semiconductor device 1 is a CMOS device including active circuitry for evaluating signals from a transducer, while the other semiconductor device 1a is a MEMS device including the transducer.

[0074] To provide electrical interconnects, conductors 5 of semiconductor devices 1, 1a are connected to active and / or passive circuits via vias 7 (e.g., tungsten vias). The dimensions of conductors 5 are designed such that any offsets caused by imperfect bonding or manufacturing tolerances, even if they affect the electrical interconnects, are negligible.

[0075] Figure 5 and Figure 6 Alternative embodiments of semiconductor device 1 and semiconductor hybrid device 10 are shown respectively. (Compared to...) Figure 3 and Figure 4 Compared to the embodiments shown, these embodiments are characterized by the presence of sacrificial material 5b remaining on the conductor material 5a of each semiconductor device 1, 1a. As per [reference to...] Figure 2 As described in the embodiments of the semiconductor devices, in some cases, the residual sacrificial material 5b may be beneficial for bonding and lead to improved results.

[0076] Figures 1A to 6 The embodiments shown represent exemplary embodiments of semiconductor device 1, semiconductor hybrid device 10, and manufacturing methods according to the improved concept. Therefore, they do not constitute a complete list of all embodiments according to the improved concept. For example, actual semiconductor device configurations may differ from the illustrated embodiments in shape, size, and materials.

[0077] Explanation of reference numerals in the attached figures

[0078] 1,1a Semiconductor Devices

[0079] 2 Substrate

[0080] 2a substrate

[0081] 2b insulation layer

[0082] 3 surfaces

[0083] 4 dielectrics

[0084] 5 conductors

[0085] 5a conductor material

[0086] 5b Sacrificial Material

[0087] 6-bonded surface

[0088] 7 vias

[0089] 10 Hybrid Semiconductor Devices

Claims

1. A semiconductor device (1), comprising: Substrate (2), which has a surface (3); Conductor (5), comprising a conductor material (5a) covering at least a portion of said surface (3); and The dielectric (4) is disposed on the portion of the surface (3) not covered by the conductor (5); in The conductor (5) is in contact with the substrate (2); The conductor (5) and the dielectric (4) form a layer; The bonding surface (6) of the layer has a surface morphology of less than 10 nm, wherein the bonding surface (6) is away from the substrate (2). Semiconductor device (1) does not have diffusion barrier; and The conductor (5) includes a sacrificial material (5b) disposed on the surface of the conductor material (5a) away from the substrate (2), and the sacrificial material (5b) is a dielectric material different from the dielectric (4). The dielectric (4) and the sacrificial material (5b) form the bonding surface (6), and the bonding surface is planarized to form the surface morphology.

2. The semiconductor device (1) according to claim 1, wherein, The conductor material (5a) includes one of aluminum, titanium, tungsten, silicon, nitride, or any combination thereof.

3. The semiconductor device (1) according to claim 1 or 2, wherein The substrate (2) includes an insulating layer (2b) disposed on the substrate (2a); and The surface (3) is the surface of the insulating layer (2b) that is opposite to the substrate (2a).

4. The semiconductor device (1) according to claim 3, wherein the insulating layer (2b) is an oxide layer.

5. The semiconductor device (1) according to claim 3, wherein, The substrate is a silicon substrate.

6. A semiconductor hybrid device (10), comprising: The semiconductor device (1) according to claim 1; and Another semiconductor device (1a) having another bonding surface; The semiconductor device (1) is bonded to the other semiconductor device (1a).

7. The semiconductor hybrid device (10) according to claim 6, wherein The semiconductor device (1) is a CMOS device; and The other semiconductor device (1a) is a MEMS and / or CMOS device.

8. The semiconductor hybrid device (10) according to claim 6 or 7, wherein, The other semiconductor device (1a) is the semiconductor device (1) according to claim 1.

9. A method for manufacturing a semiconductor device (1), the method comprising: A substrate (2) having a surface (3) is provided; A conductor (5) is deposited on the surface (3); Patterning and structuring the conductor (5); Dielectric (4) is deposited on the conductor (5) and on the exposed portion of the surface (3); as well as The bonding surface (6) of the semiconductor device (1) is formed by removing part of the dielectric (4) through multiple chemical mechanical planarization (CMP) steps. The bonding surface (6) has a surface morphology of less than 10 nm. The deposition of conductor (5) includes depositing conductor material (5a) on the surface (3) and depositing sacrificial material (5b) on the conductor material (5a), wherein the sacrificial material (5b) is a conductive material different from the conductor material (5a); Forming the bonding surface (6) includes removing at least a portion of the sacrificial material (5b); The dielectric (4) and the layer of the sacrificial material (5b) remaining on the semiconductor device form the bonding surface (6), which is planarized to form the surface morphology.

10. The method of claim 9 further comprises bonding another semiconductor device (1a) to the bonding surface (6).

11. The method according to claim 10, wherein, The hybrid bonding is a wafer-to-wafer or die-to-wafer hybrid bonding.

12. The method according to claim 9, wherein the conductive material is titanium nitride.

13. The method according to claim 9 or 10, wherein, Execute multiple CMP steps consecutively.

14. The method of claim 13, wherein the plurality of CMP steps are performed without intermediate metal deposition.

15. The method according to claim 9 or 10, wherein, At least one of the multiple CMP steps is a timed CMP step.

16. The method according to claim 9 or 10, wherein, Multiple CMP steps differ from one another in terms of slurry composition and / or material selectivity.

17. The method according to claim 9 or 10, wherein, Multiple CMP steps include dielectric removal and polishing steps.

18. The method according to claim 9 or 10, wherein The first polishing slurry is used to perform the first step of a series of CMP steps, wherein the first polishing slurry removes the dielectric (4); and The second step in a series of CMP steps is performed using a second polishing slurry, which has a selectivity of 0.9 to 1.1 for the materials of the dielectric (4) and the conductor (5).

19. The method according to claim 18, wherein, The second polishing slurry is selective for the dielectric (4) and the sacrificial material (5b) of the conductor (5).

20. The method according to claim 18, wherein, The selectivity mentioned is a uniform selectivity.

21. The method according to claim 9 or 10, wherein, The polishing slurry used during multiple CMP steps is a non-cerium dioxide-based polishing slurry.

22. The method according to claim 9 or 10, wherein, The manufacturing method is CMOS compatible.

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