An interdigital capacitor and a multiplying digital-to-analog conversion circuit

Abstract

An interdigital capacitor and a multiplying digital-to-analog conversion circuit. The interdigital capacitor includes: at least one first metal layer, in each first metal layer, a first electrode is provided, at least one first finger metal connected to the first electrode, and a second electrode, a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. Among them, at least one first finger metal and the plurality of second finger metals are alternately arranged to form a capacitor, and at least one third finger metal is a dummy finger metal.

Description

Technical Field

[0001] The present application relates to the field of circuit technologies, and in particular, to an interdigital capacitor and a multiplying digital-to-analog conversion circuit. Background Art

[0002] With the rapid development of digital electronic technologies, various digital devices, especially digital electronic computers, are widely used in various fields of the national economy, such as industrial control, communication, etc. Digital devices can only process digital signals. Therefore, analog signals (such as temperature, pressure) need to be converted into digital signals by an analog-to-digital converter (ADC) before they can be processed by digital devices.

[0003] ADCs based on binary weighted capacitor networks (such as pipelined ADCs, charge redistribution successive approximation register (SAR) ADCs) have the characteristics of low cost and easy integration, and are widely used in digital devices. Among them, the accuracy of capacitors has a great influence on the performance of ADCs based on capacitor arrays.

[0004] For example, a multiplying digital-to-analog converter (MDAC) is a key circuit in a pipelined ADC. Improving the performance of the MDAC is one of the keys to improving the overall performance of the pipelined ADC. As Figure 1 shown, the MDAC adopts a capacitor charge transfer closed-loop structure and a sampling capacitor array. C i is the sampling capacitor, C f is the closed-loop feedback capacitor, D i = ±1, which is determined by the output of the sub-ADC in the pipelined ADC. Φ1 and Φ2 are switches controlled by a sampling and holding control clock signal, V ref is the reference voltage of the sub-DAC. Assuming that the gain of the operational amplifier A is infinite, the transfer function of the MDAC can be obtained according to the principle of charge conservation as:

[0005]

[0006] Where C s is the total sampling capacitor, and W i represents the weight of each unit sampling capacitor. It can be seen from the above formula that sampling capacitor mismatch will cause linear gain (C s / C f ) error and analog-to-digital conversion DAC error in the transfer function, making the final output quantization result of the pipelined ADC non-linear.

[0007] As the requirements for the accuracy of ADCs based on binary weighted capacitor networks are getting higher and higher, among the existing capacitor types, only metal-oxide-metal (MOM) capacitors can be fabricated with relatively small capacitance values and at low cost. Therefore, in order to improve the accuracy of ADCs based on binary weighted capacitor networks, it is urgent to propose a high-precision MOM capacitor. Summary of the Invention

[0008] This application provides an interdigital capacitor and a multiplying digital-to-analog conversion circuit to reduce the mismatch rate of the interdigital capacitor and improve the accuracy of the interdigital capacitor.

[0009] In a first aspect, this application provides an interdigital capacitor, which includes: at least one first metal layer, in each first metal layer, a first electrode is provided, at least one first finger metal connected to the first electrode, and a second electrode, a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. Among them, at least one first finger metal and a plurality of second finger metals are alternately arranged to form a capacitor, and at least one third finger metal is a dummy finger metal, that is, at least one third finger metal does not form a capacitor with any one of at least one first finger metal and a plurality of second finger metals.

[0010] Through the above solution, since there is one or more dummy finger metals (third finger metals) in the first metal layer of the interdigital capacitor, when the layout area of the interdigital capacitor is fixed, the capacitance value of the interdigital capacitor can be flexibly changed by adjusting parameters such as the number of first finger metals, the number of second finger metals and third finger metals, and the length of the first finger metal and the length of the second finger metal. In addition, since there is one or more dummy finger metals in the first metal layer of the interdigital capacitor, the layout sizes of interdigital capacitors with different capacitance values can be the same, which is beneficial to the layout of the circuit layout where the interdigital capacitor is located, the reasonable utilization of the area, and is beneficial to reducing the process deviation between interdigital capacitors with different capacitance values.

[0011] In a possible implementation manner, the first metal electrodes in two adjacent first metal layers are connected to each other through a first conductive channel, and the second metal electrodes in two adjacent first metal layers are connected to each other through a second conductive channel. Among them, the first conductive channel and the second conductive channel can be through holes filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers.

[0012] In a possible implementation manner, at least one third finger metal is located on the same side of a plurality of second finger metals; or, when the first metal layer includes a plurality of third finger metals, the plurality of third finger metals are located on both sides of the plurality of second finger metals.

[0013] In a possible implementation, when the first metal layer includes a plurality of first interdigital metals, the lengths of the plurality of first interdigital metals are different.

[0014] In a possible implementation, the lengths of the plurality of second interdigital metals are different.

[0015] In a possible implementation, for any one of the first metal layers in the interdigital capacitor, the number of first interdigital metals, the number of second interdigital metals, the effective length of the first interdigital metals, and the distance between adjacent first interdigital metals and second interdigital metals are set according to the capacitance value of the first metal layer. Wherein, the effective length of the first interdigital metal is the length of the part of the first interdigital metal that can form a sidewall capacitance with the adjacent second interdigital metal; the capacitance value of the first metal layer is positively correlated with the number of first interdigital metals, the number of second interdigital metals, and the effective length of the first interdigital metals; the capacitance value of the first metal layer is negatively correlated with the distance between adjacent first interdigital metals and second interdigital metals.

[0016] In a possible implementation, the distance between adjacent two interdigital metals in the first metal layer is greater than or equal to a first threshold value, and the width of each interdigital metal in the first metal layer is greater than or equal to a second threshold value. Wherein, when the distance between adjacent two interdigital metals in the first metal layer is greater than or equal to the first threshold value and the width of each interdigital metal in the first metal layer is greater than or equal to the second threshold value, the interdigital capacitor can be placed horizontally and vertically.

[0017] In a possible implementation, the distance between adjacent two interdigital metals in the first metal layer can be greater than or equal to 0.08 μm, and the width of each interdigital metal in the first metal layer can be greater than or equal to 0.08 μm.

[0018] In a possible implementation, the interdigital capacitor further includes a second metal layer disposed on at least one first metal layer, and the second metal layer is used to shield the interference of the external environment to at least one first metal layer.

[0019] In a possible implementation, the second metal layer includes a third electrode and a plurality of fourth interdigital metals respectively connected to the third electrode. Wherein, the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, or the third electrode is electrically connected to the second electrode in the second metal layer adjacent to the second metal layer through a third conductive channel. Wherein, the third conductive channel can be a through hole filled with metal (such as tungsten) in the dielectric layer between the second metal layer and the first metal layer adjacent to the second metal.

[0020] Further, the second metal layer may further include a fifth electrode. When the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel; when the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel.

[0021] In a possible implementation, the interdigital capacitor may further include a third metal layer disposed under at least one first metal layer, and the third metal layer is used to shield the interference of the external environment to at least one first metal layer.

[0022] In a possible implementation, the third metal layer includes a fourth electrode and a plurality of fifth interdigital metals respectively connected to the fourth electrode. The fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, or the fourth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel. The fourth conductive channel may be a through hole filled with a metal (such as tungsten) in the dielectric layer between the third metal layer and the first metal layer adjacent to the second metal layer.

[0023] Further, the third metal layer may further include a sixth electrode. When the fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel; when the fourth electrode is electrically coupled to the second electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel.

[0024] In a possible implementation, in order to meet the requirements of the processing technology for the metal density in the interdigital capacitor, the interdigital capacitor further includes at least one fourth metal layer for density filling, that is, for increasing the metal density of the layer where the fourth metal layer is located in the interdigital capacitor. At least one fourth metal layer is disposed on the top of the interdigital capacitor, that is, all the fourth metal layers are disposed on the top of the interdigital capacitor; or at least one fourth metal layer is disposed on the bottom of the interdigital capacitor, that is, all the fourth metal layers are disposed on the bottom of the interdigital capacitor; or a part of at least one fourth metal layer is disposed on the top of the interdigital capacitor, and another part of at least one fourth metal layer is disposed on the bottom of the interdigital capacitor.

[0025] In a possible implementation, each fourth metal layer includes one or more strip-shaped filling metals.

[0026] In one possible implementation, in order to minimize the influence of the filling metal on the interdigital capacitor, the length direction of the filling metal is perpendicular to the length direction of the first interdigital metal and the length direction of the second interdigital metal respectively.

[0027] In one possible implementation, the interdigital capacitor further includes a substrate, an intrinsic layer (such as an NT N layer) is provided in the substrate, and at least one first metal layer is provided on the upper surface of the intrinsic layer to avoid interference caused by noise in the substrate to the interdigital capacitor.

[0028] In one possible implementation, the interdigital capacitor is a metal-oxide-metal (MOM) capacitor, and the MOM capacitor includes a plurality of first metal layers stacked parallel to each other.

[0029] In a second aspect, the present application further provides another interdigital capacitor, which includes: at least one first metal layer, a first electrode is provided in each first metal layer, at least one first interdigital metal connected to the first electrode, and a second electrode, and a plurality of second interdigital metals connected to the second electrode. Wherein, at least one first interdigital metal and at least one second interdigital metal are alternately arranged to form a capacitor, and the number of the second interdigital metals is greater than the number of the first interdigital metals.

[0030] In one possible implementation, the first metal electrodes in two adjacent first metal layers are connected to each other through a first conductive channel, and the second metal electrodes in two adjacent first metal layers are connected to each other through a second conductive channel. Wherein, the first conductive channel and the second conductive channel can be through holes filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers.

[0031] In one possible implementation, when the first metal layer includes a plurality of first interdigital metals, the lengths of the plurality of first interdigital metals are different.

[0032] In one possible implementation, the lengths of the plurality of second interdigital metals are different.

[0033] In one possible implementation, for any one of the first metal layers in the interdigital capacitor, the number of the first interdigital metals, the number of the second interdigital metals, the effective length of the first interdigital metals, and the distance between the adjacent first interdigital metal and the second interdigital metal are set according to the capacitance value of the first metal layer. Wherein, the effective length of the first interdigital metal is the length of the part of the first interdigital metal that can form a sidewall capacitance with the adjacent second interdigital metal; the capacitance value of the first metal layer is positively correlated with the number of the first interdigital metals, the number of the second interdigital metals, and the effective length of the first interdigital metals; the capacitance value of the first metal layer is negatively correlated with the distance between the adjacent first interdigital metal and the second interdigital metal.

[0034] In a possible implementation, the distance between two adjacent first interdigital metals and the second interdigital metal in the first metal layer is greater than or equal to a first threshold, and the widths of the first interdigital metal and the second interdigital metal in the first metal layer are greater than or equal to a second threshold. Wherein, when the distance between two adjacent first interdigital metals and the second interdigital metal in the first metal layer is greater than or equal to the first threshold and the width of each interdigital metal in the first metal layer is greater than or equal to the second threshold, the interdigital capacitor can be placed horizontally and vertically.

[0035] In a possible implementation, the distance between two adjacent interdigital metals in the first metal layer can be greater than or equal to 0.08 μm, and the width of each interdigital metal in the first metal layer can be greater than or equal to 0.08 μm.

[0036] In a possible implementation, the interdigital capacitor further includes a second metal layer disposed on at least one first metal layer, and the second metal layer is used to shield the interference of the external environment on at least one first metal layer.

[0037] In a possible implementation, the second metal layer includes a third electrode and a plurality of fourth interdigital metals respectively connected to the third electrode. Wherein, the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, or the third electrode is electrically connected to the second electrode in the second metal layer adjacent to the second metal layer through a third conductive channel. Wherein, the third conductive channel can be a through hole filled with metal (such as tungsten) in the dielectric layer between the second metal layer and the first metal layer adjacent to the second metal layer.

[0038] Further, the second metal layer may further include a fifth electrode. Wherein, when the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, the fifth electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through a fifth conductive channel; when the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, the fifth electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a fifth conductive channel.

[0039] In a possible implementation, the interdigital capacitor may further include a third metal layer disposed under at least one first metal layer, and the third metal layer is used to shield the interference of the external environment on at least one first metal layer.

[0040] In a possible implementation, the third metal layer includes a fourth electrode and a plurality of fifth interdigital metals respectively connected to the fourth electrode. Among them, the fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel, or the fourth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel. Among them, the fourth conductive channel can be a through hole filled with a metal (such as tungsten) in the dielectric layer between the third metal layer and the first metal layer adjacent to the second metal layer.

[0041] Furthermore, the third metal layer may further include a sixth electrode. Among them, when the fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel, the sixth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through a sixth conductive channel; when the fourth electrode is electrically coupled to the second electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel, the sixth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through a sixth conductive channel.

[0042] In a possible implementation, in order to meet the requirements of the processing technology for the metal density in the interdigital capacitor, the interdigital capacitor further includes at least one fourth metal layer, and the fourth metal layer is used for density filling, that is, for increasing the metal density of the layer where the fourth metal layer is located in the interdigital capacitor. Among them, at least one fourth metal layer is provided on the top of the interdigital capacitor, that is, all the fourth metal layers are provided on the top of the interdigital capacitor; or, at least one fourth metal layer is provided at the bottom of the interdigital capacitor, that is, all the fourth metal layers are provided at the bottom of the interdigital capacitor; or, a part of at least one fourth metal layer is provided on the top of the interdigital capacitor, and another part of at least one fourth metal layer is provided at the bottom of the interdigital capacitor.

[0043] In a possible implementation, each fourth metal layer includes one or more strip-shaped filling metals.

[0044] In a possible implementation, in order to minimize the influence of the filling metal on the interdigital capacitor, the length directions of the filling metals are respectively perpendicular to the length directions of the first interdigital metal and the second interdigital metal.

[0045] In a possible implementation, the interdigital capacitor further includes a substrate, and an intrinsic layer (such as NT_N layer) is provided in the substrate, and at least one first metal layer is provided on the upper surface of the intrinsic layer to avoid the interference caused by the noise in the substrate to the interdigital capacitor.

[0046] In a possible implementation, the interdigital capacitor is a metal-oxide-metal MOM capacitor, and the MOM capacitor includes a plurality of first metal layers stacked parallel to each other.

[0047] In a third aspect, the present application also provides a multiplicative digital-to-analog conversion circuit, which includes a switched-capacitor array, a feedback capacitor, and an operational amplifier. Among them, the switched-capacitor array includes k switches and k interdigital capacitors corresponding to the k switches one by one, where the k switches are any one of the possible implementation manners provided in the above first aspect or second aspect, and k is a positive integer; for any one of the k switches, the switch is configured to selectively output a voltage to be processed or a reference voltage to the first end of the interdigital capacitor corresponding to the switch, and the second ends of the interdigital capacitors corresponding to the switch are respectively coupled to the first input end of the operational amplifier and the first end of the feedback capacitor, the second end of the operational amplifier is grounded, and the second end of the feedback capacitor is coupled to the output end of the operational amplifier.

[0048] In a possible implementation manner, the capacitance values of the k interdigital capacitors are C, 2C, 2 2 C,..., 2 k-1 C, where C is a constant. Description of the Drawings

[0049] Figure 1 is a schematic structural diagram of an MDAC in the prior art;

[0050] Figure 2 is a schematic structural diagram of a MOM capacitor in the prior art;

[0051] Figure 3 is a schematic diagram showing the relationship between the capacitance value of the interdigital capacitor provided in the embodiment of the present application and the number of finger metals in the interdigital capacitor;

[0052] Figure 4a is one of the schematic structural diagrams of an interdigital capacitor provided in the embodiment of the present application;

[0053] Figure 4b is one of the schematic structural diagrams of a first metal layer provided in the embodiment of the present application;

[0054] Figure 4c is another schematic structural diagram of a first metal layer provided in the embodiment of the present application;

[0055] Figure 4d is yet another schematic structural diagram of a first metal layer provided in the embodiment of the present application;

[0056] Figure 4e is still another schematic structural diagram of a first metal layer provided in the embodiment of the present application;

[0057] Figure 5a is a schematic structural diagram of a horizontally placed interdigital capacitor provided in the embodiment of the present application;

[0058] Figure 5bSchematic diagram of the structure of a vertically placed interdigital capacitor provided by an embodiment of the present application;

[0059] Figure 6 Fifth schematic diagram of the structure of the first metal layer in an interdigital capacitor provided by an embodiment of the present application;

[0060] Figure 7a Second schematic diagram of the structure of an interdigital capacitor provided by an embodiment of the present application;

[0061] Figure 7b Third schematic diagram of the structure of an interdigital capacitor provided by an embodiment of the present application;

[0062] Figure 7c Fourth schematic diagram of the structure of an interdigital capacitor provided by an embodiment of the present application;

[0063] Figure 8 Fifth schematic diagram of the structure of an interdigital capacitor provided by an embodiment of the present application;

[0064] Figure 9 Sixth schematic diagram of the structure of an interdigital capacitor provided by an embodiment of the present application;

[0065] Figure 10 Schematic diagram of the structure of a multiplication digital-to-analog conversion circuit provided by an embodiment of the present application. Detailed implementation manners

[0066] The MOM capacitor adopts a method combining a finger structure and a stacked layer, and a capacitor with a larger capacitance value can be fabricated on a relatively small area. With the evolution of the processing technology and the increase of the parasitic capacitance of the traces, the difficulty of realizing a high-precision MOM capacitor increases accordingly. The capacitance value of the existing MOM capacitor changes with the number of interdigital metals and the ratio W / L of the width W of the interdigital metal to the length L of the interdigital metal, and cannot achieve an equal-proportion change, which will lead to a relatively high capacitance mismatch rate, thereby restricting the improvement of the performance of the ADC based on the binary weighted capacitor network.

[0067] In the existing layout of the MOM capacitor, according to the requirements of the processing technology, the number of interdigital metal electrodes is 4*N (N is an integer, * represents multiplication). The capacitance value of the MOM capacitor is mainly formed by the sidewall capacitance of two adjacent interdigital metals. For example, as Figure 2The vertically placed MOM capacitor is shown. Assume that the capacitance value of the unit capacitance formed by two adjacent finger metals in the MOM capacitor is C0. Under the condition that the width and length of the finger metals remain unchanged, when the MOM capacitor includes 12 finger metals, the capacitance value of the MOM capacitor is 11*C0. When the MOM capacitor includes 24 finger metals, the capacitance value of the MOM capacitor is 23*C0. That is, the capacitance value of the MOM capacitor is always (M - 1)*C0, where M is the number of finger metals included in the MOM capacitor. Therefore, when the number of finger metals in the MOM capacitor changes in equal proportion, the capacitance value of the MOM capacitor does not change in the same proportion, as Figure 3 shown, where the actual capacitance value refers to the capacitance value of the existing MOM capacitor, and the ideal capacitance value refers to the capacitance value of the MOM capacitor whose capacitance value changes in equal proportion according to the number of finger metals. From Figure 3 it can be seen that when the number of finger metals in the MOM capacitor changes in proportion, the actual capacitance value is larger than the ideal capacitance value, which will cause linear errors in the ADC based on the binary weighted capacitor network.

[0068] In addition, for the MOM capacitor provided by the existing 16-nanometer (nm) process library, the capacitance value of the smallest size is 2.33 femtofarads (fF). For the ADC circuit design with higher precision requirements, the capacitance value of the smallest capacitor is required to reach 0.25 fF. Therefore, it needs to be realized by connecting multiple capacitors in series, resulting in a large layout area overhead.

[0069] Based on this, the present application provides an interdigital capacitor and a multiplying digital-to-analog conversion circuit to improve the above-mentioned defects existing in the existing MOM capacitor.

[0070] The present application provides an interdigital capacitor, and specifically, the interdigital capacitor can be a MOM capacitor. As Figure 4aAs shown, the interdigital capacitor includes at least one first metal layer 410. In each first metal layer 410, a first electrode 411 is provided, at least one first interdigital metal 412 connected to the first electrode 411, and a second electrode 413, a plurality of (two or more) second interdigital metals 414 connected to the second electrode 413, and at least one third interdigital metal 415 connected to the second electrode 413. Among them, at least one first interdigital metal 412 and a plurality of second interdigital metals 414 are alternately arranged to form a capacitor. At least one third interdigital metal 415 is a dummy interdigital metal. Those skilled in the art should know that in integrated circuit design, in addition to designing circuits that can implement the logic or functions of the circuit to ensure correct LVS (Layout Versus Schematics) verification, some graphics unrelated to LVS, that is, dummy circuits, will also be added according to design requirements. Therefore, it can be understood that at least one third interdigital metal 415, as a dummy circuit, will not form a capacitor with any one of at least one first interdigital metal 412 and at least one second interdigital metal 414.

[0071] Among them, the first electrode can be a positive electrode or a negative electrode. When the first electrode is a positive electrode, the second electrode is a negative electrode, and when the first electrode is a negative electrode, the second electrode is a positive electrode. The first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 are finger-shaped metals (fingers) connected to the corresponding electrodes in the interdigital capacitor. The first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 in the first metal layer 410 of the interdigital capacitor are usually multiple mutually parallel conductive electrodes obtained by photolithography and etching of the metal on the first metal layer 410, and are usually arranged in a comb shape (i.e., comb structure). The first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 are the comb teeth parts. Therefore, the interdigital metals (the first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415) in the interdigital capacitor can also be called electrode fingers. At least one first interdigital metal 412 and a plurality of second interdigital metals 414 are alternately arranged, which means that the first interdigital metal 412 and the second interdigital metal 414 are arranged alternately and repeatedly. For example, as Figure 4a shown, the first metal layer 410 includes 2 first interdigital metals 412 and 3 second interdigital metals. These 5 interdigital metals appear alternately in the horizontal direction according to the rule of first the first interdigital metal 412 and then the second interdigital metal 414.

[0072] When the interdigital capacitor includes multiple (two or more) first metal layers 410, the multiple first metal layers 410 can be stacked parallel to each other. When the interdigital capacitor is a MOM capacitor, the MOM capacitor generally includes multiple first metal layers 410 stacked parallel to each other. Further, the first metal electrodes 411 in two adjacent first metal layers 410 are connected to each other through a first conductive channel, and the second metal electrodes 413 in two adjacent first metal layers 410 are connected to each other through a second conductive channel. The first conductive channel and the second conductive channel can be through holes filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers 410.

[0073] A dielectric (not shown in the figure, usually an oxide) can be provided between adjacent first finger metals 412 and second finger metals 414 in the same first metal layer 410. Figure 4a Between two adjacent first metal layers 410, they can also be separated by a dielectric layer (not shown in the figure). Figure 4a Not shown in the figure).

[0074] Since there is one or more dummy finger metals, i.e., third finger metals 415, in the first metal layer 410 of the interdigital capacitor, when the layout area of the interdigital capacitor is fixed, the capacitance value of the interdigital capacitor can be flexibly changed by adjusting parameters such as the number of first finger metals 412, the number of second finger metals 414 and third finger metals 415, the length of the first finger metal 412, and the length of the second finger metal 414. In addition, since there is one or more dummy finger metals in the first metal layer 410 of the interdigital capacitor, the layout sizes of interdigital capacitors with different capacitance values can be the same, which is beneficial to the layout of the circuit layout where the interdigital capacitor is located, the rational utilization of the area, and is beneficial to reducing the process deviation between interdigital capacitors with different capacitance values, and thus can improve the matching of the interdigital capacitor.

[0075] Further, when the first metal layer 410 includes multiple first finger metals 412, the lengths of the multiple first finger metals 412 are different. The lengths of the multiple second finger metals 414 can be the same or different, that is, the lengths of the multiple first finger metals 412 are different and the lengths of the multiple second finger metals 414 are the same, as shown in Figure 4b the figure, or the lengths of the multiple first finger metals 412 are different and the lengths of the multiple second finger metals 414 are also different, as shown in Figure 4c the figure; or the lengths of the multiple second finger metals 414 are different, as shown in Figure 4d the figure. At this time, the capacitances formed by each two adjacent first finger metals 412 and second finger metals 414 in the first metal layer 410 can be different, so that the capacitance value of the first metal layer 410 can change more flexibly according to actual requirements.

[0076] It should be noted that the different lengths of multiple first interdigital metals 412 mean that the lengths of some or all of the first interdigital metals 412 among the multiple first interdigital metals 412 are different, and the different lengths of multiple second interdigital metals 414 mean that the lengths of some or all of the second interdigital metals 412 among the multiple second interdigital metals 414 are different.

[0077] Furthermore, as Figure 4e shown, at least one third interdigital metal 415 can be located on the same side of multiple second interdigital metals 414; or, when the first metal layer 410 includes multiple third interdigital metals 415, the multiple third interdigital metals 415 are located on both sides of the multiple second interdigital metals 414, as Figure 4a shown. In addition, when the length of the second interdigital metal 414 is greater than the length of the first interdigital metal 412 adjacent to the second interdigital metal, the third interdigital metal 415 can also be located at the position corresponding to the first interdigital metal 412 adjacent to the second interdigital metal 414, and the sum of the length of the third interdigital metal 415 and the length of the first interdigital metal 412 is less than the length of the second interdigital metal 414. That is to say, when the first metal layer 410 includes multiple third interdigital metals 415, the lengths of some or all of the multiple third interdigital metals 415 can be different.

[0078] In specific implementation, the number of first interdigital metals 412, the number of second interdigital metals 414, the effective length of the first interdigital metal 412 (the effective length of the second interdigital metal 414 forming the sidewall capacitance is the same as the effective length of the first interdigital metal 412 forming the sidewall capacitance), and the distance between the adjacent first interdigital metal 412 and the second interdigital metal 414 are set according to the capacitance value of the first metal layer 410. Among them, the effective length of the first interdigital metal 412 is the length of the part of the first interdigital metal 412 that can form a sidewall capacitance with the adjacent second interdigital metal 414; the capacitance value of the first metal layer 410 is positively correlated with the number of first interdigital metals 412, the number of second interdigital metals 414, and the effective length of the first interdigital metal 412; the capacitance value of the first metal layer 410 is negatively correlated with the distance between the adjacent first interdigital metal 412 and the second interdigital metal 414.

[0079] Specifically, for any one of the first metal layers 410 in the interdigital capacitor, the capacitance value of the capacitance of the first metal layer 410 is the sum of the capacitance values of multiple sidewall capacitances formed by at least one first finger metal 412 and multiple second finger metals 414 in the first metal layer 410. Among them, the sidewall capacitance is the capacitance formed between an adjacent first finger metal 412 and a second finger metal 414, and the interdigital capacitor is obtained by paralleling the capacitances of the first metal layers 410 included in the interdigital capacitor. Therefore, in order to achieve an interdigital capacitor with a set capacitance value, the number of sidewall capacitances formed by at least one first finger metal 412 and multiple second finger metals 414 and the capacitance value of each sidewall capacitance are set according to the capacitance value of the first metal layer 410. The number of sidewall capacitances formed by at least one first finger metal 412 and multiple second finger metals 414 is related to the number of first finger metals 412 and the number of second finger metals 414. N1 first finger metals 412 and N2 second finger metals 414 can form (N1 + N2) - 1 sidewall capacitances. At this time, the capacitance value of the first metal layer 410 is where C i is the capacitance value of the i-th sidewall capacitance among the (N1 + N2) - 1 sidewall capacitances.

[0080] Since the lengths of each first finger metal 412 included in the first metal layer 410 can be the same or different, the lengths of each second finger metal 412 included in the first metal layer 410 can be the same or different, the lengths of the first finger metals 412 and the second finger metals 414 included in the first metal layer 410 can be the same or different, the distances and other parameters between every two adjacent first finger metals 412 and second finger metals 412 in the first metal layer 410 can be the same or different, etc., therefore, the capacitance values of the N - 1 sidewall capacitances may be the same or different. In most cases, the lengths of each first finger metal 412 and the second finger metals 414 included in the first metal layer 410 are the same, the distances between adjacent first finger metals 412 and second finger metals 412 are also the same, the capacitance values of the (N1 + N2) - 1 sidewall capacitances are also equal, and the sum of the capacitance values of the N - 1 sidewall capacitances is ((N1 + N2) - 1) * C, where C is the capacitance value of any one of the (N1 + N2) - 1 sidewall capacitances.

[0081] Further, the effective length of the first interdigital metal 412 forming the sidewall capacitor and the distance between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor are set according to the capacitance value of the sidewall capacitor. The effective length of the first interdigital metal is the length of the part of the first interdigital metal that can form a sidewall capacitor with the adjacent second interdigital metal. The capacitance value of the sidewall capacitor is positively correlated with the length of the shortest interdigital metal among the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor. That is, when other parameters of the first interdigital metal 412 and the second interdigital metal 413 forming the sidewall capacitor (the width of the first interdigital metal 412 and the width of the second interdigital metal 414, the distance between the first interdigital metal 412 and the second interdigital metal 414) remain unchanged, the longer the length of the shortest interdigital metal among the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor, the larger the capacitance value of the sidewall capacitor, and the shorter the length of the shortest interdigital metal among the first interdigital metal 412 and the second interdigital metal 414, the smaller the capacitance value of the sidewall capacitor. The capacitance value of the sidewall capacitor is negatively correlated with the distance between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor. When other parameters of the first interdigital metal 412 and the second interdigital metal 413 forming the sidewall capacitor remain unchanged (the width of the first interdigital metal 412 and the width of the second interdigital metal 414, and the length of the first interdigital metal 412 and the length of the second interdigital metal), the larger the distance between the first interdigital metal 412 and the second interdigital metal 414 adjacent to the first interdigital metal 412 forming the sidewall capacitor, the smaller the capacitance value of the sidewall capacitor, and the smaller the distance between the first interdigital metal 412 and the second interdigital metal 414 adjacent to the first interdigital metal 412 forming the sidewall capacitor, the larger the capacitance value of the sidewall capacitor.

[0082] Among them, in the scenario where the width of the first interdigital metal 412 is equal to the width of the second interdigital metal 414, the capacitance value C0 of the sidewall capacitor, the effective lengths L of the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor, the width W of the first interdigital metal 412 (or the second interdigital metal 414), and the distance S between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor satisfy the following conditions:

[0083]

[0084] ε is the dielectric constant of the dielectric between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor, and L is the length of the part of the first interdigital metal 412 and the second interdigital metal 414 that can form a capacitor.

[0085] In practical applications, due to the limitations of the processing technology, the capacitance value of the smallest MOM capacitor provided by the existing 16nm process library is 2.33fF. For the design of ADC circuits with relatively high precision requirements, the capacitance value of the smallest capacitor is required to reach 0.25fF. Therefore, it needs to be realized by connecting multiple capacitors in series, resulting in a large layout area overhead. The interdigital capacitor provided by the embodiment of the present application can obtain an interdigital capacitor with a smaller capacitance value by adjusting the length of the first interdigital metal 412, the length of the second interdigital metal, the number of the first interdigital metals 412, and the number of the second interdigital metals 414. For example, the interdigital capacitor provided by the embodiment of the present application can reach 1.202fF, or even smaller. Compared with the smallest capacitor 2.33178fF that can be provided in the existing process library, the capacitance value of the interdigital capacitor provided by the embodiment of the present application is reduced by 50%. Specifically, the distance between two adjacent first interdigital metals 412 and the second interdigital metal 414 can be greater than or equal to 0.08μm.

[0086] Furthermore, during the processing of the interdigital capacitor, when the placement direction (horizontally or vertically) of the interdigital capacitor is different, the processing technology has different requirements for the distance between adjacent interdigital metals in the interdigital capacitor and the width of the interdigital metals in the interdigital capacitor. Therefore, in order to ensure that the interdigital capacitor can be placed horizontally (such as Figure 5a ), and can also be placed vertically (such as Figure 5b ), that is, the interdigital capacitor can be flipped arbitrarily, the distance between two adjacent interdigital metals in the first metal layer 410 (including the distance between the adjacent first interdigital metal 412 and the second interdigital metal 414, the distance between the adjacent second interdigital metal 414 and the third interdigital metal 415, and the distance between adjacent third interdigital metals) is greater than or equal to the first threshold, and the width of each interdigital metal in the first metal layer 410 (including the width of the first interdigital metal 412, the width of the second interdigital metal 414, and the distance of the third interdigital metal 415) is greater than or equal to the second threshold, so as to meet the minimum width and spacing design rule check (DRC) for horizontal and vertical placement, so that the interdigital capacitor can be placed horizontally and vertically. For the 16nm process library, the first threshold can be 0.08μm, and the second threshold can be 0.08μm.

[0087] For example, as shown in (a)-(d) of Figure 6 , the areas of the first metal layer 410 are the same, and the widths of the first interdigital metal 412, the second interdigital metal 414, and the distance between two adjacent first interdigital metals 412 and the second interdigital metal 414 in the first metal layer 410 shown in (a)-(d) are the same. Figure 6The first metal layer 410 shown in (a) includes 1 first interdigital metal 412, 2 second interdigital metals 414, and 7 third interdigital metals 415. The lengths of the first interdigital metal 412 and the second interdigital metals 414 that can form the capacitive part, that is, the effective lengths of the first interdigital metal 412 and the second interdigital metals 414 are L. At this time, the capacitance of the first metal layer 410 is C1; Figure 6 The first metal layer 410 shown in (b) includes 1 first interdigital metal 412, 2 second interdigital metals 414, and 6 third interdigital metals 415. The lengths of the first interdigital metal 412 and the second interdigital metals 414 that can form the capacitive part, that is, the effective lengths of the first interdigital metal 412 and the second interdigital metals 414 are 2L. At this time, the theoretical value of the capacitance of the first metal layer 410 is 2C1; Figure 6 The first metal layer 410 shown in (c) includes 2 first interdigital metals 412, 3 second interdigital metals 414, and 4 third interdigital metals 415. The lengths of the first interdigital metal 412 and the second interdigital metals 414 that can form the capacitive part, that is, the effective lengths of the first interdigital metal 412 and the second interdigital metals 414 are 2L. At this time, the theoretical value of the capacitance of the first metal layer 410 is 4C1. By analogy, different capacitance values can be obtained. Since the third interdigital metal 415 in the first metal layer 410 is a dummy metal and does not contribute to the capacitance value of the first metal layer 410, when the first metal layer 410 needs to be configured with a larger capacitance value, there may be no third interdigital metal in the first metal layer 410, such as Figure 6 The first metal layer 410 shown in (d) includes 4 first interdigital metals 412 and 5 second interdigital metals 414. The lengths of the first interdigital metal 412 and the second interdigital metals 414 that can form the capacitive part, that is, the effective lengths of the first interdigital metal 412 and the second interdigital metals 414 are 2L. At this time, the theoretical value of the capacitance of the first metal layer 410 is 8C1.

[0088] In the scenario where the first metal layer 410 does not include the third interdigital metal 415, the number of the first interdigital metals 412 in the first metal layer 410 is not equal to the number of the second interdigital metals 414, and the difference between the number of the first interdigital metals 412 and the number of the second interdigital metals 414 in the first metal layer 410 is 1, so that the capacitance value of the first metal layer 410 can change in proportion. For example, as Figure 6 shown in (d).

[0089] When the widths of both the first interdigital metal 412 and the second interdigital metal 414 are 0.08 micrometers (μm) and L is 3.16 μm, for Figure 6Performing simulation on the layout of the first metal layer 410 shown in (a)-(d) in the figure can obtain the results shown in Table 1. It can be seen from Table 1 that by adjusting parameters such as the number of the first interdigital metals 412, the number of the second interdigital metals 412, and the effective lengths of the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer 410, an equal-proportion change in the capacitance value of the interdigital capacitor can be achieved. In the capacitance network of the ADC based on the capacitance network, the capacitance values of the capacitors usually change according to the law of a geometric sequence with a common ratio of 2. Therefore, when the capacitors in the capacitance network of the ADC based on the capacitance network adopt the interdigital capacitor provided in this application, since the interdigital capacitor provided in the embodiments of this application can achieve a high-precision interdigital capacitor by adjusting the parameters of the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer, and the capacitance value of the interdigital capacitor can change in equal proportion, the conversion accuracy of the ADC of the capacitance network and the linearity of the output result can be effectively improved.

[0090] Table 1 Capacitance Value Simulation Results

[0091]

[0092] In addition, in specific implementation, in order to shield the influence of the external environment on the interdigital capacitor, the interdigital capacitor provided in the embodiments of this application further includes a second metal layer 420 disposed on at least one first metal layer 410, and the second metal layer 420 is used to shield the interference of the external environment on at least one first metal layer 410.

[0093] Specifically, as Figure 7a shown, the second metal layer 420 includes a third electrode 421 and a plurality of fourth interdigital metals 422 respectively connected to the third electrode 421. Among them, the third electrode 421 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the second metal layer 420 through a third conductive channel, or the third electrode 421 is electrically connected to the second electrode 413 in the second metal layer 410 adjacent to the second metal layer 420 through a third conductive channel. Among them, the third conductive channel can be a through hole filled with a metal (such as tungsten) in the dielectric layer between the second metal layer 420 and the first metal layer 410 adjacent to the second metal.

[0094] Further, the second metal layer 420 may further include a fifth electrode 423. When the third electrode 421 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the second metal layer 420 through a third conductive channel, the fifth electrode 423 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the second metal layer 420 through a fifth conductive channel; when the third electrode 421 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the second metal layer 420 through a third conductive channel, the fifth electrode 423 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the second metal layer 420 through a fifth conductive channel.

[0095] In addition, in order to ensure that the parasitic capacitances generated by the fourth interdigital metal 422 in the second metal layer 420 on the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer 420 are the same and avoid capacitance mismatch, the distance between the fourth interdigital metal 422 corresponding to the first interdigital metal 412 and the fourth interdigital metal 422 corresponding to the second interdigital metal 414 is the same as the distance between the first interdigital metal 412 and the second interdigital metal 414, and the dimensional parameters (length, width, etc.) of the fourth interdigital metal 422 corresponding to the first interdigital metal 412 in the second metal layer 420 are the same as the parameters (length, width, etc.) of the fourth interdigital metal 422 corresponding to the second interdigital metal 414 in the second metal layer 420.

[0096] To shield the influence of the external environment on the interdigital capacitor, the interdigital capacitor provided in the embodiment of the present application may further include a third metal layer 430 disposed under at least one first metal layer 410, and the third metal layer 430 is used to shield the interference of the external environment on at least one first metal layer 410.

[0097] Specifically, as Figure 7b shown, the third metal layer 430 includes a fourth electrode 431 and a plurality of fifth interdigital metals 432 respectively connected to the fourth electrode 431. The fourth electrode 431 is electrically coupled to the first electrode 411 in the first metal layer 410 adjacent to the third metal layer 430 through a fourth conductive channel, or the fourth electrode 431 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the third metal layer 430 through a fourth conductive channel. The fourth conductive channel may be a through hole filled with a metal (such as tungsten) in the dielectric layer between the third metal layer 430 and the first metal layer 410 adjacent to the second metal.

[0098] The third metal layer 430 may further include a sixth electrode 433. When the fourth electrode 431 is electrically coupled to the first electrode 411 in the first metal layer 410 adjacent to the third metal layer 430 through a fourth conductive channel, the sixth electrode 433 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the third metal layer 430 through a sixth conductive channel; when the fourth electrode 431 is electrically coupled to the second electrode 413 in the first metal layer 410 adjacent to the third metal layer 430 through a fourth conductive channel, the sixth electrode 433 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the third metal layer 430 through a sixth conductive channel.

[0099] In addition, to ensure that the parasitic capacitances generated by the fifth interdigital metal 432 in the third metal layer 430 on the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer 420 are the same and avoid capacitance mismatch, the distance between the fifth interdigital metal 432 corresponding to the first interdigital metal 412 and the fifth interdigital metal 432 corresponding to the second interdigital metal 414 is the same as the distance between the first interdigital metal 412 and the second interdigital metal 414. The parameters (length, width, etc.) of the fifth interdigital metal 432 corresponding to the first interdigital metal 412 in the third metal layer 430 are the same as the parameters (length, width, etc.) of the fifth interdigital metal 432 corresponding to the second interdigital metal 414 in the third metal layer 430.

[0100] That is to say, the interdigital capacitor provided by the embodiment of the present application may include any one of the second metal layer 420 and the third metal layer 430, such as Figure 7a or Figure 7b as shown, or may include both the second metal layer 420 and the third metal layer 430 at the same time, such as Figure 7c as shown.

[0101] Furthermore, to meet the requirements of the processing technology for the metal density in the interdigital capacitor, as Figure 8 shown, the interdigital capacitor provided by the embodiment of the present application further includes at least one fourth metal layer 440 for density filling, that is, for increasing the metal density of the layer where the fourth metal layer 440 is located in the interdigital capacitor. Among them, at least one fourth metal layer 440 is disposed on the top of the interdigital capacitor, that is, all the fourth metal layers 440 are disposed on the top of the interdigital capacitor; or, at least one fourth metal layer 440 is disposed at the bottom of the interdigital capacitor, that is, all the fourth metal layers 440 are disposed at the bottom of the interdigital capacitor; or, a part of at least one fourth metal layer 440 is disposed on the top of the interdigital capacitor, and another part of at least one fourth metal layer 440 is disposed at the bottom of the interdigital capacitor.

[0102] In a scenario where the second metal layer 420 and the third metal layer 430 are not included in the interdigital capacitor, the top of the interdigital capacitor is above at least one first metal layer 410 (i.e., above the topmost first metal layer 410 in at least one first metal layer 410), and the bottom of the interdigital capacitor is below at least one first metal layer 410 (i.e., below the bottommost first metal layer 410 in at least one first metal layer 410). In a scenario where the second metal layer 420 is included in the interdigital capacitor but the third metal layer 430 is not included, the top of the interdigital capacitor is above the second metal layer 420, and the bottom of the interdigital capacitor is below at least one first metal layer 410 (i.e., below the bottommost first metal layer 410 in at least one first metal layer 410). In a scenario where the third metal layer 430 is included in the interdigital capacitor but the second metal layer 420 is not included, the top of the interdigital capacitor is above at least one first metal layer 410 (i.e., above the topmost first metal layer 410 in at least one first metal layer 410), and the bottom of the interdigital capacitor is below the third metal layer 430. In a scenario where the second metal layer 420 and the third metal layer 430 are included in the interdigital capacitor, the top of the interdigital capacitor is above the second metal layer 420, and the bottom of the interdigital capacitor is below the third metal layer 430.

[0103] In a specific implementation, each fourth metal layer 440 may include one or more strip-shaped metals. To minimize the influence of the strip-shaped metals on the interdigital capacitor, the length direction of the strip-shaped metals is perpendicular to the length direction of the first interdigital metal 412. Usually, the first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 in the first metal layer 410 are arranged in parallel. Therefore, the length direction of the strip-shaped metals being perpendicular to the length direction of the first interdigital metal 412 also means that the length direction of the strip-shaped metals is perpendicular to the lengths of both the second interdigital metal 414 and the third interdigital metal 415.

[0104] Furthermore, as Figure 9 shown, the interdigital capacitor provided by the embodiment of the present application further includes a substrate 450. An intrinsic layer (such as an NT_N layer) 451 is provided in the substrate 450, and at least one first metal layer 410 is disposed on the upper surface of the intrinsic layer 451 to avoid interference caused by noise in the substrate 450 to the interdigital capacitor. Among them, the substrate 450 is usually a semiconductor material, such as single crystal, crystalline silicon, or amorphous silicon or silicon germanium (SiGe), or it can also be a mixed semiconductor material, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, alloy semiconductor, or a combination thereof, etc.; the intrinsic layer 451 refers to an undoped region.

[0105] Through the above solution, the interdigital capacitor provided by the embodiment of the present application includes a first interdigital metal 412 and a second interdigital metal 413 that can form a capacitor, as well as a dummy interdigital metal (i.e., a third interdigital metal). By adjusting the parameters of the first interdigital metal 412 and the second interdigital metal 414, such as the length of the first interdigital metal 412 and the length of the second interdigital metal, the number of the first interdigital metals 412 and the number of the second interdigital metals 414, etc., fine adjustment of the capacitance value of the interdigital capacitor can be achieved. Compared with the prior art, an interdigital capacitor with higher precision and a flexibly variable capacitance value can be provided.

[0106] Based on the above embodiments, the present application further provides a multiplying digital-to-analog conversion circuit, which can be applied to a pipelined analog-to-digital converter. As Figure 10 shown, the multiplying digital-to-analog conversion circuit includes: a switched-capacitor array 1010, a feedback capacitor Cf, and an operational amplifier 1020. Among them, the switched-capacitor array 1010 includes k switches (S1, S2,..., Sk), and k interdigital capacitors (C1, C2,..., Ck) provided by any one of the above embodiments corresponding to the k switches one by one, where k is a positive integer; for any one of the k switches, the first end of the switch is used to selectively output a voltage to be processed or a reference voltage to the first end of the interdigital capacitor corresponding to the switch, the second end of the interdigital capacitor corresponding to the switch is respectively coupled to the first input end of the operational amplifier 1020 and the first end of the feedback capacitor Cf, the second end of the operational amplifier 1020 is grounded, and the second end of the feedback capacitor Cf is coupled to the output end of the operational amplifier 1030.

[0107] Among them, the switches in the switched-capacitor array 1010 can be controllable switches such as metal oxide semiconductor (MOS) field effect transistors or triodes.

[0108] In a specific implementation, for any one of the k switches, the switch includes a first signal input end, a second signal input end, and a signal output end. The first signal input end is used to input a voltage to be processed, the second signal input end is used to input a reference voltage, and the signal output end is used to selectively output the voltage to be processed or the reference voltage to the first end of the interdigital capacitor corresponding to the switch.

[0109] The switch selectively outputs the voltage to be processed or the reference voltage to the first end of the interdigital capacitor corresponding to the switch, usually realized by the control of the sample-and-hold signal. At this time, the switch may further include a control terminal for inputting the sample-and-hold signal. Specifically, in the sampling stage, under the control of the sample-and-hold signal, the switch turns on the path between the first signal input terminal and the signal output terminal, turns off the path between the second signal input terminal and the signal output terminal, and outputs the voltage to be processed to the first end of the interdigital capacitor corresponding to the switch. In the holding stage, the path between the first signal input terminal and the signal output terminal is turned off, and the path between the second signal input terminal and the signal output terminal is turned on, and the reference voltage is output to the first end of the interdigital capacitor corresponding to the switch. Wherein, the switch is two single-pole single-throw switches or a single-pole multi-throw switch (such as a single-pole double-throw switch), etc.

[0110] Further, the capacitances of the k interdigital capacitors are C, 2C, 2 2 C,..., 2 k-1 C, where C is a constant. Among them, the capacitances of the k interdigital capacitors being C, 2C, 2 2 C,..., 2 k-1 C can be realized by adjusting one or more of the parameters such as the length of the first finger metal 412, the length of the second finger metal, the number of the first finger metals 412, the number of the second finger metals 414, and the distance between the first finger metal 412 and the second finger metal 414 in the interdigital capacitor.

[0111] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.

Claims

1. An interdigital capacitor, characterized in that, Comprising: At least one first metal layer; Wherein, each first metal layer is provided with: A first electrode; At least one first interdigital metal electrically connected to the first electrode; A second electrode; A plurality of second interdigital metals and at least one third interdigital metal electrically connected to the second electrode; Wherein, the at least one first interdigital metal and the plurality of second interdigital metals are alternately arranged to form a capacitor, and the at least one third interdigital metal is a dummy interdigital metal; When the first metal layer includes a plurality of first interdigital metals, the lengths of the plurality of first interdigital metals are different.

2. The interdigital capacitor according to claim 1, characterized in that, The at least one third interdigital metal is all located on the same side of the plurality of second interdigital metals; Or, when the first metal layer includes a plurality of third interdigital metals, the plurality of third interdigital metals are located on both sides of the plurality of second interdigital metals.

3. The interdigital capacitor according to claim 1 or 2, characterized in that, The lengths of the plurality of second interdigital metals are different.

4. The interdigital capacitor according to claim 1, characterized in that, The number of the first interdigital metals, the number of the second interdigital metals, the effective length of the first interdigital metals, and the distance between adjacent first interdigital metals and second interdigital metals are set according to the capacitance value of the capacitor of the first metal layer; Wherein, the effective length of the first interdigital metal is the length of the part of the first interdigital metal that can form a sidewall capacitance with an adjacent second interdigital metal; the capacitance value of the capacitor of the first metal layer is positively correlated with the number of the first interdigital metals, the number of the second interdigital metals, and the effective length of the first interdigital metals; the capacitance value of the capacitor of the first metal layer is negatively correlated with the distance between adjacent first interdigital metals and second interdigital metals.

5. The interdigital capacitor according to claim 1, characterized in that, The first electrodes in two adjacent first metal layers are connected through a first conductive channel, and the second electrodes in two adjacent first metal layers are connected through a second conductive channel.

6. The interdigital capacitor according to claim 1, characterized in that, Further comprising: A second metal layer disposed above the at least one first metal layer; the second metal layer is used to shield the interference of the external environment on the at least one first metal layer.

7. The interdigital capacitor according to claim 6, characterized in that, The second metal layer includes a third electrode and a plurality of fourth interdigital metals respectively connected to the third electrode; Wherein, the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, or the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through a third conductive channel.

8. The interdigital capacitor according to claim 1, characterized in that, Further comprising: A third metal layer disposed below the at least one first metal layer; the third metal layer is used to shield the interference of the external environment on the at least one first metal layer.

9. The interdigital capacitor according to claim 8, characterized in that, The third metal layer includes a fourth electrode and a plurality of fifth interdigital metals respectively connected to the fourth electrode; Wherein, the fourth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel, or the fourth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel.

10. The interdigital capacitor according to claim 1, characterized in that, Further comprising: At least one fourth metal layer, and the fourth metal layer is used for metal density filling; Wherein, the at least one fourth metal layer is disposed on the top of the interdigital capacitor; Alternatively, the at least one fourth metal layer is disposed at the bottom of the interdigital capacitor; or, a part of the at least one fourth metal layer is disposed on top of the multi-layer first metal layer, and another part of the at least one fourth metal layer is disposed at the bottom of the multi-layer first metal layer.

11. The interdigital capacitor according to claim 10, characterized in that, Each fourth metal layer includes one or more strip-shaped metals.

12. The interdigital capacitor according to claim 11, characterized in that, The length direction of the strip-shaped metal is perpendicular to the length direction of the first interdigital metal.

13. The interdigital capacitor according to claim 1, characterized in that, Further included is: a substrate, an intrinsic layer is disposed in the substrate, and the at least one first metal layer is disposed on the upper surface of the intrinsic layer.

14. The interdigital capacitor according to claim 1, characterized in that, The distance between two adjacent interdigital metals in the first metal layer is greater than or equal to a first threshold, the width of each interdigital metal in the first metal layer is greater than or equal to a second threshold, and the first threshold and the second threshold satisfy the minimum width and spacing design rule check for horizontal and vertical placement.

15. The interdigital capacitor according to claim 1, characterized in that, The interdigital capacitor is a metal-oxide-metal (MOM) capacitor, and the MOM capacitor includes a plurality of the first metal layers stacked in parallel.

16. A multiplication digital-to-analog conversion circuit, characterized in that, Included are: a switched capacitor array, a feedback capacitor, and an operational amplifier; wherein, the switched capacitor array includes k switches, and k interdigital capacitors as described in any one of claims 1-15 corresponding to the k switches one by one, k is a positive integer; for any one of the k switches, the switch is configured to selectively output a voltage to be processed or a reference voltage to the first end of the interdigital capacitor corresponding to the switch, and the second end of the interdigital capacitor corresponding to the switch is respectively coupled to the first input end of the operational amplifier and the first end of the feedback capacitor; The second end of the operational amplifier is grounded, and the second end of the feedback capacitor is coupled to the output end of the operational amplifier.

17. The circuit according to claim 16, characterized in that, The capacitances of the k interdigital capacitors are C, 2C, 2 2 C, …, 2 k-1 C, where C is a constant.

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