Transition metal dichalcogenides and uses thereof

Abstract

A material (1) comprising: a transition metal dichalcogenide (107), the transition metal dichalcogenide (107) comprising a surface (109), at least a portion of which is surface-modified with one or more Group 1 metals (103), wherein the one or more Group 1 metals comprise cesium and / or rubidium.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims the benefit of Singapore Patent Application No. 10201906808T, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to transition metal dichalcogenides, and in particular to the use of transition metal dichalcogenides in electronic devices. Background Art

[0004] Two-dimensional (2D) transition metal dichalcogenides (TMDs) have been established as promising building blocks for next-generation nanoelectronic devices, showing great potential to extend the scaling limits of silicon-based complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs).

[0005] As one of the most studied TMD materials, tungsten diselenide (WSe2) has three main polymorphs, including semiconducting triangular prisms (2H phase), metallic octahedrons (1T phase) and distorted octahedrons (1T' phase). 2H semiconductor WSe2 exhibits great advantages in complementary logic devices due to its bipolar transport properties with high current on / off ratio. However, similar to other TMDs, transistors based on 2H WSe2 usually have high Schottky barrier height and high contact resistance at the metal contact / WSe2 interface, which degrades the performance of WSe2 FETs, including conductivity and carrier mobility.

[0006] To reduce the contact resistance of WSe2-based FETs, various approaches are currently being explored, such as metal contact engineering, ionic liquid gates, photodoping, and surface charge transfer doping.

[0007] Several methods have also been employed to induce the 2H to 1T / 1T' phase transition in TMDs, such as alkali metal intercalation, strain engineering, ionic liquid gates, and laser irradiation. However, alkali metal intercalation requires immersing the TMDs in chemical liquids, such as n-butyllithium (n-BuLi) or tert-butyllithium (t-BuLi), which is complex and time-consuming. Strain engineering and ionic liquid gates require harsh conditions to succeed. High-energy laser irradiation can cause undesirable and irreversible damage to the sample.

[0008] There is a constant need to improve the performance of electronic devices based on TMD materials. Summary of the Invention

[0009] In a first aspect, a material is provided, comprising: a transition metal dichalcogenide (TMD), the transition metal dichalcogenide comprising a surface, at least a portion of which is surface modified with one or more Group 1 metals, wherein the one or more Group 1 metals include Cs and / or Rb.

[0010] Transition metal dichalcogenides (TMDs) have the general formula MX2, where M is a transition metal atom and X is a chalcogen atom.

[0011] The transition metal dichalcogenide may include one or more of: MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali-doped MoTe2, alkali-doped MoSe2, alkali-doped MoS2, alkali-doped WSe2, and alkali-doped WS2. The transition metal dichalcogenide may include one or more of WSe2 and / or MoTe2. The transition metal dichalcogenide may include WSe2.

[0012] The TMD may contain one or more impurities.

[0013] The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of 1 to 5 layers. A portion or all of the transition metal dichalcogenide may comprise a monolayer or a bilayer.

[0014] "Surface-modified" or "surface modification" refers to the alteration of a material's surface by the introduction of physical, chemical, or biological properties that differ from those originally found on the material's surface. For example, a surface is modified if it is functionalized by adding new functions, features, capabilities, or properties to the material. The modification changes the surface chemistry of the material. In this regard, the modification or functionalization is only on the surface and does not permeate the material. In contrast, "doping" refers to the intentional introduction of impurities into an intrinsic semiconductor to modulate its electrical, optical, and structural properties. In this regard, the impurities are present within the semiconductor.

[0015] A portion of the TMD surface may be surface modified, while a portion may not be surface modified. The entire surface may be surface modified. Multiple portions of the surface may be surface modified. The surface may be modified with a mixture of two or more alkali metals. The surface may be modified with only cesium and / or rubidium. A portion of the TMD may be surface modified with cesium and / or rubidium, while another portion may be surface modified with another alkali metal. The one or more alkali metals may contain one or more impurities.

[0016] The one or more alkali metals may include cesium and one or more elements selected from lithium, sodium, potassium, and rubidium.

[0017] The one or more alkali metals may include rubidium and one or more elements selected from lithium, sodium, potassium, and cesium.

[0018] The alkali metal can be in direct contact with the surface of the TMD. A direct interface can exist between the alkali metal and the TMD.

[0019] One or more Group 1 metals can form a layer on the surface of the TMD. The layer of the Group 1 metal can have a thickness greater than or equal to 0.2 nm. The layer can have a thickness less than or equal to 5.0 nm. The layer of the Group 1 metal can have a thickness of 0.4 nm to 2.0 nm.

[0020] For the avoidance of doubt, it is expressly intended that where multiple numerical ranges relating to the same feature are recited herein, the endpoints of each range are intended to be combined in any order to provide other intended (and implicitly disclosed) ranges. Thus, with respect to the above-mentioned related numerical ranges, disclosed are:

[0021] 0.0nm to 0.01nm, 0.0nm to 0.05nm, 0.0nm to 0.07nm, 0.0nm to 0.08nm, 0.0nm to 0.1nm, 0.0nm to 0.19nm, 0.0nm to 0.20nm, 0.0nm to 0.4nm 0.0nm to 0.5nm, 0.0nm to 0.6nm 0.0nm to 1.0nm, 0.0nm to 2.0nm, 0.0nm to 5.0nm;

[0022] 0.01nm to 0.05nm, 0.01nm to 0.07nm, 0.01nm to 0.08nm, 0.01nm to 0.1nm, 0.01nm to 0.19nm, 0.01nm to 0.20nm, 0.01nm to 0.4nm 0.01nm to 0.5nm, 0.01nm to 0.6nm 0.01nm to 1.0nm, 0.01nm to 2.0nm, 0.01nm to 5.0nm;

[0023] 0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to 0.1nm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm 0.05nm to 0.5nm, 0.05nm to 0.6nm 0.05nm to 1.0nm, 0.05nm to 2.0nm, 0.05nm to 5.0nm;

[0024] 0.07nm to 0.08nm, 0.07nm to 0.1nm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm 0.07nm to 0.5nm, 0.07nm to 0.6nm 0.07nm to 1.0nm, 0.07nm to 2.0nm, 0.07nm to 5.0nm;

[0025] 0.08nm to 0.1nm, 0.08nm to 0.19nm, 0.08nm to 0.20nm, 0.08nm to 0.4nm 0.08nm to 0.5nm, 0.08nm to 0.6nm 0.08nm to 1.0nm, 0.08nm to 2.0nm, 0.08nm to 5.0nm;

[0026] 0.10nm to 0.19nm, 0.10nm to 0.20nm, 0.10nm to 0.4nm, 0.10nm to 0.5nm, 0.10nm to 0.6nm 0.10nm to 1.0nm, 0.10nm to 2.0nm, 0.10nm to 5.0nm;

[0027] 0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm 0.19nm to 1.0nm, 0.19nm to 2.0nm, 0.19nm to 5.0nm;

[0028] 0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm 0.2nm to 1.0nm, 0.2nm to 2.0nm, 0.2nm to 5.0nm;

[0029] 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to 1.0nm, 0.4nm to 2.0nm, 0.4nm to 5.0nm;

[0030] 0.5nm to 0.6nm, 0.5nm to 1.0nm, 0.5nm to 2.0nm, 0.5nm to 5.0nm;

[0031] 0.6nm to 1.0nm, 0.6nm to 2.0nm, 0.6nm to 5.0nm;

[0032] 1.0 nm to 2.0 nm, 1.0 nm to 5.0 nm; and

[0033] 2.0nm to 5.0nm.

[0034] One or more surface-modified portions of the TMD may be in a different phase than one or more unsurface-modified portions of the TMD. One or more surface-modified portions may be in a 1T or 1T' phase, while one or more unsurface-modified portions may be in a 2H phase.

[0035] As known in the art, "2H" refers to a hexagonal phase structure and "1T" refers to a metallic monoclinic or octahedral phase structure.

[0036] In one aspect, an electronic device is provided, comprising: a transition metal dichalcogenide (TMD), the TMD comprising first and second portions surface-modified with one or more Group 1 metals and a third portion not surface-modified with the one or more Group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprise cesium and / or rubidium.

[0037] The transition metal dichalcogenide may include one or more of: MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali-doped MoTe2, alkali-doped MoSe2, alkali-doped MoS2, alkali-doped WSe2, and alkali-doped WS2. The transition metal dichalcogenide may include one or more of WSe2 and / or MoTe2. The transition metal dichalcogenide may include WSe2.

[0038] The one or more alkali metals may include cesium, and the transition metal dichalcogenide may include WSe2.

[0039] The TMD may contain one or more impurities.

[0040] The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of 1 to 5 layers. A portion or all of the transition metal dichalcogenide may comprise a monolayer or a bilayer.

[0041] The surface can be modified with a mixture of two or more alkali metals. The surface can be modified with only cesium and / or rubidium. A portion of the TMD can be surface modified with cesium and / or rubidium, while another portion can be surface modified with another alkali metal. The one or more alkali metals can contain one or more impurities.

[0042] One or more Group 1 metals can form a layer on the surface of the TMD. The layer of the Group 1 metal can have a thickness greater than or equal to 0.2 nm. The layer can have a thickness less than or equal to 5.0 nm. The layer of the Group 1 metal can have a thickness of 0.4 nm to 2.0 nm.

[0043] The thickness of the plurality of or more alkali metals may fall within one of the following ranges: 0.0 nm to 0.01 nm, 0.0 nm to 0.05 nm, 0.0 nm to 0.07 nm, 0.0 nm to 0.08 nm, 0.0 nm to 0.1 nm, 0.0 nm to 0.19 nm, 0.0 nm to 0.20 nm, 0.0 nm to 0.4 nm, 0.0 nm to 0.5 nm, 0.0 nm to 0.6 nm, 0.0 nm to 1.0 nm, 0.0 nm to 2.0 nm, 0.0 nm to 5.0 nm; 0.01 nm to 0.05 nm, 0.01 nm to 0.07 nm, 0.01 nm to 0.08 nm, 0.01 nm to 0.1 nm, 0.01 nm to 0.19 nm, 0.01 nm to 0.20 nm, 0.01 nm to 0.4 nm 0.01nm to 0.5nm, 0.01nm to 0.6nm 0.01nm to 1.0nm, 0.01nm to 2.0nm, 0.01nm to 5.0nm; 0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to 0.1nm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm 0.05nm to 0.5nm, 0.05nm to 0.6nm0.05nm to 1.0nm, 0.05nm to 2.0nm, 0.05nm to 5.0nm;

[0044] 0.07nm to 0.08nm, 0.07nm to 0.1nm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm 0.07nm to 0.5nm, 0.07nm to 0.6nm 0.07nm to 1.0nm, 0.07nm to 2.0nm, 0.07nm to 5.0nm; 0.08nm to 0.1nm, 0.08nm to 0.19nm, 0.08nm to 0.20nm, 0.08nm to 0.4nm 0.08nm to 0.5nm, 0.08nm to 0.6nm 0.08nm to 1.0nm, 0.08nm to 2.0nm, 0.08nm to 5.0nm; 0.10nm to 0.19nm, 0.10nm to 0.20nm, 0.10nm to 0.4nm, 0.10nm to 0.5nm, 0.10nm to 0.6nm 0.10nm to 1.0nm, 0.10nm to 2.0nm, 0.10nm to 5.0nm;

[0045] 0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm 0.19nm to 1.0nm, 0.19nm to 2.0nm, 0.19nm to 5.0nm; 0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm0.2nm to 1.0nm, 0.2nm to 2.0nm, 0.2nm to 5.0nm; 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to 1.0nm, 0.4nm to 2.0nm, 0.4nm to 5.0nm; 0.5nm to 0.6nm, 0.5nm to 1.0nm, 0.5nm to 2.0nm, 0.5nm to 5.0nm; 0.6nm to 1.0nm, 0.6nm to 2.0nm, 0.6nm to 5.0nm; 1.0nm to 2.0nm, 1.0nm to 5.0nm; and 2.0nm to 5.0nm.

[0046] One or more surface-modified portions of the TMD may be in a different phase than one or more unsurface-modified portions of the TMD. One or more surface-modified portions may be in a 1T or 1T' phase, while one or more unsurface-modified portions may be in a 2H phase.

[0047] The device may exhibit substantially ohmic contact characteristics with respect to the first and second electrodes. In this context, ohmic contact characteristics means that the current between the two electrodes of the device has a substantially linear dependence on the voltage.

[0048] The device may have a Schottky barrier height of less than or equal to 10 meV. The device may have a Schottky barrier height of less than or equal to 9.4 meV. The device may have a Schottky barrier height of 9 meV to 10 meV or 9.4 meV to 10 meV.

[0049] The field-effect electron mobility of the device can reach 35 cm at room temperature (298K). 2 V 1 s -1 or larger, especially 37.7cm 2 V 1 s -1 or larger, more particularly 70cm 2 V 1 s -1 The device may have a field effect electron mobility at room temperature (298K) falling within one of the following ranges: 35 cm 2 V 1 s -1 Up to 37.7cm 2 V 1 s-1 , 35cm 2 V 1 s -1 Up to 70cm 2 V -1 s -1 , 35cm 2 V 1 s -1 Up to 75cm 2 V -1 s -1 ; 37.5cm 2 V 1 s -1 Up to 70cm 2 V -1 s -1 、37.5cm 2 V 1 s -1 Up to 75cm 2 V -1 s -1 ; 70cm 2 V 1 s -1 Up to 75cm 2 V -1 s -1 .

[0050] The device can have a 10 6 or greater, especially 10 7 or greater, further especially 10 8 or greater current on / off ratio. The device can have a current on / off ratio of approximately 10 9 The current on / off ratio of the device at room temperature can fall into one of the following ranges: 10 6 to 10 7 , 10 6 to 10 8 , 10 6 to 10 9 ; 10 7 to 10 8 , 10 7 to 10 9 ; and 10 8 to 10 9 .

[0051] The device can have 85mV dec at room temperature (298K). -1 or less, especially 75mV dec -1 or less, further especially at 60mV dec -1 to 75mV dec -1The device can have a subthreshold swing of 61mV dec -1 The device can have a subthreshold swing that falls within one of the following ranges: 60mV dec -1 to 61mV dec -1 、60mV dec -1 to 75mV dec -1 、60mV dec -1 to 85mV dec -1 ;61mV dec -1 to 75mV dec -1 、61mV dec -1 to 85mV dec -1 ; and 75mV dec -1 to 85mV dec -1 .

[0052] The electronic device may be a field effect transistor.

[0053] The electronic device may be a logic inverter. The gain of the inverter may be greater than 100. The gain of the inverter may be greater than 5 while consuming less than 10 pW.

[0054] The material and / or device may be maintained under substantially vacuum conditions. The device may be operated under substantially vacuum conditions. The device may further comprise a vacuum chamber configured to house the surface-modified TMD under substantially vacuum conditions. Substantially vacuum conditions refer to 10 -7 mbar or lower pressure.

[0055] The material and / or device may be maintained under a nitrogen atmosphere. The material and / or device may be packaged in a nitrogen atmosphere. The nitrogen atmosphere may be a substantially 100% nitrogen environment.

[0056] The material and / or device may include packaging configured or arranged to prevent oxygen and water from contacting the surface-modified TMD. The packaging may be configured to maintain the surface-modified TMD under vacuum. The packaging may be configured to maintain the surface-modified TMD in a nitrogen (N2) or other inert atmosphere.

[0057] In one aspect, a method of producing a material is provided, the material comprising: a transition metal dichalcogenide (TMD), the transition metal dichalcogenide comprising a surface, at least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and / or Rb, the method comprising: providing the transition metal dichalcogenide; and evaporating the one or more Group 1 metals onto at least a portion of the surface of the transition metal dichalcogenide, wherein the one or more Group 1 metals comprise Cs and / or Rb.

[0058] In one aspect, a method for producing an electronic device is provided, the electronic device comprising: a transition metal dichalcogenide (TMD), the TMD comprising a first and second portion surface-modified with one or more Group 1 metals and a third portion that is not surface-modified with the one or more Group 1 metals; and a first and second electrode, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprise cesium and / or rubidium, the method comprising: providing a transition metal dichalcogenide layer and first and second electrodes on a surface of a substrate such that the first and second electrodes are in electrical contact with the transition metal dichalcogenide layer; evaporating the one or more Group 1 metals onto the surfaces of the first and second portions of the transition metal dichalcogenide layer such that the thickness of the one or more Group 1 metals is at least 0.2 nm, wherein the first and second portions of the transition metal dichalcogenide layer are adjacent to the first and second electrodes, respectively, and wherein the one or more Group 1 metals comprise Cs and / or Rb. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The following describes the embodiments with reference to the accompanying drawings, in which:

[0060] Figure 1 shows a material according to one embodiment;

[0061] Figure 2 shows a material according to one embodiment;

[0062] Figure 3a and Figure 3b The 2H phase and 1T' phase of WSe2 are shown respectively;

[0063] Figure 4 A device according to one embodiment is shown;

[0064] Figure 5 A device according to one embodiment is shown;

[0065] Figure 6 A device according to one embodiment is shown;

[0066] Figure 7 A method of producing a material according to one embodiment is shown;

[0067] Figure 8a shows the line profiles derived from atomic force microscope (AFM) images of a bilayer WSe2 device;

[0068] Figure 8b Raman measurements of a bilayer WSe2 device are shown;

[0069] Figure 8c Shows the photoluminescence (PL) measurement of a bilayer WSe2 device;

[0070] Figure 9a Schematic diagram of a double-layer WSe2 device with surface modification is shown;

[0071] Figure 9b and Figure 9c The transfer characteristics of the original bilayer WSe2 FET (I sd -V g );

[0072] Figure 9d The evolution of the transfer characteristics of the WSe2 FET with varying Cs thickness is shown.

[0073] Figure 9e The relationship between the conductivity (G) of WSe2 FET and Cs thickness at Vg = 0V is shown;

[0074] Figure 9f The output curves of the original and 1.0 nm Cs-modified WSe2 FETs are shown (I sd -V sd );

[0075] Figure 9g and Figure 9h shows the temperature-dependent transport measurements of Cs-modified WSe2 FETs;

[0076] Figure 9i Shown is the conductivity evolution of a bilayer WSe2 device functionalized with 1.0 nm Cs versus temperature at different Vg.

[0077] Figure 10 (a) to Figure 10 (d) shows the in situ XPS and UPS results of the double-layer WSe2 device;

[0078] Figure 11a Shown are the photoluminescence (PL) spectra of the bilayer WSe2 flakes before and after 0.1 nm Cs modification;

[0079] Figure 11bRaman measurements of bilayer WSe2 flakes before and after 0.1 nm Cs modification are shown;

[0080] Figure 12a shows the evolution of the transmission characteristics of a device according to one embodiment as a function of the Cs thickness;

[0081] Figure 12b shows the evolution of the field-effect electron mobility of the device;

[0082] Figure 12c and Figure 12d The output curves of the device before and after Cs modification under a certain range of gate voltages are shown respectively;

[0083] Figure 13a shows the Schottky barrier height of a multi-phase transistor according to one embodiment;

[0084] Figure 13b shows that the V g =5V, the width-normalized total resistance (R tot );

[0085] Figure 14a FIG4 shows the evolution of device transmission characteristics of a sandwich structure device according to one embodiment as the Cs thickness changes;

[0086] Figure 14b The relationship between the corresponding electron mobility and Cs thickness is shown;

[0087] Figure 14c and Figure 14d The output curves of the device before and after 1.0nm Cs contact doping at different gate voltages ranging from 1V to 5V are shown respectively;

[0088] Figure 14e FIG4 shows the evolution of device transmission characteristics of another sandwich structure device according to one embodiment as the Cs thickness changes;

[0089] Figure 15a shows the transfer characteristics of a logic inverter according to one embodiment;

[0090] Figure 15b shows the output characteristics of the inverter;

[0091] Figure 15c shows the inverter at three different V DD Down with V IN Varying extraction gain;

[0092] Figure 15d shows the evolution of the inverter power dissipation versus V DD relationship;

[0093] Figure 16 (a) shows the output characteristics of a non-inverting WSe2 inverter according to one embodiment; and

[0094] Figure 16 (b) shows the inverter's V IN Changing output curve and corresponding voltage gain. DETAILED DESCRIPTION

[0095] For the purposes of brevity and clarity, the description of the embodiments of the present disclosure relates to transition metal dichalcogenides and their uses, with reference to the accompanying drawings. Although the various aspects of the present disclosure will be described in conjunction with the embodiments provided herein, it should be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications and equivalents to the embodiments described herein, which are all included within the scope of the present disclosure as defined by the appended claims. In addition, in the following detailed description, specific details are set forth to provide a thorough understanding of the present disclosure. However, a person of ordinary skill in the art, i.e., a skilled person, will recognize that the present disclosure can be practiced without the specific details of a combination of specific embodiments from various aspects and / or with multiple details of a combination of specific embodiments from various aspects. In many cases, well-known systems, methods, processes and components are not described in detail so as not to unnecessarily obfuscate the embodiments of the various aspects of the present disclosure.

[0096] In embodiments of the present disclosure, the description of a given element or consideration or use of a particular element number in a particular figure or its mention in the corresponding descriptive material may encompass the same, equivalent or similar elements or element numbers specified in another figure or descriptive material related thereto.

[0097] References to "one embodiment / example," "another embodiment / example," "some embodiments / examples," "some other embodiments / examples," etc. indicate that the embodiment / embodiment so described may include a particular feature, structure, characteristic, property, element, or limitation, but not every embodiment / embodiment must include that particular feature, structure, characteristic, property, element, or limitation. Furthermore, repeated use of the phrase "in one embodiment / example" or "in another embodiment / example" does not necessarily refer to the same embodiment / embodiment.

[0098] The terms "comprising," "including," "having," etc. do not exclude the presence of features / elements / steps other than those listed in the embodiments, nor do they require the presence of other features. The fact that certain features / elements / steps are described in different embodiments does not mean that the combination of these features / elements / steps cannot be used in the embodiments.

[0099] As used herein, the terms "a" and "an" are defined as one or more than one. Unless otherwise indicated, the use of " / " in a figure or related text should be understood to mean "and / or". The description of a specific value or value range herein should be understood to include or describe an approximate value or value range.

[0100] Figure 1 A schematic diagram of a material 1 according to one embodiment is shown. Figure 1 In an embodiment, the material comprises a layer 101 of a transmissive metal dichalcogenide (TMD).

[0101] On the surface 109 of the TMD 101, a layer 103 of one or more alkali metals is provided, that is, the surface of the TMD is surface-modified with one or more alkali metals. Figure 1 In an embodiment, an alkali metal is provided on the surface of the two portions 105 of the TMD 101. Figure 1 In some embodiments, portions 107 of the TMD located between regions 105 are not surface modified by the alkali metal 103. In other embodiments, all portions of the TMD may be surface modified, or only one portion or more portions of the TMD may be surface modified.

[0102] The thickness of the TMD is not particularly limited. In embodiments, the TMD may be configured as a single layer, a double layer, or a multilayer, for example, having a thickness of 3 to 5 layers. However, a single layer, a double layer, or other substantially two-dimensional TMD may be advantageous for use in electronic devices, thereby enabling the provision of low-profile devices.

[0103] The thickness of the TMD layer can be roughly determined by using a high-resolution optical microscope (eg, Nikon Eclipse LV100D) and further confirmed by atomic force microscopy (AFM).

[0104] In one embodiment, the alkali metal layer comprises cesium and / or rubidium.

[0105] In one embodiment, the alkali metal layer comprises a mixture of more than one alkali metal.

[0106] The alkali metal layer may contain cesium and one or more elements selected from lithium, sodium, potassium, and rubidium.

[0107] The alkali metal layer may contain rubidium and one or more elements selected from lithium, sodium, potassium, and cesium.

[0108] In one embodiment, the thickness of the alkali metal layer is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the alkali metal layer can be in the range of 0.4 nm to 2 nm. In one embodiment, the thickness of the cesium and / or rubidium layer is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the cesium and / or rubidium layer can be in the range of 0.4 nm to 2 nm. Thicknesses within this range can impart favorable electrical properties to the surface modified portion 105 of the TMD. These properties will be discussed further below.

[0109] The thickness of the alkali metal layer can be determined gravimetrically, for example using a quartz crystal microbalance.

[0110] X-ray photoelectron spectroscopy (XPS) can also be used to determine the thickness of alkali metals. One such method for determining the thickness of alkali metals is given in the following reference: Seah, MP, & Dench, WA (1979), Quantitative electron spectroscopy of surfaces: A standard data base for electron inelastic mean free paths in solids. Surf. Interface Anal., 1(1), 2-11.

[0111] In an embodiment, the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali-doped MoTe2, alkali-doped MoSe2, alkali-doped MoS2, alkali-doped WSe2, and alkali-doped WS2.

[0112] In particular, the TMD may be selected from WSe 2 and MoTe 2. More particularly, the TMD may be WSe 2.

[0113] In one embodiment, the alkali metal may include cesium and / or rubidium, and the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali-doped MoTe2, alkali-doped MoSe2, alkali-doped MoS2, alkali-doped WSe2, and alkali-doped WS2. In particular, the alkali metal may include cesium and / or rubidium, and the TMD may be selected from WSe2 and MoTe2. More particularly, the alkali metal may include cesium and / or rubidium, and the TMD may include tungsten diselenide (WSe2).

[0114] Figure 2 A material according to this embodiment is shown in FIG, which is a schematic diagram of a WSe2 surface modified with Cs. Figure 2 In the embodiment of the present invention, WSe2 is provided as a single layer. However, in other embodiments, WSe2 can be provided as a double layer or multilayer (e.g., 3 to 5 layers) material.

[0115] In one embodiment, the unsurface-modified portion 107 of the TMD 101 (if present) may have a 2H crystal structure. In one embodiment, surface modification of one or more portions 105 of the TMD 101 may result in these portions having a different phase than the unsurface-modified portion 107. In one embodiment, one or more portions 105 may have a 1T or 1T' crystal structure, particularly a 1T' crystal structure. Figure 3a and Figure 3b The 2H and 1T' crystal structures of WSe2 are shown respectively, where the tungsten atom is represented by 301 and the selenium atom is represented by 303.

[0116] High-resolution transmission electron microscopy (HRTEM) can be used to directly observe the atomically clear interface between the 2H and 1T / 1T' phases in materials according to embodiments. For example, a protocol suitable for such characterization is provided in Kappera, R., et al. Nat. Mater. 13.12 (2014): 1128.

[0117] The crystal structure of the TMD in the surface modified portion can depend on the thickness of the alkali metal layer 103 present on the surface. In embodiments, the thickness of the alkali metal 103 can be selected so that the surface modified portion 105 of the TMD has a substantially 1T or 1T' crystal structure. Typically, the TMD will exhibit 1T or 1T' characteristics with a larger thickness of the alkali metal, as shown in the experimental results discussed below.

[0118] In one embodiment, the unsurface-modified portion 107 of the TMD 101 may be a semiconductor. In one embodiment, the surface modification of one or more portions 105 may cause these portions to exhibit different electrical properties than the unsurface-modified portion 107 of the TMD. In one embodiment, one or more portions 105 may exhibit metallic properties. In one embodiment, one or more portions 105 may exhibit n-type doping properties.

[0119] The electrical characteristics of the surface modified and unmodified portions can be determined by examining the electrical transport properties of the material according to methods known in the art.

[0120] In one embodiment, the electrical properties of the surface modified portions of the TMDs can depend on the thickness of the alkali metal layer 103 on their respective surfaces. In one embodiment, the thickness of the alkali metal layer can be selected so that the surface modified portions 105 of the TMDs exhibit metallic or substantially metallic properties. Typically, the surface modified portions of the TMDs will exhibit metallic properties at greater thicknesses of the alkali metal.

[0121] In other embodiments, the thickness of the alkali metal can be selected to obtain other electrical properties relative to the unsurface-modified TMD, such as n-type doping properties.

[0122] In one embodiment, the thickness of the alkali metal is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the alkali metal may be in the range of 0.4 nm to 2 nm. In this embodiment, the TMD may exhibit metallic properties and ohmic contact properties.

[0123] In one embodiment, the thickness of the alkali metal layer may be less than 0.4 nm. In one embodiment, the thickness of the alkali metal layer may be 0.2 nm to 0.4 nm. In this embodiment, the TMD may exhibit n-type doping characteristics in the surface-modified portion 105 of the TMD relative to the unmodified portion 107.

[0124] In one embodiment, the thickness of the cesium and / or rubidium is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the cesium and / or rubidium can be in the range of 0.4 nm to 2 nm. In this embodiment, the TMD can exhibit metallic properties and ohmic contact properties.

[0125] In one embodiment, the thickness of the cesium and / or rubidium may be less than 0.4 nm. In one embodiment, the thickness of the cesium and / or rubidium may be 0.2 nm to 0.4 nm. In this embodiment, the TMD may exhibit n-type doping characteristics in the surface-modified portion 105 of the TMD relative to the unmodified portion 107.

[0126] According to the above embodiment, Figure 1 The material may include a multiphase contact within the TMD layer at an interface 111 between the surface modified portion and the unmodified portion. In an embodiment, the multiphase contact is between the 2H phase in the unmodified portion and the 1T' phase in the surface modified portion.

[0127] Therefore, the materials according to the above embodiments can make it possible to utilize the semiconducting and metallic properties of two phases of TMDs within the same material, namely the favorable ambipolar transport properties of the 2H phase and the favorable ohmic electrical contact through the surface-doped metallic 1T′ portion.

[0128] In particular, by employing metallic 1T / 1T' phase TMDs as buffer contact layers, the materials according to the above embodiments can be advantageously deployed in electronic devices such as transistors, thereby realizing 2H-1T / 1T' multiphase transistors with low contact resistance and ohmic characteristics.

[0129] Compared with the metal contacts in existing 2D TMD transistors, the 2H-1T / 1T' multiphase contacts in the materials according to the above-mentioned embodiments can: i) avoid lattice mismatch between the metal electrode and the channel material, which significantly improves the carrier injection efficiency; ii) eliminate the Fermi level pinning effect originating from surface states; and iii) form an atomically clear interface to avoid the formation of chemical bonds at the metal / semiconductor interface (which will produce large strain in the lattice).

[0130] As shown in the examples below, surface modification with cesium and / or rubidium results in devices with very favorable electrical properties.

[0131] Surface modification with alkali metals, particularly cesium and / or rubidium, to achieve multiphase contacts in TMDs as described above offers a facile, non-destructive approach to achieving ohmic contacts in 2D materials while maintaining bipolar properties. Indeed, alkali metal surface functionalization, particularly with cesium and / or rubidium, can be performed in situ, as discussed further below. Phase transitions performed in this manner also enable a high degree of control over the region of the TMD that undergoes the phase transition.

[0132] For traditional semiconductors, ion implantation and thermal diffusion have been widely used to precisely tune the concentrations of different carriers in them. However, in 2D materials, these doping techniques may disrupt the crystal lattice or introduce a large number of defects into the material due to their atomically thin nature, thereby compromising their intrinsic properties. In contrast, surface modification is particularly effective in 2D materials due to their large surface-to-bulk ratio.

[0133] Device

[0134] In one embodiment, the material according to the above embodiment is used in an electronic device. Figure 1 The materials are used in field effect transistors (FETs).

[0135] A schematic diagram of an n-type FET device according to this embodiment is shown in FIG. Figure 4 shown.

[0136] In this embodiment, the transistor includes a single layer of TMD 101 arranged on a substrate 401. Figure 4In the embodiment of the present invention, the substrate is a p-type silicon wafer having a SiO2 layer. It will be understood by those skilled in the art that other suitable substrates having insulating properties may be used according to the embodiment.

[0137] The source and drain electrodes 403 are provided at both ends of the TMD layer 101 on the substrate. The reason for this arrangement will become apparent from the following discussion. Figure 4 In the embodiment of the present invention, the electrode 403 includes palladium (Pd). However, those skilled in the art will understand that other suitable metal materials can be used according to the embodiment.

[0138] In this embodiment, a photoresist material layer 405 is provided on a portion of the surface of the TMD layer 101. Figure 4 In some embodiments, a photoresist such as PMMA is used because its photoresist properties are advantageously used during the manufacturing process (see below). In other embodiments, the top layer of the photoresist material layer 405 can be any insulating material that can encapsulate the TMD layer 101 to avoid modification by one or more alkali metals (including Cs and / or Rb modification). In embodiments, the photoresist or other insulating layer 405 can be partially or completely omitted.

[0139] In one embodiment, the ends 105 of the TMD layer adjacent to the source and drain electrodes 403 are not covered by the dielectric 405 , ie they are exposed.

[0140] In one embodiment, a back gate electrode (not shown) is disposed on the silicon substrate.

[0141] The alkali metal layer 103 exists on a portion of the surface of both ends of the TMD layer 101 that is not covered by the photoresist 405. Therefore, the TMD layer 101 is surface-modified at each end 105 but not modified in the middle. In one embodiment, the alkali metal layer contains cesium and / or rubidium.

[0142] In an embodiment, the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali-doped MoTe2, alkali-doped MoSe2, alkali-doped MoS2, alkali-doped WSe2, and alkali-doped WS2.

[0143] In particular, the TMD may be selected from WSe 2 and MoTe 2. More particularly, the TMD may be WSe 2.

[0144] In one embodiment, each portion of the TMD layer on which the alkali metal is present has a width in the range of 0.2 μm to 5 μm. In one embodiment, they have a width in the range of 0.2 μm to 0.3 μm.

[0145] As mentioned above, above a certain base metal thickness, the TMD layer may be metallic at each end 105, but in the region 107 located below the photoresist 405, towards the middle of the layer 107, it behaves as a semiconductor. Figure 4 In one embodiment, the TMD functions as an n-type unipolar semiconductor. In one embodiment, the TMD has a 1T phase or a 1T' phase at each end 105 adjacent to the source and drain electrodes 403, and has a 2H phase in a portion 107 below the gate electrode that is not surface-modified with an alkali metal. Thus, the TMD includes a multiphase contact 111, and the device 4 is a multiphase transistor.

[0146] In one embodiment, the thickness of the alkali metal is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the alkali metal is in the range of 0.4 nm to 2 nm, as this ensures good ohmic contact between the source and drain electrodes and the TMD, as shown in the examples discussed below. In one embodiment, the thickness of the alkali metal is about 1.0 nm.

[0147] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the cesium and / or rubidium is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the cesium and / or rubidium is in the range of 0.4 nm to 2 nm. In one embodiment, the thickness of the cesium and / or rubidium is about 1.0 nm.

[0148] In one embodiment, the thickness of the alkali metal is selected based on the desired device properties.

[0149] In one embodiment, the thickness of the alkali metal is chosen such that there is a substantially ohmic contact between the electrode and the TMD layer, ie the current between the source and drain electrodes 403 has a substantially linear voltage dependence.

[0150] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is such that the current on / off ratio of the device 4 at room temperature (298K) is at least 10 6 .

[0151] The current on / off ratio of a device is defined as the ratio of the on-state current to the off-state current, that is, the ratio of the maximum current to the minimum current in the transfer characteristic curve.

[0152] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is such that the field effect electron mobility in the device at room temperature (298K) is at least 30 cm 2 V -1 s -1 .

[0153] The field-effect electron mobility μ of the device is calculated from the current between the source and drain (I sd ) transfer curve versus the potential difference between source and drain (V sd ) is obtained from the linear relationship:

[0154]

[0155] Where L and W represent the length and width of the conduction channel between the source and drain electrodes 403, respectively, and C i represents the capacitance per unit area of ​​the dielectric (i.e., SiO2 in this embodiment), and dI sd / dV sd Represents the slope of the linear region in the transfer curve.

[0156] exist Figure 4 In the arrangement of , the electrodes 403 interface with the surface modified portions 105 of the TMD 101, ie they are in direct electrical contact with these portions. However, the majority of the channel remains unmodified.

[0157] This arrangement thus provides a field-effect transistor based on the semiconducting properties of the TMD while ensuring direct electrical contact between the source and drain electrodes and the metallic part of the TMD, thereby ensuring ohmic contact with low contact resistance and avoiding the appearance of Schottky barriers at the contact between the electrodes and the semiconductor material.

[0158] Therefore, the above-described alkali metal functionalization according to embodiments, in particular the functionalization using cesium and / or rubidium, provides a simple method for realizing high performance transistors with high mobility, high current on / off ratio, and low subthreshold swing. Figure 4 The device is a high-quality device that has fast on / off speed and is cost-effective.

[0159] Figure 5 A sandwich structure FET according to one embodiment of the present invention is shown.

[0160] As in Figure 4 In the embodiment of the present invention, the transistor 5 includes a single-layer TMD 101, a source electrode and a drain electrode 403 are provided at both ends of the TMD layer 101 on a substrate 401, and a photoresist material layer 405 is arranged on a portion of the surface of the TMD layer 101. Figure 5 In the embodiment of the present invention, the photoresist 405 is PMMA, however, those skilled in the art will understand that other materials can be used according to the embodiment. In the embodiment, the photoresist or other insulating layer 405 can be partially or completely omitted.

[0161] The TMD and the source and drain electrodes are arranged on the dielectric layer 501. Figure 5In the embodiment of the present invention, the dielectric layer includes a hexagonal boron nitride (h-BN) sheet. However, those skilled in the art will understand that other dielectric layers may be used depending on the embodiment.

[0162] In one embodiment, the thickness of the dielectric layer 501 (h-BN in this embodiment) may specifically be in the range of 10 nm to 20 nm. Thinner dielectric layers may cause unwanted quantum tunneling into the device.

[0163] A dielectric layer is disposed on the bottom gate electrode layer 503. Figure 5 In an embodiment, the bottom gate electrode comprises a graphene layer. Those skilled in the art will appreciate that other suitable materials may be used depending on the embodiment. In one embodiment, the thickness of the bottom gate electrode layer may be less than 10 nm.

[0164] As mentioned above about Figure 4 As described in the embodiment of FIG. 4 , the above-mentioned sandwich arrangement is arranged on a silicon-based substrate 401 .

[0165] As in Figure 4 In the embodiment, the alkali metal layer exists on portions 105 of the surface of the TMD at both ends of the TMD layer 101 that are not covered by the photoresist 405. Therefore, the TMD layer 101 is surface-modified at each end 105 but is not modified in the central portion 107 thereof.

[0166] In one embodiment, the width of each portion 105 of the TMD layer on which the alkali metal is present (ie, the distance these portions extend from the electrode 403) is in the range of 0.2 μm to 5 μm. In one embodiment, they have a width in the range of 0.2 μm to 0.3 μm.

[0167] In one embodiment, Figure 5 The alkali metal layer used in an embodiment comprises cesium and / or rubidium.

[0168] exist Figure 5 In an embodiment, the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped MoS2, alkali metal-doped WSe2, and alkali metal-doped WS2.

[0169] In particular, the TMD may be selected from WSe 2 and MoTe 2. More particularly, the TMD may be WSe 2.

[0170] As mentioned above, above a certain base metal thickness, the TMD layer may be metallic at each end 105, but in the region 107 located below the photoresist 405, towards the middle of the layer 107, it behaves as a semiconductor. Figure 5 In an embodiment, the TMD functions as an n-type unipolar semiconductor. In one embodiment, the TMD has a 1T phase or a 1T' phase at each end 105 adjacent to the source and drain electrodes 403, and has a 2H phase in the portion 107 below the photoresist 405 that is not surface-modified with an alkali metal. Thus, the TMD includes a multiphase contact 111 and the device 5 is a multiphase transistor.

[0171] In one embodiment, the thickness of the alkali metal is in the range of 0.2 nm to 5 nm. In one embodiment, the thickness of the alkali metal is in the range of 0.4 nm to 2 nm. In one embodiment, the thickness of the alkali metal is about 1.0 nm.

[0172] In one embodiment, the thickness of the alkali metal is selected based on the desired device properties.

[0173] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is such that an ohmic contact exists between the electrode and the TMD layer.

[0174] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is such that the current on / off ratio of the device 5 at room temperature (298K) is at least 10 7 , especially in 10 7 to 10 9 within the range.

[0175] The current on / off ratio of a device is defined as the ratio of the on-state current to the off-state current, that is, the ratio of the maximum current to the minimum current in the transfer characteristic curve.

[0176] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is such that the field effect electron mobility of the surface modified portion of the TMD is at least 70 cm 2 V -1 s -1 .

[0177] The field-effect electron mobility μ of the device is calculated from the current between the source and drain (I sd ) transfer curve versus the potential difference between source and drain (V sd ) is obtained from the linear relationship:

[0178]

[0179] Where L and W represent the length and width of the conduction channel between the source and drain 403 electrodes, respectively, and C i Indicates dielectric 501 (i.e. Figure 5 In the embodiment of BN), the capacitance per unit area is dI sd / dVsd Represents the slope of the linear region in the transfer curve.

[0180] In one embodiment, the alkali metal comprises cesium and / or rubidium, and the thickness of the alkali metal is selected so that the subthreshold swing is less than 85 mV dec -1 , especially at 60mV dec -1 to 85mV dec -1 within the range.

[0181] The subthreshold swing of the device is determined by dV g / d(logI sd ) is determined, where V g is the gate voltage, I sd is the current between the source and drain electrodes.

[0182] Figure 6 A transistor-based logic inverter is shown according to one embodiment. The device includes a transistor-based logic inverter that provides an input signal (V IN ) of the back gate electrode 503 and the dielectric layer 501 arranged on the substrate 401, such as the combination Figure 4 The device is described.

[0183] The device also includes three parallel electrodes 605, 607, and 609, which are arranged on the dielectric layer 501 and serve as power supply (VDD; 605), output signal (VOUT; 607) and ground (GND; 609), respectively. The TMD layer 101 between them forms two series channels 601 and 603.

[0184] The photoresist 405 is arranged to completely cover the TMD of one channel 601 so that there is no surface modification of the TMD in the channel, thus enabling the channel to maintain the p-type dominant ambipolar characteristics of the TMD.

[0185] In contrast, another channel 603 is only partially covered by PMMA photoresist 405, with an alkali metal surface modification at each end adjacent to the corresponding electrode 605. Therefore, this channel behaves as described above with respect to Figure 4 and Figure 5 The n-type transistor.

[0186] In an embodiment, the photoresist layer 405 may be completely or partially omitted from one or both channels.

[0187] therefore, Figure 6The embodiment corresponds to a TMD inverter with two series channels. By spatially controlling the exposed area near the metal electrode of one TMD channel, a unipolar multiphase n-type transistor is obtained. In contrast, the other channel is completely covered with PMMA photoresist, where the p-type-dominated bipolar transport characteristics are preserved. Figure 6 In the embodiment, multilayer h-BN and graphene are used as dielectric layer and bottom gate electrode respectively, however, the skilled person will understand that other suitable materials can be used according to the embodiment. Graphene provides input signal (V IN ), the three parallel electrodes on the TMD sheet are used as power supplies (V DD ), output signal (V OUT ) and ground (GND).

[0188] In one embodiment, the thickness of the alkali metal layer is selected based on the desired properties of the n-type channel.

[0189] In one embodiment, the thickness of the alkali metal is in the range of 0.2 nm to 5 nm, in particular in the range of 0.4 nm to 2 nm. In one embodiment, the thickness of the alkali metal is about 1.0 nm.

[0190] In one embodiment, the alkali metal includes cesium and / or rubidium, and the thickness of the alkali metal may be such that when V DD =2.5V, the gain of inverter 6 can be realized (-dV OUT / dV IN ) is greater than 100.

[0191] In one embodiment, the alkali metal includes cesium and / or rubidium, and the thickness of the alkali metal may be such that when V DD =0.5V, for a static power consumption of less than 10pW (defined as P = V DD ×I DD ), the inverter can obtain a gain greater than 5.

[0192] As shown below, experimental results show that the inverter according to this embodiment has a high voltage gain, thereby enabling fast logic state inversion, high precision, and low power consumption.

[0193] Although the three devices 4, 5, and 6 according to the embodiment have been described, Figure 1 While the integration of materials of the embodiments described above is illustrated, those skilled in the art will appreciate that these devices are merely representative of potential applications for materials according to the embodiments. In fact, the materials according to the embodiments described above are highly flexible and compatible with a wide variety of device architectures. They can be applied to virtually any electronic and optoelectronic device to improve charge injection / collection efficiency. The thickness of the alkali metal layer can be varied to fine-tune the material's electrical properties depending on its intended implementation.

[0194] Figure 7 Shown is a production method according to one embodiment Figure 1 It is also applicable to the Figure 4 、 Figure 5 and Figure 6 Generate relevant layers in the device.

[0195] In step S701, a TMD 101 is provided. Depending on the requirements of the final material, the layer can be a single layer, a double layer, or include three or more layers. Bulk TMD crystals are commercially available from, for example, HQ-Graphene. Single and double layer TMDs can be produced from bulk TMDs by mechanical exfoliation, for example using Scotch tape.

[0196] In one embodiment, the TMD may be transferred to a suitable substrate, such as silicon dioxide, before performing step S703. In one embodiment, the electrodes may be patterned onto the TMD using electron beam lithography before performing step S703. Thus, steps S703 to S707 may be performed in situ in the electronic device, such as described above with respect to Figure 4 、 Figure 5 and Figure 6 Those electronic devices described.

[0197] If electrode patterning is performed, after patterning the source and drain electrodes on the TMD, the electrodes can be thermally evaporated onto the substrate, for example, by thermally evaporating Pd and / or Au. Excess metal can then be removed from the sample according to procedures known in the art, for example, by soaking in acetone. The method then proceeds to step S703.

[0198] In step S703, the surface 109 of the TMD layer is coated with a barrier layer 405 of a photoresist such as PMMA. In one embodiment, the barrier layer is applied to the TMD layer using spin coating.

[0199] In step S705, electron beam lithography (EBL) is used to remove the photoresist on the portions of the TMD layer to be surface modified 105. In the embodiment of Figure S705, these are portions at the edges of the layer.

[0200] In step S707, a layer 103 of one or more alkali metals is evaporated directly onto the TMD layer. In one embodiment, this is accomplished under vacuum using one or more alkali metal getters. Suitable getters are commercially available, for example from SAES. In one embodiment, the one or more alkali metals include cesium and / or rubidium, and the layer of cesium and / or rubidium is evaporated onto the TMD layer using, for example, a cesium and / or rubidium getter.

[0201] In one embodiment, an alkali metal getter is heated in a high vacuum chamber with a TMD to achieve evaporation of alkali metal onto the exposed surface of the TMD.Evaporation of alkali metal from the getter can be achieved, for example, by supplying a DC current to a feedthrough in the vacuum chamber.

[0202] In one embodiment, the vacuum chamber should be at a temperature less than 10 -7 mbar high vacuum conditions. Such pressures can be achieved by pumping a suitable chamber with a turbopump. Turbopumps suitable for achieving high vacuum are commercially available, for example, from Pfeiffer Vacuum GmbH. Chamber components suitable for supporting such a vacuum are also commercially available, for example, from UHV Design.

[0203] Due to the presence of the photoresist 405 as a barrier layer, the film growth of the alkali metal is confined to the exposed portions 105 and 105 of the TMD layer.

[0204] The thickness of the alkali metal can be monitored by monitoring the weight of the material during the evaporation process, for example using a quartz crystal microbalance (QCM), thereby enabling it to be controlled as appropriate based on the desired material or device properties.

[0205] Quartz crystal microbalances (and corresponding feedthroughs) suitable for use in accordance with embodiments are commercially available, for example from Testbourne Ltd.

[0206] In one embodiment, the vacuum chamber is configured such that the QCM is positioned to protect the sample from alkali metal deposition while achieving a desired evaporation rate from the alkali metal getter. Once the desired rate is achieved, the QCM is removed to allow alkali metal deposition. Once the desired evaporation rate on the sample is complete, the QCM is returned to its original position to prevent further deposition on the sample.

[0207] Suitable in situ vacuum characterization systems for use in accordance with embodiments are given in Lei, B., et al. (2017). NanoResearch, 10(4), 1282-1291.

[0208] Depending on the desired application, the photoresist layer may or may not be removed after application.

[0209] therefore, Figure 7 The method provides a method for producing materials and devices according to embodiments that can be performed in situ and easily integrated with conventional CMOS processes, thereby enabling direct integration into the manufacturing process. The method provides an efficient, damage-free, and non-volatile process for achieving phase transitions in TMDs such as WSe2.

[0210] Example

[0211] Selected advantageous physical properties of the above-described embodiments will now be described with reference to the following non-limiting examples.

[0212] Fabrication of pristine 2D WSe2 transistors

[0213] WSe2 flakes were mechanically peeled off from bulk WSe2 crystals (commercially available from HQ-graphene) using scotch tape and then quickly transferred to a degenerate p-type doped silicon substrate with 300nm SiO2. Monolayer and bilayer WSe2 were discovered using a high-resolution optical microscope (Nikon Eclipse LV100D) and further verified by AFM and Raman measurements. Polymethylmethacrylate (PMMA) photoresist (commercially available from MicroChem) was then spin-coated on a silicon substrate for conventional electron beam lithography (EBL) processing. After patterning the source and drain electrodes onto WSe2, 5nm Pd and 60nm Au were thermally evaporated onto the substrate. The sample was then immersed in acetone for approximately 1 hour to remove excess metal.

[0214] Figures 8a to 8c Results are shown for a bilayer WSe2 device, where a WSe2 flake was mechanically exfoliated onto a degenerate p-type doped silicon wafer with a 300nm SiO2 layer. Standard photolithography was then performed to define the WSe2 channel, followed by metal deposition of Pd / Au. Figure 8a Figure 5 shows the line profile derived from an atomic force microscopy (AFM) image of the device. It reveals that the thickness of the WSe2 flake is about 1.7 nm, indicating its bilayer nature. Raman and photoluminescence (PL) measurements (respectively) Figure 8b and Figure 8c ) was further verified. The three Raman characteristic peaks are located at 250cm -1 (E 1 2g )、257.5cm -1 (A 1g ) and 309cm -1 (B 1 2g ), the PL spectrum 801 shows a direct bandgap emission peak 803 at ~1.64 eV and an indirect bandgap emission peak 805 at ~1.57 eV, further confirming the bilayer nature of the WSe2 flakes.

[0215] Surface modification with Cs

[0216] To investigate the phase transition induced by Cs modification in bilayer WSe2 by in situ electrical measurements, the pristine WSe2 device was wire-bonded to a lead chip carrier and loaded into a home-made high vacuum system (~10 -7 mbar). The vacuum system was manufactured according to the design given by Lei, B., et al. (2017), Nano Research, 10(4), 1282-1291.

[0217] An Agilent 2912A precision source / measure unit (SMU) was used to perform the relevant electrical measurements. Cesium was directly evaporated onto the device from a SAES getter in situ, and the nominal thickness was calibrated using a quartz crystal microbalance (QCM) (commercially available from Testbourne Ltd). The temperature-dependent experiments described below were performed on a cryogenic stage, with liquid nitrogen used for sample cooling.

[0218] The sample is loaded onto the sample stage through a flexible, quick-access door. After several hours of pumping, the sample is pulled back to a specific location for in-situ deposition, where a thermal diffusion cell is equipped to evaporate the dopant. A quartz crystal microbalance (QCM) is placed in front of the sample stage to accurately monitor the deposition rate. Once the Cs evaporation rate is confirmed, the QCM is moved upward to allow Cs to deposit onto the sample. After evaporation, the QCM is moved downward to block Cs. Cs is evaporated using a DC current (3.8A) supplied via a feedthrough.

[0219] Figure 9a A schematic diagram of a double-layer WSe2 923 device in a FET structure is shown, where Pd / Au (5nm / 60nm) is used as the metal contact 921 and a 300nm SiO2 layer is used as the dielectric.

[0220] Figure 9b and Figure 9c The pristine double-layer WSe2 FET under high vacuum conditions (10 -7 mbar) under the transmission characteristics (I sd -V g The results clearly reveal the hole-dominated bipolar transport characteristics, where at a fixed bias (V sd =1V) and scan the gate voltage from -80V to 50V.

[0221] Figure 9dThe evolution of the transfer characteristics of a WSe2 FET as a function of Cs thickness is shown after in-situ deposition of Cs on the device as described above. The thicknesses shown are 0 nm (901), 0.01 nm (903), 0.07 nm (905), 0.19 nm (907), 0.4 nm (909), and 1.0 nm (911). Two distinct phases are observed, including: i) a pronounced n-type doping phase with strongly enhanced on-current in the electron transport mechanism at low Cs doping levels (nominal Cs thickness < 0.2 nm); ii) when the nominal Cs thickness is above 0.4 nm, the WSe2 device exhibits almost gate-independent transfer characteristics, indicating a semiconductor-to-metal phase transition.

[0222] Figure 9e The relationship between the conductivity (G) and the Cs thickness at Vg = 0 V is shown. sd / V sd ) has significantly increased by nearly 7 orders of magnitude, from 2.1×10 -11 S to 1.0nm Cs modified 1.1×10 -4 S.

[0223] Figure 9f The original (915) and 1.0nm (913) Cs modified WSe2 FETs are shown at different gate voltages V from 0V to 50V. g The output curve (I sd / V sd As shown in the output curves of the WSe2 device before and after 1.0nm Cs modification, the original WSe2 device exhibits Schottky contact characteristics, while the Ohmic contact characteristics are confirmed after 1.0nm Cs modification. sd The large enhancement reveals the reduction of contact resistance and channel resistance originating from the semiconductor-to-metal phase transition.

[0224] The semiconductor-to-metal phase transition in the bilayer WSe2 device was further characterized by temperature-dependent transport measurements. The temperature-dependent experiments were performed on a cryogenic stage using liquid nitrogen for sample cooling, and the results were shown in Figure 9g and Figure 9h The conductivity evolution of the original (917) and Cs-modified (919) bilayer WSe2 devices varies with temperature, with a gate voltage of Vg = -80 V ( Figure 9g ) and 50V( Figure 9h ).

[0225] from Figure 9g and Figure 9hAs can be seen in the figure, the semiconducting and metallic bilayer WSe2 devices exhibit opposite temperature-dependent evolution trends. For the pristine semiconducting WSe2 device, the conductivity gradually increases with increasing temperature, which is attributed to the significant enhancement of thermally activated carriers. In contrast, in the 1.0nm Cs-modified metallic WSe2 device, increasing temperature leads to a decrease in conductivity. High temperatures enhance electron scattering in the metallic WSe2, leading to a decrease in conductivity.

[0226] Figure 9i The conductivity evolution with respect to temperature of a bilayer WSe2 device functionalized with 1.0 nm Cs is shown at different Vgs from -80 V to 50 V. At all gate voltages, the conductivity gradually decreases with increasing temperature, clearly revealing the metallic nature of the Cs-modified WSe2 flakes and further confirming the semiconductor-to-metal phase transition induced by the Cs surface functionalization.

[0227] In order to understand the semiconductor-to-metal phase transition mechanism of Cs-modified WSe2, in situ XPS / UPS experiments were further performed. -10 In situ UPS and XPS measurements were performed on bulk WSe2 (obtained from HQ-graphene) modified with Cs in a 1000 nm CMOS process. He I (21.2 eV) was used as the excitation source and a sample bias voltage of 5 V was applied for UPS characterization. Al Kα (148.7 eV) was used as the excitation source for XPS measurements. The nominal thickness of the in situ deposited Cs layer was estimated by monitoring the decay of the WSe2 core level peak and further calibrated by QCM. The results are shown in Figure 2. Figure 10 As shown, Figure 10 (a) shows the UPS spectrum evolution in the low kinetic energy region, Figure 10 (b) shows the XPS core level spectrum of W 4f as the thickness of Cs on WSe2 changes; Figure 10 (c) shows the XPS core level spectrum of Se 3d as a function of Cs thickness on WSe2, and Figure 10 (d) shows the UPS valence band spectrum near the Fermi level region. In all figures, the original WSe2 is represented as 1001, 0.01nm Cs is represented as 1003, 0.10nm Cs is represented as 1005, 0.20nm Cs is represented as 1007, 0.40nm Cs is represented as 1009, and 1.00nm Cs is represented as 1011. Here represents the work function, and ΔE represents the energy difference.

[0228] The work function (WF) of pristine WSe2 was measured to be approximately 4.02 eV, which dropped sharply to approximately 2.2 eV after 1.0 nm Cs modification. The reduction in WF implies significant electron transfer from Cs to WSe2 at the Cs / WSe2 interface, which is caused by the ultra-low WF of Cs (approximately 2.14 eV).

[0229] Figure 10 (b) and Figure 10 (c) shows the evolution of the binding energy of the W 4f and Se 3d core levels as a function of Cs thickness, respectively. As the Cs deposition thickness increases to 0.2 nm, the electron doping effect of Cs on WSe2 shifts the Fermi level of WSe2 toward its conduction band, so the binding energies of W 4f and Se 3d increase slightly by 0.1 eV and 0.15 eV, respectively. Interestingly, when the Cs thickness increases from 0.2 nm to 1.0 nm, the W 4f and Se 3d core energy levels shift to lower binding energies by approximately 0.3 eV and approximately 0.35 eV, respectively. This is consistent with previous reports on K functionalization, whereby electron doping induces a semiconductor-to-metal (2H to 1T') phase transition in bilayer WSe2. Further Cs deposition leads to the accumulation of negative charges on the metallic WSe2 surface, so that the core energy level peak shifts to lower binding energies.

[0230] Figure 10 The valence band spectrum shown in (d) further verifies the metallization of heavily doped WSe2. At low surface modification levels (Cs thickness < 0.4 nm), a downward bending of the valence band is observed due to electron doping. When the Cs thickness is greater than 0.4 nm, a sharp peak appears near the Fermi level, clearly showing a metallic feature, which further confirms the semiconductor-to-metal phase transition.

[0231] Figure 11a Shown are the photoluminescence (PL) spectra of bilayer WSe2 flakes before (1103) and after (1101) 0.1 nm Cs modification. Figure 11b The Raman spectra of pristine, 0.1 nm and 1.0 nm Cs-modified WSe2 are shown. Among the three polymorphs of WSe2, 1T and 1T' are both metallic. Previous reports have shown that the 1T phase of group VI TMDs is unstable and spontaneously transforms to the 1T' phase with energy relaxation. Therefore, without wishing to be bound by theory, we propose that the metallic phase of WSe2 after Cs doping is 1T'. In situ Raman and PL were performed to reveal the phase transition of Cs-modified WSe2. Figure 11a and Figure 11bThe results show the in situ PL and Raman spectra of bilayer WSe2 before and after Cs deposition. After 0.1 nm Cs deposition, the PL peak of bilayer WSe2 is immediately quenched due to significant charge transfer. The original bilayer WSe2 shows three characteristic peaks in the Raman spectrum, which are located at 250 cm -1 (E 1 2g )、257.5cm -1 (A 1g ) and 309cm -1 (B 1 2g ). After 0.1nm Cs coverage, the intensity of these peaks is greatly reduced. Further increasing the Cs thickness to 1.0nm leads to a phase transition of the bilayer WSe2 from the semiconducting 2H phase to the 1T' metallic phase. B 1 2g The peak disappears completely, and five new peaks appear in the low wavenumber region at about 93 cm -1 、114cm -1 , 227cm -1 、242cm -1 and 260cm -1 These new peaks correspond to the characteristic peaks of WSe2 in the 1T' phase. Therefore, without wishing to be bound by theory, the phase transition of Cs-modified WSe2 observed here can be attributed to the 2H to 1T' phase transition.

[0232] Multiphase device manufacturing

[0233] For according to Figure 4 To fabricate a multiphase device using an embodiment of the present invention, a pristine WSe2 device was first fabricated according to the method described above. To achieve a partially surface-modified device, PMMA photoresist was again spin-coated, and a second EBL process was performed to expose the desired area around the contacts after stripping away excess metal. The device was then loaded into a vacuum system as previously described for cesium evaporation for electrical characterization.

[0234] Figure 12a The evolution of the transfer characteristics with varying Cs thicknesses of 0 nm (1301), 0.05 nm (1303), 0.20 nm (1305), 0.50 nm (1307), and 1.00 nm (1309) is shown. As mentioned previously, the WSe2 flakes are n-type doped at low Cs deposition levels. Further increasing the Cs thickness to high levels induces a phase transition in the exposed regions, leading to 1T' contacts. The saturation current with 1T' phase contact is about 2 orders of magnitude higher than that of the original device with Pd contact, resulting in a huge gate modulation effect and a gate current of about 10 7 High current on / off ratio.

[0235] The field effect electron mobility also increased from 0.6 cm 2 V -1 s -1 Significantly increased to 37.7cm 2 V -1 s -1 ,like Figure 12b As shown in Figure 3, the evolution of electron mobility with Cs thickness is shown. This shows that the device with 1T' contact has superior transport performance.

[0236] Figure 12c and Figure 12d 1.0 nm Cs functionalized before ( Figure 12d ) and after ( Figure 12c The pristine transistor exhibits clear Schottky contact characteristics, while an ideal ohmic contact can be observed after Cs functionalization, as reflected by the symmetric and linear characteristics of the output curve.

[0237] Therefore, in situ Cs surface modification has been demonstrated to be an effective method to induce semiconductor-to-metallic phase transition in 2H WSe2, which provides an opportunity to realize high-performance 2H-1T′ multiphase WSe2 transistors by spatially controlling the phase transition region.

[0238] The gate voltage V g The results of varying the Schottky barrier height are as follows Figure 13a As shown. Figure 13a For electron transport, the SB in the multiphase transistor was determined to be as low as approximately 9.4 meV. This negligible SB can significantly enhance electron injection into the semiconductor, leading to true ohmic contact characteristics under high electrostatic doping.

[0239] To further quantify the contact quality of an ideal n-type multiphase WSe2 transistor, the width-normalized contact resistance (R c A series of WSe2 (5-layer) transistors with different channel lengths were used for the measurements. To ensure accuracy, it was assumed that the channel segments covered by the metal contacts had no effect on the overall channel length. In addition, since one of the Schottky contacts can easily become forward biased when a high bias voltage is applied, a very small bias (about 10 mV) was used to avoid underestimating R. c . Figure 13b shows that the V g = Total resistance normalized by width with channel length at 5V (R tot ). R totis a linear fit, where the y-intercept yields the total contact resistance (2R c ), the slope represents the sheet resistance of the channel (R sh ). g =5 V, a low contact resistance of about 4.3 kΩμm is obtained, which can be attributed to the combined effects of the reduced SB height and narrowed SB width.

[0240] To create the basis Figure 5 In a sandwich structure device of an embodiment of the present invention, a few-layer graphene (commercially available from HQ-Graphene) is first peeled off on a SiO2 / Si substrate using scotch tape. Then, 15nm thick hexagonal boron nitride (n-BN) (commercially available from ACS Material, LLC) and WSe2 (commercially available from HQ-Graphene) are subsequently peeled off on a viscoelastic stamp using polydimethylsiloxane (PDMS) (commercially available from Merck Group) and transferred to the desired graphene sheet. The above procedure is used to obtain a contact exposure channel to realize a 2H-1T' multiphase FET. The device is then placed in a high vacuum chamber for further measurements.

[0241] Figure 14a The evolution of the device transfer characteristics with varying Cs thickness is shown. Results are shown for Cs thicknesses of 0.0 nm (1401), 0.01 nm (1403), 0.08 nm (1405), 0.20 nm (1407), and 1.00 nm (1409).

[0242] Low levels of Cs deposition induce electron doping effects in the uncovered WSe2. Further increasing the Cs thickness leads to a phase transition of the uncovered WSe2, thus achieving a 2H-1T' contact. Remarkably, the on-state current of the 2H-1T' multiphase device is about three orders of magnitude higher than that of the original device with Pd contact, resulting in an ultra-high current on / off ratio of about 10 8 In addition, it is defined as dV g / d(logI sd ) is optimized to 75mV dec -1 , close to 60mV dec -1 The field-effect mobility can be extracted from the linear region of the transfer curve using the following equation:

[0243]

[0244] Where L and W represent the length and width of the conduction channel respectively, C i represents the capacitance per unit area of ​​the dielectric, and dI sd / dV sd Represents the slope of the linear region in the transfer curve graph.

[0245] Figure 14b The relationship between the electron mobility and the Cs thickness is shown. The electron mobility increases from 1.33 cm 2 V -1 s -1 Significantly increased by nearly 50 times to 70cm 2 V -1 s -1 .

[0246] Figure 14c and Figure 14d The 1.0 nm Cs contact before doping ( Figure 14c ) and after ( Figure 14d ). Even at high electrostatic doping levels (Vg ~ 5V), the output curve of the original WSe2 device is nonlinear, illustrating the clear Schottky contact characteristics. After 1.0nm Cs modification, the current is greatly improved by more than 2 orders of magnitude at each gate voltage. In addition, the output curve is almost linear, especially at low V sd state, indicating an almost ideal ohmic contact.

[0247] according to Figure 5 The second sandwich structure device of the embodiment is manufactured according to the same procedure as described above. Figure 14e The evolution of the transmission characteristics of the second device with varying Cs thickness is shown. Results are shown for 0.0 nm (i.e., pristine WSe2; 1413) and 1.00 nm (1411) Cs thickness.

[0248] It was found that the current on / off ratio of the Cs-doped device was even higher, about 10 9 In addition, the defined subthreshold swing (SS) was measured to be 61mV dec -1 .

[0249] according to Figure 6 The device of the embodiment of the invention was fabricated as described above for the FET sandwich device, but modified to obtain contact exposed channels and full PMMA covered channels. As before, the device was loaded into a high vacuum chamber for further measurements.

[0250] Figure 15a The transfer characteristics of N-FET 1501 and P-FET 1503 are shown, demonstrating that a unipolar multiphase n-type transistor can be obtained by spatially controlling the exposed area near the metal electrode of one WSe2 channel, while the p-type-dominated ambipolar transfer characteristics are retained in the other channel that is completely covered by PMMA photoresist.

[0251] Figure 15b shows the V DD =1V(1505), 2V(1507) and 2.5V(1509) IN The output characteristics of the in-phase WSe2 inverter are varied. By sweeping the input voltage from -1V to 2V, the inverter goes through the "high state" (high V OUT ), "High Slope" (V OUT sharp drop) and "low state" (low V OUT A key parameter for evaluating inverter performance is the voltage gain defined by the slope of the output characteristic (Gain = -dV OUT / dV IN ). This is Figure 16 (a) further shows that the V DD =0.5V(1601), 1.0V(1603), 1.5V(1605), 2.0V(1607) and 2.5V(1609), with V IN Changing output characteristics.

[0252] Figure 15c shows the three different V DD (As above) with V IN Variation of the extraction gain. At a small V of 1V DD The gain is about 13. By setting V DD Increasing to 2V and 2.5V, the gains can reach 49 and 106, respectively. Notably, these gains are the highest among all the same-phase transistors based on 2D materials. Without wishing to be bound by theory, we propose that such high gains are mainly attributed to the low SS of the Cs-modified WSe2 transistor (about 75mV dec -1 ) and ultra-high current on / off ratio (approximately 10 8 ), which ensures that the inverter switches quickly between "high" and "low" states.

[0253] Figure 15d shows the V DD The evolution of the power consumption of the device. DD =2.5V, the power is about 280nW, at V DD = 0.5V and gradually decreases to an ultra-low value of about 5pW. It is worth noting that V DD The gain at 0.5V can be maintained at a moderate level of about 8, which is highly competitive among all logic inverters based on 2D materials due to such ultra-low power consumption. Figure 16 (b) shows that the V DD =0.5V, with VIN The changing output curve (1611) and the corresponding voltage gain (1613).

[0254] The above results indicate that a semiconductor to metal (2H to 1T') phase transition is achieved in WSe2 by in situ Cs surface functionalization. The in situ electrical characterization of WSe2 FETs first revealed the phase transition. Cs-functionalized WSe2 transistors exhibit gate-independent transfer characteristics with conductivity increased by nearly 7 orders of magnitude. As revealed by in situ UPS / XPS and Raman measurements, the 2H to 1T' phase transition originates from the colossal electron doping from Cs to WSe2. By implementing the 1T' phase WSe2 thus formed as a contact electrode, a significantly enhanced field-effect electron mobility (increased by nearly 50 times to approximately 70 cm) was obtained. 2 V -1 s -1 ) 2H-1T' multiphase WSe2 transistor. In addition, the device also shows about 10 8 Ultra-high current on / off ratio and about 75mV dec -1 Low SS, thus achieving ultra-low power consumption of about 5pW and about 10 6 The high-performance WSe2 logic inverter with high voltage gain is higher than that of all the same-phase inverters based on 2D materials.

[0255] Although the above results were obtained under vacuum, the skilled artisan will appreciate that any environment excluding oxygen and water may be used equivalently, such as substantially 100% N2, or other inert environment under normal atmospheric conditions.

[0256] Therefore, alkali metal functionalization-induced phase transitions in TMDs, especially Cs metal functionalization-induced phase transitions, provide a simple approach to realize high-performance TMD multiphase transistors and logic inverters.

[0257] In particular, in situ alkali metal surface modification, especially in situ Cs surface modification, has been demonstrated to be an effective method to induce semiconductor-to-metallic phase transition in 2H TMDs, which provides an opportunity to realize high-performance 2H-1T′ multiphase TMD transistors by spatially controlling the phase transition region.

[0258] In the foregoing detailed description, embodiments of the present disclosure relating to transition metal dichalcogenides and devices thereof are described with reference to the accompanying drawings provided. The description of various embodiments herein is not intended to introduce or be limited to a specific or particular representation of the present disclosure, but is merely to illustrate non-limiting examples of the present disclosure. The present disclosure is intended to address at least one of the above-mentioned problems and difficulties associated with the prior art. Although only some embodiments of the present disclosure are disclosed herein, it will be apparent to a person of ordinary skill in the art in view of the present disclosure that various changes and / or modifications may be made to the disclosed embodiments without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure and the scope of the appended claims are not limited to the embodiments described herein.

[0259] Further implementations are given in the following description:

[0260] 1. A transition metal dichalcogenide (TMD) comprising a first portion, wherein the first portion is surface-modified with a Group 1 alkali metal.

[0261] 2. The TMD according to 1, wherein the Group 1 alkali metal forms a layer on one side of the first portion.

[0262] 3. The TMD according to 1 or 2, wherein the Group 1 alkali metal is selected from lithium, sodium, potassium, rubidium, cesium or francium.

[0263] 4. The TMD according to any one of 1 to 3, further comprising a second portion, wherein the first portion has a different phase structure from the second portion.

[0264] 5. The TMD according to any one of 1 to 4, wherein the first portion has a metallic octahedral (1T′) phase structure.

[0265] 6. The TMD according to any one of 1 to 5, wherein the thickness of the Group 1 alkali metal in the first portion is from about 0.2 nm to about 10 nm.

[0266] 7. The TMD according to any one of 1 to 6, wherein the TMD is selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped MoS2, alkali metal-doped WTe2, alkali metal-doped WSe2 or alkali metal-doped WS2.

[0267] 8. An electronic device comprising:

[0268] a transition metal dichalcogenide (TMD) layer comprising a first portion, wherein the first portion is surface-modified with a Group 1 alkali metal; and

[0269] A pair of electrodes connected to the TMD layer.

[0270] 9. The electronic device according to 8, wherein the electrical conductivity thereof is at least 4 times that of the control.

[0271] 10. The electronic device according to 8 or 9, having a contact resistance of about 1 kΩμm to about 10 kΩμm.

[0272] 11. The electronic device according to any one of 8 to 10, having a diameter of at least about 70 cm 2 V -1 s -1 electron mobility.

[0273] 12. The electronic device according to any one of 8 to 11, having a current on / off ratio of at least about 80.

[0274] 13. The electronic device according to any one of 8 to 12, having a current density of at least about 60 mV dec -1 The subthreshold swing (SS) of

[0275] 14. The electronic device according to any one of 8 to 13, having a voltage gain of about 100.

[0276] 15. The electronic device according to any one of 8 to 14, having a power consumption of less than about 10 pW.

[0277] 16. The electronic device according to any one of 8 to 15, which is a logic inverter or a field effect transistor.

[0278] 17. An electronic circuit comprising the electronic device according to any one of 8 to 16.

[0279] 18. An electronic system comprising the electronic circuit described in 17.

Claims

1. A material for use in an electronic device, comprising: Transition metal dichalcogenides (TMDs); as well as a layer of one or more Group 1 metals on a surface of at least a portion of the transition metal dichalcogenide, the at least a portion of the transition metal dichalcogenide being surface-modified by the layer of the one or more Group 1 metals and comprising a 1T phase or a 1T' phase; wherein the one or more Group 1 metals include Cs and / or Rb, and wherein the thickness of the layer of the one or more Group 1 metals is greater than or equal to 0.2 nm.

2. The material according to claim 1, wherein The transition metal dichalcogenide includes one or more of MoS2, WS2, MoSe2, WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped MoS2, alkali metal-doped WSe2 and alkali metal-doped WS2.

3. The material according to claim 2, wherein The transition metal dichalcogenide includes one or more of WSe2 and / or MoTe2.

4. The material according to claim 3, wherein The transition metal dichalcogenide includes WSe2.

5. The material according to any one of claims 1 to 4, wherein The layer of the one or more Group 1 metals is formed on surfaces of at least a first portion and a second portion of the transition metal dichalcogenide, the first portion and the second portion of the transition metal dichalcogenide both comprising a 1T phase or a 1T′ phase.

6. The material according to claim 5, wherein The transition metal dichalcogenide further includes a third portion located between the first portion and the second portion, the third portion not being surface-modified with the one or more Group 1 metals.

7. The material according to claim 6, wherein The first portion and the second portion are in a different structural phase than the third portion.

8. The material according to claim 1, wherein The layer of the one or more Group 1 metals has a thickness of 0.4 nm to 2.0 nm.

9. The material according to any one of claims 1 to 4, wherein At least a portion of the transition metal dichalcogenide has a thickness of 1 to 5 layers.

10. The material according to any one of claims 1 to 4, wherein At least a portion of the transition metal dichalcogenide is a monolayer or a bilayer.

11. An electronic device comprising: The material according to claim 6; and a first electrode and a second electrode, The first electrode and the second electrode are in direct electrical contact with the first portion and the second portion of the transition metal dichalcogenide, respectively.

12. The electronic device according to claim 11, wherein The electronic device exhibits substantially ohmic contact characteristics with respect to the first electrode and the second electrode. The electronic device according to claim 11 , having a Schottky barrier height less than or equal to 10 meV.

14. The electronic device according to claim 11, wherein The electronic device is a field effect transistor.

15. The electronic device according to claim 11, wherein The electronic device is a logic inverter.

16. A method for producing a material for use in an electronic device according to any one of claims 1 to 4, the method comprising: providing an initial transition metal dichalcogenide comprising a 2H phase; and The one or more Group 1 metals are evaporated onto at least a portion of the initial transition metal dichalcogenide to form the layer of the one or more Group 1 metals, so as to surface-modify the at least a portion of the initial transition metal dichalcogenide and induce a phase change, thereby forming the at least a portion of the transition metal dichalcogenide comprising a 1T phase or a 1T' phase.

17. A method of producing the electronic device according to claim 11, the method comprising: providing a layer of the transition metal dichalcogenide and the first and second electrodes on a surface of a substrate such that the first and second electrodes are in electrical contact with the layer of the transition metal dichalcogenide; The one or more Group 1 metals are evaporated onto surfaces of the first portion and the second portion of the layer of the transition metal dichalcogenide to form the layer of the one or more Group 1 metals so that the thickness of the layer of the one or more Group 1 metals is greater than or equal to 0.2 nm, wherein the first portion and the second portion of the layer of the transition metal dichalcogenide are adjacent to the first electrode and the second electrode, respectively.

18. The method according to claim 17, wherein Evaporating the one or more Group 1 metals onto the surfaces of the first portion and the second portion of the layer of the transition metal dichalcogenide includes forming a barrier layer on portions of the surfaces of all portions of the layer of the transition metal dichalcogenide except the first portion and the second portion before evaporating the one or more Group 1 metals.

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