A method for detecting the vertical gate depth of transfer tubes in CMOS image sensors

Abstract

The present invention discloses a method for detecting the depth of the vertical gate of a CMOS image sensor transfer tube. By combining planar and vertical gates of the same layout area, the effective electrical thickness (EOT) of the planar gate polysilicon of a reference CMOS image sensor transfer tube is obtained through a planar test, and the capacitance (C) of the vertical gate structure of the CMOS image sensor transfer tube to be tested is obtained through a vertical test. ox(VTG) , and then calculate the equivalent depth of the vertical gate of the transfer tube of the CMOS image sensor to be tested based on this, effectively monitoring the vertical gate depth. It can realize online monitoring of the transfer tube gate depth of all CMOS image sensors without damaging the silicon wafer, making it easy to timely discover abnormalities in the transfer tube gate depth and effectively monitor the product quality of CMOS image sensors.

Description

Technical Field

[0001] The present invention relates to semiconductor detection technology, and in particular to a method for detecting the vertical gate depth of a transfer tube of a CMOS image sensor. Background Art

[0002] CMOS image sensors have experienced rapid development over the past decade and are now widely used in mobile phones, computers, digital cameras, and other fields. To meet market demand and integrate more pixels per unit area, the pixel size of CMOS image sensors has gradually shrunk from 5.6mm to 1.0mm. However, this reduction in pixel size cannot simply translate to a reduction in the dimensions of the photodiode (photodiode) due to the limitations of the photodiode's effective full well capacity (FWC). If the size is too small, insufficient electrons can be stored, resulting in severe image quality degradation.

[0003] The basic structure of a common 4T CMOS image sensor is as follows Figure 1 As shown, it consists of a photodiode (PD) 10, a transfer transistor (Tx) 11, a reset transistor (RST) 13, an amplifier transistor (SF) 14, and a row select transistor (RS) 15. When the transfer transistor (Tx) 11 is closed for light sensing, the PN junction of the photodiode (PD) 10 captures sunlight to generate electrons and holes. Under the action of the built-in electric field of the PN junction, the photogenerated electrons accumulate at the top. When the gate of the transfer transistor (Tx) 11 is powered on and turned on, they are transferred through the surface channel to the floating diffusion region (Floating Diffusion) 12 between the transfer transistor (Tx) 11 and the reset transistor (RST) 13, and then read. The electron transfer path is shown as follows: Figure 2 As shown in the figure, this electron transfer method has a narrow path. Electrons deep within the photodiode must travel through the entire junction region, where they are easily recombined, resulting in low extraction efficiency. Furthermore, electrons deep within the PN junction require a certain amount of time and voltage to complete transfer, which is not conducive to fast reading. To increase the speed and efficiency of electron transfer, developing a three-dimensional pixel region to replace the traditional two-dimensional channel structure is an effective way to address these issues.

[0004] like Figure 3As shown in the figure, the development of vertical gate can extend the channel deep into the photodiode, and the electron transmission channel is transformed from a planar channel to a three-dimensional channel. The electron transmission channel is multiplied, and the transmission rate of photogenerated electrons is greatly increased. Moreover, the depth of the channel can reduce the residual electrons in the diode, improve the utilization rate of photogenerated electrons, and ultimately improve the full well capacity of the photodiode. However, due to the small size of the vertical gate structure used for small pixels and the obvious load effect when etching silicon (the depth corresponding to large and small sizes will be quite different), the depth of the vertical gate in large areas is smaller than that of normal small sizes, such as Figure 3 and Figure 4 As shown, the vertical gate depth detection of the transfer tube (Tx) cannot be implemented in a normal manner, and the vertical gate depth can only be checked by destructive slicing. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for detecting the vertical gate depth of the transfer tube of a CMOS image sensor, which can effectively monitor the vertical gate depth and realize online monitoring of the transfer tube gate depth of all CMOS image sensors without damaging the silicon wafer.

[0006] To address the above technical issues, the present invention provides a method for detecting the vertical gate depth of a CMOS image sensor transfer tube. The vertical gate polysilicon of the CMOS image sensor transfer tube to be tested includes a flat plate portion and n vertical pillars, where n is a positive integer. The flat plate portion is formed on the surface of a first-type doped epitaxial layer. The n vertical pillars are terminated with the flat plate portion and formed within the first-type doped epitaxial layer. The detection method includes the following steps:

[0007] 1. Detecting the effective electrical thickness (EOT) of the planar gate polysilicon of a reference CMOS image sensor transfer transistor, where the gate polysilicon of the reference CMOS image sensor transfer transistor is formed on the surface of the first type doped epitaxial layer and has the same cross-sectional shape as the flat plate portion of the vertical gate polysilicon of the CMOS image sensor transfer transistor under test;

[0008] Detect the capacitance C of the vertical gate structure of the transfer tube of the CMOS image sensor to be tested ox(VTG) ;

[0009] 2. Calculate the vertical gate depth H of the transfer tube of the CMOS image sensor to be tested,

[0010]

[0011] ε0 is the dielectric constant of vacuum; ε ris the relative dielectric constant; W is the cross-sectional area of ​​the flat plate portion; and w is the cross-sectional perimeter of a vertical column of vertical gate polysilicon.

[0012] Preferably, the cross section of the flat plate portion is rectangular.

[0013] Preferably, the cross section of the flat plate portion is square.

[0014] Preferably, w=2π*r, the vertical column of the vertical gate polysilicon is cylindrical, and r is the cross-sectional radius of the cylindrical vertical column of the vertical gate polysilicon.

[0015] Preferably, n is 7, 8, 9, or 10.

[0016] Preferably, the n vertical pillars are uniformly formed in the first type doped epitaxial layer.

[0017] Preferably, the CMOS image sensor includes a photodiode, a transfer tube, a floating diffusion region, and a reset tube that are adjacent to each other in sequence;

[0018] The photodiode includes a second type of photosensitive doped region formed on top of a first type of doped epitaxial layer;

[0019] A pinning layer of first-type doping is formed on the surface of the second-type photosensitive doping region;

[0020] The floating diffusion region is formed in a well doped with a first type of doping;

[0021] A gate structure of the transfer tube is formed on the top of the first type doped epitaxial layer between the floating diffusion region and the photodiode.

[0022] Preferably, the CMOS image sensor further includes a reset area;

[0023] The gate structure of the reset transistor is formed between the floating diffusion region and the reset region;

[0024] The floating diffusion region and the reset region are both formed in a well doped with a first type of doping;

[0025] The reset region has a second type of doping;

[0026] The reset area is used to be connected to the power supply voltage;

[0027] The gate of the amplifier tube is connected to the floating diffusion region, the source outputs the amplified signal, and the drain is connected to the power supply voltage;

[0028] The selection tube is used to select the amplified signal output by the amplifying tube for output;

[0029] The gate of the selection tube is connected to a selection signal.

[0030] Preferably, the first type is N-type and the second type is P-type; or,

[0031] The first type is P type, and the second type is N type.

[0032] The present invention provides a method for detecting the vertical gate depth of a CMOS image sensor transfer tube. By combining planar and vertical gates of the same layout area, the effective electrical thickness (EOT) of the planar gate polysilicon of a reference CMOS image sensor transfer tube is obtained through a planar test, and the capacitance (C) of the vertical gate structure of the CMOS image sensor transfer tube to be tested is obtained through a vertical test. ox(VTG) , and then calculate the equivalent depth of the vertical gate of the transfer tube of the CMOS image sensor to be tested based on this, effectively monitoring the vertical gate depth. It can realize online monitoring of the transfer tube gate depth of all CMOS image sensors without damaging the silicon wafer, making it easy to timely discover abnormalities in the transfer tube gate depth and effectively monitor the product quality of CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is the basic structure of the 4T CMOS image sensor;

[0035] Figure 2 This is a schematic diagram of electron transfer in a planar gate transfer tube CMOS image sensor after the transfer tube is opened;

[0036] Figure 3 This is a schematic diagram of electron transfer in a small-size vertical gate transfer tube CMOS image sensor after the transfer tube is opened;

[0037] Figure 4 This is a schematic diagram of a large-scale vertical gate transfer tube CMOS image sensor;

[0038] Figure 5 is a schematic cross-sectional view of a planar gate transfer tube;

[0039] Figure 6 It is a three-dimensional schematic diagram of a planar gate transfer tube;

[0040] Figure 7 is a schematic cross-sectional view of a vertical gate transfer tube;

[0041] Figure 8It is a three-dimensional schematic diagram of a vertical gate transfer tube. DETAILED DESCRIPTION

[0042] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0043] Example 1

[0044] like Figure 1 As shown in FIG, a method for detecting the vertical gate depth of a CMOS image sensor transfer tube is Figure 7 、 Figure 8 As shown, the vertical gate polysilicon of the transfer tube of the CMOS image sensor to be tested includes a flat plate portion and n vertical columns, where n is a positive integer; the flat plate portion is formed on the surface of the first type doped epitaxial layer; the n vertical columns are terminated with the flat plate portion and formed in the first type doped epitaxial layer; the testing method includes the following steps:

[0045] 1. Detect the effective electrical thickness EOT of the planar gate polysilicon of the reference CMOS image sensor transfer tube, such as Figure 5 、 Figure 6 As shown, the gate polysilicon of the reference CMOS image sensor transfer tube is formed on the surface of the first type doped epitaxial layer, and has the same cross-sectional shape as the flat plate portion of the vertical gate polysilicon of the CMOS image sensor transfer tube to be tested;

[0046] Detect the capacitance C of the vertical gate structure of the transfer tube of the CMOS image sensor to be tested ox(VTG) ;

[0047] 2. Calculate the vertical gate depth H of the transfer tube of the CMOS image sensor to be tested,

[0048]

[0049] ε0 is the dielectric constant of vacuum; ε r is the relative dielectric constant; W is the cross-sectional area of ​​the flat plate portion; and w is the cross-sectional perimeter of a vertical column of vertical gate polysilicon.

[0050] Refer to the effective electrical thickness EOT of the transfer tube gate of the CMOS image sensor, which can be easily obtained through testing;

[0051] The capacitance C of the vertical gate structure of the transfer tube of the CMOS image sensor to be tested ox(VTG) , which can be easily obtained through testing;

[0052] Stotal =W+w*H*n, (Formula 2);

[0053]

[0054] S total The sum of the surface areas of the gate polysilicon plate portion and each vertical column contacting the epitaxial layer of the transfer tube of the CMOS image sensor to be tested;

[0055] C ox(bulk) A silicon oxide capacitor with a rectangular cross-section gate polysilicon;

[0056] According to equations (2), (3), and (4), taking w = 2π*r, we can obtain (Equation 1).

[0057] The method for detecting the vertical gate depth of a CMOS image sensor transfer tube in Example 1 combines planar and vertical gates of the same layout area, obtains the effective electrical thickness (EOT) of the planar gate polysilicon of a reference CMOS image sensor transfer tube through a planar test, and obtains the capacitance (C) of the vertical gate structure of the CMOS image sensor transfer tube to be tested through a vertical test. ox(VTG) , and then calculate the equivalent depth of the vertical gate of the transfer tube of the CMOS image sensor to be tested based on this, effectively monitoring the vertical gate depth. It can realize online monitoring of the transfer tube gate depth of all CMOS image sensors without damaging the silicon wafer, making it easy to timely discover abnormalities in the transfer tube gate depth and effectively monitor the product quality of CMOS image sensors.

[0058] Example 2

[0059] According to the method for detecting the vertical gate depth of the transfer tube of a CMOS image sensor according to the first embodiment, the cross section of the flat plate portion is rectangular.

[0060] Preferably, the cross section of the flat plate portion is square.

[0061] Preferably, w=2π*r, the vertical column of the vertical gate polysilicon is cylindrical, and r is the cross-sectional radius of the cylindrical vertical column of the vertical gate polysilicon.

[0062] Preferably, n is 7, 8, 9, or 10.

[0063] Preferably, the n vertical pillars are uniformly formed in the first type doped epitaxial layer.

[0064] Example 3

[0065] Based on the vertical gate depth detection method of the CMOS image sensor transfer tube of embodiment 1, Figure 1As shown, the CMOS image sensor includes a photodiode (PD) 10, a transfer transistor (Tx) 11, a floating diffusion region (FD) 12, and a reset transistor (RST) 13 that are adjacent to each other in sequence;

[0066] The photodiode 10 includes a second type of photosensitive doped region 101 formed on top of the first type doped epitaxial layer 1;

[0067] A first-type doped pinning layer 102 is formed on the surface of the second-type photosensitive doping region 101;

[0068] The floating diffusion region 12 is formed in a well 17 with a first type of doping;

[0069] A gate structure of the transfer tube 11 is formed on the top of the first type doped epitaxial layer 1 between the floating diffusion region 12 and the photodiode 10 .

[0070] Preferably, the CMOS image sensor further includes a reset area 16;

[0071] The gate structure of the reset transistor 13 is formed between the floating diffusion region 12 and the reset region 16;

[0072] The floating diffusion region 12 and the reset region 16 are both formed in a well 17 doped with the first type of doping;

[0073] The reset region 16 has a second type of doping;

[0074] The reset area 16 is used to connect to the power supply voltage VDD;

[0075] The gate of the amplifier tube 14 is connected to the floating diffusion region 12, the source outputs the amplified signal, and the drain is connected to the power supply voltage VDD;

[0076] The selection tube 15 is used to select and output the amplified signal output by the amplifying tube 14;

[0077] The gate of the selection transistor 15 is connected to the selection signal Rs.

[0078] Preferably, the first type is N-type and the second type is P-type; or, the first type is P-type and the second type is N-type.

[0079] In the third embodiment of the vertical gate depth detection method for the transfer tube of a CMOS image sensor, when the transfer tube (Tx) 11 is closed for light sensing, the PN junction of the photodiode (PD) 10 captures sunlight to generate electrons and holes. The photogenerated electrons accumulate toward the top under the action of the built-in electric field of the PN junction. When the gate of the transfer tube (Tx) 11 is powered on and turned on, they are transmitted through the surface channel to the floating diffusion region (Floating Diffusion) 12 between the transfer tube (Tx) 11 and the reset tube (RST) 13.

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for detecting the vertical gate depth of a CMOS image sensor transfer tube. The vertical gate polysilicon of the CMOS image sensor transfer tube to be tested comprises a flat plate portion and n vertical pillars, where n is a positive integer. The flat plate portion is formed on the surface of a first-type doped epitaxial layer. The n vertical pillars are terminated by the flat plate portion and formed within the first-type doped epitaxial layer. The method is characterized in that: The detection method includes the following steps:

1. Detecting the effective electrical thickness (EOT) of the planar gate polysilicon of a reference CMOS image sensor transfer transistor, where the gate polysilicon of the reference CMOS image sensor transfer transistor is formed on the surface of the first type doped epitaxial layer and has the same cross-sectional shape as the flat plate portion of the vertical gate polysilicon of the CMOS image sensor transfer transistor under test; Detect the capacitance C of the vertical gate structure of the transfer tube of the CMOS image sensor to be tested ox(VTG) ; 2. Calculate the vertical gate depth H of the transfer tube of the CMOS image sensor to be tested, ε0 is the dielectric constant of vacuum; ε r is the relative dielectric constant; W is the cross-sectional area of ​​the flat plate portion; and w is the cross-sectional perimeter of a vertical column of vertical gate polysilicon.

2. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: The cross section of the flat plate portion is rectangular.

3. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: The cross section of the flat plate portion is square.

4. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: w=2π*r, the vertical column of the vertical gate polysilicon is cylindrical, and r is the cross-sectional radius of the cylindrical vertical column of the vertical gate polysilicon.

5. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: n is 7, 8, 9, or 10.

6. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: N vertical columns are uniformly formed in the first type doped epitaxial layer.

7. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 1, wherein: The CMOS image sensor includes a photodiode, a transfer tube, a floating diffusion area, and a reset tube that are adjacent to each other in sequence; The photodiode includes a second type of photosensitive doped region formed on top of a first type of doped epitaxial layer; A pinning layer of first-type doping is formed on the surface of the second-type photosensitive doping region; The floating diffusion region is formed in a well doped with a first type of doping; A gate structure of the transfer tube is formed on the top of the first type doped epitaxial layer between the floating diffusion region and the photodiode.

8. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 7, wherein: The CMOS image sensor further includes a reset area; The gate structure of the reset transistor is formed between the floating diffusion region and the reset region; The floating diffusion region and the reset region are both formed in a well doped with a first type of doping; The reset region has a second type of doping; The reset area is used to be connected to the power supply voltage; The gate of the amplifier tube is connected to the floating diffusion region, the source outputs the amplified signal, and the drain is connected to the power supply voltage; The selection tube is used to select the amplified signal output by the amplifying tube for output; The gate of the selection tube is connected to a selection signal.

9. The method for detecting the vertical gate depth of a CMOS image sensor transfer tube according to claim 8, wherein: The first type is N-type and the second type is P-type; or, The first type is P type, and the second type is N type.

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