Vehicle interface data identification device, method and chip

Abstract

The present application provides a vehicle interface data identification device, which may include: multiple groups of signal transceivers, multiple groups of signal controllers, and a logic control module connected to each of the multiple groups of signal controllers; the first group of signal transceivers is used to transmit the first digital signal to the first group of signal controllers when receiving the first digital signal; the first group of signal controllers is used to transmit the first digital signal to the logic control module; the logic control module is used to determine the first pin of the vehicle interface corresponding to the first digital signal after identifying the first digital signal. The embodiment of the present invention can effectively and quickly identify the bus type connected to each pin of the vehicle interface, which is conducive to improving the diagnostic efficiency of the diagnostic equipment.

Description

Technical Field

[0001] The present application relates to the field of automobile detection technology, and in particular to a vehicle interface data recognition device, method and chip. Background Art

[0002] With the rapid development of automobile technology, in order to adapt to technological development and meet user needs, various automotive diagnostic equipment has emerged in an endless stream. In order to accurately diagnose vehicle faults, general diagnostic equipment needs to be connected to the vehicle interface through a specific connection line to obtain the required vehicle data for the next step of diagnosis. The interface usually connected to the diagnostic equipment is the On Board Diagnostics (OBD) interface. Generally, the OBD II interface of a car will have 16 pins. In addition to 3 pins involving the body ground, signal ground and power supply, the remaining pins also involve the Controller Area Network (CAN) line, K line, J1850 line, etc. Vehicles produced by different manufacturers, or different models of the same manufacturer, may have different definitions and functions of each pin of the OBD interface.

[0003] Before the diagnosis begins, the diagnostic device needs to determine the bus type connected to each pin in a certain way. The current solution needs to determine the bus type corresponding to the pin based on the bus characteristics such as the signal parameters and baud rate output by the pin before continuing the subsequent operation. The recognition efficiency of this solution is low, the processing flow is lengthy, and the adaptability is weak.

[0004] Therefore, how to efficiently and conveniently identify the signals of different pins of the vehicle interface is a problem that needs to be solved urgently in this application. Summary of the invention

[0005] The present application provides a vehicle interface data identification device, method and chip, which can effectively and quickly identify the bus type connected to each pin of the vehicle interface, which is beneficial to improving the diagnostic efficiency of the diagnostic equipment.

[0006] In the first aspect, an embodiment of the present invention provides a vehicle interface data identification device, which may include: multiple groups of signal transceivers, multiple groups of signal controllers, and a logic control module connected to each group of signal controllers in the multiple groups of signal controllers; the type of digital signals received by each group of signal transceivers in the multiple groups of signal transceivers is different and unique; a group of signal transceivers in the multiple groups of signal transceivers corresponds to a group of controllers in the multiple groups of signal controllers; the multiple groups of signal transceivers include a first group of signal transceivers; the multiple groups of signal controllers include a first group of signal controllers corresponding to the first group of signal transceivers; the first group of signal transceivers is used to transmit the first digital signal to the first group of signal controllers when receiving the first digital signal; the first group of signal controllers is used to transmit the first digital signal to the logic control module; the logic control module is used to determine the first pin of the vehicle interface corresponding to the first digital signal after identifying the first digital signal.

[0007] In an embodiment of the present invention, the configuration of multiple groups of signal transceivers and multiple groups of signal controllers can cover all bus types that may be connected to each pin of the OBD II interface. Each group of signal transceivers has a corresponding signal controller connected to it, and can normally receive and send signals. More importantly, after receiving a certain type of signal, the signal type that can be passed by each group of signal transceivers is unique, so that the signal type and the corresponding OBD interface pin number (different pin numbers correspond to unique pins / pins / pins of the vehicle interface) can be determined by the logic control module. For example, if it is CAN signal data, the data passes through the K transceiver, and the back-end controller corresponding to the K transceiver cannot receive the data; while the data can pass through the CAN transceiver, so that the CAN controller receives the CAN signal data, which is convenient for the logic control module to identify the signal.

[0008] In a possible implementation, the device also includes multiple groups of data selectors (or multiplexers); one group of signal controllers in the multiple groups of signal controllers corresponds to one group of data selectors in the multiple groups of data selectors; the multiple groups of data selectors include a first group of data selectors corresponding to the first group of signal controllers; the first group of signal controllers includes a multi-channel signal controller; the first group of data selectors is used to select the second digital signal output by the first signal controller in the multi-channel signal controller when the logic control module sends a second digital signal to the multiple groups of signal controllers.

[0009] In a possible implementation, the device also includes a first-in-first-out memory FIFO (i.e., a multiplexer) connected to the multiple groups of signal transceivers; the first-in-first-out memory FIFO is used to: receive the first digital signal in a receiving order, and / or, send the first digital signal to the multiple groups of signal transceivers in a sending order.

[0010] In one possible implementation, the device also includes an analog-to-digital converter ADC connected to the multiplexer; the ADC is used to: when the device is connected to the vehicle interface, receive a first analog signal sent by the vehicle interface; convert the received first analog signal into the first digital signal; and send the first digital signal to the multiplexer.

[0011] In a possible implementation, when the vehicle interface identification device establishes a connection with the vehicle via a wireless connection, the ADC may convert a first analog signal received by the device into a first digital signal; and then send the first digital signal to a first-in-first-out memory.

[0012] In a possible implementation manner, each group of signal transceivers includes one or more signal transceivers; and each group of signal controllers includes one or more signal controllers.

[0013] In a possible implementation, the device further includes a bus connected to the logic control module, and a processor connected to the bus; the processor is configured to communicate with the logic control module through the bus.

[0014] In one possible implementation, the device also includes a bus transceiver connected to the multiple groups of data selectors; the bus transceiver is used to determine the corresponding second pin of the vehicle interface according to the second digital signal when the logic control module outputs a second digital signal; convert the second digital signal into a corresponding second analog signal; and send the second analog signal to the second pin.

[0015] In a possible implementation manner, the first group of signal transceivers are further configured to: when receiving a signal other than the first digital signal, stop transmitting signals to the first group of signal controllers.

[0016] In one possible implementation, the device also includes an analog switch connected to the ADC, and a sample-and-hold circuit connected to the analog switch; the sample-and-hold circuit is also connected to the vehicle interface, and is used to receive and hold multiple analog signals sent by the vehicle interface; the analog switch is used to select some of the multiple analog signals according to an analog switch switching signal, and send the some analog signals to the ADC.

[0017] In the second aspect, an embodiment of the present invention provides a vehicle interface data identification method, which may include: when receiving a first digital signal, transmitting the first digital signal to a first group of signal controllers in a plurality of signal controllers through a first group of signal transceivers in a plurality of signal transceivers; each group of signal transceivers in the plurality of signal transceivers receives a different and unique type of digital signal; a group of signal transceivers in the plurality of signal transceivers corresponds to a group of controllers in the plurality of signal controllers; transmitting the first digital signal to a logic control module through the first group of signal controllers; after identifying the first digital signal, determining a first interface pin corresponding to the first digital signal through the logic control module.

[0018] In a possible implementation manner, the method further includes: receiving the first digital signal in a receiving order through a multiplexer, and / or sending the first digital signal to the multiple groups of signal transceivers in a sending order through a multiplexer.

[0019] In a possible implementation manner, the method further includes: converting the received first analog signal into the first digital signal through an analog-to-digital converter ADC; and sending the first digital signal to the multiplexer.

[0020] In a possible implementation manner, each group of signal transceivers includes one or more signal transceivers; and each group of signal controllers includes one or more signal controllers.

[0021] In a possible implementation manner, the method further includes: communicating with a logic control module through a processor and a bus.

[0022] In one possible implementation, the method also includes: when the logic control module sends a second digital signal to the multiple groups of signal controllers, selecting the second digital signal output by the first signal controller of the multiple signal controllers in the first group of signal controllers through the first group of data selectors; wherein, a group of signal controllers in the multiple groups of signal controllers corresponds to a group of data selectors in the multiple groups of data selectors; and the multiple groups of data selectors include a first group of data selectors corresponding to the first group of signal controllers.

[0023] In one possible implementation, the method also includes: when the logic control module outputs a second digital signal, determining the corresponding second pin of the vehicle interface according to the second digital signal through a bus transceiver; converting the second digital signal into a corresponding second analog signal through a bus transceiver; and sending the second analog signal to the second pin through a bus transceiver.

[0024] In a possible implementation manner, the method further includes: when receiving a signal other than the first digital signal, causing the first group of signal transceivers to stop transmitting signals to the first group of signal controllers.

[0025] In a third aspect, an embodiment of the present invention provides a vehicle interface data identification chip, which may include any one of the devices described in the first aspect; the aforementioned chip includes a processor and an interface, which can be used to identify the type of bus connected to the interface pin of the vehicle OBD.

[0026] In a fourth aspect, an embodiment of the present invention provides a vehicle interface data identification device, which may include the device in the aforementioned first aspect or a chip having the aforementioned third aspect built in. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0028] Figure 1 is a schematic diagram of a vehicle interface data recognition scenario provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of the system architecture of a vehicle interface data identification device provided by an embodiment of the present invention;

[0030] Figure 3 is a structural schematic diagram of a vehicle interface identification device provided by an embodiment of the present invention;

[0031] Figure 4 It is a schematic diagram of the structure of an input module of a vehicle interface identification device provided by an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of an interface signal conversion transmission process provided by an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of a specific interface signal conversion transmission process provided by an embodiment of the present invention;

[0034] Figure 7 It is a schematic diagram of the structure of an output module of a vehicle interface identification device provided by an embodiment of the present invention;

[0035] Figure 8 It is a structural schematic diagram of a measurement function of a vehicle interface identification device provided by an embodiment of the present invention;

[0036] Fig. 9 It is a flow chart of a vehicle interface identification method provided by an embodiment of the present invention;

[0037] Fig.10 is a schematic diagram of the architecture of a chip provided by an embodiment of the present invention;

[0038] Fig.11 It is a structural schematic diagram of a device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0040] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0041] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] First, some terms in the embodiments of the present invention are explained to facilitate understanding by those skilled in the art.

[0043] (1) On Board Diagnostics (OBD) monitors the exhaust gas level of the vehicle at any time according to the engine's operating status. Once the exhaust gas level exceeds the standard, an alarm will be issued immediately. When a system fault occurs, the Malfunction Indicator Lamp (MIL) or the Check Engine Warning Light will light up, and the Powertrain Control Module (PCM) will store the fault information in the memory. The fault code can be read from the PCM through a certain program. Based on the fault code prompt, maintenance personnel can quickly and accurately determine the nature and location of the fault. One of the mature functions of OBDⅡ is that when the system lights up the fault light, it records the data of all sensors and drivers, which can meet the needs of diagnosis and maintenance to the greatest extent. The computer capacity of this system has not only been greatly improved, but it can also track the damage of components. OBD monitors the engine, catalytic converter, particulate filter, oxygen sensor, emission control system, fuel system, exhaust gas recirculation system (EGR) and other systems and components in real time.

[0044] (2) Analog-to-Digital Converter (ADC) is a device that converts continuously changing analog signals into discrete digital signals. Real-world analog signals, such as temperature, pressure, sound, or images, need to be converted into digital forms that are easier to store, process, and transmit.

[0045] (3) First Input First Output (FIFO) memory is divided into a write-only area and a read-only area. The read and write operations can be performed asynchronously. The data written in the write area is read out from the read area in the order in which it was written. This is similar to a buffer that absorbs the speed difference between the write and read ends. Computer serial ports generally also have FIFO buffers.

[0046] (4) Advanced eXtensible Interface (AXI) is a bus protocol that is an on-chip bus for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, supporting unaligned data transmission. In burst transmission, only the first address is required. Separate read and write data channels are provided, and outstanding transmission access and out-of-order access are supported, making timing closure easier. AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex system on chip (SoC) design.

[0047] (5) CAN local area network controller, referred to as CAN controller, is a serial data communication bus developed to solve the data exchange between many measurement and control components in modern automobiles. The CAN controller is used to convert the messages (messages) to be sent and received into CAN frames that comply with the CAN specification, and exchange information on the CAN-bus through the CAN transceiver.

[0048] (6) Sample-and-hold circuit (sample / hold), also known as sample-and-hold amplifier. When performing A / D conversion on an analog signal, a certain conversion time is required. During this conversion time, the analog signal must remain basically unchanged to ensure conversion accuracy. The sample-and-hold circuit is a circuit that implements this function.

[0049] The vehicle interface data identification device involved in the present application is further described in detail below in conjunction with the accompanying drawings.

[0050] See also Figure 1 , Figure 1 is a schematic diagram of a vehicle interface data recognition scenario provided by an embodiment of the present invention; Figure 1 As shown, the scenario includes a vehicle, a diagnostic device and a vehicle identification device; the vehicle can be connected to the vehicle identification device through a 16-pin interface and a data cable; the vehicle identification device can be connected to the diagnostic device through Bluetooth or a wired method. Among them, the vehicle may include one or more vehicles to be diagnosed or tested; the vehicle in this application scenario is illustrated by taking a vehicle shown in the figure as an example, and the vehicle has a 16-pin OBD interface and can be connected to the vehicle identification device by wire. Alternatively, the vehicle identification device can establish communication with the vehicle system through a wireless connection such as wifi. The specific vehicle information is not limited in the embodiments of the present invention.

[0051] The diagnostic device can be connected to the vehicle identification device in a wired or wireless manner. According to the user's specific diagnostic needs and judgment, a diagnostic device connected to the vehicle identification device can be selected from a plurality of alternative diagnostic devices. Figure 1 A connected diagnostic device is used as an example for explanation. The diagnostic device provides the required diagnostic service to the user through the vehicle information received by the vehicle identification device.

[0052] The vehicle identification device can be an independent device, or two sub-devices with independent functions; wherein the two sub-devices are used in conjunction with each other and exchange and process data with each other through a network. Optionally, the sub-devices can be the same in hardware structure and design, but can differ in software configuration, or the tool types can be distinguished by the usage permissions opened by the tools.

[0053] It should be noted that this application scenario is only an exemplary scenario description; the application scenarios involved in the embodiments of the present invention include but are not limited to the above application scenarios.

[0054] See also Figure 2 , Figure 2 is a schematic diagram of the system architecture of a vehicle interface data identification device provided by an embodiment of the present invention; Figure 2 As shown, the system architecture may include a first module 21 and a second module 22. Specifically, the first module 21 may include a processor 211 and a memory 212, and the processor 211 and the memory 212 may be connected via a second bus 213; the second module 22 may include one or more peripherals ( Figure 2 Take the peripherals A211, B222 and C223 as examples; the peripherals may be custom peripherals or standard peripherals; the embodiment of the present invention does not specifically limit the number and type of peripherals). The peripherals A221, B222 and C223 are connected to the first bus 224; the first bus 224 may be an Advanced eXtensible Interface (AXI) bus; optionally, the second bus 213 and the first bus 224 may be the same type of bus or different types of buses. The first module 21 is interconnected with the second module 22 via the AXI bus.

[0055] When the system architecture is applied to the ZYNQ chip, the first module 21 may be a processing system (PS), and the second module 22 may be a programmable logic device (PL). The first module 21 and the second module 22 are connected via a bus.

[0056] It should be noted that the system architecture is an example system architecture of a vehicle interface data identification device involved in an embodiment of the present invention; the embodiment of the present invention includes but is not limited to the above system architecture.

[0057] Based on the system architecture mentioned above, the PL side of a specific vehicle interface identification device involved in the embodiment of the present invention is described below. In the embodiment of the present invention, the vehicle interface takes the OBD interface as an example, and the hardware modules and connection methods involved in the device are all exemplary examples and descriptions.

[0058] See also Figure 3 , Figure 3 is a schematic diagram of the structure of a vehicle interface identification device provided by an embodiment of the present invention; Figure 3As shown, the components of the device belong to the peripheral part of the second module, and may specifically include an analog-to-digital converter (ADC) 31, a first-in first-out memory (FIFO) 32, a plurality of signal transceivers (such as Figure 3 As shown, it may include a CAN transceiver group 33, a SCAN transceiver group 34, a K line transceiver group 35, a LIN line transceiver group 36, a J1850 transceiver group 37), and multiple groups of signal controllers (such as Figure 3 As shown, it may include a CAN controller group 38, a K line controller group 39, an L line controller group 40, a J1850 controller group 41) and a logic control module 30. The logic control module 30 is connected to each of the multiple groups of signal controllers; for example, the logic control module 30 is connected to the CAN controller group 38 to receive the signal sent by the CAN control group 38.

[0059] Each of the aforementioned multiple groups of signal transceivers receives a different type of digital signal, and one group of signal transceivers in the multiple groups of signal transceivers corresponds to a group of controllers of the same type in the multiple groups of signal controllers; for example, the CAN transceiver group 33 can receive CAN signal data and send the CAN signal data to the back-end CAN controller group 38. The CAN transceiver group 33 corresponds to the CAN controller group 38; the K-line transceiver group 35 corresponds to the K-line controller group 39; and the LIN line transceiver group 36 corresponds to the LIN line controller group 40. In particular, both the CAN transceiver group 33 and the SCAN transceiver group 34 can correspond to the CAN controller group 38.

[0060] Optionally, the first group of signal transceivers is also used to stop transmitting signals to the first group of signal controllers when receiving a signal other than the first digital signal. For example, when the CAN transceiver receives a K-line signal, it cannot send the K-line signal to the back-end CAN controller. Optionally, each group of transceiver groups may include one or more signal transceivers; for example, the CAN transceiver group may include multiple CAN transceivers. The embodiment of the present invention does not limit the number of transceivers in each group and the type of each group of transceivers.

[0061] In the embodiment of the present invention, the K-line transceiver group 35 is used as the first group of signal transceivers as an example; and the K-line transceiver group 35 has only one transceiver, and the K-line controller group 39 has only one controller, and the K-line transceiver corresponds to the K-line controller. After the vehicle interface identification device is connected to the interface (hereinafter, the OBD II interface is taken as an example), ADC31 selects some of the 13 pins connected to the OBD interface to access ADC31 according to the analog switch switching signal. Optionally, the analog switch switching signal is sent by the logic control module 30 to ADC31; the signal is used to instruct ADC31 to switch the access to the pin signal.

[0062] The digital signal of ADC31 is sent to FIFO32 and sent out from FIFO32 in a first-in-first-out order, and is received by each transceiver group at the back end. Among them, the K-line signal transceiver 35 is used to transmit the first digital signal to the first group of signal controllers (i.e., K-line controllers) when receiving the first digital signal (i.e., K-line signal); the first group of signal controllers is used to transmit the first digital signal to the logic control module 30; the logic control module 30 is used to determine the first interface pin corresponding to the first digital signal after identifying the first digital signal. After the K-line signal is sent to all signal transceiver groups, only the K-line transceiver group 35 can pass the K-line signal. Then the K-line signal passes through the K-line controller in the K-line controller group 39 and is sent to the logic control module 30. When the logic control module 30 determines that some of the pins of the OBDII are connected to the device, it determines the number of the OBDII pin where the K-line signal source is located according to the received K-line signal.

[0063] Optionally, after receiving the first digital signal in a receiving order, the FIFO memory 32 sends the first digital signal to the multiple groups of signal transceivers in a sending order. Optionally, the ADC 31 converts the first analog signal received from the data line pin into the first digital signal; and sends the first digital signal to the FIFO memory 32. Optionally, each group of signal transceivers includes one or more signal transceivers; each group of signal controllers includes one or more signal controllers.

[0064] In one possible implementation, FIFO, multiple transceiver groups (such as CAN transceiver group, SCAN transceiver group, K-line transceiver group, etc.), corresponding multiple CAN controller groups (such as CAN controller group, K-line controller group) and logic control module are integrated in the chip (such as ZYNQ7020 chip); while the analog-to-digital converter ADC is an independent device outside the chip. Or Figure 3 All the devices shown can be integrated into a chip.

[0065] In an embodiment of the present invention, the configuration of multiple groups of signal transceivers and multiple groups of signal controllers can cover all bus types that may be connected to each pin of the OBD II interface. Each group of signal transceivers has a corresponding signal controller connected to it, and can normally receive and send signals. More importantly, after receiving a certain type of signal, the signal type that can be passed by each group of signal transceivers is unique, so that the signal type and the corresponding OBD interface pin number can be determined by the logic control module. For example, if it is CAN signal data, the data passes through the K transceiver, and the back-end controller corresponding to the K transceiver cannot receive the data; while the data can pass through the CAN transceiver, so that the CAN controller receives the CAN signal data, which is convenient for the logic control module to identify the signal.

[0066] A vehicle interface identification device according to an embodiment of the present invention is described above. The following further describes the multiple transceiver groups and controller groups involved therein.

[0067] See also Figure 4 , Figure 4 1 is a schematic diagram of the structure of an input module of a vehicle interface identification device provided by an embodiment of the present invention; wherein the analog-to-digital converter ADC is an off-chip device independent of the chip 2. Figure 4 As shown, in the input module (i.e., RX module), each transceiver group may include multiple signal transceivers, for example, the LIN line transceiver group 36 may include LIN line transceiver 0, LIN line transceiver 1, and LIN line transceiver 2, etc. Each group of signal controllers may include multiple signal controllers, for example, the LIN line controller group 40 corresponding to the LIN line transceiver group 36 includes LIN line controller 0, LIN line controller 1, LIN line controller 2, etc., wherein LIN line controller 0 corresponds to LIN line transceiver 0, that is, LIN line transceiver 0 can send data to LIN line controller 0, and LIN line controller 0 can send data to LIN line transceiver 0. For the connection correspondence between transceivers and controllers of other signal types, please refer to this description and will not be repeated here. Further optionally, the logic control module may be MARST.

[0068] For example, after MARST switches the pin of the signal control part interface through the analog switch to access ADC31, the K-line digital signal passes through FIFO32, is received by K-line transceiver 1, and is sent to K-line controller 1. K-line controller 1 sends the K-line digital signal to MARST; MARST determines the number of the OBD interface corresponding to the signal based on the K-line digital signal.

[0069] The above describes the input module involved in the embodiment of the present invention. The following describes the vehicle interface signal conversion and transmission process involved in the embodiment of the present invention.

[0070] See also Figure 5 , Figure 5 FIG. 1 is a schematic diagram of an interface signal conversion transmission process provided by an embodiment of the present invention; Figure 5 As shown, the process involves chip 2, analog-to-digital converter 31, differential driver 51, analog switch 52, sampling and holding circuit 53 and OBD interface 1. Some pins of the OBD interface can be connected to the vehicle interface identification device through a connecting line. The vehicle signal is sent from the pins of the OBD interface to the sampling and holding circuit, and some or all of the signals are selected by the analog switch to be transmitted to the differential driver. The differential driver converts the received ordinary signal into a differential signal and transmits the differential signal to the analog-to-digital converter. The analog-to-digital converter interacts with the chip through the signal channel / channel. Optionally, the chip controls which pins in the OBD interface are connected to the chip by sending an analog switch switching signal to the analog switch. It can be understood that the differential driver is used in conjunction with the analog-to-digital converter. Optionally, the analog-to-digital converter can directly receive and process the signal of the analog switch, so the aforementioned differential driver is not a necessary component.

[0071] exist Figure 5 Based on the device composition shown in the figure, examples are given in combination with specific device composition. Figure 6 , Figure 6 FIG. 1 is a schematic diagram of a specific interface signal conversion transmission process provided by an embodiment of the present invention; Figure 6 As shown, chip 2 can be ZYNQ7020; analog-to-digital converter 31 can be AD9288; differential driver 51 can include a first differential driver and a second differential driver (both can be AD8137); analog switch 52 can be ADG707; sampling and holding circuit 53 can include multiple sampling and holding circuits corresponding to multiple OBD pins. OBD2-OBD13 in the OBD interface can output valid signals for chip detection; the sampling and holding circuits connected to OBD2-OBD13 can include sampling and holding circuit 2, sampling and holding circuit 3, ..., sampling and holding circuit 13 shown in the figure. Each OBD pin sends a signal to ADG707 through the corresponding sampling and holding circuit; after being selected by ADG707, the signal is sent to AD9288 through two AD8137s according to the preset transmission rules, and finally transmitted to chip ZYNQ7020.

[0072] The above describes the function of the device for identifying the vehicle interface according to the embodiment of the present invention. The following describes the signal output function of the device.

[0073] See also Figure 7 , Figure 7 is a schematic diagram of the output module structure of a vehicle interface identification device provided by an embodiment of the present invention; Figure 7 As shown, in the output module (ie, TX module), a bus physical transceiver (or bus transceiver) 50, multiple groups of data selectors (specifically, CAN data selector 42, K line data selector 43, LIN line data selector 44, J1850 data selector 45), multiple groups of signal controllers and logic control module 30 may be included. One group of signal controllers in the multiple groups of signal controllers corresponds to one group of data selectors in the multiple groups of data selectors; for example, J1850 data selector 45 corresponds to J1850 controller group 41, and J1850 data selector 45 may select a controller of a certain path in J1850 controller group 45 (such as J1850 controller 3) according to the specific data transmission situation.

[0074] Among them, the bus physical transceiver 50 integrates a multifunctional multi-channel transceiver; optionally, the bus physical transceiver 50 can be a chip with the aforementioned functions. Specifically, the bus physical transceiver 50 shown in the figure integrates a CAN transceiver (including a CAN0 transceiver 505 and a CAN1 transceiver 504), a K line transceiver 501, a LIN line transceiver 502, and a J1850 transceiver 503. Optionally, the bus physical transceiver 50 can also include other types of transceivers in addition to the above transceivers; the embodiment of the present invention does not limit this. It can be understood that since there are two CAN signal data on the OBDII, two CAN transceivers are generally provided.

[0075] MARST determines the number of the OBDII pin where the signal source is located based on the input signal RX, and controls the bus physical transceiver to switch the OBDII pin to output the signal to the same as the RX signal source, ensuring that data reception and transmission are on the same set of CAN signals. Among them, after receiving the digital signal output by the logic control module, the bus physical transceiver converts the digital signal into an analog signal of the corresponding protocol format through the built-in transceiver. Optionally, the bus physical transceiver can switch the output signal to any OBDII pin. The bus physical transceiver supports pin switching internally. For example, the CAN controller data is output to its CAN transceiver. It can output the TX data (i.e., output data) of the transceiver to any pin on the OBDII through programming.

[0076] In combination with the reception and identification of the K-line signal in the aforementioned embodiment, the feedback output process of the K-line signal is described below in combination with the device part of the embodiment of the present invention. After identifying the K-line signal, the logic control module sends a feedback second digital signal (K-line feedback signal) to the K-line controller 0 under certain conditions or instructions. The first group of data selectors (corresponding to the K-line data selector) is used to select the second digital signal output by the first signal controller (corresponding to the K-line controller 0) in the multi-channel signal controller. The bus transceiver is used to determine the corresponding second pin of the vehicle interface according to the second digital signal when the logic control module outputs the second digital signal; convert the second digital signal into a corresponding second analog signal; and send the second analog signal to the second pin.

[0077] Optionally, the device interface or chip interface involved in the embodiments of the present invention also supports general-purpose input / output (GPIO) programming.

[0078] The above describes the identification interface pin and output signal functions of the device involved in the embodiment of the present invention. The following describes a signal measurement function of the aforementioned device.

[0079] See also Figure 8 , Figure 8 is a structural diagram of a measurement function of a vehicle interface identification device provided by an embodiment of the present invention; Figure 8 As shown, the modules involved in the signal measurement function (such as oscilloscope function) include analog-to-digital converter ADC31, first-in-first-out memory FIFO32, logic control module 30 and signal input measurement module 60. Among them, ADC31 is connected to FIFO32 to send the signal to FIFO32; FIFO32 is connected to logic control module 30 to send the two-channel waveform data to logic control module 30; logic control module 30 is connected to signal input measurement module 60, and logic control module 30 is used to select signal current or control range switching; signal input measurement module 60 is connected to ADC31 to feed back data-related results to ADC31.

[0080] Next, an embodiment of the method of the present invention is described. Fig. 9 , Fig. 9 It is a flow chart of a vehicle interface identification method provided by an embodiment of the present invention; the method embodiment takes a C-end tool as an example of the execution subject and is explained from the C-end tool side, which may specifically include steps S701-S703.

[0081] Step S701: when a first digital signal is received, the first digital signal is transmitted to a first signal controller in a plurality of signal controllers through a first signal transceiver in a plurality of signal transceivers.

[0082] Specifically, each group of signal transceivers in the multiple groups of signal transceivers receives a different type of digital signal and each group of signal transceivers receives, passes and sends a unique type of digital signal; a group of signal transceivers in the multiple groups of signal transceivers corresponds to a group of controllers in the multiple groups of signal controllers.

[0083] Step S702: Transmit the first digital signal to a logic control module through the first group of signal controllers.

[0084] Step S703: after identifying the first digital signal, determining a first interface pin corresponding to the first digital signal through the logic control module.

[0085] In a possible implementation manner, the method further includes: receiving the first digital signal in a receiving order through a multiplexer, and / or sending the first digital signal to the multiple groups of signal transceivers in a sending order through a multiplexer.

[0086] In a possible implementation manner, the method further includes: converting the received first analog signal into the first digital signal through an analog-to-digital converter ADC; and sending the first digital signal to the multiplexer.

[0087] In a possible implementation manner, each group of signal transceivers includes one or more signal transceivers; and each group of signal controllers includes one or more signal controllers.

[0088] In a possible implementation, the method further includes: communicating with a logic control module via a processor and a bus.

[0089] In one possible implementation, the method also includes: when the logic control module sends a second digital signal to the multiple groups of signal controllers, selecting the second digital signal output by the first signal controller of the multiple signal controllers in the first group of signal controllers through the first group of data selectors; wherein, a group of signal controllers in the multiple groups of signal controllers corresponds to a group of data selectors in the multiple groups of data selectors; and the multiple groups of data selectors include a first group of data selectors corresponding to the first group of signal controllers.

[0090] In one possible implementation, the method also includes: when the logic control module outputs a second digital signal, determining the corresponding second pin of the vehicle interface according to the second digital signal through a bus transceiver; converting the second digital signal into a corresponding second analog signal through a bus transceiver; and sending the second analog signal to the second pin through a bus transceiver.

[0091] In a possible implementation manner, the method further includes: when receiving a signal other than the first digital signal, causing the first group of signal transceivers to stop transmitting signals to the first group of signal controllers.

[0092] It should be noted that the relevant description in the embodiment of the method can refer to the description of the device function and structure in the aforementioned device embodiment, which will not be repeated here.

[0093] See also Fig.10 , Fig.10 is a schematic diagram of the architecture of a chip provided by an embodiment of the present invention; Fig.10 As shown, the chip architecture includes a processor and an interface. The processor may include the above Figure 2-Figure 6 The device structure of any one of the above. The interface is connected to the processor; the interface is used for the chip to interact with other hardware structures or modules. It can be understood that the chip is equipped with Fig.10 The device of the chip shown can realize the signal type of each pin of the vehicle interface (such as the OBD interface).

[0094] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a device provided by an embodiment of the present invention. The aforementioned device can perform interface recognition and signal processing by executing the method in the aforementioned method embodiment. The device 9 may include at least one storage component 901, at least one communication component 902, and at least one processing component 903. In addition, the device may also include common components such as an antenna and a power supply, which will not be described in detail here.

[0095] The storage component 901 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, an optical disc storage (which may include a compressed optical disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory may be independent and connected to the processor via a bus. The memory may also be integrated with the processor.

[0096] The communication component 902 may be used to communicate with other devices or communication networks, such as an upgrade server, a key server, and in-vehicle devices.

[0097] The processing unit 903 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above program.

[0098] Fig.11 When the device shown is used to execute the method in the aforementioned method embodiment, the processing component 903 is used to transmit the first digital signal to the first group signal controller in the multiple groups of signal transceivers when receiving the first digital signal. The first group signal controller transmits the first digital signal to the logic control module. After identifying the first digital signal, the logic control module determines the first interface pin corresponding to the first digital signal.

[0099] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described order of actions, because according to the present invention, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0101] In the several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The units of the above device embodiments may or may not be physically separated, and some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0102] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit. If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0103] Based on such understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and can include several instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., and can be a processor in a computer device) to perform all or part of the steps of the above methods of various embodiments of the present invention. Among them, the aforementioned storage medium can include: U disk, mobile hard disk, disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes. As described above, the above embodiments are only used to illustrate the technical solution of the present invention, rather than to limit it; although the present invention is described in detail with reference to the aforementioned embodiments, ordinary technicians in the field should understand that: it is still possible to modify the technical solutions recorded in the aforementioned embodiments, or to replace some of the technical features therein by equivalent; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A data recognition device for a vehicle interface, characterized in that: include: A plurality of groups of signal transceivers, a plurality of groups of signal controllers and a plurality of groups of data selectors, and a logic control module connected to each of the plurality of groups of signal controllers; The type of digital signal received by each group of signal transceivers in the plurality of groups of signal transceivers is different and unique; A group of signal transceivers in the plurality of groups of signal transceivers corresponds to a group of controllers in the plurality of groups of signal controllers; the plurality of groups of signal transceivers include a first group of signal transceivers; the plurality of groups of signal controllers include a first group of signal controllers corresponding to the first group of signal transceivers; a group of data selectors in the plurality of groups of data selectors corresponds to a group of signal controllers in the plurality of groups of signal controllers; the plurality of groups of data selectors include a first group of data selectors corresponding to the first group of signal controllers; the first group of signal controllers includes a multi-channel signal controller; The first group signal transceiver is used to send the first digital signal to the first group signal controller when receiving the first digital signal; The first group of signal controllers is used to send the first digital signal to the logic control module; The logic control module is used to determine the first pin of the vehicle interface corresponding to the first digital signal after identifying the first digital signal; The first group of data selectors is used to select the second digital signal output by the first signal controller in the multiple signal controllers when the logic control module sends the second digital signal to the multiple signal controllers.

2. The device according to claim 1, characterized in that The device also includes a multiplexer connected to the multiple groups of signal transceivers; The multiplexer is used to: receive the first digital signal in a receiving order, and / or send the first digital signal to the multiple groups of signal transceivers in a sending order.

3. The device according to claim 2, characterized in that The device also includes an analog-to-digital converter ADC connected to the multiplexer; The ADC is used to: when connected to the vehicle interface, receive a first analog signal sent by the vehicle interface; converting the first analog signal into the first digital signal; The first digital signal is sent to the multiplexer.

4. The device according to claim 1, characterized in that The device also includes a bus transceiver connected to the plurality of groups of data selectors; The bus transceiver is used for determining the corresponding second pin of the vehicle interface according to the second digital signal when the logic control module outputs the second digital signal; converting the second digital signal into a corresponding second analog signal; The second analog signal is sent to the second pin.

5. The device according to any one of claims 1 to 4, characterized in that: The first group signal transceiver is further used to stop sending signals to the first group signal controller when receiving a signal other than the first digital signal.

6. The device according to claim 5, characterized in that Each group of signal transceivers includes one or more signal transceivers; each group of signal controllers includes one or more signal controllers.

7. The device according to claim 3, characterized in that The device also includes an analog switch connected to the ADC, and a sample-and-hold circuit connected to the analog switch; The sample-and-hold circuit is used to receive and hold a plurality of analog signals sent by the vehicle interface; The analog switch is used to select part of the multiple analog signals according to the analog switch switching signal, and send the part of the analog signals to the ADC.

8. A vehicle interface data identification method, characterized in that: include: When receiving the first digital signal, the first digital signal is sent to the first group of signal controllers in the plurality of signal controllers through the first group of signal transceivers in the plurality of signal transceivers; the type of digital signal received by each group of signal transceivers in the plurality of signal transceivers is different and unique; a group of signal transceivers in the plurality of signal transceivers corresponds to a group of controllers in the plurality of signal controllers; a group of signal controllers in the plurality of signal controllers corresponds to a group of data selectors in the plurality of data selectors; the plurality of data selectors include a first group of data selectors corresponding to the first group of signal controllers; Sending the first digital signal to a logic control module through the first group of signal controllers; After identifying the first digital signal, determining, by the logic control module, a first pin of the vehicle interface corresponding to the first digital signal; When the logic control module sends a second digital signal to the multiple groups of signal controllers, the first group of data selectors selects the second digital signal output by the first signal controller of the multiple signal controllers in the first group of signal controllers.

9. A vehicle interface data identification chip, characterized in that: Comprising the device as described in any one of claims 1-7.

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