Method and system for logical to physical mapping of data storage devices

Abstract

The present disclosure provides a method and system for logical to physical mapping of a data storage device. The method includes maintaining first type information representing at least a portion of a logical to physical address translation mapping. Further, the method includes maintaining second type information related to the logical to physical translation mapping as a portion of a physical page. Further, the method includes completing the logical to physical mapping based on the first type information and the second type information to determine a physical location of data stored in each logical page within one or more of the physical pages.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory device, and in particular, to a solid state storage device (SSD). BACKGROUND

[0002] Computer memory refers to a data storage device used to store information used in a computer system or computer hardware. Solid state drives (SSDs) and hard disk drives (HDDs) are examples of storage devices in which information can be written to and read from the storage device.

[0003] SSDs can use a general storage algorithm to determine an optimized write and read order to be used on a host computing system. High levels of performance, endurance, and power consumption can be achieved by the SSD when the host behavior matches a predetermined pattern. However, if the host pattern deviates from the expected inherent in the programming of the memory device, performance can be compromised. Therefore, there is a need in the art for a method of programming a storage device to adapt the storage algorithm of the storage device based on the host computing system. SUMMARY

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key or essential inventive concepts of the claimed subject matter, nor is this Summary intended to be used to determine the scope of the claimed subject matter.

[0005] The present disclosure describes a method for logical to physical (L2P) mapping of a data storage device including a non-volatile memory device. The method includes maintaining first type information at least partially representing a logical to physical (L2P) address translation mapping. Further, the method includes maintaining second type information related to the L2P translation mapping as part of a physical page. Further, the method includes completing the logical to physical mapping based on the first type information and the second type information, thereby determining a physical location of data stored in each logical page (L-page) within one or more of the physical pages.

[0006] The present disclosure also describes a method of storing data in a memory device, the method including: storing data corresponding to a plurality of logical pages in physical pages of the memory device; storing first address information in a logical to physical (L2P) table, wherein the first address information indicates the physical pages storing the logical pages; storing second address information in a spare area of the physical pages, wherein the second address information indicates a location within the physical pages of each of the logical pages; and reading at least a portion of the data from the memory device based at least in part on the first address information and the second address information.

[0007] The present disclosure supports large capacity SSDs (32 TB) without increasing the logical page size and causing read-modify-write overhead and associated durability implications. The present disclosure is scalable for smaller capacity drives for lower granularity logical page sizes, e.g., 512B size logical pages, but 4KB granularity physical level, and 2 TB SSD capacity.

[0008] To further clarify the details of the present application, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the application and are therefore not to be considered limiting of its scope. The application will be described and explained with additional specificity and detail through the use of the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] The application will become better understood from the following detailed description with reference to the drawings, in which like elements are depicted by the same characters throughout the figures, in which:

[0010] Figure 1 shows a state of a prior art logical to physical (L2P) address mapping for an SSD according to embodiments of the present disclosure;

[0011] Figure 2 shows a method of operation according to embodiments of the present disclosure;

[0012] Figure 3 shows a system according to embodiments of the present disclosure;

[0013] Figure 4 shows an example layout of an L2P mapping table according to embodiments of the present disclosure;

[0014] Figure 5 shows a layout of a spare area in a physical page according to embodiments of the present disclosure;

[0015] Figure 6 shows a "write" operation and garbage collection (GC) according to embodiments of the present disclosure;

[0016] Figure 7 shows a "read" operation according to embodiments of the present disclosure;

[0017] Figure 8 shows a "read" operation by alternative representation according to embodiments of the present disclosure; Figure 7

[0018] ​Furthermore, those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and that the figures do not necessarily show all of the components of a particular apparatus or method. For example, a flow diagram can illustrate a method comprising steps related to the most prominent functionality of that method. Additionally, with respect to the apparatus, one or more components of the apparatus can have been represented in the figures by conventional symbols, and the figures can show specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the more pertinent aspects of the embodiments. DETAILED DESCRIPTION

[0019] The present disclosure provides a method for L2P mapping for data storage devices, including non-volatile memory devices such as solid state drives (SSDs). An SSD can use a storage algorithm to determine an optimized write and read order to be used on a host computing system. However, if the host pattern deviates from the expected in programming inherent to the SSD, performance can suffer. Thus, an SSD with the ability to adapt the storage algorithm using actual host behavior rather than expected host behavior can enable improved synergy with the host, resulting in improved performance, endurance, and / or power consumption.

[0020] The systems and methods described in the present disclosure include maintaining information representative of at least a portion of a logical-to-physical address translation mapping. Additional information related to the logical-to-physical translation mapping can also be maintained as part of a physical page. Logical-to-physical mapping can be performed based on the information to determine a physical location of data stored in each logical page within one or more of the physical pages.

[0021] Reference will now be made to embodiments illustrated in the drawings, and specific language will be used herein to describe the same in order to facilitate the understanding of the principles of the present disclosure. It will be understood, however, that no limitation of the scope of the disclosure is intended by this specific language, and alterations and further modifications in the illustrated systems and further applications of the principles of the present disclosure as illustrated therein are contemplated as would normally occur to one skilled in the art to which the disclosure pertains.

[0022] Those skilled in the art will appreciate that the foregoing general description and the following detailed description are explanatory only and are not intended to be limiting.

[0023] Reference throughout this specification to "an aspect", "another aspect" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Accordingly, appearances of the phrases "in one embodiment", "in another embodiment", and similar language in various places throughout this specification do not necessarily all refer to the same embodiment.

[0024] The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not only include those steps but can include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or subsystems or elements or structures or components proceeded by "comprises... a" does not, without more constraints, preclude the existence of other devices or other subsystems or other elements or other structures or other components or additional devices or additional subsystems or additional elements or additional structures or additional components.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The

[0026] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0027] Figure 1 A state of prior art L2P address mapping for an SSD according to embodiments of the present disclosure is shown. In an SSD architecture, the SSD maintains a data structure, such as an L2P table, within a memory buffer to map logical page addresses in a logical block address (LBA) space to physical page addresses in the NAND memory of the SSD. The L2P table can store logical to physical page mappings. The length and width of the L2P table can determine the capacity of the SSD. For a given SSD, the length and width are limited by the available dynamic random access memory (DRAM) size.

[0028] In one example, with a standard 32-bit DRAM and a 4KB physical page size, up to 2 32 x 4KB = 16TB capacity can be implemented within the SSD. However, to implement a 32TB or greater capacity, a higher logical page size can be used. However, with such higher logical page size, a 4KB write operation incurs a "read-modify-write" overhead, impacting the endurance of the storage device.

[0029] While the length of the L2P in the DRAM can be managed by loading L2P table entries on demand, the width of the L2P table entries is not managed. Thus, with a 4KB logical page size in a 32-bit DRAM and in a host memory buffer (HMB), the maximum capacity of the SSD supported is 2 32 x 4KB = 16TB.

[0030] However, considering the example of a DRAM of 32 TB memory size, L2P table entries use 33 bits, thus exceeding the current 32-bit limit of DRAM. Therefore, conventional SSDs perform mapping with 8 KB page size instead of 4 KB page size to fit L2P table entries into 32 bits. With 8 KB mapping, any 4 KB random write uses read-modify-write overhead, which increases write amplification and affects endurance. An option to address the current constraint is to use multiple levels of L2P tables. However, such a mechanism would use multiple NAND reads for lookup, resulting in additional latency.

[0031] Figure 2 A method of operation in accordance with the present disclosure is shown. A method for L2P mapping of a data storage device including a non-volatile memory device is disclosed. The method includes maintaining first type information representing at least in part a logical to physical (L2P) address translation mapping (step 102). Further, the method includes maintaining second type information related to the L2P address translation mapping as part of a physical page (step 104). The second type information is stored within a spare area of the non-volatile memory to enable the L2P table and the spare area to present a complete logical to physical mapping. An order of logical pages within the physical page corresponds to an order of logical page numbers (LPNs) in the spare area of the physical page. A plurality of logical page (L-page) numbers (LPNs) of a plurality of logical pages are stored within such a spare area of the physical page.

[0032] The method further includes completing the L2P mapping based on the first type information and the second type information to determine a physical location of data stored in each logical page within one or more of the physical pages (step 106).

[0033] The method includes writing data into a plurality of logical pages (L-pages) corresponding to a single physical page of the non-volatile memory, wherein each of the plurality of L-pages is associated with an L-page number configured to enable the controller to logically direct data in the corresponding physical page. The write operation includes updating a spare area of the physical page (currently under consideration) of the non-volatile memory to indicate the L-page number. The L2P address translation mapping is updated to point to the physical page defining a storage location of the logical page. The written data is transferred to the physical location of the non-volatile memory in accordance with the updated L2P address translation mapping.

[0034] During a read operation, the method further includes extracting a physical page holding a plurality of logical pages based on the first type of information. The contents of the physical page are accessed to determine an offset at a location of a logical page corresponding to the first type of information. The offset corresponding to the logical page directed by the first type of information is transferred to enable a data transfer to the volatile memory to implement the read operation. The read operation is defined by the operation of the data extractor to transfer the logical page corresponding to the first type of information from the physical page to the volatile memory to implement the read operation.

[0035] Figure 3 A detailed internal architecture of a system or SSD storage module 300 according to an embodiment of the present application is shown. The SSD storage module 300 includes a memory 302 and a processing device (or referred to as a processor) 304 for performing the method steps 102-106. Figure 2 Likewise, there can be a peripheral card interface such as PCIe, Serial ATA (SATA), or any other interface that facilitates the operational interconnection between the storage module 300 and a host computing system (or referred to as a host). The host can include a CPU and an operating system. While the storage module 300 can be removably connected to the host through PCIe, the storage module 300 can also be integrated with the chipset of the host computing system.

[0036] The storage module 300 includes at least one of a storage buffer and a memory 302 (e.g., a non-volatile memory) configured to hold a first type of information representing at least some of a logical-to-physical (L2P) address translation map and hold a second type of information associated with the L2P address translation map as part of a physical page. The memory 302 stores the second type of information in a spare area and stores the L2P table within the storage buffer to implement a complete logical-to-physical mapping.

[0037] The physical page of the non-volatile memory includes an order of logical pages corresponding to an order of logical page numbers in a spare area of the physical page. The spare area of the physical page includes a plurality of logical page numbers storing a plurality of logical pages. In one example, the storage buffer corresponds to a 96 KB buffer of double data rate random access memory (RAM) including at least one of 24 4 KB logical pages and 12 8 KB logical pages.

[0038] Further, the processing device 304 is configured to complete the L2P mapping based on the first type of information and the second type of information to determine a physical location within one or more of the physical pages of the non-volatile memory relative to data stored in each logical page.

[0039] Figure 4 An example embodiment depicting operations according to the present disclosure is shown. More specifically, Figure 4An example layout of a L2P mapping table according to the present disclosure is shown.

[0040] According to embodiments of the present disclosure, the L2P mapping provides 4KB granularity at the logical level, while providing 8KB granularity at the physical level. Additionally or alternatively, while the physical page size in the NAND is 8KB, the 8KB physical page is logically divided into two logical pages each of 4KB size, such that each 8KB physical page holds two logical pages of 4KB size. However, the present embodiments should not be construed as limiting, and can be extended to cover lower granularity logical page mapping, e.g., 512B size logical pages, but with 4KB granularity at the physical level.

[0041] In one example, the first information, as discussed in Figure 1 corresponds to a logical page LI, which results in a physical address of a physical page P as part of the L2P address mapping. However, unlike the conventional mechanism where LI is used as the first information alone to read data Dl from the physical page, the present disclosure uses a second information or logical page number corresponding to the logical page LI actually stored within the physical page P. Accordingly, the offset is computed based on the second information or logical page number to return the data Dl. Details regarding the logical page number and offset computation have been further mentioned in the description of Figure 6 to Figure 8 .

[0042] In other cases, where L2 is the first information to locate the physical page P, the corresponding logical page number is found from the physical page P as the second information to compute the offset to return the data D2 from the physical page P.

[0043] Figure 5 An example embodiment depicting operations according to the present disclosure is shown. More specifically, Figure 5 A layout of a spare area in a physical page according to the present disclosure is shown.

[0044] While each entry of the L2P table is for a 4KB logical page, the L2P table points to an 8KB physical page in the NAND. In Figure 5 , within the spare area of the 8KB physical page, the logical page numbers (LPNs) of two pages are stored individually as LPN1 / LPN2 within the respective spare areas of the two logical pages LPN1, LPN2 (e.g., the NAND spare area layout in Eagle FTL). In another approach, the spare areas of 4KB logical pages are combined in each 8KB to indicate the stored LPNs. However, the order or sequence of the logical pages corresponding to LPN1 / LPN2 within the 8KB physical page follows the same order as the order of the logical page numbers LPN1 / LPN2 in the spare area.

[0045] The L2P table stores only a portion of the logical to physical mapping, and the remaining mapping is completed from the spare area. In some cases, since the mapping is a spare portion of the same physical page, there is no additional read penalty for lookups.

[0046] Figure 6 An example embodiment depicting operations in accordance with the present disclosure is shown. More specifically, Figure 6 A "write" operation and garbage collection (GC) in accordance with the present disclosure is shown.

[0047] In Figure 6 In (a), a "write" implemented by a host (i.e., an operating system of a computing system) is accumulated in a host memory buffer (e.g., a 96-KB buffer (24 4KB logical pages or 12 8KB logical pages (e.g., pages 1 through 12))) for completion of the write operation. A spare area in the host memory buffer is updated to indicate logical page numbers (e.g., LPN1, LPN9, LPN5, LPN8,..., LPNx, and LPNy, where x and y are positive integers greater than 1).

[0048] In Figure 6 In (b), once the 96KB buffer (i.e., the host memory buffer) is occupied and filled with data, programming to the NAND is completed, and accordingly, data is transferred from the DRAM to the NAND (e.g., pages p through p+12). Thus, in Figure 6 In (c), the L2P is updated to point to the physical page storing the logical page in view of the completed write operation.

[0049] The processing device 304 of the storage module is configured to facilitate a write operation by receiving data to be written in a plurality of logical pages corresponding to a single physical page of the non-volatile memory, each of the plurality of L pages being associated with an L page number configured to enable the controller to logically direct the data in one corresponding physical page. Accordingly, a spare area within the non-volatile memory is updated to indicate the logical page number. Further, the write data within the volatile memory is transferred to a physical location of the non-volatile memory. The L2P address translation mapping is also updated to point to the physical page defining the storage location of the logical page in view of the completed write operation.

[0050] Figure 7 And Figure 8 An example embodiment depicting operations in accordance with the present disclosure is shown. More specifically, Figure 7 And Figure 8 A "read" operation in accordance with the present disclosure is shown.

[0051] Step 702, as part of the initiation of the read operation, the file transfer logic (FTL) fetches the 8KB physical page P holding the logical page LI based on the read command directed to read the content of the logical page LI. The physical page P is obtained based on the mapping through the L2P mapping table.

[0052] Step 704, the data from the physical page is read as Dl and D2. The fetched data is analyzed for internal data corruption and corrected by the Error Correction Code memory (ECC) through the state of the art standard.

[0053] Step 706 represents the processing of the data to extract the relevant data belonging to the logical page LI. This processing can be performed through a dedicated hardware engine or in software. Additionally or alternatively, the processing comprises analyzing the spare area of the physical page P and finding the offset where the logical page Ll is located. At step 708, the data is returned based on the offset.

[0054] In one example, based on the spare area, the corresponding logical page L2 from the spare area is received. Based on the sequential combination of the logical addresses LI and L2, a match is obtained and multiplied by 4096 (due to the 4KB logical page size), and an offset value is obtained for the logical address LI. Such offset value presents the physical address and / or location of the data Dl within the physical page P to extract the data Dl that can correspond to the 4KB logical page LI.

[0055] At step 706, the extracted data Dl corresponding to the 4KB logical page LI in the 8KB physical page is sent to the RAM / DRAM as part of the read operation.

[0056] The additional 4KB transfer can be interpreted as causing a latency (e.g., of multiple microseconds), and this additional 4KB transfer is substantially offset due to the increase in endurance in new NAND memories (e.g., as QLC NAND). The endurance of the NAND memory is increased by avoiding read-modify-write.

[0057] During the read operation, the processing device 304 is configured to fetch, based on the first type of information, a physical page holding a plurality of logical pages, access the content of the physical page to determine an offset at a location of a logical page corresponding to the first type of information, and transfer the offset corresponding to the logical page directed by the first type of information to implement a data transfer to a volatile memory to implement the read operation.

[0058] The processing device 304 comprises a data fetching module for implementing the read operation when transferring the logical page corresponding to the first type of information from the physical page to the volatile memory (i.e., DRAM).

[0059] This disclosure provides support for large-capacity SSDs (32TB or more) without increasing the logical page size and incurring read-modify-write overhead and associated durability effects.

[0060] Therefore, according to embodiments of the present invention, a method for storing data in a memory device may include: storing data corresponding to a plurality of logical pages in physical pages of the memory device; storing first address information in a logic-to-physical (L2P) table, wherein the first address information indicates the physical page storing the logical pages; storing second address information in a spare area of ​​the physical page, wherein the second address information indicates the location of each of the logical pages within the physical page; and reading at least a portion of the data from the memory device based at least partially on the first address information and the second address information.

[0061] In some cases, the method may further include: receiving a write command from an external host device, wherein the write command includes an indication of data of a logical page (e.g., a logical page number), and wherein the data is stored in response to the write command. In some cases, the method may include: receiving a read command from an external host device, wherein the read command indicates one or more logical pages; identifying a physical page based on the read command and first address information in an L2P table; and identifying one or more portions of a physical page storing one or more logical pages based on second address information stored in a spare area, wherein at least a portion of the data is read in response to the read command.

[0062] In some cases, the method may include: transferring one or more logical pages from physical pages to volatile memory, wherein at least a portion of the data is read from the volatile memory. In some cases, the method may include: accessing the contents of physical pages to determine an offset at a location within the logical pages, wherein one or more logical pages are transferred based on the offset.

[0063] Although specific language has been used to describe the disclosure, it is not intended to impose any limitations on the method. It will be apparent to those skilled in the art that various working modifications can be made to achieve the inventive concept taught herein.

[0064] The accompanying drawings and the foregoing description provide examples of embodiments. Those skilled in the art will understand that one or more of the described elements can be well combined into a single functional element. Optionally, a particular element may be divided into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of processes described herein may be changed and is not limited to the manner described herein.

[0065] Moreover, the acts of any of the processes can occur in any order, and are not necessarily limited to the ordering of the acts as described. Further, not all of the acts can be required, and some acts can be performed in parallel. The scope of embodiments is not limited to the specific examples described herein. Numerous variations are possible, as will be apparent to those having skill in the art. Any of the embodiments described herein can be combined with any other embodiment described herein. The scope of embodiments is limited only by the claims.

[0066] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems and any component(s) that can cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.

Claims

1. A method for logical-to-physical mapping of a data storage device including a non-volatile memory device, the method comprising: The first type of information in non-volatile memory is defined as representing at least a portion of a logical-to-physical address translation mapping, wherein the first type of information indicates a physical page storing a logical page; The second type of information related to the logical-to-physical address translation mapping is defined as a portion of the physical pages within non-volatile memory, wherein the second type of information indicates the location of each logical page within the physical page; and The first type of information and the second type of information are mapped to draw a logical-to-physical mapping, thereby determining the physical location of the data stored in each logical page within one or more physical pages.

2. The method according to claim 1, wherein, The second type of information is stored in the spare area of ​​non-volatile memory, thus enabling the logical-to-physical table and the spare area to present a complete logical-to-physical mapping.

3. The method according to claim 1, further comprising: Data is written to multiple logical pages corresponding to a single physical page in non-volatile memory. Each logical page is associated with a logical page number, which is configured to enable the controller to logically direct the data in the corresponding physical page. Update the spare area in the non-volatile memory to indicate the logical page number; Update the logical-to-physical address translation mapping to point to the physical page that defines the storage location of the logical page; as well as The updated logical-to-physical address translation mapping is used to transfer the written data to the physical location of the non-volatile memory, thereby enabling the data to be written into the non-volatile memory.

4. The method according to claim 1, further comprising: Physical pages that are extracted and saved based on the first type of information; Access the contents of the physical page to determine the offset of the physical location in the logical page corresponding to the first type of information; as well as The offset corresponding to the logical page indicated by the first type of information is transmitted to realize the data transfer to volatile memory to realize the read operation of non-volatile memory.

5. The method according to claim 4, wherein, Read operations are defined by the data extractor as follows: The logical page corresponding to the first type of information is transferred from the physical page to the volatile memory to perform the read operation.

6. The method according to claim 1, wherein, The order of logical pages within a physical page corresponds to the order of multiple logical page numbers in the spare area of ​​the physical page.

7. The method according to any one of claims 1 to 6, wherein, Multiple logical page numbers of multiple logical pages are stored in the spare area of ​​the physical page.

8. A data storage device for logical-to-physical mapping, the device comprising: At least one of a storage buffer and a non-volatile memory is configured to: retain first type information representing at least a portion of a logical-to-physical address translation mapping, wherein the first type information indicates a physical page storing a logical page; and retain second type information related to the logical-to-physical address translation mapping as part of the physical page, wherein the second type information indicates the location of each logical page within the physical page; and A processing device is used to map first type information and second type information to form a logical-to-physical mapping, thereby determining the physical location of data stored in a logical page within a physical page.

9. The apparatus according to claim 8, wherein, Non-volatile memory stores second-type information in a spare area and stores the logic-to-physical table in a storage buffer to achieve a complete logic-to-physical mapping.

10. The apparatus according to claim 8, wherein, The processing device is configured to perform write operations in the following manner: Receive data to be written into multiple logical pages corresponding to a single physical page in non-volatile memory, each of the multiple logical pages being associated with a logical page number configured to enable the controller to logically direct the data in the corresponding physical page; Update the spare area in the non-volatile memory to indicate the logical page number; Update the logical-to-physical address translation mapping to point to the corresponding physical page that defines the storage location of the logical page; as well as The updated logical-to-physical address translation mapping will transfer the written data to the physical location of the non-volatile memory.

11. The apparatus according to claim 8, wherein, During the read operation, the processing device is configured to: Physical pages that are extracted and saved based on the first type of information; Access the contents of the physical page to determine the offset of the logical page corresponding to the first type of information; as well as The offset corresponding to the logical page indicated by the first type of information is transferred to realize the read operation by transferring data to the volatile memory.

12. The apparatus according to claim 11, wherein, The processing device includes a data extraction module for implementing read operations, the read operations including: The logical page corresponding to the first type of information is transferred from the physical page to the volatile memory to perform the read operation.

13. The apparatus according to claim 12, wherein, The order of logical page numbers in the spare area of ​​a physical page corresponds to the order of logical pages within the physical page.

14. The apparatus according to claim 13, wherein, The spare area of ​​a physical page includes multiple logical page numbers, which indicate the location where the multiple logical pages are stored.

15. The apparatus according to claim 8, wherein, The storage buffer corresponds to a 96KB buffer, which includes at least one of a) 24 logical pages of 4KB and b) 12 logical pages of 8KB, and the 96KB buffer is defined by double data rate random access memory.

16. A method for storing data in a memory device, the method comprising: Data corresponding to multiple logical pages is stored in physical pages of the memory device; The first address information is stored in the logical-to-physical table, wherein the first address information indicates the physical page that stores the logical page; The second address information is stored in a spare area of ​​the physical page, wherein the second address information indicates the location of each of the plurality of logical pages within the physical page; and At least a portion of data is read from the memory device based on a read command, first address information, and second address information, wherein the read command indicates one or more logical pages among the plurality of logical pages.

17. The method according to claim 16, further comprising: Receive a write command from an external host device, wherein the write command includes an indication of logical page data, and the data is stored in response to the write command.

18. The method according to claim 16 or claim 17, further comprising: Receive read commands from external host devices; Physical pages are identified based on the read command and the first address information logically entered into the physical table; One or more portions of the physical page storing the one or more logical pages are identified based on second address information stored in the spare area, wherein at least a portion of the data is read in response to a read command.

19. The method according to claim 18, further comprising: The one or more logical pages are transferred from physical pages to volatile memory, wherein at least a portion of the data is read from the volatile memory.

20. The method according to claim 18, further comprising: Access the physical page to determine the offset of its location in the logical page, wherein the one or more logical pages are transmitted based on the offset.

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