Method of performing read / write operations and computing system hosting a client device

Abstract

Methods of performing read / write operations and computing systems hosting a client device are provided. The method of performing a write operation includes selecting, by a host, at least one free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB to track free write buffers; sending, by the host, at least one logical address accessed from the cache structure for the selected write buffer to issue a write command to a non-volatile memory; receiving, from the non-volatile memory, a lock instruction for the selected write buffer; updating, based on the received lock instruction, a state of the selected write buffer within the cache structure; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.

Description

Technical Field

[0001] At least some exemplary embodiments of the inventive concept relate to a memory device, and more specifically, to a solid-state memory device (SSD). Background Technology

[0002] Storage modules (such as solid-state drives (SSDs)) typically use generalized models to determine write and read patterns optimized for the host computing system. Storage modules exhibit optimal levels of performance, endurance, and power consumption when host behavior matches these expected patterns. As desired, storage modules whose storage algorithms adapt to real, rather than expected, host behavior achieve synergistic effects with improved host performance, resulting in better performance, endurance, and / or power consumption.

[0003] A host memory buffer (HMB) is a feature supported by SSDs (e.g., defined by NVMe 1.2 and later), where a portion of the host computing system's host memory is exposed to the SSD via a peripheral interface connector (e.g., PCIe). Client SSDs utilize this connector feature to store a portion of the L2P (Logical to Physical) table and write data to the HMB buffer instead of writing it to the SSD's built-in DRAM. SSDs utilizing this HMB feature can reduce the amount of DRAM, which helps reduce both cost and power requirements, making them suitable for low-power, mobile devices such as tablets and smartphones.

[0004] Host systems using HMB-based client SSDs incur "two-transfer" overhead on PCIe when writing data from the host buffer to the SSD or NAND memory (or simply NAND). Figure 1 The state of prior art write transmission from HMB 126 is described, and the underlying flow of steps 101 to 104 is shown below:

[0005] like Figure 1As shown, host system 120 includes processor 122 (e.g., central processing unit (CPU)) and memory 124 (e.g., double data rate (DDR) dynamic random access memory (DRAM) (or simply DDR memory or DDR)). Furthermore, memory 124 includes HMB 126. Host system 120 can be connected to solid-state drive (SSD) 140 via peripheral component interconnect high-speed (PCIe) bus 130. SSD 140 may include host interface logic (HIL) 142 and back-end NAND manager 144. When an application in host system 120 wants to write data to SSD 140, the application first allocates a buffer in HMB 126 via step 101 and writes the data to the buffer. HIL 142 and back-end NAND manager 144 can both be implemented by circuitry or circuit systems.

[0006] The application then forwards the buffer to the underlying file system or NVMe drive (executed by the processor) via step 102a to transfer the data to SSD 140. In one example, although host system 120 may have multiple layers of buffer copies, Figure 1 This example assumes a write-through or direct I / O type system in which there is no additional buffer copy from the application to the driver.

[0007] The host's NVMe drive then issues write commands to the SSD via the Logical Block Address (LBA) and a buffer pointer. The SSD typically has a module called Host Interface Logic (HIL) 142 responsible for handling NVMe commands, as well as another layer for back-end NAND management. HIL 142 keeps incoming write data in a pool of write buffers until the data is written to the NAND or SSD.

[0008] When a write command is received, HIL 142 allocates a write buffer in HMB 126 via step 102b, and transfers data from the user buffer (or user write / read buffer) to the write buffer in HMB 126 via step 103, thereby completing the write command.

[0009] In a subsequent step 104, once the data in the NAND programmable units (typically 48KB or 96KB) has been accumulated in the write buffer, the back-end NAND manager 144, which forms part of the SSD 140, retrieves the data from the write buffer from the HMB 126 and programs the data in the write buffer into the NAND. Once programming is complete, the write buffer is released.

[0010] As from Figure 1As can be seen, during steps 103 and 104, the data written to the buffer or HMB 126 is transferred twice via the PCIe bus 130, once to the HMB 126 and once from the HMB 126 to the NAND memory of the SSD 140, thereby incurring write overhead.

[0011] Figure 2 The state of the prior art "read transfer" from HMB 126 is described, and the underlying flow of steps 201 to 203 is shown below:

[0012] When an application wants to read, it allocates a buffer (user read buffer) via step 201a and issues a read command to the NVMe drive. The NVMe drive then issues a read command to the SSD 140 based on the given logical block address (LBA) and buffer pointer.

[0013] When a read command is received, HIL 142 checks via step 201b whether the requested LBA is already available in the write buffer. In existing SSD systems, this check can be performed by the back-end NAND manager based on the LBA's L2P entry.

[0014] If the requested LBA is in the write buffer of HMB 126, the data is transferred from HMB 126 to the user read buffer via PCIe bus 130 through step 202.

[0015] If the requested LBA is not in the write buffer, the read request is converted into a NAND read request, and data is transferred from the NAND memory of the SSD 140 to the user read buffer via the backend NAND manager 144.

[0016] Once the data is transmitted to the user read buffer, the read command is completed, and the application can access the data from the user read buffer via step 203.

[0017] For example from here Figure 2 As can be seen, even if the "buffer or HMB" is available in the DDR memory 124 or HMB 126 of the host system 120, the data must still be transferred on the PCIe bus 130 via step 202. Summary of the Invention

[0018] According to at least some example embodiments of the inventive concept, a method for performing a write operation includes: selecting at least one free write buffer from a plurality of write buffers in a shared memory buffer (SMB) by a host accessing a cache structure within the shared memory buffer (SMB) to track free write buffers; sending at least one logical address for the selected write buffer accessed from the cache structure by the host to issue a write command to non-volatile memory; receiving a lock instruction for the selected write buffer from the non-volatile memory; updating the state of the selected write buffer within the cache structure based on the received lock instruction; and allowing the non-volatile memory to retrieve the contents of one or more locked write buffers including the selected write buffer.

[0019] According to at least some example embodiments of the inventive concept, a method for performing a read operation includes: detecting a logical address in at least one write buffer of the SMB based on a cache structure within the shared memory buffer (SMB); and allowing direct access by the host to the SMB to transfer data from the at least one write buffer to an allocated read buffer, thereby enabling a read operation defined by internal data transfer within the SMB.

[0020] According to at least some example embodiments of the inventive concept, a computing system hosting a client device including non-volatile memory includes: a shared memory buffer including: a plurality of write buffers configured to accumulate data for the non-volatile memory; and a cache structure located within the shared memory buffer (SMB) for tracking free write buffers among the plurality of write buffers within the SMB; and processing circuitry configured to: select at least one free buffer from the plurality of write buffers of the SMB by accessing the cache structure within the SMB; send at least one logical address for the selected write buffer accessed from the cache structure to issue a write command to the non-volatile memory; receive a lock instruction for the selected write buffer from the non-volatile memory, thereby updating the state of the selected write buffer within the cache structure; and allow the non-volatile memory to retrieve the contents of one or more locked write buffers including the selected write buffer.

[0021] According to at least some embodiments of the inventive concept, a computing system hosting a client device defined by non-volatile memory includes: a shared memory buffer, comprising: a plurality of write buffers configured to accumulate data for the non-volatile memory; and a cache structure located within the shared memory buffer (SMB) configured to track free write buffers among the plurality of write buffers within the SMB; and processing circuitry configured to: detect a logical address in at least one write buffer of the SMB based on the cache structure within the SMB; allocate a read buffer within the SMB; and allow direct access to the SMB by an application to transfer data internally from the at least one write buffer to the allocated read buffer within the SMB, thereby enabling a read operation. Attached Figure Description

[0022] The above and other features and advantages of the inventive concept will become clearer from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings. The drawings are intended to depict exemplary embodiments of the inventive concept and should not be construed as limiting the intended scope of the claims. Unless explicitly stated otherwise, the drawings are not to be considered as drawn to scale.

[0023] Figure 1 This illustrates the state of a prior art write transfer from the host memory buffer (HMB) for a solid-state drive (SSD);

[0024] Figure 2 This illustrates the status of existing technology read transfers from HMB to SSDs;

[0025] Figure 3 The method of operation according to at least one example embodiment of the inventive concept is shown;

[0026] Figure 4 Another method of operation according to at least one example embodiment of the inventive concept is shown;

[0027] Figure 5 A system according to at least one example embodiment of the inventive concept is shown;

[0028] Figure 6A and Figure 6B A precursor for write / read transfers from an HMB is shown according to at least one example embodiment of the inventive concept;

[0029] Figure 7 A write transfer operation from an HMB is illustrated according to at least one example embodiment of the inventive concept;

[0030] Figure 8A host drive is shown that uses a free buffer in the HMB to execute a write command according to at least one example embodiment of the inventive concept; and

[0031] Figure 9 The illustration shows read transfer operations from an HMB according to at least some example embodiments of the inventive concept.

[0032] Furthermore, those skilled in the art will understand that the elements in the accompanying drawings are shown for simplicity and need not necessarily be drawn to scale. For example, the flowcharts illustrate the methods according to the most significant steps relating to aspects that help improve understanding of at least some exemplary embodiments of the inventive concept. Moreover, regarding the construction of the apparatus, one or more components of the apparatus may already be represented by conventional symbols in the drawings, which may show only those specific details relevant to understanding at least some exemplary embodiments of the inventive concept, so as not to obscure the drawings with details that would be readily apparent to those of ordinary skill in the art who benefit from the description herein. Detailed Implementation

[0033] Reference will be made to the embodiments shown in the accompanying drawings for the purpose of facilitating an understanding of the principles of at least some exemplary embodiments of the inventive concept, and specific language will be used to describe the embodiments shown in the drawings. However, it will be understood that this is not intended to limit the scope of the at least some exemplary embodiments of the inventive concept, and such changes and further modifications in the illustrated systems, as well as such further applications of the principles of the at least some exemplary embodiments of the inventive concept shown herein, are considered to be commonly thought of by those skilled in the art in relation to the at least some exemplary embodiments of the inventive concept.

[0034] Those skilled in the art will understand that the foregoing general description and the following detailed description are illustrative of at least some exemplary embodiments of the inventive concept and are not intended to limit it.

[0035] Throughout this specification, references to "one aspect," "another aspect," or similar language mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one exemplary embodiment of the inventive concept. Therefore, the phrases "in one embodiment," "in another embodiment," and similar language appearing throughout this specification may, but do not necessarily, refer to the same embodiment.

[0036] The terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusionary inclusion, such that a process or method that includes a list of steps includes not only those steps but may also include other steps not expressly listed or inherent to such a process or method. Similarly, the use of “comprising…” does not exclude the presence of other devices or subsystems or elements or structures or components without further limitation.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which at least some exemplary embodiments of the inventive concept pertain. The systems, methods, and examples provided herein are illustrative only and are not intended to be limiting.

[0038] At least some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings:

[0039] Figure 3 A method of operation according to at least one example embodiment of the inventive concept is illustrated. This method refers to a method for performing write operations within a computing system hosting a client device defined by non-volatile memory.

[0040] The method includes a host selecting at least one free write buffer from a plurality of write buffers in a shared memory buffer (SMB) to initialize the write buffer, wherein the selection includes accessing cache information within the SMB for tracking (or finding) the free write buffer (step 302). According to at least one example embodiment of the inventive concept, the cache information is a data structure used to track the logical address of data within the write buffer and the state of the write buffer. This data structure may include an entry for each write buffer, defined as the logical address (e.g., logical block address (LBA)) of the data currently in the write buffer and the locked or unlocked state of the write buffer. However, as a precursor to step 302, the host device (hereinafter, may also be referred to as host / system / host system / host computing system / host computing device) registers the base address and size of the cache information or cache data structure associated with the SMB with the non-volatile memory.

[0041] The method further includes the host sending at least one logical block address (LBA) for the selected write buffer to access cache information to issue a write command to non-volatile memory (step 304). In response, a lock instruction for the selected write buffer is received from the non-volatile memory, thereby updating the state of the selected write buffer within the cache information (step 306).

[0042] According to at least one example embodiment of the inventive concept, prior to locking the selected write buffer, a controller associated with the nonvolatile memory checks the quantity or amount of data accumulated in the write buffer in order to schedule the retrieval of data from the plurality of write buffers, including the selected write buffer, to the nonvolatile memory.

[0043] The method also includes allowing non-volatile memory to extract the contents of one or more locked write buffers, including the selected write buffer (step 308). Such extraction of the contents of one or more locked write buffers by non-volatile memory corresponds to a single-step transfer of data from the SMB to the non-volatile memory via PCIe. Subsequently, after the extraction is completed, the cache information is updated to unlock the selected write buffer for further use. This update includes marking the logical address of the data as invalid as part of unlocking the selected write buffer.

[0044] Figure 4 A method of operation according to another embodiment of this subject matter is illustrated. This method refers to a method for performing a read operation within a computing system hosting a client device defined by non-volatile memory.

[0045] The method includes the host detecting a logical address corresponding to at least one write buffer of the shared memory buffer (SMB) based on cached information within the SMB (step 402). Furthermore, if the logical address corresponding to the at least one write buffer is unavailable, a read command is issued from the host to the non-volatile memory.

[0046] The method then further includes allowing direct access to the SMB by the host to transfer data from at least one write buffer to an allocated read buffer, thereby enabling a read operation defined by internal data transfer within the SMB (step 404). Such access to the SMB is an access to main memory defined by an internal direct memory access (DMA) operation, without requiring data transfer over PCIe.

[0047] Figure 5A detailed internal structure of a system 500 of a managed client device (e.g., SSD 140) according to at least one example embodiment of the inventive concept is shown. System 500 includes a memory 502 (i.e., main memory) and a processor 504 for performing... Figure 3 Method steps 302 to 308 and Figure 4 Method steps 402 to 404. Processor 504 may be processing circuitry (such as hardware including logic circuitry, hardware / software combination executing software, or a combination thereof). For example, processing circuitry may more specifically include, but is not limited to: central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, programmable logic unit (such as field-programmable gate array (FPGA)), microprocessor, application-specific integrated circuit (ASIC), etc.

[0048] Similarly, peripheral card interfaces (such as PCIe, Serial ATA (SATA), or any other interface that facilitates operational interconnection between the storage module and the host computing system 500) may be present. Figure 5 In the example shown, PCIe bus 300 is connected between host computing system 500 and SSD 140. Although SSD 140 is removably connected to host 500 via PCIe bus 300, SSD 140 may also be integrated with the chipset of the host computing system. In this specification, SSD 140 may also be referred to as non-volatile memory 140 or client SSD 140. SSD 140 may include a controller. The controller of SSD 140 can control the overall operation of SSD 140 and one or more components of SSD 140. The controller of SSD 140 may be processing circuitry (such as hardware including logic circuitry, a hardware / software combination executing software, or a combination thereof). For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a programmable logic unit (such as a field-programmable gate array (FPGA)), a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0049] System 500 hosts client devices defined by non-volatile memory (SSD). The client device may include memory 502, which includes a shared memory buffer (SMB) and cached information within the SMB. The SMB includes multiple write buffers for accumulating data for the non-volatile memory, and the cached information within the SMB is used to track free write buffers among the multiple write buffers within the SMB. References are made below to at least some example embodiments. Figure 6A In more detail, the SMB can be implemented by the HMB 526 in memory 502. Alternatively, see below. Figure 6B In more detail, the SMB can be implemented by the controller memory buffer (CMB) 646 in the SSD 140. According to at least some example embodiments, the memory 502 can be implemented by, for example, dual data rate (DDR) dynamic random access memory (DRAM).

[0050] System 500 may further include processor 504, configured to: select at least one free write buffer from a plurality of write buffers in the shared memory buffer (SMB) by accessing cache information within the SMB to initialize the write buffer. Processor 504 sends at least one logical address (LBA) for the selected write buffer to access the cache information to issue a write command to non-volatile memory 140. A "lock" instruction for the selected write buffer is received from non-volatile memory 140, thereby updating the state of the selected write buffer within the cache information. Non-volatile memory 140 is allowed to retrieve the contents of one or more locked write buffers, including the selected write buffer.

[0051] According to at least one example embodiment of the inventive concept, cache information is a data structure used to track the logical address of data within a write buffer and the state of the write buffer. For each write buffer, the data structure includes an entry defined as the logical block address (LBA) of the data currently in the write buffer and the locked or unlocked state of the write buffer.

[0052] In addition, the controller (i.e., the back-end NAND manager 144) is associated with the non-volatile memory 140 to check the amount or quantity of accumulated data in the write buffer before locking the selected write buffer, in order to schedule the retrieval of data from the multiple write buffers, including the selected write buffer, to the non-volatile memory.

[0053] Figure 6A and Figure 6B This description illustrates a precursor for write / read transfers from an HMB 526 according to at least one example embodiment of the inventive concept. The description shows a cached data structure (e.g., a 5-byte cached data structure) for tracking the write buffer in the HMB 526. The cached data structure can be stored as... Figure 6A HMB 526 shown in the image or as shown in the image Figure 6B The controller memory buffer (CMB) 646 is shown in the figure. Although this topic illustrates the operation of the HMB, which forms part of the DDR within a host computing device, this topic can be extended to cover the presence of cached data structures in the client management buffer (CMB) within an SSD.

[0054] As from Figure 6A And later from Figure 8 As can be seen, the cache data structure has LBA entries (LBA N) (e.g., LBA N1, LBA N2, LBA N3) and lock / unlock states (or lock / idle states) for each write buffer. More specifically, each entry has the logical block address of the data currently in the write buffer (e.g., N1, N2, N3) and whether the write buffer is currently locked / unlocked by the SSD. The lock / unlock state can be described by logical states 1 / 0.

[0055] While the backend NAND manager 144 of the SSD 140 is accumulating programmable units of data in the write buffer of the HMB 526, the write buffer is kept locked, so that the lock state can be maintained as "logical state 1" in the cache structure. When the write to "NAND" is complete, the write buffer is unlocked, and the write buffer changes from the locked state to the free state (e.g., logical state 0). At any time, when an application / drive needs to find a free write buffer, it can look for a write buffer that is not locked or whose lock state is set to 0.

[0056] The host's NAND or NVMe drive registers the base address and size of the HMB cache structure with the SSD using a new vendor-unique register cache command. Thus, the host device (e.g., host system) 500 and the SSD 140 recognize each other.

[0057] Figure 7 This diagram illustrates a write transfer operation from an HMB according to an embodiment of this subject matter. More specifically, this figure corresponds to... Figure 3 Method steps 302 to 308.

[0058] In step 702, corresponding to step 302, an application executing in the host device (e.g., host system 500) or a driver forming part of the operating system (OS) 510 of the host device (e.g., host system 500) allocates a buffer directly from the write buffer of the HMB 526 and initializes the buffer or the HMB 526.

[0059] In step 704a, corresponding to step 304, the drive or NVMe drive of the host computing device (e.g., host system 500) issues a 'write command' to the SSD 140 to provide the LBA and buffer pointer.

[0060] In step 704b, corresponding to step 304, when a write command is received from the host computing device (e.g., host system 500), HIL 142 forwards the write command to the SSD's back-end NAND manager 144 or controller. HIL 142 checks whether there is sufficient data (e.g., equal to 48KB or 96KB) in the write buffer to issue a NAND write.

[0061] In step 706, corresponding to step 306, when the desired space is found or the desired buffer is located, the backend NAND manager 144 locks the specific selected buffer by updating the cache structure and tracks the write operations in the selected buffer.

[0062] In step 708, corresponding to step 308, once enough data has accumulated in the write buffer (e.g., equal to 48KB or 96KB), the back-end NAND manager 144 extracts the data for programming into the NAND.

[0063] In step 710, once programming is complete via step 708, the back-end NAND manager 144 marks the previously 'locked' buffer as 'unlocked' or 'free'. Therefore, the LBA (LPN identifier) ​​stored in the NAND and provided earlier during steps 704a and 704b is considered invalid.

[0064] Figure 8 A host drive is shown that uses a free buffer in an HMB 526 to execute write commands according to at least one example embodiment of the inventive concept.

[0065] like Figure 8 The “cache data structure” described herein is an index table that describes the logical block address (LBA) for each occupied buffer in the HMB 526 in the form of LBA N1, LBA N2, LBA N3, etc. A missing LBA or a “0” for any index entry indicates an empty buffer. Furthermore, each index entry (e.g., index 1, index 2… index n, where n is a positive integer greater than 1) is associated with a corresponding “locked or idle” identifier represented by a binary digit 1 or 0.

[0066] The HMB 526 is then a stack of buffers 1, 2, 3, 4...n (where n is a positive integer greater than 1), each buffer corresponding to an index entry in the cache data structure. Each buffer corresponds to a "4KB" size. In one example, based on the LBA allocation as done in the cache data structure, each occupied buffer is assigned LBA N1, LBA N2, LBA N3, etc. However, the free buffers in the HMB 526 hold no allocated LBAs and are therefore referred to as "free" buffers or empty buffers ready to store data.

[0067] During a write operation, an NVMe write command from the host drive or NVMe drive (e.g., write operation code CDW0, data pointer CDW6, starting LBA M CDW11, etc.) checks for empty or free buffers in the HMB by checking for free entries in the cache data structure. Based on the index entries marked "free" in the cache data structure, the NVMe write command selects the corresponding free buffer in HMB 526 and transmits the allocated LBA (e.g., LBA M) to the SSD via steps 704a and 704b. Based on this, a locking command issued from the back-end NAND manager representing the SSD (via step 706) locks the buffer corresponding to the LBAM and updates the lock / free status to '1'. Furthermore, the index entries in the cache data structure are also updated using the LBA M allocated for the selected buffer.

[0068] Reconsider Figure 1 The existing technology operation described herein involves the initial 4KB of data being transferred via PCIe to the Host Memory Buffer (HMB) 526 to write 4KB to the SSD. Assuming an example with a PCIe speed of 3GB / s, this 4KB transfer takes approximately 1.3μs to complete. The write to the HMB 526 is completed while the data is being transferred to the HMB. Subsequently, the accumulated data is written to the NAND (e.g., the NAND memory of the SSD 140) by transferring data again from the HMB 526 via PCIe (e.g., PCIe bus 130).

[0069] In such Figure 7 In the suggested example implementation depicted, no PCIe transfer occurs while the buffer is locked after step 706 and is being accumulated. Therefore, in one example, at least 1.3 μs of write time is saved, and the latency for completing the write command is significantly reduced (or alternatively, there is virtually no latency for completing the write command). The complexity of buffer release / locking is similar when checking the buffer's busy or idle status from the host drive or from HIL142.

[0070] Figure 9 A read transfer operation from an HMB 526 is illustrated according to at least one example embodiment of the inventive concept. The read transfer operation may, for example, correspond to... Figure 4 The method and steps.

[0071] In step 902, the application or driver of the host device (e.g., host system 500) allocates a user read buffer as in step 702. However, in cases such as Figure 2 Before issuing a read command to the SSD 140 as depicted, the host device (e.g., host system 500) searches for the LBA corresponding to the write buffer of the HMB 526 by looking up in a cache data structure. If the LBA is available within the cache data structure, an internal DMA (Direct Memory Access) is performed within the HMB to transfer data from the write buffer to the read buffer. Therefore, as can be seen from the accompanying figures, no PCIe transaction is performed when data is transferred from the write buffer to the read buffer in the HMB 526.

[0072] If the LBA is not available in the cached data structure, a write command is issued to the SSD 140.

[0073] In step 904, upon completion of DMA and transfer of data to the read buffer, the application accesses the read buffer.

[0074] Reconsider Figure 2 The existing technology operation described herein involves a transfer through the PCIe to the host buffer when a cache hit occurs during a read. Assuming an example PCIe speed of 3GB / s, the transfer would take approximately 1.3μs to complete. According to... Figure 9 In the proposed implementation described herein, internal DMA transfers are performed within the host (e.g., host system 500). This is based on a CPU architecture executing at a bus speed of approximately 8 GB / s. Figure 9 The example read operation shown can complete the transfer in just about 0.5 μs, thus improving time efficiency by about 150% (e.g., compared to conventional techniques). In addition to saving data transfers over PCIe, at least some example embodiments of the inventive concept also save (e.g., reduce) read command transfers over the PCIe interface. The general-command overhead is approximately 64 bytes of SQ (submission queue) entries and 16 bytes of CQ (completion queue) entries per command.

[0075] In summary, at least some example embodiments of the inventive concept can provide host buffer-to-NAND transfers (i.e., write operations) requiring only a single transfer via PCIe, and provide the ability to complete host read operations directly from the HMB without any transfer via PCIe. At least some example embodiments of the inventive concept can be achieved by ensuring that new NVMe vendor-specific commands define the data structure (i.e., the cache data structure) used for writing buffer cache (cache information) and registering this cache data structure with the SSD.

[0076] At least some exemplary embodiments of the inventive concept also include a method for direct transfer from the user buffer to NAND memory (e.g., the NAND memory of an SSD) and thus achieving a single transfer via PCIe. As part of a read operation, at least some exemplary embodiments of the inventive concept include performing a transfer directly from the HMB to the user buffer without any exchange of commands or data with the SSD. The proposed method improves the read and / or write performance of HMB-based DRAM-less client SSDs.

[0077] Although specific language has been used to describe the disclosure, it is not intended to impose any limitations due to that language. As will be apparent to those skilled in the art, various feasible modifications can be made to the method in order to implement at least some of the exemplary embodiments of the inventive concept taught herein.

[0078] The accompanying drawings and the foregoing description provide examples of embodiments. Those skilled in the art will understand that one or more of the described elements can be well combined into a single functional element. Optionally, a particular element can be split into multiple functional elements. Elements from one embodiment can be added to another embodiment. For example, the order of the processes described herein can be changed and is not limited to the manner described herein.

[0079] Furthermore, the actions in any flowchart need not be performed in the order shown; nor do all actions necessarily need to be executed. Moreover, actions that are independent of other actions can be performed in parallel with other actions. The scope of the embodiments is not limited to these specific examples. Numerous variations (such as differences in structure, size, and material use) are possible, whether explicitly given in the specification or not. The scope of the embodiments is at least as broad as that given by the claims.

[0080] Exemplary embodiments of the inventive concept have thus been described, and it will be apparent that these embodiments can be varied in many ways. Such variations are not to be considered as departing from the spirit and scope of the inventive concept's intent, and all such modifications, as will be apparent to those skilled in the art, are intended to be included within the scope of the claims.

Claims

1. A method for performing a write operation, the method comprising: The host selects at least one free write buffer from among the multiple write buffers of the shared memory buffer by accessing the cache structure within the shared memory buffer to track free write buffers; The host sends at least one logical address for the selected write buffer to the cache structure to issue a write command to the non-volatile memory. Receive a lock command for the selected write buffer from non-volatile memory; Based on the received locking instruction, update the state of the selected write buffer within the cache structure; as well as Allows non-volatile memory to extract the contents of one or more locked write buffers, including the selected write buffer.

2. The method according to claim 1, wherein, The step of selecting at least one free write buffer from the plurality of write buffers includes: initializing the selected write buffer.

3. The method according to claim 1, wherein, The cache structure is a data structure used to track the logical addresses of data within the plurality of write buffers and the state of the plurality of write buffers. For each write buffer, the data structure includes entries, the entries including: The logical address of the data currently being written to the buffer; and Write to the locked or unlocked state of the buffer.

4. The method according to claim 3, further comprising: Before locking the selected write buffer, the amount of accumulated data in the plurality of write buffers is checked by a controller associated with the nonvolatile memory in order to schedule the retrieval of data from the plurality of write buffers, including the selected write buffer, to the nonvolatile memory.

5. The method according to claim 4, further comprising: After the extraction is completed, the cache structure is updated to unlock the selected write buffer for further use.

6. The method according to claim 5, wherein, The re-update process includes marking the logical address of the data as invalid as part of unlocking the selected write buffer.

7. The method according to any one of claims 1 to 6, wherein, The retrieval of the contents of one or more locked write buffers from non-volatile memory corresponds to a single-step transfer of data from a shared memory buffer to non-volatile memory via a high-speed interface interconnected with peripheral components.

8. The method according to claim 1, further comprising: Register the base address and size of the cache structure associated with the shared memory buffer in the non-volatile memory.

9. A method for performing a read operation, the method comprising: The host detects the logical address corresponding to at least one write buffer of the shared memory buffer based on the cache structure within the shared memory buffer; as well as Direct access to the shared memory buffer by the host is permitted to transfer data from the at least one write buffer to the allocated read buffer, thereby enabling read operations defined by internal data transfers within the shared memory buffer.

10. The method according to claim 9, wherein, The access to the shared memory buffer is an access to main memory defined by internal direct memory access operations, without requiring data transfer through a high-speed interface interconnected with peripheral components.

11. The method of claim 9, further comprising: If the logical address corresponding to the at least one write buffer is unavailable, a read command is issued from the host to the non-volatile memory.

12. A computing system for hosting a client device, the client device including non-volatile memory, the computing system comprising: Shared memory buffer, including: Multiple write buffers are configured to accumulate data for non-volatile memory; and A cache structure, located within a shared memory buffer, is configured to track free write buffers among the plurality of write buffers within the shared memory buffer; and The processing circuit is configured as follows: At least one free write buffer is selected from the plurality of write buffers of the shared memory buffer by accessing the cache structure within the shared memory buffer; Send at least one logical address for the selected write buffer access from the cache structure to issue a write command to non-volatile memory; Receive a lock instruction for the selected write buffer from non-volatile memory, thereby updating the state of the selected write buffer within the cache structure; and Allows non-volatile memory to extract the contents of one or more locked write buffers, including the selected write buffer.

13. The system according to claim 12, wherein, The cache structure is a data structure configured to track the logical addresses of data within the plurality of write buffers and the state of the plurality of write buffers. For each write buffer, the data structure includes entries, the entries including: The logical address of the data currently being written to the buffer; and Write to the locked or unlocked state of the buffer.

14. The system of claim 12, further comprising: A controller, associated with nonvolatile memory, is configured to: examine the amount of accumulated data in the plurality of write buffers before locking the selected write buffer, in order to schedule the retrieval of data from the plurality of write buffers, including the selected write buffer, to the nonvolatile memory.

15. The system according to any one of claims 12 to 14, further comprising: The data transfer interface is configured for data exchange between a shared memory buffer and a non-volatile memory, wherein the retrieval of the contents of the one or more locked write buffers by the non-volatile memory corresponds to a single-step transfer of data through the data transfer interface.

16. A computing system for hosting client devices, the client devices being defined by non-volatile memory, the computing system comprising: Shared memory buffer, including: Multiple write buffers are configured to accumulate data for non-volatile memory; and A cache structure, located within a shared memory buffer, is configured to track free write buffers among the plurality of write buffers within the shared memory buffer; and The processing circuit is configured as follows: The logical address corresponding to at least one write buffer of the shared memory buffer is detected based on the cache structure within the shared memory buffer. Allocate a read buffer within the shared memory buffer; and Allows direct access by the application to the shared memory buffer to transfer data from the at least one write buffer to the allocated read buffer within the shared memory buffer, thereby enabling read operations.

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