A method and apparatus for designing a fence device

Abstract

The application provides a design method and device of a fence device, and relates to the technical field of integrated circuits. The method is used to solve the problems of long layout design time and low efficiency of a field effect device of a fence GAA structure. The method comprises the following steps: generating an MEOL dynamic link library according to a middle way MEOL capacitor model and a fence GAA layout library, wherein the GAA layout library is an integrated circuit device layout library of the fence GAA structure, and comprises a plurality of GAA layouts; the MEOL capacitor model is an MEOL model based on GAA device process design parameters; obtaining an RC process database of the GAA by calling the MEOL dynamic link library and a back-end BEOL capacitor model; performing 2.5D layout scanning on the GAA RC process database according to a current layout design, and obtaining RC parasitic parameters matched with the current layout design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a design method and device of a gate-all-around (GAA) device. BACKGROUND

[0002] With the development of integrated circuit technology, the gate-all-around (GAA) device has better gate control capability and stronger short channel effect inhibition than the single-gate planar structure and the three-gate FET of the fin (Fin) structure, and thus is a hot candidate for the next generation of field effect devices. Therefore, the layout design optimization of the GAA device has become a more difficult technical problem.

[0003] The existing layout design of the field effect device can be realized by the layout parasitic extraction (LPE) function of the electronic design automation (EDA) tool, for example, the field effect tube of the Fin structure. Specifically, a series of processes such as resistance capacitance (RC) process data modeling, production layout, and 2.5D parasitic extraction RC parameter can be performed.

[0004] However, since the FET of the GAA structure is more complex than the FET of the planar or Fin structure, the generated RC process database has a large capacity, the lookup table takes too long time, and the existing built-in layout design library cannot cover the actual GAA layout design, so the existing layout design efficiency of the GAAFET is relatively low. SUMMARY

[0005] The present application provides a design method and device of a gate-all-around (GAA) device, which solves the problem of long layout design time and low efficiency of the field effect device of the GAA structure.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, a design method of a gate-all-around (GAA) device is provided, which includes: generating a MEOL dynamic link library according to a middle MEOL capacitance model and a GAA layout library, wherein the GAA layout library is an integrated circuit device layout library of the GAA structure, includes a plurality of GAA layouts, and the MEOL capacitance model is a MEOL model based on GAA device process design parameters; obtaining a resistance capacitance (RC) process database of the GAA by calling the MEOL dynamic link library and a back BEOL capacitance model; and performing 2.5D layout scanning on the GAA RC process database according to a current layout design, to obtain RC parasitic parameters matched with the current layout design.

[0008] In the technical solution, a new GAA layout library is designed, and a dynamic MEOL capacitor link library is generated according to the MEOL capacitor model corresponding to the GAA layout in the GAA layout library. Therefore, when designing the GAA layout, a GAA layout in the GAA layout library can be called to obtain the resistance and capacitance values corresponding to the current layout design based on the GAA process database including the MEOL capacitor model and the BEOL capacitor model file. Therefore, the time for generating the RC parameters is saved, and the extraction efficiency of the RC parameters is improved. In addition, by designing a new GAA layout library, the layout design of the actual GAA is avoided due to the fact that the existing built-in layout library cannot cover the layout design of the actual GAA. Therefore, a series of iterative operations for repeatedly adjusting the precision of the 2.5D extraction tool to match the 3D electric field solver tool are avoided, and the delivery efficiency of the layout design is further improved.

[0009] In a possible design, the MEOL capacitor model is obtained by training a neural network. In the possible implementation, the MEOL capacitor model is obtained by training the neural network, so that the RC extraction efficiency of the GAA layout is improved.

[0010] In a possible design, before the MEOL dynamic link library is generated by compiling the MEOL capacitor model and the GAA layout library, the method further includes: obtaining the MEOL capacitor model by training a neural network based on a large number of GAA layout process sizes and test data or simulation data of the MEOL capacitor corresponding to the GAA layout obtained by three-dimensional Monte Carlo simulation of the GAA layout.

[0011] In the possible implementation, the MEOL capacitor model is obtained by training a large number of GAA layout process sizes and test data or simulation data of the MEOL capacitor corresponding to the GAA layout based on a neural network algorithm. Therefore, the MEOL capacitor data corresponding to any GAA layout design in the GAA layout library can be quickly matched based on the MEOL capacitor model, and the RC extraction efficiency and extraction precision of the GAA layout are effectively improved.

[0012] In a possible design, the BEOL capacitor model includes a BEOL parasitic capacitor lookup table based on the process size of the interconnection line layout in the GAA layout.

[0013] In a possible design, before the MEOL dynamic link library is generated by compiling the MEOL capacitor model and the GAA layout library, the method further includes: obtaining the BEOL parasitic capacitor lookup table corresponding to a plurality of GAA layouts by simulating the BEOL capacitor model file based on the process design parameters of the interconnection line layout in the actual GAA device through a three-dimensional electric field solver.

[0014] In a possible design, before the MEOL dynamic link library is generated according to the MEOL capacitor model and the GAA layout library, the method further includes: designing a plurality of GAA layout patterns according to layout design process rules and actual requirements, and the GAA layout library includes the plurality of GAA layout patterns.

[0015] In a possible design, the GAA layout library includes at least one of the following GAA layouts: a GAA layout in which gate vias are distributed in a source or drain position area, a GAA layout in which vias are respectively arranged at both ends of a gate, a GAA layout in which the number of metal lines is increased, a GAA layout in which the number of metal lines is reduced, a GAA layout with a large gate pitch, and a GAA layout with an elongated gate end.

[0016] In the possible implementation, the GAA layout pattern can be designed according to layout design process rules and actual requirements, for example, the GAA layout in which gate vias are distributed in a source or drain position area can effectively save layout area, the GAA layout in which vias are respectively arranged at both ends of a gate can reduce the effective resistance of the gate end, the GAA layout in which the number of metal lines is increased or reduced can optimize the resistance or resistance of the source end and the drain end, the GAA layout with a large gate pitch can increase the driving current, and the GAA layout with an elongated gate end can effectively increase the threshold voltage and reduce the leakage.

[0017] In a possible design, the MEOL capacitor includes at least one of the following: a front and back top edge capacitor of a gate to a nanowire or a nanosheet, an up and down top edge capacitor of a gate to a nanowire or a nanosheet, a longitudinal coupling capacitor of a gate to a source or a drain, a longitudinal coupling capacitor of a gate to a source or drain via, a capacitor of a gate to a substrate, a capacitor of a gate to a metal line 1, a coupling capacitor between metal line 2 layers, a capacitor between metal line 1 and metal line 2, and a capacitor of metal line 1 to metal line 2.

[0018] In a possible design, the GAA device process design parameter includes at least one of the following: a height, a width, and a thickness of a nanosheet or a nanowire, a height, a width, and a thickness of a gate, a width, a length, and a thickness of a metal interconnection line, a thickness and a dielectric constant of a dielectric layer.

[0019] In a second aspect, a device for designing a gate-all-around (GAA) device is provided. The device includes a compiling module configured to generate a MEOL dynamic link library by compiling a middle-of-line (MEOL) capacitance model and a GAA layout library, wherein the GAA layout library is a layout library of an integrated circuit device of a GAA structure, and includes a plurality of GAA layouts, and the MEOL capacitance model is a MEOL model based on process design parameters of the GAA device; an RC extraction module configured to obtain a resistance-capacitance (RC) process database of the GAA by calling the MEOL dynamic link library and a back-end-of-line (BEOL) capacitance model; and a layout scanning module configured to perform 2.5D layout scanning on the GAA RC process database according to a current layout design, to obtain RC parasitic parameters matched with the current layout design.

[0020] In a possible design, the MEOL capacitance model is obtained by training a neural network.

[0021] In a possible design, the device further includes a MEOL capacitance model training module configured to train a neural network based on a large number of process sizes of GAA layouts, and test data of MEOL capacitances corresponding to the GAA layouts or simulation data of the MEOL capacitances obtained by performing three-dimensional Monte Carlo simulation on the GAA layouts, to obtain the MEOL capacitance model.

[0022] In a possible design, the BEOL capacitance model includes a BEOL parasitic capacitance lookup table based on process sizes of interconnection line layouts in the GAA layouts.

[0023] In a possible design, the device further includes a BEOL capacitance model generation module configured to simulate a BEOL capacitance model file by a three-dimensional electric field solver based on process design parameters of interconnection line layouts in an actual GAA device, to obtain a plurality of BEOL parasitic capacitance lookup tables corresponding to the GAA layouts.

[0024] In a possible design, the device further includes a GAA layout generation module configured to design a plurality of GAA layout patterns according to layout design process rules and actual requirements, and the GAA layout library includes the plurality of GAA layout patterns.

[0025] In a possible design, the GAA layout library includes at least one of the following GAA layouts: a GAA layout in which gate vias are distributed in a source or drain position region, a GAA layout in which vias are respectively arranged at both ends of a gate, a GAA layout in which a number of metal line windings is increased, a GAA layout in which a number of metal line windings is reduced, a GAA layout with a large gate pitch, and a GAA layout with a gate end elongated.

[0026] In a possible design, the MEOL capacitance includes at least one of the following: a front-back top edge capacitance of the gate to the nanowire or nanosheet, an up-down top edge capacitance of the gate to the nanowire or nanosheet, a longitudinal coupling capacitance of the gate to the source or drain, a longitudinal coupling capacitance of the gate to the source or drain via, a capacitance of the gate to the substrate, a capacitance of the gate to the metal line 1, a coupling capacitance between the metal line 2 and the same layer, a capacitance between the metal line 1 and the metal line 2, and an edge capacitance of the metal line 1 to the metal line 2.

[0027] In a possible design, the GAA device process design parameter includes at least one of the following: a height, a width, and a thickness of the nanosheet or nanowire, a height, a width, and a thickness of the gate, a width, a length, and a thickness of the metal interconnection line, a thickness and a dielectric constant of the dielectric layer.

[0028] In a third aspect, an electronic device is provided, and the electronic device includes a processor and a memory; and the processor is configured to execute instructions stored in the memory to implement the method in any one of the first aspect.

[0029] In a fourth aspect, a computer-readable storage medium is provided, and the computer-readable storage medium stores instructions, when the instructions are executed by a computer or a processor, the computer or the processor can execute the method in any one of the first aspect.

[0030] In a fifth aspect, a computer program product is provided, and when the computer program product runs on a computer, the computer program product enables the computer to execute the method in any one of the first aspect.

[0031] It can be understood that any one of the design apparatuses of the gate-all-around device, the electronic device, the computer-readable storage medium, and the computer program product provided above can be used to execute the corresponding method provided above, and therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding method provided above, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A structure diagram of a GAA device provided by an embodiment of the present application;

[0033] Figure 2 A structure schematic diagram of a processing apparatus provided by an embodiment of the present application;

[0034] Figure 3 A flowchart of a design method of a gate-all-around device provided by an embodiment of the present application;

[0035] Figure 4 A structure schematic diagram of a neural network provided by an embodiment of the present application;

[0036] Figure 5 A design flow chart of a gate-all-around device provided by an embodiment of the present application is provided.

[0037] Figures 6 to 11 A layout design schematic diagram of a gate-all-around device provided by an embodiment of the present application is provided.

[0038] Figure 12 A schematic diagram of a design device of a gate-all-around device provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0039] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0040] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or having more advantages than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0042] First, the integrated circuit device of the gate-all-around GAA structure applied in the present application and the technical terms involved are briefly introduced.

[0043] Gate-all-around device: refers to a multi-gate three-dimensional field effect transistor, whose gate completely surrounds the channel region of a nanowire or a nanosheet, so that the device has stronger driving current, thereby effectively suppressing the short channel effect.

[0044] Parasitic capacitance: is the capacitance between electronic elements or between circuit modules in a circuit due to close proximity. For example, in the design of an integrated circuit, no capacitance is designed at a certain position, but due to the mutual capacitance effect between wires, the parasitic capacitance refers to the capacitance generated due to the mutual capacitance effect, also known as stray capacitance.

[0045] Since integrated circuits are fabricated layer by layer by so-called planar process, the process design of each layer of dielectric, including height, width, thickness, length or dielectric constant, has a great impact on the performance of GAA devices, such as parasitic and coupling capacitances in GAA device structures. Therefore, the chip design of integrated circuits needs to define detailed process dimensions, perform layout design and continue layout simulation, etc.

[0046] For logic devices of field effect transistors, first, the area for fabricating transistors needs to be divided on the silicon substrate, then ion implantation is performed to realize N-type and P-type regions, second, the gate is made, and then ion implantation is performed again to complete the source and drain of each transistor. The above part of the process flow is to realize N-type and P-type field effect transistors on the silicon substrate, which is also called Front End Of Line (FEOL) process.

[0047] Corresponding to FEOL is Back-End-Of-Line (BEOL) and Mid-End-Of-Line (MEOL) process. Among them, BEOL is actually to build several layers of conductive metal lines, and the metal lines between different layers are connected by columnar metal (via). For example, copper (Cu) lines can be selected as conductive metal, so BEOL can also be called Cu interconnect. These copper lines are responsible for connecting the transistors on the substrate according to the design requirements to realize specific functions.

[0048] Common gate-all-around devices can have a structure as shown in Figure 1 , including nanosheet GAA device 1 and nanowire GAA device 2. As shown in Figure 1 , BEOL can include metal layer Metal1 and metal layer Metal2, and BEOL capacitance can include: coupling capacitance Cc between Metal2, covering capacitance Ca between Metal1 and Metal2, edge capacitance Cf from Metal2 to Metal1, etc.

[0049] MEOL refers to the structure surrounding the nanowire Nanowire or nanosheet Nanosheet, as shown in Figure 1As shown, the middle channel can refer to the structure below Metal1. Therefore, the middle channel capacitance is strongly related to the GAA device structure. Middle channel parasitic capacitances can include: the front and rear top edge capacitances Cfo1 from the gate to the nanosheet or nanowire, the top and bottom top edge capacitances Cfo2 from the gate to the nanosheet or nanowire, the vertical coupling capacitances Cco1 from the gate to the source and drain, the vertical coupling capacitance Cco2 from the gate to the metal via VIA1, the capacitance Cgb from the gate to the substrate, and the capacitance Cgm from the gate to Metal1, etc.

[0050] EDA tools are design software aids and programmable chip aids. They have powerful functions and can generally be used for circuit design and simulation. They can also perform automatic placement and routing of chip layouts and output various netlist files for interconnection with third-party software. EDA tools can be broadly classified into three categories: chip design aids, programmable chip design aids, and system design aids.

[0051] Layout Parasitic Extraction (LPE) extracts device process parameters, interconnections, parasitic resistances, and capacitances from a chip-level layout, generating a netlist file. This netlist file can then be used to reconstruct the circuit diagram. Additionally, LPE compares the layout with the current circuit diagram to identify incorrect resistors and capacitors, generating a resistor / capacitor lookup table.

[0052] The 2.5D algorithm is a graph matching extraction algorithm technique that lies between two-dimensional and three-dimensional extraction modes. It is often used for large-scale parasitic extraction of landmasses.

[0053] Figure 2 This is a schematic diagram of the structure of a processing device 200 provided in an embodiment of this application. When the processing device 200 has the function of the electronic device described in the embodiment of this application, the processing device 200 can be an electronic device or a chip or system on a chip in an electronic device.

[0054] like Figure 2 As shown, the processing device 200 may include a processor 201, a communication line 202, and a communication interface 203. Furthermore, the processing device 200 may also include a memory 204. The processor 201, memory 204, and communication interface 203 can be connected via the communication line 202.

[0055] The processor 201 can be a central processing unit (CPU), a general-purpose processor network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device, or any combination thereof. The processor 201 can also be other devices with processing functions such as circuits, devices, or software modules, etc.

[0056] The communication line 202 is used to transmit information between the components included in the processing apparatus 200.

[0057] The communication interface 203 is used to communicate with other devices or communication networks. The communication network can be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 203 can be an interface circuit, a pin, a radio frequency module, a transceiver, or any device capable of communication.

[0058] The memory 204 is used to store instructions. The instructions can be computer programs.

[0059] The memory 204 can be a read-only memory (ROM) or other type of static storage device that can store static information and / or instructions, or a random access memory (RAM) or other type of dynamic storage device that can store information and / or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magneto-optical disk storage, a magnetic disk storage medium, or other magnetic storage device, optical disk storage including a compact disk, a laser disc, an optical disc, a digital versatile disc, or a Blu-ray disc, etc.

[0060] It should be noted that the memory 204 can exist independently of the processor 201, or can be integrated with the processor 201. The memory 204 can be used to store instructions or program codes or some data, etc. The memory 204 can be located in the processing apparatus 200 or outside the processing apparatus 200, without limitation. The processor 201 is used to execute the instructions stored in the memory 204 to implement the methods provided by the embodiments described below.

[0061] In an example, the processor 201 can include one or more CPUs, for example Figure 2 CPU0 and CPU1 in FIG. 1.

[0062] As an optional implementation, the processing apparatus 200 includes multiple processors, for example, in addition to the processor 201 in FIG. 1, the processor 207 can also be included. Figure 2

[0063] As an optional implementation, the processing apparatus 200 further includes an output device 205 and an input device 206. Exemplarily, the input device 206 is a keyboard, a mouse, a microphone, a joystick or the like, and the output device 205 is a display screen, a speaker or the like.

[0064] It should be noted that the processing apparatus 200 can be a desktop computer, a laptop computer, a network server, a mobile phone, a tablet computer, a wireless terminal, an embedded device, a chip system or an electronic device having a similar structure as shown in FIG. 1. In addition, Figure 2 the constituent structures shown in FIG. 1 do not constitute a limitation on the processing apparatus, and the processing apparatus can include more or fewer components than those shown in the figure, or combine certain components, or different component arrangements. Figure 2 Figure 2

[0065] In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0066] The embodiments of the present application provide a design method of a gate-all-around device, which is applied to a processing apparatus or an electronic device capable of realizing the design of the gate-all-around device, and the like. Specifically, part or all of the work flow can be realized through the EDA tool and / or other layout design and layout simulation tool configured by the processing apparatus or the electronic device, which is not limited in the present application.

[0067] As shown in FIG. 1, the method can include: Figure 3

[0068] S301: generating a MEOL dynamic link library according to a middle way MEOL capacitor model and a gate-all-around GAA layout library.

[0069] The GAA layout library is a layout pattern library of an integrated circuit device including a gate-all-around structure, and the GAA layout library includes multiple GAA layout patterns of different layouts and different process sizes. Unlike the existing EDA built-in layout, for example, including a single gate or a fin three-gate structure, the GAA layout library in the embodiments of the present application is multiple GAA layouts newly designed and generated based on the actual GAA device design process, for example, including the GAA layout pattern shown in FIG. 2. Figure 1 ​​​​The conventional GAA layout of the nanosheet and nanowire, and other improved GAA layout. Specifically, several improved GAA layout patterns will be described in detail below, and will not be repeated here.

[0070] Based on the above GAA layout library, the MEOL capacitance model of the present application is a MEOL model based on the process design parameters of the GAA device in the GAA layout library. That is, unlike the existing MEOL parasitic capacitance model file of single-gate or fin structure, the MEOL capacitance model in the present application is based on the design and process size of the newly designed GAA layout layout, and the obtained MEOL capacitance model.

[0071] In an embodiment, the MEOL parasitic capacitance model can be obtained according to neural network training. Specifically, the MEOL capacitance model can be obtained through neural network algorithm according to a large number of process parameters and capacitance resistance parameters of layout design through data training.

[0072] Specifically, according to a large number of GAA layout patterns in the GAA layout library, a large number of process parameters of the GAA layout and the actual measured MEOL capacitance test data corresponding to the GAA layout, or the 3D Monte Carlo simulation of the GAA layout design to obtain the MEOL capacitance simulation data, etc. Through the parameter training of the neural network, the MEOL capacitance model is obtained. For example, the MEOL capacitance formula can be obtained, and when designing a certain GAA layout, the process parameters of the GAA layout can be combined with the corresponding MEOL capacitance formula of the GAA layout, so as to obtain the capacitance resistance value and other parameters corresponding to the GAA layout.

[0073] As shown in the example, Figure 4 As shown, the input layer of the neural network inputs a plurality of GAA layout designs, wherein any GAA layout can include its layout process size, such as the height, width, thickness of nanosheet or nanowire, the height, width, thickness of the gate, the width, length, thickness of the metal interconnection line, the thickness of the dielectric layer, the dielectric constant and other process design parameters. For example, it can include Figure 4 The parameters marked in the NSL, NSW, NST, GATET, GATEW, GMS, TCT, TCL and TCW in the figure. After the operation of the MEOL capacitance model of the neural network, the output layer can obtain all the MEOL capacitance values of the GAA layout, such as Figure 4The front and back top edge capacitance Cfo1 of the gate to the nanosheet or nanowire, the upper and lower top edge capacitance Cfo2 of the gate to the nanosheet or nanowire, the longitudinal coupling capacitance Cco1 of the gate to the source and drain, the longitudinal coupling capacitance Cco2 of the gate to the metal via VIA1, the capacitance Cgb of the gate to the substrate, the capacitance Cgm of the gate to Metal1, and the like.

[0074] The MEOL dynamic link library refers to a file library generated by compiling according to the MEOL capacitance model and the gate-all-around GAA layout library. It is generally generated by an interconnect technology profile (ITP). The ITP describes in detail the process parameters such as the size, shape of the MEOL device, the width, thickness of the BEOL interconnect line, and the dielectric constant value of the dielectric layer.

[0075] S302: Obtain the resistance-capacitance RC process database of the GAA by calling the MEOL dynamic link library and the back-end BEOL capacitance model.

[0076] The BEOL capacitance model is a BEOL model based on the process design parameters of the GAA device, and the BEOL capacitance model includes a BEOL parasitic capacitance lookup table based on the interconnect line layout process size in the GAA layout.

[0077] Specifically, the back-end BEOL capacitance model can be a series of BEOL parasitic capacitance lookup tables under different GAA layout patterns obtained by calling a 3D field solver to simulate the actual BEOL parasitic model file ITP according to the process parameters provided by the device manufacturer, combined with process fluctuation parameters. That is, the BEOL capacitance model includes BEOL capacitance parameters under different GAA layout patterns, and can also be a parasitic model file obtained according to the interconnect line layout process size based on the BEOL capacitance in the actual GAA device combined with process fluctuation parameters.

[0078] The EDA tool can perform fitting by calling the MEOL dynamic link library and the BEOL capacitance model to generate a brand new GAA capacitance-resistance RC process database.

[0079] S303: Perform 2.5D layout scanning on the GAARC process database according to the current layout design to obtain RC parasitic parameters matched with the current layout design, and perform post-layout simulation.

[0080] The current layout design is a pattern currently designed for GAA layout design, a layout pattern in the GAA layout library, or a layout obtained by fine-tuning based on a layout pattern in the GAA layout library.

[0081] The obtained GAARC process database is scanned according to the current layout design to obtain a corresponding capacitance-resistance value or a capacitance netlist. Thus, the current layout design can be simulated and manufactured according to the obtained resistance-capacitance value.

[0082] The post-layout simulation refers to simulation of parasitic parameters and interconnection delay parameters in the extracted circuit netlist after the layout design is completed, analysis of the circuit, and ensuring that the circuit meets the design requirements. If the post-simulation can obtain the expected result, the layout data can be directly delivered to the layout manufacturing link.

[0083] The embodiment of the application generates a dynamic MEOL capacitance link library by designing a new GAA layout library and obtaining a MEOL capacitance model corresponding to the GAA layout from the GAA layout library. Thus, when a new GAA layout is designed, a GAARC process database including a MEOL capacitance model and a BEOL capacitance model file can be called based on a pre-configured GAA layout pattern in the GAA layout library, 2.5D layout scanning is performed, and a resistance-capacitance RC parasitic parameter corresponding to the current layout design is obtained. The overall layout design process can be as shown in Figure 5 Further, post-layout simulation can be performed. Thus, the time for generating RC parameters is saved, and the extraction efficiency of RC parameters is improved. In addition, by designing a new GAA layout library, the actual GAA layout design cannot be covered by the existing built-in layout library, thereby avoiding a series of iterative operations for repeatedly adjusting the precision of the 2.5D extraction tool to match the 3D electric field solver tool, and further improving the delivery efficiency of the layout design.

[0084] In an embodiment, a large number of optimized GAA layout designs conforming to design rules and design requirements are designed according to layout design process rules and actual requirements, for RC parasitic modeling and layout extraction scanning. The GAA layout library can include a large number of GAA layout patterns. Next, several GAA layout designs are introduced.

[0085] As shown in Figure 6 , two different GAA layout designs are shown. As shown in the layout of GAA1, the via VG of the gate Gate can be at the position shown in Figure 6 , that is, the position of the non-source distribution.

[0086] In another embodiment, a high-density GAA layout as shown in Figure 6 may also be designed, such as GAA2 as shown in Figure 6 . The via VG of the gate Gate can be laid out in the active region, i.e. in the range of the source layout as shown in Figure 6 , so as to save the layout area.

[0087] In an embodiment, a low gate resistance GAA layout as shown in Figure 7 may be designed, i.e. the via VG can be introduced at both ends of the gate Gate of the GAA device, so as to reduce the effective resistance of the gate end.

[0088] In an embodiment, a low source-drain resistance GAA layout as shown in Figure 8 may be designed, e.g. by increasing the number of windings of Metal1, so as to optimize the resistance of the source end and the drain end.

[0089] In an embodiment, a low source-drain capacitance GAA layout as shown in Figure 9 may be designed, e.g. by reducing the number of windings of Metal1, so as to optimize the capacitance of the source end and the drain end.

[0090] In an embodiment, a large gate pitch GAA layout as shown in Figure 10 may be designed, by increasing the gate pitch, so as to increase the driving current. For example, the value of the gate pitch as indicated in Figure 10 may be increased.

[0091] In an embodiment, a gate end elongation GAA layout as shown in Figure 11 may be designed, by adjusting the amount of the gate end elongation, so as to increase the threshold voltage and reduce the leakage. For example, the values of the gate end elongation 1 and the gate end elongation 2 as indicated in Figure 11 may be adjusted, specifically, the values of the gate end elongation 1 and the gate end elongation 2 can be increased.

[0092] In addition, based on the above embodiments, the application further provides a design device for a gate-all-around device, as shown in Figure 12 , the device 1200 comprises a compiling module 1201, an RC extraction module 1202 and a layout scanning module 1203.

[0093] The compiling module 1201 is configured to generate a MEOL dynamic link library by compiling a MEOL capacitance model and a gate-all-around GAA layout library, wherein the GAA layout library is a gate-all-around GAA structure integrated circuit device layout library comprising a plurality of GAA layouts, and the MEOL capacitance model is a MEOL model based on GAA device process design parameters.

[0094] The RC extraction module 1202 is configured to obtain a GAA resistance-capacitance (RC) process database by calling a MEOL dynamic link library and a BEOL capacitance model.

[0095] The layout scanning module 1203 is configured to perform 2.5D layout scanning on the GAARC process database according to a current layout design to obtain RC parasitic parameters matched with the current layout design.

[0096] In an embodiment, the MEOL capacitance model is obtained by neural network training.

[0097] In an embodiment, the apparatus 1200 further comprises a MEOL capacitance model training module configured to train a MEOL capacitance model by neural network training based on a large number of GAA layout process sizes and test data of MEOL capacitance corresponding to the GAA layout or simulation data of MEOL capacitance obtained by performing three-dimensional Monte Carlo simulation on the GAA layout.

[0098] In an embodiment, the BEOL capacitance model comprises a BEOL parasitic capacitance lookup table based on interconnection line layout process sizes in a GAA layout.

[0099] In an embodiment, the apparatus 1200 further comprises a BEOL capacitance model generation module configured to simulate a BEOL capacitance model file by a three-dimensional electric field solver to obtain a BEOL parasitic capacitance lookup table corresponding to a plurality of GAA layouts based on process design parameters of interconnection line layouts in actual GAA devices.

[0100] In an embodiment, the apparatus 1200 further comprises a GAA layout generation module configured to design a plurality of GAA layout patterns according to layout design process rules and actual requirements, and the GAA layout library comprises the plurality of GAA layout patterns.

[0101] In an embodiment, the GAA layout library comprises at least one of the following GAA layouts: a GAA layout in which gate vias are distributed in a source or drain position area, a GAA layout in which vias are arranged at both ends of a gate, a GAA layout in which the number of metal line windings is increased, a GAA layout in which the number of metal line windings is reduced, a GAA layout with a large gate pitch, and a GAA layout with a gate end elongation.

[0102] In one embodiment, the MEOL capacitor includes at least one of the following: gate-to-nanowire or nanosheet front and rear top edge capacitance, gate-to-nanowire or nanosheet top and bottom edge capacitance, gate-to-source or drain longitudinal coupling capacitance, gate-to-source or drain via capacitance, gate-to-substrate capacitance, gate-to-metal line 1 capacitance, metal line 2 interlayer coupling capacitance, metal line 1 and metal line 2 capacitance, and metal line 1 to metal line 2 edge capacitance.

[0103] In one embodiment, the process design parameters of the GAA device include at least one of the following: the height, width, and thickness of the nanosheet or nanowire; the height, width, and thickness of the gate; the width, length, and thickness of the metal interconnect; and the thickness and dielectric constant of the dielectric layer.

[0104] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0105] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0106] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of designing a fence device, characterized by, The method comprises: According to the middle way MEOL capacitor model and the surrounding fence GAA layout library, a MEOL dynamic link library is compiled, wherein the GAA layout library is an integrated circuit device layout library of a surrounding fence GAA structure, and comprises a plurality of GAA layouts; and the MEOL capacitor model is a MEOL model based on the GAA device process design parameters; An RC process database of the GAA is obtained by calling the MEOL dynamic link library and a back-end BEOL capacitor model; According to the current layout design, 2.5D layout scanning is performed on the RC process database of the GAA, so as to obtain RC parasitic parameters matched with the current layout design.

2. The method of claim 1, wherein, The MEOL capacitor model is obtained through neural network training.

3. The method according to claim 1 or 2, characterized in that, Before the MEOL dynamic link library is compiled according to the MEOL capacitor model and the GAA layout library, the method further comprises: According to a large number of GAA layout process sizes, and test data of MEOL capacitors corresponding to the GAA layouts or MEOL capacitor simulation data obtained by performing three-dimensional Monte Carlo simulation on the GAA layouts, a MEOL capacitor model is obtained through neural network training.

4. The method according to any one of claims 1 to 3, characterized in that, The BEOL capacitor model comprises a BEOL parasitic capacitor lookup table based on interconnection line layout process sizes in the GAA layout.

5. The method according to any one of claims 1 to 4, characterized in that, Before the MEOL dynamic link library is compiled according to the MEOL capacitor model and the GAA layout library, the method further comprises: According to process design parameters of interconnection line layouts in an actual GAA device, a BEOL capacitor model file is simulated by a three-dimensional electric field solver, so as to obtain a BEOL parasitic capacitor lookup table corresponding to a plurality of GAA layouts.

6. The method according to any one of claims 1 to 5, characterized in that, Before the MEOL dynamic link library is compiled according to the MEOL capacitor model and the GAA layout library, the method further comprises: According to layout design process rules and actual requirements, a plurality of GAA layout patterns are designed, and the GAA layout library comprises the plurality of GAA layout patterns.

7. The method according to any one of claims 1 to 6, characterized in that, The GAA layout library comprises at least one of the following GAA layouts: a GAA layout in which gate vias are distributed in a source or drain position area, a GAA layout in which vias are respectively arranged at both ends of a gate, a GAA layout in which the number of metal line windings is increased, a GAA layout in which the number of metal line windings is reduced, a GAA layout with a large gate pitch, and a GAA layout with a gate end elongation.

8. The method according to any one of claims 1 to 7, characterized in that, The MEOL capacitor comprises at least one of: a front and back top edge edge capacitor of a gate to a nanowire or a nanosheet, an up and down top edge edge capacitor of the gate to the nanowire or the nanosheet, a longitudinal coupling capacitor of the gate to a source or a drain, a longitudinal coupling capacitor of the gate to a source or drain via, a capacitor of the gate to a substrate, a capacitor of the gate to a metal line 1, a coupling capacitor between metal line 2 same layers, a capacitor between the metal line 1 and the metal line 2, and a capacitor of the metal line 1 to the metal line 2.

9. The method according to any one of claims 1 to 8, characterized in that, The GAA device process design parameters comprise at least one of: Height, width, thickness of nanosheet or nanowire, height, width, thickness of gate, width, length, thickness of metal interconnect line, thickness of dielectric layer, dielectric constant.

10. A design apparatus of a fence device, characterized by comprising: The device comprises: A compiling module configured to generate a MEOL dynamic link library by compiling a MEOL capacitance model and a GAA layout library, wherein the GAA layout library is a layout library of an integrated circuit device of a gate-all-around (GAA) structure, and comprises a plurality of GAA layouts, and the MEOL capacitance model is a MEOL model based on GAA device process design parameters; An RC extraction module configured to obtain an RC process database of a GAA by calling the MEOL dynamic link library and a BEOL capacitance model; A layout scanning module configured to perform 2.5D layout scanning on the RC process database of the GAA according to a current layout design, and obtain RC parasitic parameters matched with the current layout design.

11. The apparatus of claim 10, wherein, The MEOL capacitance model is obtained by neural network training.

12. The apparatus of claim 10 or 11, wherein, The device further comprises: A MEOL capacitance model training module configured to train the MEOL capacitance model by neural network based on a large number of GAA layout process sizes, and test data of MEOL capacitance corresponding to the GAA layouts or simulation data of MEOL capacitance obtained by three-dimensional Monte Carlo simulation on the GAA layouts.

13. The apparatus of any of claims 10-12, wherein, The BEOL capacitance model comprises a BEOL parasitic capacitance lookup table based on interconnect line layout process sizes in the GAA layout.

14. The apparatus of any one of claims 10-13, wherein, The device further comprises: A BEOL capacitance model generation module configured to simulate a BEOL capacitance model file by a three-dimensional electric field solver to obtain a BEOL parasitic capacitance lookup table corresponding to a plurality of GAA layouts according to process design parameters of interconnect line layouts in an actual GAA device.

15. The apparatus of any of claims 10-14, wherein, The device further comprises: A GAA layout generation module configured to design a plurality of GAA layout patterns according to layout design process rules and actual requirements, and the GAA layout library comprises the plurality of GAA layout patterns.

16. The apparatus of any one of claims 10-15, wherein, The GAA layout library comprises at least one of the following GAA layouts: A GAA layout in which gate vias are distributed in a source or drain position area, a GAA layout in which vias are arranged at both ends of a gate, a GAA layout in which the number of metal line windings is increased, a GAA layout in which the number of metal line windings is reduced, a GAA layout with a large gate pitch, and a GAA layout with a gate end elongation.

17. The apparatus of any of claims 10-16, wherein, The MEOL capacitance comprises at least one of the following: Capacitance from a gate to front and back top edge edges of a nanowire or nanosheet, capacitance from a gate to upper and lower top edge edges of a nanowire or nanosheet, longitudinal coupling capacitance from a gate to a source or drain, longitudinal coupling capacitance from a gate to a source or drain via, capacitance from a gate to a substrate, capacitance from a gate to a metal line 1, coupling capacitance between metal line 2 in the same layer, capacitance between metal line 1 and metal line 2, and edge capacitance from metal line 1 to metal line 2.

18. The apparatus of any of claims 10-17, wherein, The GAA device process design parameters comprise at least one of the following: Height, width, thickness of nanosheet or nanowire, height, width, thickness of gate, width, length, thickness of metal interconnect, thickness, dielectric constant of dielectric layer.

19. An electronic device, comprising: The electronic device comprises: a processor and a memory; wherein the processor is configured to execute instructions stored in the memory to implement the method of any one of claims 1-9.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, when the instructions are executed by a computer or a processor, the computer or the processor can execute the method of any one of claims 1-9.

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