Display devices

Abstract

This application relates to a display device. The display device includes: a display panel having a first panel region, a curved region, and a second panel region arranged along a first direction therein; and a support layer below the first panel region of the display panel, wherein the curved region of the display panel is curved toward the lower portion of the support layer, and a portion of the support layer is located between the first panel region and the second panel region. The display panel also includes a first alignment mark in the first panel region, and a first alignment opening overlapping the first alignment mark is defined in the support layer. In the thickness direction of the display panel, the first alignment opening does not overlap with the second panel region, the first alignment opening is spaced apart from the edge of the support layer, and the first alignment opening is completely surrounded by the support layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0103871, filed on August 19, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In this document, some aspects of embodiments of the present disclosure relate to display devices with relatively enhanced product reliability. Background Technology

[0004] Display devices display various images on a screen to provide information to users. Typically, display devices display information within a designated screen area. Recently, flexible display devices, including foldable flexible display panels, have been developed. Unlike rigid display devices, flexible display devices are generally designed to fold, roll, or bend without damaging or destroying the display. Flexible display devices, whose shape can be changed in various ways, are portable and not limited to existing screen sizes, thus improving user convenience and experience.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Some aspects of embodiments of this disclosure include display devices with relatively improved product reliability.

[0007] According to some embodiments of the present invention, a display device includes a display panel and a support layer. A first panel region, a curved region, and a second panel region are defined in the display panel along a first direction. The support layer is located below the first panel region of the display panel. The curved region of the display panel may be curved toward the lower part of the support layer. A portion of the support layer may be located between the first panel region and the second panel region. The display panel may include a first alignment mark in the first panel region. A first alignment opening overlapping the first alignment mark may be defined in the support layer. In the thickness direction of the display panel, the first alignment opening may not overlap with the second panel region. The first alignment opening may be spaced apart from the edge of the support layer and may be completely surrounded by the support layer.

[0008] According to some embodiments, the first alignment opening may be spaced apart from the second panel region in a second direction intersecting the first direction.

[0009] According to some embodiments, there may be multiple first alignment openings, and the multiple first alignment openings may be spaced apart, with the second panel area inserted between the multiple first alignment openings.

[0010] According to some implementations, there may be multiple first alignment marks, and the display panel may be aligned with the support layer such that the multiple first alignment marks overlap with the multiple first alignment openings respectively.

[0011] According to some embodiments, the support layer may include a first edge and a second edge extending along a first direction, and a third edge and a fourth edge extending along a second direction intersecting the first direction, wherein the bending region may bend around the fourth edge, and the first alignment opening may be closest to the fourth edge among the first edge and the fourth edge.

[0012] According to some embodiments, the display panel may further include a second alignment mark in a first panel area, wherein a second alignment opening overlapping the second alignment mark may be defined in a support layer, and the second alignment opening may be closest to the first edge among the first edge to the fourth edge.

[0013] According to some embodiments, the second alignment opening may be spaced apart from the first edge, and the second alignment opening may be completely surrounded by the support layer.

[0014] According to some embodiments, the second alignment opening may be connected to the first edge, and the first edge and the sidewall defining the second alignment opening may be connected to each other.

[0015] According to some implementations, the foldable area may be defined in the first panel area, and multiple openings may be defined in the area of ​​the support layer that overlaps with the foldable area.

[0016] According to some implementations, the first alignment opening may be spaced apart from a plurality of openings in a first direction.

[0017] According to some embodiments, the display panel may include: a base layer; a circuit layer on the base layer and including a plurality of metal layers; a light-emitting element layer on the circuit layer; and an encapsulation layer on the light-emitting element layer; wherein the first alignment mark may be on the same layer as any of the plurality of metal layers.

[0018] According to some embodiments, the sidewall defining the first alignment opening may have a closed curve shape.

[0019] According to some embodiments of the present invention, a display device includes a display panel and a support layer. A first panel region, a curved region, and a second panel region are defined in the display panel along a first direction. The support layer is located below the first panel region of the display panel. The curved region of the display panel may be curved toward the lower part of the support layer. A portion of the support layer may be located between the first panel region and the second panel region. A plurality of alignment openings may be defined in the support layer. The distance between the plurality of alignment openings in a second direction intersecting the first direction is greater than the width of the second panel region in the second direction. Each of the plurality of alignment openings may be completely surrounded by the support layer.

[0020] According to some implementations, the plurality of alignment openings may be defined as spaced apart, and the second panel area is interposed between the plurality of alignment openings.

[0021] According to some embodiments, sidewalls defining a plurality of aligned openings may be defined in the support layer. Each of the sidewalls may have a closed curved shape.

[0022] According to some implementations, the display panel may include a plurality of alignment marks in a first panel area, and the plurality of alignment marks may overlap with a plurality of alignment openings respectively.

[0023] According to some embodiments, the display panel may further include: a base layer; a circuit layer on the base layer and including a plurality of metal layers; a light-emitting element layer on the circuit layer; and an encapsulation layer on the light-emitting element layer; and each of the plurality of alignment marks may be on the same layer as any of the plurality of metal layers.

[0024] According to some implementations, multiple alignment openings can be defined adjacent to the edge of the support layer, and the curved area of ​​the display panel can be curved around the edge of the support layer at the same time.

[0025] According to some implementations, the foldable area may be defined in the first panel area, and multiple openings may be defined in the area of ​​the support layer that overlaps with the foldable area of ​​the display panel.

[0026] According to some implementations, the plurality of alignment openings may be spaced apart from the plurality of openings in a first direction. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of embodiments of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate aspects of some embodiments of the inventive concept and, together with the description, serve to explain the principles of embodiments of the inventive concept. In the drawings:

[0028] Figure 1A and Figure 1BThis is a perspective view of an electronic device according to some embodiments of the present invention;

[0029] Figure 2 This is an exploded perspective view of an electronic device according to some embodiments of the present invention;

[0030] Figure 3 This is a cross-sectional view of a display module according to some embodiments of the present invention;

[0031] Figure 4 This is a plan view of a display panel according to some embodiments of the present invention;

[0032] Figure 5 This is a cross-sectional view of a display device according to some embodiments of the present invention;

[0033] Figure 6 This is a cross-sectional view of a display device according to some embodiments of the present invention;

[0034] Figure 7A This is a rear view showing some components of a display device according to some embodiments of the concept of the present invention;

[0035] Figure 7B This illustrates some embodiments based on the concept of the present invention. Figure 7A A magnified view of further details of region AA;

[0036] Figure 8 This illustrates some embodiments based on the concept of the present invention. Figure 7A A magnified view of further details of area BB;

[0037] Figure 9 This illustrates some embodiments based on the concept of the present invention. Figure 7A A magnified view of further details of area BB;

[0038] Figure 10 This is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present invention;

[0039] Figure 11 This is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present invention;

[0040] Figure 12 These are cross-sectional views of a display panel and an input sensor according to some embodiments of the present invention; and

[0041] Figure 13 This is a rear view of a display device according to some embodiments of the present invention. Detailed Implementation

[0042] It should be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "attached to" another element, it can be directly on, directly connected to, or directly attached to the other element, or a third intermediary element may be present.

[0043] Throughout this specification, the same reference numerals denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of components are exaggerated for the purpose of effectively describing the technical content. The term "and / or" includes any and all of one or more combinations that can be defined by the relevant components.

[0044] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the invention, and similarly, a second component may be referred to as a first component. The singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise.

[0045] Furthermore, this paper uses spatial relative terms such as “below,” “lower,” “above,” and “upper” to describe the relationship between one component or feature shown in the figure and another component or feature. The terms are spatial relative descriptors and are based on the directions shown in the figure.

[0046] It should also be understood that, when used in this specification, the terms “comprising” or “having” specify the presence of the stated features, integrals, steps, operations, components, or portions, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, components, portions, or combinations thereof.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0048] In the following sections, some aspects of embodiments of the invention will be explained in more detail with reference to the accompanying drawings.

[0049] Figure 1A and Figure 1B This is a perspective view of an electronic device ED according to some embodiments of the present invention. Figure 1A The electronic device ED is shown in its flat (or folded) state, and Figure 1BThe folded state of the electronic device ED is shown.

[0050] refer to Figure 1A and Figure 1B An electronic device ED according to some embodiments of the present invention may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. That is, when the electronic device ED is in an unfolded state or a flat state, or in an unfolded configuration or a flat configuration, the display surface DS may be a plane parallel to the plane defined by the first direction DR1 and the second direction DR2. The electronic device ED can provide an image IM to a user through the display surface DS.

[0051] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display an image IM. The non-display area NDA may surround the display area DA. However, embodiments of the present invention are not limited thereto, and the shapes of the display area DA and the non-display area NDA may be changed.

[0052] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, as used herein, "in the plane" can be defined as the state viewed from the third direction DR3. Additionally, "in the thickness direction" can be defined as the state viewed from the third direction DR3. In the following text, the first direction DR1 to the third direction DR3 refer to the same reference numerals as those indicating the directions from the first direction axis to the third direction axis.

[0053] The electronic device ED may include a foldable region FA and multiple non-foldable regions NFA1 and NFA2. The non-foldable regions NFA1 and NFA2 may include a first non-foldable region NFA1 and a second non-foldable region NFA2. In a first direction DR1, the foldable region FA may be located between the first non-foldable region NFA1 and the second non-foldable region NFA2. The foldable region FA may be referred to as the first region FA, the first non-foldable region NFA1 may be referred to as the second region NFA1, and the second non-foldable region NFA2 may be referred to as the third region NFA2.

[0054] like Figure 1B As shown, the foldable region FA can be folded around a folding axis FX parallel to the second direction DR2. The foldable region FA has a specific curvature and radius of curvature. The first non-foldable region NFA1 and the second non-foldable region NFA2 can face each other, and the electronic device ED can be folded inward so that the display surface DS is not exposed to the outside.

[0055] According to some embodiments of the present invention, the electronic device ED can be folded outward, exposing the display surface DS to the outside. According to some embodiments of the present invention, the electronic device ED can be configured to interchangeably repeat inward or outward folding operations from an unfolding operation, but the embodiments of the present invention are not limited thereto. According to some embodiments of the present invention, the electronic device ED can be configured to select any one of an unfolding operation, an inward folding operation, and an outward folding operation.

[0056] Multiple sensing areas SA1, SA2, and SA3 can be defined within the electronic device ED. Figure 1A The example shows three sensing areas SA1, SA2 and SA3, but the number of sensing areas SA1, SA2 and SA3 is not limited to this.

[0057] Sensing regions SA1, SA2, and SA3 may include a first sensing region SA1, a second sensing region SA2, and a third sensing region SA3. For example, the first sensing region SA1 may overlap with the camera module, the second sensing region SA2 may overlap with the first illumination sensor, and the third sensing region SA3 may overlap with the second illumination sensor, but the embodiments of the present invention are not limited thereto.

[0058] The electronic module (e.g., a camera module, a first illuminance sensor, or a second illuminance sensor) can receive external input transmitted through each of the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3, or can provide output through each of the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3.

[0059] A first sensing area SA1 may be surrounded by a display area DA, and each of a second sensing area SA2 and a third sensing area SA3 may be included within the display area DA. That is, the second sensing area SA2 and the third sensing area SA3 may display an image IM. The transmittance of each of the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3 may be higher than the transmittance of the display area DA. Furthermore, the transmittance of the first sensing area SA1 may be higher than the transmittance of each of the second sensing area SA2 and the third sensing area SA3.

[0060] According to some embodiments of the present invention, the camera module can be surrounded by a display area DA, and each of the first and second illuminance sensors can overlap with the display area DA. Therefore, the area where the camera module, the first illuminance sensor, and the second illuminance sensor are arranged may not be located in the non-display area NDA. Thus, the ratio of the area of ​​the display area DA to the area of ​​the front surface of the electronic device ED can be increased.

[0061] Figure 2 This is an exploded perspective view of an electronic device according to some embodiments of the concept of the present invention.

[0062] refer to Figure 2 The electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and housings EDC1 and EDC2. According to some embodiments, the electronic device ED may also include a mechanical structure to control the folding operation of the display device DD.

[0063] The display device DD generates images and senses external input. The display device DD includes a window module WM and a display module DM. The window module WM provides the front surface of the electronic device ED.

[0064] The display module DM may include at least one display panel DP. Figure 2 In this diagram, the display module DM is shown as identical to the display panel DP; however, in practice, the display module DM can have a stacked structure in which multiple components are stacked. A detailed description of the stacked structure of the display module DM will be given below.

[0065] The display panel DP includes display areas DA corresponding to the electronic devices ED (see...). Figure 1A ) and non-display area NDA (see Figure 1A The display module DM includes the display area DP-DA and the non-display area DP-NDA. In this specification, "area / part corresponding to another area / part" means that the areas / parts overlap, but is not limited to areas / parts having the same area. The display module DM may include a driver chip DIC located in the non-display area DP-NDA. The display module DM may also include a flexible printed circuit film FCB coupled to the non-display area DP-NDA.

[0066] The driver chip (DIC) may include driving elements for driving the pixels of the display panel (DP), such as data driving circuitry. Figure 2 The diagram illustrates a structure where the driver chip DIC is mounted on a display panel DP, but embodiments of the invention are not limited thereto. For example, the driver chip DIC can be mounted on a flexible printed circuit film FCB.

[0067] The electronic module (EM) includes at least one main controller. The EM may include a wireless communication module, a camera module, a proximity sensor module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. The EM is electrically connected to the power supply module (PSM).

[0068] The main controller controls the overall operation of the electronic device ED. For example, the main controller activates or deactivates the display device DD based on user input. The main controller can control the operation of the display device DD and other modules. The main controller may include at least one microprocessor.

[0069] Housings EDC1 and EDC2 house the display module DM, the electronics module EM, and the power supply module PSM. Two separate housings EDC1 and EDC2 are shown by way of example, but embodiments of the invention are not limited thereto. According to some embodiments, the electronic device ED may also include a hinge structure for connecting the two housings EDC1 and EDC2. These housings EDC1 and EDC2 may be coupled to the window module WM. Housings EDC1 and EDC2 protect the components housed within them, such as the display module DM, the electronics module EM, and the power supply module PSM.

[0070] Figure 3 This is a cross-sectional view of a display module according to some embodiments of the present invention. Figure 3 It is along Figure 2 A sectional view taken from line I-I'.

[0071] refer to Figure 3 The display module DM may include a display panel DP, an input sensor IS located on the display panel DP, an optical film LF located on the input sensor IS, and a lower component LM located below the display panel DP. An adhesive layer may be located between the components if necessary.

[0072] The display panel (DP) may include a base layer, a circuit element layer on the base layer, a display element layer on the circuit element layer, and a thin-film encapsulation layer on the display element layer. The base layer may include a plastic film. For example, the base layer may include polyimide. Essentially, the planar shape of the base layer may be as described below. Figure 4 The display panel DP shown has the same planar shape.

[0073] The circuit element layer may include organic layers, inorganic layers, semiconductor patterns, conductive patterns, signal lines, etc. Organic layers, inorganic layers, semiconductor layers, and conductive layers can be formed on a base layer using methods such as coating and deposition. Then, the organic layers, inorganic layers, semiconductor layers, and conductive layers can be selectively patterned through several photolithography processes to form semiconductor patterns, conductive patterns, and signal lines.

[0074] Semiconductor patterns, conductive patterns, and signal lines can form pixel driving circuits and will be described below. Figure 4 The pixel PX shown has signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL. The pixel driving circuit may include at least one transistor.

[0075] The display element layer includes components for use as described below. Figure 4 The pixel PX shown is a light-emitting element. Each light-emitting element is electrically connected to at least one transistor. A thin-film encapsulation layer may be located on the display element layer to seal the display element layer. The thin-film encapsulation layer may include sequentially stacked inorganic, organic, and inorganic layers. The stacking structure of the thin-film encapsulation layer is not particularly limited.

[0076] An input sensor IS may include multiple sensing electrodes for sensing external input, traces connected to the multiple sensing electrodes, and inorganic and / or organic layers for insulating / protecting the multiple sensing electrodes or traces. The input sensor IS may be a capacitive sensor, but is not particularly limited thereto.

[0077] When manufacturing the display panel DP, the input sensor IS can be directly formed on the thin-film encapsulation layer via a continuous process. In this specification, the display panel DP with the input sensor IS integrated can be limited to an electronic panel. However, embodiments of the inventive concept are not limited to this, and the input sensor IS can be manufactured as a panel separate from the display panel DP and attached to the display panel DP via an adhesive layer.

[0078] Multiple sensing electrodes and display area DP-DA (see) Figure 4 The traces overlap with the non-display area DP-NDA (see...). Figure 4 Overlap. The traces may pass through curved regions BA (e.g., see...). Figure 4 and Figure 6 To the second panel area AA2 (see) Figure 4 The bottom extends to match Figure 4 The pad PD shown is adjacent to the circuit element layer. In this case, the trace can be located adjacent to the signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL (see Figure 1). Figure 4 On different layers.

[0079] The trace can be connected to Figure 4 The signal lines (input signal lines) for the input sensor IS are shown in the first panel area AA1 of the display panel DP. The input signal lines are... Figure 4 The signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL shown are different, but can be located on the same layer as any of these signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL. The input signal lines can be connected to the corresponding pads PD (see [link to relevant documentation]). Figure 4Therefore, the traces can be electrically connected to the same flexible printed circuit film FCB as the signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL of the circuit element layer (see...). Figure 4 ).

[0080] An optical film (LF) can reduce the reflectivity of external light. An optical film (LF) may include a phase retarder and / or a polarizer. An optical film (LF) may include at least one polarizing film.

[0081] An optical film LF according to some embodiments of the present invention may include a color filter. The color filter may have a specific arrangement. The arrangement of the color filter may be determined taking into account the emission colors of the pixels PX included in the display panel DP. Furthermore, the optical film LF may also include a black matrix adjacent to the color filter.

[0082] The optical film LF according to some embodiments of the present invention may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can be destructively interfered with, and thus the reflectivity of external light can be reduced.

[0083] The lower component LM can include various functional components. These may include a light-shielding layer that blocks light incident on the display panel DP, an impact-absorbing layer that absorbs external impacts, a support layer that supports the display panel DP, and a heat dissipation layer that radiates heat generated in the display panel DP. A detailed description of the stacking structure of the lower component LM will be given below.

[0084] Figure 4 This is a plan view of a display panel according to some embodiments of the present invention.

[0085] refer to Figure 4 The display panel (DP) may include a display area (DP-DA) and a non-display area (DP-NDA) surrounding the display area (DP-DA). The display area (DP-DA) and the non-display area (DP-NDA) are separated based on whether pixels (PX) are arranged there. Pixels (PX) are located in the display area (DP-DA). The scan driver (SDV), data driver, and transmit driver (EDV) may be located in the non-display area (DP-NDA). The data driver may be part of the circuitry configured in the driver chip (DIC).

[0086] The display panel DP includes a first panel area AA1, a second panel area AA2, and a curved area BA, which are divided along a first direction DR1. The second panel area AA2 and the curved area BA may be part of the non-display area DP-NDA. The curved area BA is located between the first panel area AA1 and the second panel area AA2.

[0087] The first panel area AA1 corresponds to Figure 1A The display surface DS area. The first panel area AA1 may include a first non-foldable area NFA10, a second non-foldable area NFA20, and a foldable area FA0. The first non-foldable area NFA10, the second non-foldable area NFA20, and the foldable area FA0 respectively correspond to Figure 1A and Figure 1B The system comprises a first non-foldable region NFA1, a second non-foldable region NFA2, and a foldable region FA. The foldable region FA0 may be referred to as the first region FA0, the first non-foldable region NFA10 may be referred to as the second region NFA10, and the second non-foldable region NFA20 may be referred to as the third region NFA20.

[0088] In the second direction DR2, the length (or width) of the bending region BA and the second panel region AA2 can be smaller than the length (or width) of the first panel region AA1. Regions with shorter lengths in the bending axis direction can be bent more easily.

[0089] The display panel (DP) may include multiple pixels (PX), multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a power line PL, and multiple pads (PD). In this document, m and n are natural numbers. Pixels (PX) may be connected to scan lines SL1 to SLm, data lines DL1 to DLn, and emission lines EL1 to ELm.

[0090] Scan lines SL1 to SLm can extend in the second direction DR2 to be electrically connected to the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and can be electrically connected to the driver chip DIC via the bend region BA. Transmit lines EL1 to ELm can extend in the second direction DR2 to be electrically connected to the transmit driver EDV.

[0091] The power line PL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The portion extending in the second direction DR2 and the portion extending in the first direction DR1 may be located on different layers. The portion of the power line PL extending in the first direction DR1 may extend to the second panel region AA2 via a bending region BA. The power line PL may provide a first voltage to the pixel PX.

[0092] The first control line CSL1 can be connected to the scan driver SDV and can extend via the bend area BA towards the bottom of the second panel area AA2. The second control line CSL2 can be connected to the transmit driver EDV and can extend via the bend area BA towards the bottom of the second panel area AA2.

[0093] When viewed in a plan view, the pad PD can be positioned adjacent to the bottom of the second panel area AA2. The driver chip DIC, power line PL, first control line CSL1, and second control line CSL2 can be electrically connected to the pad PD. The flexible printed circuit film FCB can be electrically connected to the pad PD via an anisotropic conductive adhesive layer.

[0094] Figure 5 This is a cross-sectional view of a display device according to some embodiments of the present invention. Figure 6 This is a cross-sectional view of a display device according to some embodiments of the present invention. Figure 5 It is along Figure 4 The sectional view taken from line II-II'.

[0095] Figure 5 The display device DD is shown mounted on the electronic device ED (see Figure 1A The previous state in ) and Figure 6 The display device DD is shown mounted on the electronic device ED (see Figure 1A The state in ).

[0096] refer to Figure 6 When the display device DD is installed in the electronic device ED (see Figure 1A In this configuration, the first panel area AA1 and the second panel area AA2 of the display panel DP can be located on different planes. The second panel area AA2 can be located below the first panel area AA1.

[0097] refer to Figure 5 and Figure 6 The window module WM may include a thin-film glass substrate UTG, a plastic film PF located on the thin-film glass substrate UTG, a first adhesive layer AL1 connecting the thin-film glass substrate UTG and the plastic film PF, and a border pattern BP.

[0098] Border pattern BP and Figure 1A The non-display area NDA is shown to overlap. The border pattern BP can be located on one surface of the thin-film glass substrate UTG or on one surface of the plastic film PF. Figure 5 An example is shown of a border pattern BP located on the lower surface of a plastic film PF. Embodiments of the invention are not limited thereto, and the border pattern BP may be located on the upper surface of the plastic film PF. The border pattern BP may be formed as a colored light-shielding film by, for example, a coating method. The border pattern BP may include a base material and a dye or pigment mixed with the base material. The border pattern BP may have a closed-line shape in a planar plane.

[0099] The thickness of the thin-film glass substrate UTG can be from about 15 μm to about 45 μm, for example, about 30 μm. The thin-film glass substrate UTG can be chemically strengthened glass. When using the thin-film glass substrate UTG, wrinkling can be minimized even with repeated folding and unfolding. In some embodiments of the present invention, a synthetic resin film can be used instead of the thin-film glass substrate UTG.

[0100] The thickness of the plastic film PF can be from about 50 μm to about 80 μm, for example, about 65 μm. The plastic film PF may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate. According to some embodiments, at least one of a hard coating, an anti-fingerprint layer, and an anti-reflective layer may be located on the upper surface of the plastic film PF.

[0101] The first adhesive layer AL1 can be a pressure-sensitive adhesive (PSA) film or an optically transparent adhesive (OCA) component. The adhesive layers described below can also be the same as the first adhesive layer AL1 and can include any suitable adhesive material.

[0102] The thickness of the first adhesive layer AL1 can be from about 20 μm to about 50 μm, for example, about 35 μm. The first adhesive layer AL1 can have a thickness sufficient to cover the border pattern BP. For example, the thickness of the border pattern BP can be from about 3 μm to about 8 μm, and the first adhesive layer AL1 can have a thickness such that no air bubbles are generated around the border pattern BP.

[0103] The first adhesive layer AL1 can be separated from the thin-film glass substrate UTG. The strength of the thin-film glass substrate UTG is lower than that of the plastic film PF, making it relatively easy to incur scratches. After separating the first adhesive layer AL1 and the plastic film PF, a new plastic film PF can be attached to the thin-film glass substrate UTG.

[0104] On a plane, the edge UE of the thin-film glass substrate UTG does not overlap with the border pattern BP. Because the above condition is met, the edge UE of the thin-film glass substrate UTG is exposed from the border pattern BP, and the detection device can detect minute cracks generated in the edge UE of the thin-film glass substrate UTG. The detection device may include a microscope. The detection device can take a photograph of the edge UE of the thin-film glass substrate UTG on the upper surface of the plastic film PF to examine cracks originating from the edge UE of the thin-film glass substrate UTG.

[0105] On a flat surface, the edges PE of the plastic film PF and A-E1 of the first adhesive layer AL1 can be aligned. The plastic film PF and the first adhesive layer AL1 can have the same area and the same shape.

[0106] The window module WM and the display module DM can be connected via a second adhesive layer AL2. The second adhesive layer AL2 may comprise a pressure-sensitive adhesive or a transparent adhesive such as an optically clear adhesive. The thickness of the second adhesive layer AL2 may be from about 35 μm to about 65 μm, for example, about 50 μm.

[0107] On the plane, the edges A-E2 of the second adhesive layer AL2 can overlap with the window module WM. For example, the edges A-E2 of the second adhesive layer AL2 can overlap with the thin-film glass substrate UTG. During the process of attaching the window module WM and the display module DM, pressure can be applied to the second adhesive layer AL2. Under pressure, the second adhesive layer AL2 can be stretched in directions parallel to the first direction DR1 and the second direction DR2. In this case, the area of ​​the second adhesive layer AL2 can be smaller than the area of ​​the thin-film glass substrate UTG to prevent the second adhesive layer AL2 from protruding further than the thin-film glass substrate UTG.

[0108] When the first adhesive layer AL1 and the second adhesive layer AL2 are attached, the thin-film glass substrate UTG can remain stationary, allowing for proper attachment in electronic devices (see ED). Figure 1A During the folding operation, warping or cracking may occur in the thin-film glass substrate UTG. However, according to some embodiments of the present invention, the area of ​​the second adhesive layer AL2 is smaller than the area of ​​the thin-film glass substrate UTG, so that the first adhesive layer AL1 and the second adhesive layer AL2 may not be attached, and the possibility of foreign matter adhering to the second adhesive layer AL2 can be reduced.

[0109] The display module DM may include an optical film LF, a display panel DP, a panel protective layer PPL, a barrier layer BRL, a support layer PLT, a cover layer SCV, a heat dissipation layer RHL, a padding layer CUL, an insulating layer INL, a spacer SPC, a step compensation pattern CP, and third adhesive layers AL3 to eleventh adhesive layers AL11. The third adhesive layers AL3 to eleventh adhesive layers AL11 may include pressure-sensitive adhesives or transparent adhesives such as optically transparent adhesives. In some embodiments of the present invention, some of the above components may be omitted. For example, the step compensation pattern CP and the associated tenth adhesive layer AL10 and eleventh adhesive layer AL11 may be omitted.

[0110] The optical film LF is located in the first panel area AA1. The optical film LF covers at least the display area DP-DA (see...). Figure 2 The second adhesive layer AL2 is bonded to the optical film LF and the window module WM, and the third adhesive layer AL3 is bonded to the optical film LF and the display panel DP. Although in Figure 5 and Figure 6 Only the display panel DP is shown, but as Figure 3As shown, the input sensor IS can be further located between the display panel DP and the third adhesive layer AL3.

[0111] The panel protective layer (PPL) can be located beneath the display panel (DP). The PPL protects the lower portion of the display panel (DP). The PPL can comprise a flexible plastic material. The PPL prevents or reduces scratches on the rear surface of the display panel (DP) during the manufacturing process. The PPL can be a colored polyimide film. For example, it can be an opaque yellow film, but is not limited to this.

[0112] According to some embodiments of the present invention, the panel protective layer PPL may not be located within the bending region BA. The panel protective layer PPL may include a first panel protective layer PPL-1 protecting a first panel region AA1 of the display panel DP and a second panel protective layer PPL-2 protecting a second panel region AA2 of the display panel DP. When the bending region BA bends, the second panel protective layer PPL-2 and the second panel region AA2 of the display panel DP may be located below the first panel region AA1 and the first panel protective layer PPL-1. Since the panel protective layer PPL is not located within the bending region BA, the bending region BA can therefore be bent more easily.

[0113] The fourth adhesive layer AL4 can connect the panel protective layer PPL and the display panel DP. The fourth adhesive layer AL4 may include a first portion AL4-1 corresponding to the first panel protective layer PPL-1 and a second portion AL4-2 corresponding to the second panel protective layer PPL-2. The first portion AL4-1 can connect the first panel protective layer PPL-1 to the first panel area AA1 of the display panel DP, and the second portion AL4-2 can connect the second panel protective layer PPL-2 to the second panel area AA2 of the display panel DP.

[0114] The barrier layer BRL can be located below the panel protective layer PPL. The fifth adhesive layer AL5 can be located between the panel protective layer PPL and the barrier layer BRL to attach the barrier layer BRL to the panel protective layer PPL. The fifth adhesive layer AL5 can be attached to the upper surface of the barrier layer BRL, and the fifth adhesive layer AL5 can be referred to as the upper adhesive layer.

[0115] A barrier layer (BRL) can increase resistance to compressive forces by external pressure. Therefore, a barrier layer (BRL) can be used to prevent deformation of the display panel (DP). The barrier layer (BRL) can comprise flexible plastic materials such as polyimide or polyethylene terephthalate (PET).

[0116] Furthermore, the barrier layer (BRL) can absorb light incident from the outside. The barrier layer (BRL) can include a light-shielding material or a colored film with low light transmittance. For example, the barrier layer (BRL) can be a black plastic film, such as a black polyimide film. When the display module (DM) is viewed from above the window module (WM), the components located below the barrier layer (BRL) may be visually indistinguishable to the user.

[0117] The support layer PLT is located below the barrier layer BRL. The support layer PLT may be located below the first panel area AA1. The support layer PLT may overlap with the first panel area AA1.

[0118] The support layer PLT can comprise a material with an elastic modulus of 60 GPa or higher. The support layer PLT can comprise a metallic material, such as stainless steel. For example, the support layer PLT can comprise SUS 304, but is not limited to this, and the support layer PLT can comprise various metallic materials. The support layer PLT can support the display panel DP. Furthermore, the support layer PLT can enhance the heat dissipation performance of the display device DD.

[0119] Multiple openings (OPs) can be defined in the portion of the support layer PLT corresponding to the foldable region FA0. The flexibility of the support layer PLT can be improved by the openings (OPs).

[0120] The area of ​​the barrier layer (BRL) can be smaller than the area of ​​the support layer (PLT). The area can be planar. On the planar surface, the barrier layer (BRL) can overlap with a portion of the support layer (PLT). Another portion of the support layer (PLT) may not overlap with the barrier layer (BRL).

[0121] The sixth adhesive layer AL6 may be located between the barrier layer BRL and the support layer PLT. The sixth adhesive layer AL6 may connect the barrier layer BRL and the support layer PLT. The sixth adhesive layer AL6 may include a first portion AL6-1 and a second portion AL6-2 spaced apart from each other.

[0122] The first part AL6-1 and the second part AL6-2 may be spaced apart from each other, and a plurality of openings OP are inserted between the first part AL6-1 and the second part AL6-2. In the plane, the sixth adhesive layer AL6 may not overlap with the plurality of openings OP. Furthermore, in the plane, the sixth adhesive layer AL6 may be spaced apart from the plurality of openings OP.

[0123] The first portion AL6-1 may overlap with the second region NFA10, the second portion AL6-2 may overlap with the third region NFA20, and each of the first portion AL6-1 and the second portion AL6-2 may not overlap with the first region FA0. By not forming the sixth adhesive layer AL6 in the region corresponding to the first region FA0, the flexibility of the support layer PLT can be improved.

[0124] In the region overlapping with the first region FA0, the barrier layer BRL can be separated from the support layer PLT. That is, in the region overlapping with the first region FA0, the empty space ES can be defined between the support layer PLT and the barrier layer BRL. Air can reside in the empty space ES.

[0125] When electronic devices ED (see Figure 1A When folded, the empty space ES is defined between the barrier layer BRL and the support layer PLT, such that the shape of the multiple openings OP defined in the support layer PLT cannot be visually detected from the electronic device ED (see [link]). Figure 1A External identification of ).

[0126] Furthermore, since the barrier layer BRL includes a light-shielding material or is applied as a colored film with low light transmittance, the color difference of the barrier layer BRL may not be visually identifiable from the outside. For example, the color difference between a first support region defining a plurality of openings OP in the support layer PLT and a second support region not defining a plurality of openings OP may not be visually identifiable from the outside. The first support region may be a region overlapping with a first region FA0, and the second support region may be a region overlapping with a second region NFA10 and a third region NFA20.

[0127] The thickness of the sixth adhesive layer AL6 can be less than the thickness of the fifth adhesive layer AL5. For example, the thickness of the fifth adhesive layer AL5 can be about 25 μm, and the thickness of the sixth adhesive layer AL6 can be about 16 μm.

[0128] When the thickness of the sixth adhesive layer AL6 is thin, the step difference caused by the sixth adhesive layer AL6 can be reduced. When the step difference is small, the step difference caused by the electronic device ED (see...) can be reduced. Figure 1A The shape deformation of the stacked structure caused by folding and unfolding is significant, but multiple openings (OPs) can be visually identifiable, or the sixth adhesive layer AL6 can be separated through repeated folding operations. When the thickness of the sixth adhesive layer AL6 is relatively large, multiple openings (OPs) may not be visually identifiable (or their perceptibility may be reduced), and the adhesive reliability of the sixth adhesive layer AL6 is increased during repeated folding operations, but step differences may increase. Therefore, considering folding reliability, adhesive reliability, and the visibility of multiple openings (OPs), the thickness of the sixth adhesive layer AL6 can be selected within an appropriate range.

[0129] The seventh adhesive layer AL7 can be located below the support layer PLT, and the cover layer SCV can also be located below the seventh adhesive layer AL7. The support layer PLT and the cover layer SCV can be bonded together through the seventh adhesive layer AL7. The cover layer SCV can be fabricated as a sheet and attached to the support layer PLT.

[0130] The seventh adhesive layer AL7 and the cover layer SCV can cover the multiple openings OP defined in the support layer PLT. Therefore, the cover layer SCV can prevent foreign matter from flowing into the multiple openings OP. The cover layer SCV can have a lower elastic modulus than the support layer PLT. For example, the cover layer SCV can comprise thermoplastic polyurethane, rubber, or silicone, but embodiments of the present invention are not limited thereto.

[0131] The eighth adhesive layer AL8 may be located below the cover layer SCV. The eighth adhesive layer AL8 may include a first cover portion AL8-1 and a second cover portion AL8-2. The first cover portion AL8-1 and the second cover portion AL8-2 may be spaced apart from each other. In a plane, the first cover portion AL8-1 and the second cover portion AL8-2 may be spaced apart from each other, and a plurality of openings OP are inserted between the first cover portion AL8-1 and the second cover portion AL8-2. The first cover portion AL8-1 and the second cover portion AL8-2 may not overlap in the first region FA0.

[0132] The heat dissipation layer RHL can be located below the eighth adhesive layer AL8. The heat dissipation layer RHL can be a sheet with high thermal conductivity. The heat dissipation layer RHL can include metal or metal alloy, for example, the heat dissipation layer RHL can include copper, copper alloy or graphite.

[0133] The heat dissipation layer RHL may include a first heat dissipation layer RHL-1 and a second heat dissipation layer RHL-2. The first heat dissipation layer RHL-1 and the second heat dissipation layer RHL-2 may be spaced apart by a gap (e.g., a set or predetermined gap) GP. The gap (e.g., a set or predetermined gap) GP may be from about 0.4 mm to about 2.4 mm, but the implementation is not particularly limited thereto. The gap (e.g., a set or predetermined gap) GP may be arranged to correspond to the foldable region FA0.

[0134] The first heat dissipation layer RHL-1 can be connected to the cover layer SCV via the first cover portion AL8-1, and the second heat dissipation layer RHL-2 can be connected to the cover layer SCV via the second cover portion AL8-2. In the plane, the first heat dissipation layer RHL-1 can overlap with a portion of the first region FA0 and the second region NFA10, and the second heat dissipation layer RHL-2 can overlap with another portion of the first region FA0 and the third region NFA20.

[0135] On a plane, a portion of the first heat dissipation layer RHL-1 may overlap with a portion of a plurality of openings OP, and a portion of the second heat dissipation layer RHL-2 may overlap with another portion of the plurality of openings OP. The first heat dissipation layer RHL-1 and the second heat dissipation layer RHL-2 can be used to support the support layer PLT. For example, the regions defining the plurality of openings OP of the support layer PLT can be supported by the first heat dissipation layer RHL-1 and the second heat dissipation layer RHL-2. Therefore, the first heat dissipation layer RHL-1 and the second heat dissipation layer RHL-2 can be referred to as the first lower support layer and the second lower support layer, respectively.

[0136] The ninth adhesive layer AL9 may be located below the heat dissipation layer RHL. The ninth adhesive layer AL9 may include a first portion AL9-1 corresponding to the first heat dissipation layer RHL-1 and a second portion AL9-2 corresponding to the second heat dissipation layer RHL-2. The first portion AL9-1 and the second portion AL9-2 may be spaced apart by an interval (e.g., a set or predetermined interval) GP.

[0137] The cushioning layer CUL may be located below the ninth adhesive layer AL9. The thickness of the cushioning layer CUL may be approximately 75 μm, but the implementation is not particularly limited to this. The cushioning layer CUL can absorb external impacts to protect the display panel DP. The elastic modulus of the cushioning layer CUL is lower than that of the support layer PLT. The cushioning layer CUL may include a foam sheet with specific elasticity. The cushioning layer CUL may include sponge or polyurethane.

[0138] The padding layer CUL may include a first padding layer CUL-1 corresponding to the first portion AL9-1 and a second padding layer CUL-2 corresponding to the second portion AL9-2. The first padding layer CUL-1 and the second padding layer CUL-2 may be spaced apart by an interval (e.g., a set or predetermined interval) GP. In the plane, the interval (e.g., a set or predetermined interval) GP between the first padding layer CUL-1 and the second padding layer CUL-2 may overlap with the first region FA0. In the plane, the first padding layer CUL-1 may overlap with a portion of the first region FA0 and the second region NFA10, and the second padding layer CUL-2 may overlap with another portion of the first region FA0 and the third region NFA20.

[0139] Unlike embodiments of the present invention, if the padding layer CUL is located between the support layer PLT and the display panel DP, the shape of the padding layer CUL deforms when the display panel DP is pressed, making the display panel DP easily deformable. However, in some embodiments of the present invention, the padding layer CUL can be spaced apart from the display panel DP, and the support layer PLT is inserted between the padding layer CUL and the display panel DP. Therefore, when the display panel DP is pressed, the deformation of the display panel DP can be reduced compared to the comparative example. Furthermore, since the padding layer CUL is located below the heat dissipation layer RHL and is firmly supported by the heat dissipation layer RHL, the shock absorption performance of the padding layer CUL can be improved. The insulating layer INL can be located below the padding layer CUL. The insulating layer INL may include a first insulating layer INL-1 corresponding to the first padding layer CUL-1 and a second insulating layer INL-2 corresponding to the second padding layer CUL-2. Figure 5 An embodiment using insulating tape is shown. The insulating layer INL prevents or reduces the inflow of static electricity. According to some embodiments, the flexible printed circuit film FCB may be located on the insulating layer INL. The insulating layer INL prevents the flexible printed circuit film FCB from generating electrical interference with components located on the insulating layer INL.

[0140] One surface of the step compensation pattern CP can be bonded to the support layer PLT via the tenth adhesive layer AL10. The eleventh adhesive layer AL11 is formed on the other surface of the step compensation pattern CP. When the display device DD (see...) Figure 2 Connected to electronic device ED (see Figure 2 When using other components, the eleventh adhesive layer AL11 can be used.

[0141] refer to Figure 6 The curved region BA can be bent such that the second panel region AA2 is located below the first panel region AA1. Therefore, the driver chip DIC (see...) Figure 5 The first panel area AA1 can be located below the second panel area AA2. That is, the first panel area AA1 and the second panel area AA2 are located on different planes (or reference planes). The curved area BA can be bent to bulge laterally in the cross-section. The curved area BA has a specific curvature and radius of curvature. The radius of curvature can be from approximately 0.1 mm to approximately 0.5 mm.

[0142] The bending region BA can be bent to surround the fourth edge E4 of the support layer PLT. A portion of the support layer PLT can be located between the first panel region AA1 and the second panel region AA2.

[0143] The bending protective layer BPL is located at least on the bending region BA. The bending protective layer BPL may overlap with the bending region BA, the first panel region AA1, and the second panel region AA2. The bending protective layer BPL may be located on a portion of the first panel region AA1, a portion of the second panel region AA2, and on the bending region BA.

[0144] The Bending Protective Layer (BPL) can bend along with the Bending Region BA. The BPL protects the Bending Region BA from external impacts and controls the neutral plane of the Bending Region BA. The BPL controls the stress in the Bending Region BA to bring the neutral plane closer to the signal line located within the Bending Region BA.

[0145] The second part of the second panel protective layer PPL-2, which is not attached to the fourth adhesive layer AL4, is attached to one surface of the spacer SPC. Figure 5 and Figure 6 The spacer SPC is shown as a single layer, but the spacer SPC can have a multi-layer structure, where a base layer is located between two adhesive layers. The base layer may include graphite, which has excellent heat dissipation properties.

[0146] Figure 7A This is a rear view showing some components of a display device according to some embodiments of the concept of the present invention. Figure 7B It is shown Figure 7A A magnified view of region AA.

[0147] refer to Figure 7A and Figure 7B The support layer PLT may include a region corresponding to the first region FA0 (see...). Figure 5 The folded region PLT-F corresponds to the second region NFA10 (see...). Figure 5 The first region PLT-1 and the corresponding third region NFA20 (see) Figure 5 The second region PLT-2. Multiple openings OP can be formed in the folded region PLT-F.

[0148] Multiple open sections (OPs) can be arranged according to certain rules. The multiple open sections (OPs) can be arranged in a grid pattern. Each of the multiple open sections (OPs) can be defined as completely penetrating the lower surface of the support layer PLT from the upper surface of the support layer PLT. Forming multiple open sections (OPs) in the folded region PLT-F reduces the area of ​​the folded region PLT-F of the support layer PLT, and thus reduces the rigidity of the folded region PLT-F. Therefore, the folded region PLT-F can have higher flexibility than when multiple open sections (OPs) are not formed.

[0149] The support layer PLT may include a first edge E1 and a second edge E2 extending along a first direction DR1, and a third edge E3 and a fourth edge E4 extending along a second direction DR2.

[0150] Multiple first alignment openings PLT-H1 and multiple second alignment openings PLT-H2 can be defined in the support layer PLT. For example, two first alignment openings PLT-H1 and four second alignment openings PLT-H2 can be defined in the support layer PLT.

[0151] The first alignment openings PLT-H1 may be spaced apart from each other in the second direction DR2. For example, the first alignment openings PLT-H1 may be defined as spaced apart, and the second panel region AA2 may be interposed between the first alignment openings PLT-H1. The distance DT between the first alignment openings PLT-H1 in the second direction DR2 may be greater than the width WTX of the second panel region AA2 in the second direction DR2. The first alignment openings PLT-H1 may not overlap with the second panel region AA2 and may be spaced apart from the second panel region AA2 in the second direction DR2. Furthermore, the first alignment openings PLT-H1 may be defined as spaced apart from a plurality of openings OP in the first direction DR1.

[0152] The first alignment opening PLT-H1 can be defined as the fourth edge E4, which is closest to the first edge E1, the second edge E2, the third edge E3, and the fourth edge E4. Two of the second alignment openings PLT-H2 can be defined as the closest to the first edge E1, and the remaining two second alignment openings PLT-H2 can be defined as the closest to the second edge E2.

[0153] Figure 8 It is shown Figure 7A A magnified view of region BB.

[0154] refer to Figure 8 The first panel area AA1 may include a first alignment mark AM1 and a second alignment mark AM2. The first alignment mark AM1 may overlap with the first alignment opening PLT-H1, and the second alignment mark AM2 may overlap with the second alignment opening PLT-H2.

[0155] The curved region BA can bend while surrounding the fourth edge E4. The first alignment opening PLT-H1 can be closest to the fourth edge E4. The first alignment opening PLT-H1 can be spaced a certain distance DTX from the fourth edge E4. That is, the first alignment opening PLT-H1 can be completely surrounded by the support layer PLT. The support layer PLT defines the sidewall PLTS1 of the first alignment opening PLT-H1, which can have a closed curved shape.

[0156] Figure 8The example illustrates a rounded quadrilateral shape with four straight lines and four curves for the first alignment opening PLT-H1, but the embodiments of the present invention are not limited to this. For example, the shape of the first alignment opening PLT-H1 can be changed to various shapes, such as polygonal shapes, circular shapes, elliptical shapes, irregular shapes, etc.

[0157] In the region adjacent to the fourth edge E4 near the curved region BA, electrostatic discharge may occur suddenly, and the frequency of phenomena affecting peripheral components may be more frequent than in regions adjacent to other edges. According to some embodiments of the invention, the first alignment opening PLT-H1 adjacent to the fourth edge E4 may be defined as spaced apart from the fourth edge E4. In this case, the display panel DP (see...) Figure 5 The first panel area AA1 exposed by the first alignment opening PLT-H1 can be spaced apart from the fourth edge E4. Even in the event of a sudden electrostatic discharge, the charge can pass through the support layer PLT instead of the display panel DP (see [link to relevant documentation]). Figure 5 Electrostatic discharge (ESD) can thus be reduced or eliminated. Therefore, the possibility of components in the display panel (DP) being damaged by ESD can be reduced or eliminated. Consequently, the display device's ESD (see [link to ESD description]) can be improved. Figure 5 The reliability of ).

[0158] The second alignment opening PLT-H2 can be configured to be adjacent to the first edge E1. The second alignment opening PLT-H2 can be connected to the first edge E1. Therefore, the first edge E1 and the sidewall PLTS2 defining the second alignment opening PLT-H2 can be connected to each other. In a plane, the sidewall PLTS2 can have a curved shape with an opening.

[0159] Figure 9 This illustrates some embodiments corresponding to the concept of the present invention. Figure 7A A magnified view of region BB. Figure 9 The description describes the relationship with Figure 8 Different parts, and with Figure 8 The same components described herein are indicated by the same reference numerals, and their descriptions are omitted.

[0160] refer to Figure 9 The second alignment opening PLT-H21 can be spaced a certain distance DTX1 from the first edge E1. That is, the second alignment opening PLT-H21 can be completely surrounded by the support layer PLT. The support layer PLT defines the sidewall PLTS21 of the second alignment opening PLT-H21, which can have a closed curved shape.

[0161] Figure 9The second alignment opening PLT-H21 is shown as a quadrilateral shape by way of example, but the embodiments of the present invention are not limited thereto. For example, the shape of the second alignment opening PLT-H21 can be changed to various shapes, such as polygonal shapes, circular shapes, elliptical shapes, irregular shapes, etc.

[0162] according to Figure 9 In some embodiments shown, not only the first alignment opening PLT-H1 but also the second alignment opening PLT-H21 can be spaced apart from the edge of the support layer PLT. Therefore, the display device DD (see [link to documentation]) can be further improved. Figure 2 The reliability of electrostatic discharge.

[0163] Figure 10 This is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present invention.

[0164] refer to Figure 10 The diagram shows a cross-sectional view of the display panel DP and the input sensor IS, which overlap with the first panel area AA1.

[0165] The display panel DP may include a base layer 111, a circuit layer 112, a light-emitting element layer 113, and an encapsulation layer 114.

[0166] The base layer 111 may be a component that provides a base surface for the circuit layer 112. The base layer 111 may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer 111 may be an inorganic layer, an organic layer, or a composite material layer.

[0167] Circuit layer 112 may be located on base layer 111. Circuit layer 112 may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer are formed on base layer 111 by methods such as coating and deposition, and then the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by several photolithography processes. Subsequently, the semiconductor patterns, conductive patterns, and signal lines included in circuit layer 112 may be formed.

[0168] At least one inorganic layer is formed on the upper surface of the base layer 111. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may be configured with a barrier layer and / or a buffer layer. In some embodiments of the present invention, the display panel DP is shown as including a buffer layer BFL.

[0169] The buffer layer BFL can improve the adhesion between the base layer 111 and the semiconductor pattern. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0170] The semiconductor pattern may be located on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, embodiments of the present invention are not limited thereto, and the semiconductor pattern may include amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor.

[0171] Figure 10 Only a portion of the semiconductor pattern is shown; the semiconductor pattern may also be located in other regions. The semiconductor pattern can be arranged across pixels according to specific rules. Depending on whether the pattern is doped, the semiconductor pattern can have different electrical properties. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region or a doped region with a lower doping concentration than the first region.

[0172] The first region can have a higher conductivity than the second region and is essentially used as an electrode or signal line. In essence, the second region can correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion can be the source or drain of a transistor, and other portions can be connecting electrodes or connecting signal lines.

[0173] Each pixel can have an equivalent circuit including seven transistors, a capacitor, and a light-emitting element, and the equivalent circuit diagram of a pixel can be changed in various forms. Figure 10 The example shows a transistor 100PC and a light-emitting element 100PE included in a pixel.

[0174] The source SC, active region AL, and drain DR of transistor 100PC can be formed by semiconductor patterning. The source SC and drain DR can extend from the active region AL in opposite directions in cross-section. Figure 10 A portion of a signal connection line SCL formed by a semiconductor pattern is shown. According to some embodiments, the signal connection line SCL may be connected in a plane to the drain DR of transistor 100PC.

[0175] The first insulating layer 10 may be located on the buffer layer BFL. The first insulating layer 10 may overlap with multiple pixels in a common manner and may cover a semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In some embodiments of the present invention, the first insulating layer 10 may be a single layer of silicon oxide. Not only the first insulating layer 10 but also the insulating layer of the circuit layer 112 described below may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above-described materials, but embodiments of the present invention are not limited thereto.

[0176] The gate GT of transistor 100PC is located on the first insulating layer 10. The gate GT may be part of a metal pattern. The gate GT overlaps with the active region AL. In the process of doping semiconductor patterns, the gate GT may be used as a mask.

[0177] The first alignment mark AM1 may be located on the first insulating layer 10. The first alignment mark AM1 may be located on the same layer as the gate GT and may include the same material as the gate GT. The first alignment mark AM1 may be formed simultaneously using the same process as the gate GT.

[0178] The second insulating layer 20 may be located on the first insulating layer 10 and may cover the gate GT. The second insulating layer 20 may overlap with the pixel in a common ground. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments of the present invention, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0179] The third insulating layer 30 may be located on the second insulating layer 20. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0180] The first connection electrode CNE1 can be located on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal connection line SCL through the contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0181] The fourth insulating layer 40 may be located on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. The fifth insulating layer 50 may be located on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0182] The second connecting electrode CNE2 can be located on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0183] The sixth insulating layer 60 may be located on the fifth insulating layer 50 and may cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0184] The light-emitting element layer 113 may be located on the circuit layer 112. The light-emitting element layer 113 may include a light-emitting element. For example, the light-emitting element layer 113 may include organic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs. Hereinafter, the light-emitting element 100PE is described by way of example as an organic light-emitting element, but the embodiments of the present invention are not specifically limited thereto.

[0185] The light-emitting element 100PE may include a first electrode AE, an emitting layer EL, and a second electrode CE.

[0186] The first electrode AE ​​can be located on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT-3 that penetrates the sixth insulating layer 60.

[0187] The pixel defining film 70 may be located on the sixth insulating layer 60 and may cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining film 70. The opening 70-OP of the pixel defining film 70 exposes at least a portion of the first electrode AE.

[0188] The display area DP-DA may include an emitting area PXA and a non-emitting area NPXA adjacent to the emitting area PXA. The non-emitting area NPXA may surround the emitting area PXA. In some embodiments of the present invention, the emitting area PXA is defined as a portion of the area corresponding to the first electrode AE ​​exposed by the opening 70-OP.

[0189] The emitting layer EL can be located on the first electrode AE. The emitting layer EL can be located in the region corresponding to the opening 70-OP. That is, the emitting layer EL can be formed separately in each of the pixels. When the emitting layer EL is formed separately in each of the pixels, each of the emitting layer EL can emit at least one of blue light, red light, and green light. However, embodiments of the present invention are not limited thereto, and the emitting layer EL can be commonly connected to and disposed in the pixels. In this case, the emitting layer EL can provide blue light or white light.

[0190] The second electrode CE can be located on the emitter layer EL. The second electrode CE can have a monolithic shape and can be commonly arranged in multiple pixels or commonly connected to multiple pixels.

[0191] According to some implementations, a hole control layer may be located between the first electrode AE ​​and the emitter layer EL. The hole control layer may be commonly arranged in the emitter region PXA and the non-emitter region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be located between the emitter layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in multiple pixels using an aperture mask.

[0192] The encapsulation layer 114 may be located on the light-emitting element layer 113. The encapsulation layer 114 may include inorganic layers, organic layers and inorganic layers stacked in sequence, but the layers constituting the encapsulation layer 114 are not limited to these.

[0193] The inorganic layer protects the light-emitting element layer 113 from moisture and oxygen, while the organic layer protects it from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer may include an acrylic organic layer, but the embodiments of the present invention are not limited thereto.

[0194] The input sensor IS may include a base layer 121, a first conductive layer 122, a sensing insulating layer 123, a second conductive layer 124, and a covering insulating layer 125.

[0195] The base layer 121 may be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base layer 121 may be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The base layer 121 may have a monolayer structure or may have a multilayer structure stacked along a third direction DR3.

[0196] Each of the first conductive layer 122 and the second conductive layer 124 may have a single-layer structure or may have a multi-layer structure stacked along the third direction DR3.

[0197] The single-layer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Furthermore, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0198] The multilayer conductive layer may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0199] At least one of the sensing insulating layer 123 and the covering insulating layer 125 may include an inorganic film. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0200] At least one of the sensing insulating layer 123 and the covering insulating layer 125 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and tinamylene-containing resin.

[0201] Figure 11 This is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present invention. Figure 11 The description describes the relationship with Figure 10 Different parts, and with Figure 10 The same components described herein are indicated by the same reference numerals, and their descriptions are omitted.

[0202] refer to Figure 11 The first alignment mark AM1x may be located on the third insulating layer 30. The first alignment mark AM1x may be located on the same layer as the first connecting electrode CNE1 and may include the same material as the first connecting electrode CNE1. The first alignment mark AM1x may be formed simultaneously using the same process as the first connecting electrode CNE1.

[0203] Figure 12 This is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present invention. Figure 12 The description describes the relationship with Figure 10 Different parts, and with Figure 10 The same components described herein are indicated by the same reference numerals, and their descriptions are omitted.

[0204] refer to Figure 12 The first alignment mark AM1y can be located on the fifth insulating layer 50. The first alignment mark AM1y can be located on the same layer as the second connecting electrode CNE2, and can comprise the same material as the second connecting electrode CNE2. The first alignment mark AM1y can be formed simultaneously using the same process as the second connecting electrode CNE2.

[0205] Figure 13 This is a rear view of a display device according to some embodiments of the present invention. Figure 13 The description describes the relationship with Figure 10 Different parts, and with Figure 10The same components described herein are indicated by the same reference numerals, and their descriptions are omitted.

[0206] Figure 13 The lower surface of the support layer PLT is depicted. The cover layer SCV, the heat dissipation layer RHL, the padding layer CUL, and the insulating layer INL can be sequentially located on the lower surface of the support layer PLT. This stacked structure is located in a portion of the lower surface of the support layer PLT.

[0207] The cover layer SCV overlaps with the folded area PLT-F. A diagram showing the area decreasing from the cover layer SCV, heat dissipation layer RHL, padding layer CUL to the insulating layer INL is shown, but embodiments of the inventive concept are not limited thereto. The spacer SPC is arranged to be spaced apart from the stacked structure. The eleventh adhesive layer AL11 may be located outside the stacked structure and may be arranged along the edge of the support layer PLT.

[0208] In areas adjacent to a specific edge of the support layer near a curved region, electrostatic discharge may occur suddenly, and the frequency of this phenomenon affecting peripheral components may be higher than in areas adjacent to other edges. According to some embodiments of the invention, the alignment opening adjacent to a specific edge of the support layer can be defined as spaced apart from that specific edge. In this case, the portion of the display panel exposed by the alignment opening can be spaced apart from the specific edge, allowing the charge to discharge through the support layer rather than the display panel even if an electrostatic discharge occurs suddenly. Therefore, the possibility of damage to components included in the display panel due to electrostatic discharge can be reduced or eliminated. Consequently, the reliability of the display device can be improved.

[0209] Although exemplary embodiments of the inventive concept have been described herein, it should be understood that various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept as defined by the appended claims or their equivalents. Therefore, the technical scope of the invention should not be limited to what is described in the detailed description of the specification, but should be determined by the claims and their equivalents.

Claims

1. A display device, comprising: a display panel in which a first panel area, a curved area, and a second panel area are arranged along a first direction; and a support layer under the first panel area of the display panel, wherein the curved area of the display panel is curved toward a lower portion of the support layer, and a portion of the support layer is between the first panel area and the second panel area; the display panel includes a first alignment mark in the first panel area; a first alignment opening overlapping the first alignment mark is defined in the support layer, the first alignment opening does not overlap the second panel area in a thickness direction of the display panel, the first alignment opening is spaced apart from an edge of the support layer, and the first alignment opening is completely surrounded by the support layer, wherein the support layer includes a first edge and a second edge extending along the first direction, and a third edge and a fourth edge extending along a second direction intersecting the first direction; the curved area is curved while surrounding the fourth edge, and the first alignment opening is closest to the fourth edge among the first edge to the fourth edge.

2. The display device of claim 1, wherein, The first alignment opening is spaced apart from the second panel area in a second direction intersecting the first direction.

3. The display device of claim 1, wherein, The first alignment opening is provided in a plurality, and a plurality of the first alignment openings are spaced apart, and the second panel area is between a plurality of the first alignment openings.

4. The display device of claim 3, wherein, The first alignment mark is provided in a plurality, and the display panel is aligned with the support layer so that a plurality of the first alignment marks respectively overlap a plurality of the first alignment openings. 5.The display device of claim 1, wherein: the display panel further includes a second alignment mark in the first panel area; a second alignment opening overlapping the second alignment mark is defined in the support layer; and the second alignment opening is closest to the first edge among the first edge to the fourth edge. 6.The display device of claim 5, wherein: the second alignment opening is spaced apart from the first edge; and the second alignment opening is completely surrounded by the support layer. 7.The display device of claim 5, wherein: the second alignment opening is connected to the first edge; and the first edge and a sidewall defining the second alignment opening are connected to each other. 8.The display device of claim 1, wherein: a foldable area is in the first panel area; a plurality of openings are in a region of the support layer overlapping the foldable area; and the first alignment opening is spaced apart from the plurality of openings in the first direction. 9.The display device of claim 1, wherein: the display panel includes: a base layer; a circuit layer on the base layer and including a plurality of metal layers; a light emitting element layer on the circuit layer; and an encapsulation layer on the light emitting element layer; and the first alignment mark is on a same layer as any one of the plurality of metal layers. A sidewall defining the first alignment opening has a closed curve shape.

10. The display device of claim 1, wherein, ​

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