Display device

Abstract

A display device is provided. The display device includes a virtual data unit, a sensing unit, and a timing controller. The virtual data unit is connected to one end of a data line and supplies virtual data signals to the data line. The sensing unit is connected to the opposite end of the data line and determines the load of the data line based on the virtual data signals supplied to it through the data line. The timing controller controls the supply timing of data signals to be supplied to the data line based on the load of the data line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0100139 filed on August 10, 2020, as well as all the benefits accruing therefrom, the contents of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates generally to a display device. BACKGROUND

[0003] A display device generally includes data lines, gate lines, pixels connected to the data lines and the gate lines, a gate driver for outputting gate signals to the gate lines, a data driver for outputting data signals to the data lines, and a timing controller for controlling the gate driver and the data driver.

[0004] When a thin film transistor is turned on by applying a gate signal to a gate line, a data signal applied to a data line is used for charging as a pixel voltage in a pixel. SUMMARY

[0005] In a display device, a delay time of a data signal applied to a pixel can increase as a distance of the pixel from a data driver increases. Since a charging rate of a pixel voltage of the pixel decreases as the distance of the pixel from the data driver increases, display quality of the display device can deteriorate.

[0006] An embodiment provides a display device in which a supply timing of a data signal to be supplied to a data line is controlled based on a data load of the data line so that a charging time of a pixel voltage can be secured.

[0007] According to an embodiment of the disclosure, a display device includes a virtual data unit connected to one end portion of a data line, a sensing unit connected to an opposite end portion of the data line, and a timing controller, wherein the virtual data unit supplies a virtual data signal to the data line, the sensing unit determines a load of the data line based on the virtual data signal supplied thereto through the data line, and the timing controller controls a supply timing of a data signal to be supplied to the data line based on the load of the data line.

[0008] In an embodiment, the display device can further include a data driver that supplies a data signal to the data line and a gate driver that supplies a gate signal to a gate line.

[0009] In an embodiment, the virtual data unit can be disposed in the gate driver, and the sensing unit can be disposed in the data driver.

[0010] In an embodiment, the display apparatus can further include a connection line electrically connecting the dummy data unit and the data line to each other, and a switching element connected between the connection line and the dummy data unit.

[0011] In an embodiment, the data line to which the dummy data signal is supplied can be disposed adjacent to the gate driver.

[0012] In an embodiment, the switching element can be turned on when the dummy data signal is supplied to the data line, and remain in an off state when the data signal is supplied to the data line.

[0013] In an embodiment, the sensing unit can include a converter that converts the dummy data signal into a digital form of virtual delay data, and a delay calculator that generates a data delay value based on the virtual delay data.

[0014] In an embodiment, the data delay value can be a first data delay value corresponding to a maximum load of the data line.

[0015] In an embodiment, the delay calculator can pre-store a second data delay value corresponding to a minimum load of the data line, and additionally calculate a third data delay value corresponding to an intermediate load of the data line based on the first data delay value and the second data delay value.

[0016] In an embodiment, the data driver can include a shift register that generates an activation signal, a holding latch that is supplied with data from the timing controller and sequentially stores the data from the timing controller in response to the activation signal, a control latch that is supplied with the data stored in the holding latch at the same time when a source output enable signal is supplied, a digital-analog converter that is supplied with the data from the control latch when the source output enable signal is supplied to the control latch and generates a data signal based on the data supplied thereto from the control latch, and a buffer that transmits the data signal to the data line.

[0017] In an embodiment, the timing controller can control a supply timing of the data signal by changing a supply timing of the source output enable signal.

[0018] In an embodiment, the dummy data unit can be disposed at one end portion of the gate driver, and the sensing unit can be disposed at an opposite end portion of the gate driver.

[0019] In an embodiment, the display apparatus can further include a first connection line electrically connecting the dummy data unit and the data line to each other, a second connection line electrically connecting the sensing unit and the data line to each other, a first switching element connected between the first connection line and the dummy data unit, and a second switching element connected between the second connection line and the sensing unit.

[0020] In an embodiment, the line electrically connecting the dummy data unit and the sensing unit to each other can be a dummy data line.

[0021] In an embodiment, the sensing unit can be electrically connected to at least two points of a certain gate line, and determine a load of the certain gate line based on gate signals supplied thereto from the at least two points.

[0022] In an embodiment, the certain gate line can be disposed adjacent to the data driver.

[0023] In an embodiment, the sensing unit can include a first converter converting a dummy data signal into a digital form, a second converter converting a gate signal into a digital form, and a delay calculator generating a data delay value based on the dummy delay data and the gate sensing data.

[0024] In an embodiment, the data driver can include a first data driver disposed at one side of the display panel and a second data driver disposed at an opposite side of the display panel. In this embodiment, the dummy data unit can be disposed in the first data driver, and the sensing unit is disposed in the second data driver.

[0025] In an embodiment, the dummy data unit can be disposed in a data driver disposed at one side of the display panel, and the sensing unit can be disposed at an opposite side of the display panel or in a gate driver. In this embodiment, the display apparatus can further include a connection line electrically connecting the sensing unit and the data line to each other.

[0026] In an embodiment, the timing controller can further include a source output enable signal controller controlling a supply timing of a data signal, an overdrive controller controlling an overdrive voltage based on a load, and an amplifier bias controller controlling a bias current to be supplied to an amplifier included in the data driver based on a load.

[0027] In an embodiment of a display apparatus according to the present disclosure, a supply timing of a data signal to be supplied to a data line is controlled based on a data load of the data line, so that a charging time of a pixel voltage can be effectively secured. Accordingly, the quality of an image displayed in the display apparatus can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other features of the present application will become more apparent by describing in detail embodiments thereof with reference to the attached drawings.

[0029] Figure 1 FIG. 1 is a view illustrating a display apparatus according to an embodiment of the present disclosure.

[0030] Figure 2A A dummy data signal supplied from a dummy data unit is illustrated,Figure 2B A dummy data signal input to the sensing unit via a data line is shown, and Figure 2C and Figure 2D is a graph showing a timing of a gate signal to be supplied with respect to the dummy data signal.

[0031] Figure 3 is a block diagram of an embodiment of the sensing unit shown in Figure 1

[0032] Figure 4 is a waveform graph showing a supply timing of a data signal controlled by a timing controller.

[0033] Figure 5 is a block diagram of one of a plurality of data integrated circuits included in a data driver.

[0034] Figure 6A and Figure 6B is a graph showing a display device according to an alternative embodiment of the present disclosure.

[0035] Figure 7 is a graph showing a display device according to another alternative embodiment of the present disclosure.

[0036] Figure 8A is a graph showing a first gate delay signal, and Figure 8B is a graph showing a second gate delay signal.

[0037] Figure 9 is a block diagram of an embodiment of the sensing unit shown in Figure 7

[0038] Figure 10 is a block diagram of one of a plurality of data integrated circuits included in a data driver.

[0039] Figures 11A to 11C is a graph showing a display device according to other alternative embodiments of the present disclosure.

[0040] Figure 12 is a block diagram of a timing controller according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The present application will now be described more fully with reference to the accompanying drawings, in which various embodiments of the application are shown. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0042] ​​It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0043] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms "a", "an" and "the" are intended to include both singular and plural forms, unless the context clearly indicates otherwise. For example, the term "an element" is intended to mean at least one element, unless the context clearly indicates otherwise. The term "at least one" is not intended to limit "a" or "an". The term "or" means "and / or" as used herein. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0045] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's relationship to another element as the device is oriented in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if a device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can, therefore, encompass both an orientation of "lower" and "upper," depending on the particular orientation being referred to. Similarly, if a device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The terms "below" or "beneath" can, therefore, encompass both an orientation of "below" and "above," depending on the particular orientation being referred to.

[0046] In the drawings, the size of some of the elements can be exaggerated for illustrating clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements can also be present. Like reference numerals refer to like elements throughout the specification.

[0047] Portions unrelated to the description will be omitted for clarity of the description of the disclosure, and the same or similar constituent elements will be denoted by the same reference numerals throughout the specification. Therefore, the same reference numerals can be used to identify the same or similar elements in different drawings.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] The implementations described herein are not to be interpreted to be limited to the specific shapes of regions illustrated herein, but rather include deviations from the shapes of regions that can result, for example, from manufacturing. For example, regions shown or described as flat can generally have rough and / or nonlinear features. Moreover, illustrated corners can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to show the precise shape of a region and are not intended to limit the scope of the present claims.

[0050] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 FIG. 1 is a diagram illustrating a display device 10 according to an embodiment of the present disclosure.

[0052] In an embodiment of the present disclosure, for convenience of description, a lateral direction (or horizontal direction) on a plane is referred to as a first direction DR1, and a longitudinal direction (or vertical direction) on the plane is referred to as a second direction DR2. The first direction DR1 and the second direction DR2 can mean that the first direction DR1 and the second direction DR2 respectively indicate directions.

[0053] Referring to Figure 1 An embodiment of the display device 10 can include a display panel 100, a gate driver 200, a data driver 300, and a timing controller 400.

[0054] The display panel 100 can display an image, and includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm. The plurality of gate lines G1 to Gn can extend in the first direction DR1 and be sequentially arranged in the second direction DR2. The plurality of data lines D1 to Dm can extend in the second direction DR2 and be sequentially arranged in the first direction DR1.

[0055] A plurality of pixels PX can be arranged in an area where the plurality of gate lines G1 to Gn and the plurality of data lines D1 to Dm intersect each other, or in an area defined by the plurality of gate lines G1 to Gn and the plurality of data lines D1 to Dm.

[0056] Each of the plurality of pixels PX is connected to a respective gate line among the plurality of gate lines G1 to Gn and a respective data line among the plurality of data lines D1 to Dm. When a gate signal is supplied to the respective gate line connected to each of the plurality of pixels PX, each of the plurality of pixels PX is supplied with a data signal through the respective data line connected thereto, and emits light having a luminance corresponding to the supplied data signal.

[0057] In an embodiment, each of the plurality of pixels PX can include a light emitting element, a switching transistor that transfers a data signal in response to a gate signal, a storage capacitor that stores the data signal transferred through the switching transistor, and a driving transistor that supplies a driving current corresponding to the stored data signal to the light emitting element. The light emitting device can be an organic light emitting element or an inorganic light emitting element.

[0058] The timing controller 400 can control the gate driver 200 and the data driver 300. The timing controller 400 can receive data and control signals from the outside, and generate a vertical start signal STV and a clock signal CLk, and a horizontal start signal STH and a source output enable signal SOE based on the control signals. The timing controller 400 can supply the vertical start signal STV and the clock signal CLk to the gate driver 200, and supply the horizontal start signal STH and the source output enable signal SOE to the data driver 300. In addition, the timing controller 400 can supply image data DATA to the data driver 300.

[0059] The gate driver 200 and the data driver 300 can drive the display panel 100.

[0060] The gate driver 200 can generate a gate signal in response to the vertical start signal STV and the clock signal CLk provided from the timing controller 400, and output the gate signal to a plurality of gate lines G1 to Gn.

[0061] The data driver 300 can generate a data signal (or a data voltage) based on the image data DATA, and the horizontal start signal STH and the source output enable signal SOE provided from the timing controller 400, and output the data signal to a plurality of data lines D1 to Dm.

[0062] The dummy data unit 210 can be connected to one end of at least one data line among the plurality of data lines D1 to Dm, and the sensing unit 320 can be connected to an opposite end of the at least one data line among the plurality of data lines D1 to Dm.

[0063] In an embodiment, the dummy data unit 210 can be disposed in the gate driver 200. The dummy data unit 210 can be provided in an end portion of the gate driver 200. In an embodiment, although Figure 1 The dummy data unit 210 can be disposed in the gate driver 200. The dummy data unit 210 can be provided in an end portion of the gate driver 200. In an embodiment, although

[0064] The dummy data unit 210 can supply a dummy data signal DDS to the connection line CL. The dummy data signal DDS can be a data voltage having a specific voltage value within a predetermined voltage range of a data signal (for example, a voltage in a range of 3 volts (V) to 9 V).

[0065] The connection line CL can electrically connect one data line among the plurality of data lines D1 to Dm to the dummy data unit 210. The data line connected to the dummy data unit 210 through the connection line CL can be a data line disposed adjacent to the gate driver 200. In an embodiment, as Figure 1The data line electrically connected to the dummy data unit 210 through the connection line CL can be a first data line D1 arranged adjacent to the gate driver 200.

[0066] A switching element SW can be further provided or connected between the connection line CL and the dummy data unit 210.

[0067] The switching element SW can be turned on when no data signal is supplied from the data driver 300 along the plurality of data lines D1 to Dm. In an embodiment, the switching element SW can be turned on at least once during a manufacturing process of the display panel 100. This will be described in detail later.

[0068] When the display panel 100 is normally driven, for example, when a data signal is supplied from the data driver 300 to the plurality of data lines D1 to Dm, the switching element SW remains in an off state.

[0069] The switching element SW can be turned on or off by a control signal SS. In an embodiment, the control signal SS can be a signal supplied from the outside during a manufacturing process, but the present disclosure is not limited thereto. In an alternative embodiment, the control signal SS can be supplied to the switching element SW from the timing controller 400.

[0070] In an embodiment, an opposite end portion of the data line (e.g., the first data line D1) electrically connected to the dummy data unit 210 through the connection line CL can be connected to the sensing unit 320. In such an embodiment, the opposite end portion of the first data line D1 electrically connected to the dummy data unit 210 through the connection line CL can be connected to the sensing unit 320.

[0071] In an embodiment, the sensing unit 320 can be provided in the data driver 300. However, the present disclosure is not limited thereto, and alternatively, the sensing unit 320 can be provided in the timing controller 400.

[0072] The switching element SW can be set to an on state in a period in which a load of the plurality of data lines D1 to Dm is sensed or detected during a manufacturing process or in other periods. The dummy data unit 210 supplies a dummy data signal DDS to the sensing unit 320 via the first data line D1. The dummy data signal DDS supplied to the sensing unit 320 can be delayed by a predetermined time in correspondence with a load of the data line (e.g., the first data line D1) to which the dummy data signal DDS is supplied.

[0073] The sensing unit 320 can determine the load of the first data line D1 by using the received dummy data signal DDS, and supply a data delay value DDV corresponding to the determined load to the timing controller 400. The timing controller 400 can generate a source output enable signal SOE for controlling the timing of data signals supplied to the plurality of data lines D1 to Dm, based on the supplied data delay value DDV.

[0074] The timing controller 400 can supply the source output enable signal SOE to the data driver 300. Details thereof will be described later with reference to Figure 3 The configuration of the sensing unit 320 and signal conversion will be described in detail.

[0075] Figure 2A The dummy data signal DDS supplied from the dummy data unit 210 is shown, Figure 2B The dummy data signal DDS input to the sensing unit 320 via the data line is shown, and Figure 2C and Figure 2D is a graph showing the timing of the gate signal GS to be supplied with respect to the dummy data signal DDS.

[0076] Figure 2C is a graph showing Figure 2A the comparison between the dummy data signal DDS and the gate signal GS shown in Figure 2D is a graph showing Figure 2B the comparison between the dummy data signal DDS and the gate signal GS shown in

[0077] Referring to Figure 1 , the dummy data signal DDS supplied from the dummy data unit 210 is supplied to the sensing unit 320 via the first data line D1.

[0078] The dummy data signal DDS can have a waveform (or voltage, etc.) that changes due to the load of the first data line D1. In an embodiment, as shown in Figure 2A , the dummy data signal DDS output from the dummy data unit 210 can be set to a voltage higher than the reference voltage Vref during a first time period T1, compared to the constant reference voltage Vref.

[0079] In an embodiment, as shown in Figure 2B , the dummy data signal DDS input to the sensing unit 320 via the first data line D1 can have a voltage higher than the reference voltage Vref during a second time period T2 shorter than the first time period T1, compared to the reference voltage Vref.

[0080] In this embodiment, as described above, when the voltage (or waveform) of the virtual data signal DDS changes due to the load of the first data line D1, even when the same data signal is supplied, different voltages can be charged in the plurality of pixels PX corresponding to the positions of the data driver 300 and the plurality of pixels PX. The plurality of pixels PX can generate light having different brightness based on the same data signal.

[0081] Figure 2C and Figure 2D is a graph showing a timing of the gate signal GS to be supplied with respect to the virtual data signal DDS.

[0082] Referring to Figure 2C , when the virtual data signal DDS is not delayed, the gate signal GS can overlap with the maximum voltage of the virtual data signal DDS during the third time period T3. Accordingly, during the third time period T3, the gate signal GS and the virtual data signal DDS can be stably supplied to the pixel PX.

[0083] However, referring to Figure 2D , when the virtual data signal DDS is delayed, the gate signal GS can overlap with the maximum voltage of the virtual data signal DDS during a fourth time period T4 shorter than the third time period T3. Accordingly, the voltage supplied to the pixel PX can not be sufficient to emit light having a predetermined brightness.

[0084] Figure 3 is a block diagram illustrating an embodiment of the sensing unit 320 shown in Figure 1 . Figure 4 is a waveform graph illustrating a supply timing of the data signal DS controlled by the timing controller 400.

[0085] Referring to Figure 3 , an embodiment of the sensing unit 320 can include a converter 331 and a delay calculator 333.

[0086] The converter 331 can convert the virtual data signal DDS into a digital signal. In this embodiment, the converter 331 can be an Analog-To-Digital Converter (ADC). The converter 331 can convert the virtual data signal DDS in an analog form into virtual delay data DSD. The virtual delay data DSD can be a digital value used to calculate a charging time.

[0087] In an embodiment, the converter 331 can compare the reference voltage Vref and the virtual data signal DDS as shown in Figure 2B , and output the virtual delay data DSD in a digital form based on a comparison result. The virtual delay data DSD can have a value corresponding to the second time period T2.

[0088] Converter 331 can supply virtual delayed data DSD to delay calculator 333. Delay calculator 333 can calculate the data delay value DDV of the delayed data signal DS.

[0089] In one implementation, the delay calculator 333 can determine the supply timing of the second time period T2 of the virtual data signal DDS based on the virtual delay data DSD, and calculate the data delay value DDV so that the supply timing of the second time period T2 can be set to the desired timing. In this implementation, the delay calculator 333 can calculate the data delay value DDV, and through the data delay value DDV, the maximum voltage of the gate signal GS and the data signal DS can be... Figure 4 The lands shown overlap each other to the greatest extent possible.

[0090] In this implementation, the virtual delay data DSD is the value corresponding to the maximum load of the first data line D1. The delay calculator 333 can additionally calculate the data delay value DDV corresponding to the minimum load from the maximum load by using the virtual delay data DSD.

[0091] In the implementation method, as shown in the example Figure 2A The data latency value DDV corresponding to the case where no delay occurs (i.e., minimum load) shown can be pre-stored in the latency calculator 333. The pre-stored data latency value DDV corresponding to the minimum load can be a second data latency value. In an embodiment, the second data latency value can be "00000000".

[0092] In this implementation, the latency calculator 333 calculates a data latency value DDV corresponding to the maximum load calculated using the virtual latency data DSD as described above. The data latency value DDV corresponding to the maximum load calculated using the virtual latency data DSD can be a first data latency value. In this implementation, the first data latency value can be "01001111".

[0093] Subsequently, by using the data delay value DDV corresponding to the maximum load and the data delay value DDV corresponding to the minimum load, the delay calculator 333 can additionally calculate the data delay value corresponding to the load between the maximum and minimum loads. The data delay value DDV corresponding to the intermediate load, calculated using the data delay values ​​DDV corresponding to the maximum load and the minimum load, can be a third data delay value. In an embodiment, the third data delay value can have any one of a plurality of values ​​between "01001111" and "00000000".

[0094] The data delay value DDV generated by the delay calculator 333 is supplied to the timing controller 400.

[0095] The timing controller 400 can generate a source output enable signal SOE based on the supplied data delay value DDV. The source output enable signal SOE can be a signal for controlling the output timing of the data signal DS supplied from the data driver 300.

[0096] The timing controller 400 can generate the source output enable signal SOE based on the order in which the data signal DS is supplied and the data delay value DDV. In an embodiment, the timing controller 400 can control the supply timing of the data signal DS to be supplied later based on the data delay value DDV corresponding to the maximum load of the first data line D1. In this embodiment, the timing controller 400 can control the supply timing of the data signal DS to be supplied first among all the data signals DS to be supplied based on the data delay value DDV corresponding to the minimum load of the first data line D1.

[0097] In an embodiment of the present disclosure, as described above, the load of the first data line D1 is determined by using the dummy data signal DDS measured by the sensing unit 320, and as shown in Figure 4 the supply timing of the data signal DS is controlled so that the data signal DS corresponding to the determined load can be stably supplied to the pixel PX.

[0098] In this embodiment of the present disclosure, the first data line D1 and the remaining data lines D2 to Dm can have substantially the same load as each other. In this embodiment, the plurality of data lines D1 to Dm formed by the same process are set to have the same load as each other or similar loads to each other, and thus, the load of all the remaining data lines D2 to Dm can be determined by using the dummy delay data DSD of one data line, i.e., the first data line D1.

[0099] Figure 5 is a block diagram illustrating one of the plurality of data integrated circuits 340 included in the data driver 300.

[0100] Referring to Figure 5 In an embodiment, a plurality of data integrated circuits 340 can be included in the data driver 300. The data integrated circuits 340 can be supplied with the horizontal start signal STH, the image data DATA, and the source output enable signal SOE from the timing controller 400.

[0101] The data integrated circuit 340 can output a plurality of data signals DS1 to DSk generated therein through a plurality of channels CH1 to CHk. The plurality of data signals DS1 to DSk output from the data integrated circuit 340 can have different output timings from each other.

[0102] Embodiments of the data integration circuit 340 can include a shift register 341, a serial-parallel converter 349, a holding latch 342, a control latch 343, a digital-to-analog converter (DAC) 344, and a buffer 345.

[0103] In embodiments, the shift register 341 can receive the horizontal start signal STH and shift the horizontal start signal STH to the next data integration circuit. In such embodiments, the shift register 341 can sequentially output the first to kth activation signals En1 to Enk to the holding latch 342 based on the shift of the horizontal start signal STH.

[0104] The serial-parallel converter 349 can receive the image data DATA, convert the image data DATA into the first to kth parallel data DA1 to DAk, and output the first to kth parallel data DA1 to DAk to the holding latch 342.

[0105] The holding latch 342 can sequentially and temporarily store the first to kth parallel data DA1 to DAk in response to the first to kth activation signals En1 to Enk being sequentially supplied. The holding latch 342 can output the stored first to kth parallel data DA1 to DAk to the control latch 343.

[0106] The control latch 343 can receive the first to kth parallel data DA1 to DAk corresponding to a current pixel row based on the source output enable signal SOE and simultaneously supply the first to kth parallel data DA1 to DAk stored therein corresponding to a previous pixel row to the DAC 344.

[0107] The control latch 343 can supply the first to kth parallel data DA1 to DAk stored therein to the DAC 344 when the source output enable signal SOE is supplied. That is, the output timing of the first to kth parallel data DA1 to DAk of the control latch 343 can be controlled by the source output enable signal SOE.

[0108] The source output enable signal SOE controls the supply timing based on the load of the plurality of data lines D1 to Dm, and thus, the data signal DS can be supplied at a desired time based on the load of the plurality of data lines D1 to Dm.

[0109] Accordingly, in embodiments, the timing controller 400 can supply the source output enable signal SOE having different timings for each horizontal line (i.e., for each pixel row). In such embodiments, the timing controller 400 can supply the source output enable signal SOE having different timings for each horizontal line.

[0110] The DAC 344 can generate a plurality of data signals DS1 to DSk by using the first to kth parallel data DA1 to DAk. The plurality of data signals DS1 to DSk generated by the DAC 344 can be supplied to the plurality of data lines D1 to Dk via the buffer 345.

[0111] Figure 6A and Figure 6B FIG. 1 is a diagram illustrating a display device 10 according to an embodiment of the disclosure.

[0112] In Figure 6A , the same or similar elements have been marked with the same reference numerals as those used to describe the embodiment shown in Figure 1 , and any repetitive detailed description thereof will be omitted or simplified hereinafter for convenience of description.

[0113] Referring to Figure 6A , in an alternative embodiment, the dummy data unit 210 can be arranged at one end portion of the gate driver 200, and the sensing unit 220 can be arranged at the opposite end portion of the gate driver 200.

[0114] The dummy data unit 210 can supply a dummy data signal DDS, and the sensing unit 220 can receive the dummy data signal DDS.

[0115] In this embodiment, the dummy data unit 210 is connected to one end portion of one data line among the plurality of data lines D1 to Dm via a first connection line CL1. In this embodiment, the sensing unit 220 is connected to the opposite other end portion of the one data line among the plurality of data lines D1 to Dm via a second connection line CL2.

[0116] The data line connected to the first and second connection lines CL1 and CL2 can be the data line most adjacent to the gate driver 200. In an embodiment, the data line most adjacent to the gate driver 200 can be the first data line D1.

[0117] A first switching element SW1 can be provided or connected between the first connection line CL1 and the dummy data unit 210, and a second switching element SW2 can be provided or connected between the second connection line CL2 and the sensing unit 220.

[0118] The first switching element SW1 controls connection between the first connection line CL1 and the dummy data unit 210, and the second switching element SW2 controls connection between the second connection line CL2 and the sensing unit 220.

[0119] The first and second switching elements SW1 and SW2 are simultaneously turned on and remain in an off state. The first and second switching elements SW1 and SW2 are turned on in a period (e.g., a processing period) in which the loads of the plurality of data lines D1 to Dm are sensed or detected, and remain in an off state in the remaining period.

[0120] When the first and second switching elements SW1 and SW2 are turned on, the dummy data signal DDS from the dummy data unit 210 is supplied to the sensing unit 220 via the first data line D1. Then, the sensing unit 220 can determine the loads of the plurality of data lines D1 to Dm by using the dummy data signal DDS. Other features of this embodiment are substantially the same as those described with reference to Figures 1 to 5 the described features are substantially the same, and thus any repetitive detailed description thereof will be omitted.

[0121] In an alternative embodiment, the positions of the sensing unit 220 and the dummy data unit 210 in the gate driver 200 can be modified. In the alternative embodiment, the dummy data unit 210 can be arranged in the upper side portion (the opposite end portion) of the gate driver 200, and the sensing unit 220 can be arranged in the lower side portion (one end portion) of the gate driver 200.

[0122] Figure 6B FIG. 1 is a view showing a display apparatus 10 according to another alternative embodiment.

[0123] In Figure 6B , the same or similar elements have been marked with the same reference numerals as those used in the above description of Figure 6A the embodiment shown in FIG. 1, and any repetitive detailed description thereof will be omitted or simplified in the following description for the sake of convenience.

[0124] Referring to Figure 6B , in another alternative embodiment, the dummy data unit 210 and the sensing unit 220 can be connected to each other via a separate dummy data line DDL. The dummy data line DDL can be arranged adjacent to the gate driver 200 and disposed to intersect the plurality of gate lines G1 to Gn in the display panel 100.

[0125] The dummy data unit 210 can be connected to one end (or the opposite end) of the dummy data line DDL, and the sensing unit 220 can be connected to the opposite end (or one end) of the dummy data line DDL.

[0126] The operation processes of the dummy data unit 210 and the sensing unit 220 are substantially the same as those described above, and thus any repetitive detailed description thereof will be omitted.

[0127] Figure 7FIG. 1 is a diagram illustrating a display device 10 according to an embodiment of the present disclosure.

[0128] In Figure 7 , the same or similar elements have been marked with the same reference numerals as those used to describe the embodiments shown in Figure 1 , and for the convenience of description, any repetitive detailed description thereof will be omitted or simplified in the following.

[0129] Referring to Figure 7 , in an embodiment, the sensing unit 321 can be electrically connected to at least two points of a specific gate line, and additionally determine a load of the specific gate line by receiving gate signals supplied at the at least two points.

[0130] The specific gate line to which the sensing unit 321 is electrically connected can be a gate line disposed adjacent to the data driver 300. In an embodiment, the specific gate line can be the first gate line G1 as shown in Figure 7 . Hereinafter, for the convenience of description, an embodiment in which the specific gate line is the first gate line G1 will be described in detail, but is not limited thereto.

[0131] The two points of the first gate line G1 to which the sensing unit 321 is connected can be two different points among a plurality of points at which the first gate line G1 and the plurality of data lines D1 to Dm intersect each other. In an embodiment, as shown in Figure 7 , the two points can be a point at which the first gate line G1 and the first data line D1 intersect each other and a point at which the first gate line G1 and the m-th data line Dm intersect each other.

[0132] In an embodiment, as shown in Figure 7 , the sensing unit 321 is electrically connected to the first gate line G1 at two points, but the present disclosure is not limited thereto. In an alternative embodiment, the sensing unit 321 can be electrically connected to the first gate line G1 at three or more points or to a single point.

[0133] The sensing unit 321 can be electrically connected to the first gate line G1 at the first point through a first dummy line DL1 and at the second point through a second dummy line DL2.

[0134] The sensing unit 321 can be supplied with the first gate delay signal GDS1 from the first point, and be supplied with the second gate delay signal GDS2 from the second point. The sensing unit 321 supplied with the first gate delay signal GDS1 and the second gate delay signal GDS2 can determine the load of the first gate line G1 by using the first gate delay signal GDS1 and the second gate delay signal GDS2, generate a gate sensing data delay value DDVb corresponding to the determined load, and supply the gate sensing data delay value DDVb to the timing controller 400.

[0135] Figure 8A is a graph showing the first gate delay signal GDS1, and Figure 8B is a graph showing the second gate delay signal GDS2.

[0136] Referring to Figure 8A and Figure 8B , the first gate delay signal GDS1 and the second gate delay signal GDS2 have a wavelength (or a voltage, etc.) that changes in correspondence with the load of the first gate line G1. In an embodiment, as shown in Figure 8A , the first gate delay signal GDS1 can be set to a voltage higher than the reference voltage Vref1 during the fifth time period T5, compared to the constant reference voltage Vref1.

[0137] In such an embodiment, as shown in Figure 8B , the second gate delay signal GDS2 can be set to a voltage higher than the reference voltage Vref1 for a sixth time period T6 shorter than the fifth time period T5, compared to the reference voltage Vref1.

[0138] The load of the first gate line G1 can be determined by using the first gate delay signal GDS1 and the second gate delay signal GDS2. In such an embodiment of the disclosure, the load of the first gate line G1 can be determined by using the first gate delay signal GDS1 and the second gate delay signal GDS2, by various methods currently known in the art.

[0139] Figure 9 is a block diagram showing an embodiment of the sensing unit 321 shown in Figure 7

[0140] In Figure 9 , the same or similar elements have been marked with the same reference numerals as those used above for describing the embodiment shown in Figure 3 , and any repetitive detailed description thereof will be omitted or simplified in the following for the convenience of description.

[0141] In an embodiment, as shown in Figure 9 ​As shown in FIG. 3, the sensing unit 321 can include a first converter 331a and a second converter 331b. The first converter 331a is substantially the same as the converter 331 shown in FIG. 3, and can convert the virtual data signal DDS in analog form into virtual delay data DSD. Figure 3 The converter 331 shown in FIG. 3 is substantially the same as the converter 331 shown in FIG. 3, and can convert the virtual data signal DDS in analog form into virtual delay data DSD.

[0142] The second converter 331b can convert each of the first gate delay signal GDS1 and the second gate delay signal GDS2 into a digital signal. In this embodiment, the second converter 331b can be an ADC. The second converter 331b can convert the first gate delay signal GDS1 in analog form into first gate delay data GDD1, and convert the second gate delay signal GDS2 in analog form into second gate delay data GDD2. The first gate delay data GDD1 and the second gate delay signal GDD2 can correspond to digital values used to calculate the charging time of each pixel PX.

[0143] In an embodiment, as shown in FIG. 3, the second converter 331b can output the first gate delay data GDD1 by comparing the reference voltage Vref1 and the first gate delay signal GDS1, and output the second gate delay data GDD2 by comparing the reference voltage Vref1 and the second gate delay signal GDS2. The first gate delay data GDD1 can have a value corresponding to the fifth time period T5, and the second gate delay data GDD2 can have a value corresponding to the sixth time period T6. Figure 8A and Figure 8B In an embodiment, as shown in FIG. 3, the second converter 331b can output the first gate delay data GDD1 by comparing the reference voltage Vref1 and the first gate delay signal GDS1, and output the second gate delay data GDD2 by comparing the reference voltage Vref1 and the second gate delay signal GDS2. The first gate delay data GDD1 can have a value corresponding to the fifth time period T5, and the second gate delay data GDD2 can have a value corresponding to the sixth time period T6.

[0144] The second converter 331b can supply the first gate delay data GDD1 and the second gate delay data GDD2 to the delay calculator 333. The delay calculator 333 can calculate a data sensing data delay value DDVa based on the virtual delay data DSD, and calculate a gate sensing data delay value DDVb based on the first gate delay data GDD1 and the second gate delay data GDD2. The data sensing data delay value DDVa can be a data delay value DDV shown in FIG. 3. Figure 3

[0145] The delay calculator 333 can determine a load of the first gate line G1 by using the first gate delay data GDD1 and the second gate delay data GDD2, and calculate the gate sensing data delay value DDVb corresponding to the determined load.

[0146] The data sensing data delay value DDVa and the gate sensing data delay value DDVb generated by the delay calculator 333 are supplied to the timing controller 400.

[0147] ​The timing controller 400 can generate a plurality of source output enable signals SOE1 to SOEn so that the loads of the plurality of data lines D1 to Dm and the plurality of gate lines G1 to Gn can be compensated based on the supplied data sense data delay value DDVa and the gate sense data delay value DDVb.

[0148] In an embodiment, the timing controller 400 can generate the plurality of source output enable signals SOE1 to SOEn based on the gate sense data delay value DDVb. In an embodiment, the timing controller 400 can output the first source output enable signal SOE1 based on the gate sense data delay value DDVb corresponding to the minimum load of the first gate line G1, and output the nth source output enable signal SOEn based on the gate sense data delay value DDVb corresponding to the maximum load of the first gate line G1.

[0149] In this embodiment, the timing controller 400 can control the supply timing of the first source output enable signal SOE1 to the nth source output enable signal SOEn in units of horizontal lines (or units of blocks including a plurality of horizontal lines) corresponding to the data sense data delay value DDVa.

[0150] In an embodiment of the disclosure, the first gate line G1 and the remaining gate lines G2 to Gn can have the same load as each other. In this embodiment, the plurality of gate lines G1 to Gn formed by the same process are set to have the same load as each other or have similar loads to each other, and thus, the loads of all the remaining gate lines G2 to Gn can be stably determined by using the first gate delay data GDD1 and the second gate delay data GDD2 from one gate line, i.e., the first gate line G1.

[0151] Figure 10 is a block diagram illustrating one of a plurality of data integrated circuits 340' included in the data driver 300.

[0152] Referring to Figure 10 The plurality of source output enable signals SOE1 to SOEn can be supplied to the plurality of divided regions 343a to 343n of the control latch 343', respectively. In an embodiment, the first source output enable signal SOE1 can be supplied to the first region 343a of the control latch 343', and the nth source output enable signal SOEn can be supplied to the nth region 343n of the control latch 343'.

[0153] When the plurality of source output enable signals SOE1 to SOEn are supplied, the control latch 343' supplies the first to kth parallel data DA1 to DAk stored therein to the DAC 344. That is, the output timing of the first to kth parallel data DA1 to DAk of the control latch 343' is controlled by the plurality of source output enable signals SOE1 to SOEn.

[0154] The output timing of the plurality of source output enable signals SOE1 to SOEn is controlled based on the load of the plurality of data lines D1 to Dm and the load of the plurality of gate lines G1 to Gn.

[0155] Accordingly, the timing controller 400 can supply the plurality of source output enable signals SOE1 to SOEn having different timing from each other for each of at least one horizontal line (i.e., each pixel row) and for each of at least one vertical line (i.e., each pixel column).

[0156] Figures 11A to 11C FIG. 10 is a diagram illustrating a display apparatus 10 according to other alternative embodiments of the present disclosure.

[0157] In Figures 11A to 11C , the same or similar elements have been marked with the same reference numerals as those used to describe the embodiments shown in Figure 1 , and any repetitive detailed description thereof will be omitted or simplified hereinafter for the convenience of description.

[0158] Referring to Figure 11A , in an embodiment, the data driver 300 can include a first data driver 300a and a second data driver 300b.

[0159] The first data driver 300a can be disposed at one side of the display panel 100, and the second data driver 300b can be disposed at the opposite side of the display panel 100. In an embodiment, the first data driver 300a can be disposed at the upper side of the display panel 100, and the second data driver 300b can be disposed at the lower side of the display panel 100.

[0160] The dummy data unit 310 can be disposed in the first data driver 300a, and the sensing unit 320 can be disposed in the second data driver 300b. However, the present disclosure is not limited thereto. In alternative embodiments, the dummy data unit 310 can be disposed in the second data driver 300b, and the sensing unit 320 can be disposed in the first data driver 300a.

[0161] The sensing unit 320 disposed in the second data driver 300b can determine the load of the data line (e.g., the first data line D1) by receiving a signal supplied from the dummy data unit 310 disposed in the first data driver 300a.

[0162] Referring to Figure 11B In an alternative embodiment, the data driver 300 can be disposed at one side of the display panel 100, and the sensing unit 520 can be disposed at the opposite side of the display panel 100. In an embodiment, the data driver 300 can be disposed at the upper side of the display panel 100, and the sensing unit 520 can be disposed at the lower side of the display panel 100.

[0163] The dummy data unit 310 can be disposed in the data driver 300. The sensing unit 520 can be separately provided with a connection line CL electrically connected to the first data line D1. The sensing unit 520 can determine the load of the data line (e.g., the first data line D1) by receiving a signal supplied from the dummy data unit 310.

[0164] Referring to Figure 11C In another alternative embodiment, the dummy data unit 310 can be disposed in the data driver 300, and the sensing unit 220 can be disposed in the gate driver 200. The dummy data unit 310 can be electrically connected to one side of the first data line D1, and the other side of the first data line D1 can be electrically connected to the connection line CL.

[0165] The connection line CL can be electrically connected to the sensing unit 220, and a switching element SW can be disposed or connected between the sensing unit 220 and the connection line CL. When the switching element SW is turned on, the sensing unit 220 can supply a signal supplied to the first data line D1. The sensing unit 220 can determine the load of the data line (e.g., the first data line D1) by receiving a signal supplied from the dummy data unit 310.

[0166] Referring to Figures 11A to 11C In an embodiment, the dummy data unit 310 can be separately disposed in the first data driver 300a or the data driver 300, but the present disclosure is not limited thereto. In an alternative embodiment, the dummy data unit 310 can be configured as a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C, or can be defined by a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C. Figure 5 Figure 10 In an embodiment, the dummy data unit 310 can be separately disposed in the first data driver 300a or the data driver 300, but the present disclosure is not limited thereto. In an alternative embodiment, the dummy data unit 310 can be configured as a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C, or can be defined by a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C. Figure 5 Figure 10 In an embodiment, the dummy data unit 310 can be separately disposed in the first data driver 300a or the data driver 300, but the present disclosure is not limited thereto. In an alternative embodiment, the dummy data unit 310 can be configured as a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C, or can be defined by a part of the data integration circuit 340 shown in FIG. 3B or the data integration circuit 340' shown in FIG. 3C. ​​

[0167] Figure 12 This is a block diagram illustrating a timing controller 400 according to an embodiment of the present disclosure.

[0168] Implementations of the timing controller 400 may include a source output enable signal controller 451 (hereinafter referred to as the "SOE controller"), an overdrive controller 453, and an amplifier bias controller 455.

[0169] SOE controller 451 can control the output timing of source output enable signal SOE based on the data delay value DDV as described above.

[0170] When a data signal is supplied, the overdrive controller 453 can supply an overdrive voltage by comparing previous data with the current data. The overdrive controller 453 can additionally supply a data delay value DDV and additionally control the overdrive voltage so that the loads of the multiple data lines D1 to Dm and / or the multiple gate lines G1 to Gn corresponding to the data delay value DDV are compensated.

[0171] In one implementation, the overdrive controller 453 may supply a high overdrive voltage corresponding to a first level value having the maximum data delay value DDV, and a low overdrive voltage corresponding to a second level value having the minimum data delay value DDV.

[0172] The amplifier bias controller 455 generates a bias current. The bias current generated by the amplifier bias controller 455 is supplied to... Figure 5 or Figure 10 The buffer 345 is shown in the diagram. In an embodiment, the buffer (i.e., amplifier) ​​345 is included in the channel of each of the data integrated circuits 340 and 340', and the amplifier bias controller 455 controls the bias current to each buffer 345. The amplifier 345 can supply data with different slew rates corresponding to the bias current.

[0173] The amplifier bias controller 455 may additionally supply a data delay value DDV and a bias current such that the loads of the plurality of data lines D1 to Dm and / or the plurality of gate lines G1 to Gn are compensated based on the data delay value DDV. In an embodiment, the amplifier bias controller 455 may supply a high bias current corresponding to a first level value having the maximum data delay value DDV and a low bias current corresponding to a second level value having the minimum data delay value DDV.

[0174] In the embodiment of the present application, the display device controls the supply timing of the data signal supplied to the data line based on the data on the load, so that the charging time of the pixel voltage can be ensured. Therefore, in this embodiment, the charging rate of the pixel can be improved, and the quality of the image displayed in the display device can be improved.

[0175] The present application should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the application to those skilled in the art.

[0176] While the application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope or spirit of the application as defined by the appended claims.

Claims

1. A display apparatus comprising: a dummy data unit connected to one end of a data line, wherein the dummy data unit supplies a dummy data signal to the data line, and the data line is connected to a pixel; a sensing unit connected to an opposite end of the data line, wherein the sensing unit senses a load of the data line based on the dummy data signal supplied to the sensing unit through the data line, the sensing unit is electrically connected to at least two points of a certain gate line, and determines a load of the certain gate line based on gate signals supplied to the sensing unit from the at least two points; a timing controller that controls a supply timing of a data signal to be supplied to the data line based on the load of the data line; a connection line that electrically connects the dummy data unit and the data line to each other; a switching element connected between the connection line and the dummy data unit; a data driver that supplies the data signal to the data line; and a gate driver that supplies a gate signal to a gate line, wherein the dummy data unit is disposed in the gate driver, and wherein the sensing unit is disposed in the data driver.

2. The display device according to claim 1, wherein The sensing unit comprises: a converter that converts the dummy data signal into dummy delay data in digital form; and a delay calculator that generates a data delay value based on the dummy delay data.

3. The display device according to claim 2, wherein The data delay value is a first data delay value corresponding to a maximum load of the data line.

4. The display device according to claim 3, wherein The delay calculator prestores a second data delay value corresponding to a minimum load of the data line, and additionally calculates a third data delay value corresponding to an intermediate load of the data line based on the first data delay value and the second data delay value.

5. The display device according to claim 1, wherein The data driver comprises: a shift register that generates an activation signal; a holding latch that is supplied with data from the timing controller and sequentially stores the data from the timing controller in response to the activation signal; a control latch that is simultaneously supplied with the data stored in the holding latch when a source output enable signal is supplied to the control latch; a digital-to-analog converter that is supplied with the data from the control latch when the source output enable signal is supplied to the control latch and generates the data signal based on the data supplied from the control latch to the digital-to-analog converter; and a buffer that transmits the data signal to the data line.

6. The display device of claim 5, wherein, The timing controller controls the supply timing of the data signal by changing a supply timing of the source output enable signal.

7. The display device according to claim 1, wherein The certain gate line is a gate line disposed adjacent to the data driver.

8. The display device according to claim 1, wherein The sensing unit comprises: a first converter that converts the dummy data signal into dummy delay data in digital form; and a second converter that converts the dummy delay data into an analog form. a second converter that converts the gate signals from the at least two points into a digital form of gate sensing data; and a delay calculator that generates a data delay value based on the dummy delay data and the gate sensing data.

9. The display device according to claim 1, wherein The timing controller further includes: a source output enable signal controller that controls the supply timing of the data signal; an overdrive controller that controls an overdrive voltage based on the load; and an amplifier bias controller that controls a bias current to be supplied to an amplifier included in the data driver based on the load.

10. The display device according to claim 1, wherein The switch element is turned on when the dummy data signal is supplied to the data line, and the switch element remains in an off state when the data signal is supplied to the data line.

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