Semiconductor storage device and operating method thereof

Abstract

The embodiment of the present invention provides a semiconductor memory device and an operation method thereof that can know whether the reading of setting information is completed correctly during the power-on action. The semiconductor memory device and the operation method provided by the present invention read the fuse memory when it is detected that the power supply voltage reaches the power-on detection level, and determine whether the reading of the fuse memory is completed correctly. When it is determined that it is not completed correctly, the fuse memory is read again within the maximum reading number range, and the setting information read from the fuse memory is written to the CF register. Furthermore, the identification data for identifying whether the reading of the fuse memory is completed correctly is stored in the register.

Description

Technical Field

[0001] The present invention relates to a semiconductor storage device such as a flash memory and an operation method thereof, and in particular to a startup operation of the semiconductor storage device when power is input. Background Art

[0002] NAND flash memory uses fuse memory to store parameters such as voltage, timing, internal voltage, etc. (hereinafter, information about setting such actions is referred to as setting information) for setting reading, programming, erasing, etc. For example, a fuse memory area that cannot be accessed by the user is provided in the memory cell array. When power is input, the flash memory reads the setting information stored in the fuse memory as a power-on action, and writes the setting information into a register (hereinafter, such a register storing setting information is referred to as a convenience configuration (CF) register). After the power-on action, the controller can control various actions according to the setting information stored in the CF register. Summary of the invention

[0003] Figure 1 This is a diagram to illustrate the power-on action when power is input to the flash memory. As an example, the power supply voltage VCC supplied from the outside is set to 3.0V, the action guarantee voltage of the internal circuit is 2.7~3.3V, and the power-on detection level is 2.2V. At time t1 after the power is input, the power supply voltage VCC rises to the power-on detection level, and the controller responds to the power-on detection, reads the setting information from the fuse memory, and writes the read setting information into the CF register. Afterwards, at time t2, the power supply voltage VCC rises to the action guarantee voltage, so normal action can begin.

[0004] During the boot operation, since the reading of the fuse memory is performed before the power supply voltage rises to the guaranteed voltage, when reading the setting information from the fuse memory, it may be performed at a lower voltage level, making the reading of the fuse memory unstable. If the power supply capacity on the user side is insufficient, the reading of the fuse memory cannot be performed correctly due to the fluctuation of the power supply voltage or noise, and the setting information written to the CF register will be wrong. Therefore, in order to improve reliability, it will be determined whether the reading of the fuse memory is completed correctly. If it is not completed correctly, the reading of the fuse memory will be repeated.

[0005] Figure 2 The flowchart is a flow chart showing the reading action of the fuse memory during the power-on action in the prior art. When the power supply voltage VCC reaches the power-on detection level, the power-on is detected (S100), and the internal controller reads the fuse memory (S110). The fuse memory stores characteristic data such as setting information at a specific address, and this information can be read.

[0006] The controller checks whether the characteristic data is correct (S120). For example, the characteristic data is a data type of "0" and "1" such as "AAh" or "55h". If the characteristic data is correct, the controller determines that the reading of the fuse memory is correct, and sets the setting information in the CF register to end the reading of the fuse memory (S130).

[0007] On the other hand, if the characteristic data is wrong, the controller will confirm whether the number of reads of the fuse memory has reached the maximum value (S140). If not, the fuse memory is read again (S110). If the number of reads has reached the maximum value, the controller writes the setting information into the CF register and ends the reading of the fuse memory (S150).

[0008] When the characteristic data read from the fuse memory is incorrect, it means that in the case where step S150 ends, the setting information read from the fuse memory and written into the CF register may contain errors, so that the wrong setting information is used during reading, programming, erasing, etc. (for example, applying an abnormal voltage level, or applying voltage at an inappropriate timing, etc.), resulting in erroneous operation. Furthermore, when analyzing the cause of the erroneous operation, it may take a lot of time and resources to investigate the cause because it is not known that the setting information is the cause of the erroneous operation.

[0009] The present invention aims to solve such a conventional problem and provides a semiconductor memory device that can know whether the reading of setting information is completed correctly during the power-on operation. Furthermore, the present invention aims to provide a semiconductor memory device that has the function of re-reading setting information after the power-on operation.

[0010] The semiconductor storage device of the present invention includes: a storage cell array; a storage device including a storage area configured to store setting information related to the setting of an action; a controller, when detecting that the power supply voltage is at a power-on detection level, reads the setting information from the storage device, loads the read setting information into a register, and responds to an external instruction to store identification data configured to identify whether the reading of the setting information is completed correctly in a readable register.

[0011] The operation method of the semiconductor storage device of the present invention includes: pre-storing setting information related to the setting of the action in a non-volatile storage area; detecting the power supply voltage during the power-on action, and when it is detected that the power supply voltage reaches the power-on detection level, reading the setting information from the storage area, determining whether the reading of the setting information is completed correctly, and re-reading the setting information when it is determined that the reading is not completed correctly; loading the setting information read from the storage area into a temporary register; and storing identification data in a readable temporary register, wherein the identification data is configured to identify whether the number of times the setting information is read has reached a maximum value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram for explaining the booting action of a flash memory.

[0013] Figure 2 A flow chart showing a flash memory read operation during a power-on operation in the related art.

[0014] Figure 3 A block diagram showing the structure of a flash memory according to an embodiment of the present invention.

[0015] Figure 4 A flow chart showing a flash memory read operation during a power-on operation according to an embodiment of the present invention.

[0016] Figure 5 A flow chart showing a conventional flash memory reset operation.

[0017] Figure 6 A flow chart showing the reset operation of the flash memory according to the second embodiment of the present invention.

[0018] Figure 7 A flow chart showing an internal reset operation of the fuse memory of the flash memory according to the third embodiment of the present invention.

[0019] Figure 8 A flowchart showing a power-on retry operation of a fuse memory of a flash memory according to a fourth embodiment of the present invention.

[0020] Fig. 9 A flow chart showing the reading, programming or erasing operations of the fuse memory of the flash memory according to the fifth embodiment of the present invention.

[0021] Description of reference numerals:

[0022] 100: Flash memory

[0023] 110: memory cell array

[0024] 120: Input and output buffer

[0025] 130: Address register

[0026] 140: Controller

[0027] 150: word line selection circuit

[0028] 160: Page buffer / sensing circuit

[0029] 170: Row selection circuit

[0030] 180: register

[0031] 190: Voltage detection unit

[0032] 200: Internal voltage generating circuit DETAILED DESCRIPTION

[0033] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily.

[0034] Next, the semiconductor storage device of the present invention is described. Although a NAND flash memory is used as an example of an embodiment of the semiconductor storage device, the present invention is not limited thereto. The semiconductor storage device may also be a storage device having a structure that reads setting information from a nonvolatile memory during a boot operation.

[0035] Figure 3 A block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention. Figure 3 The flash memory 100 includes: a memory cell array 110, which is formed by a plurality of memory cells; an input / output buffer 120, which is connected to an external input / output terminal I / O; an address register 130, which receives address data from the input / output buffer 120; a controller 140, which receives instruction data from the input / output buffer 120; a word line selection circuit 150, which selects a block and a word line according to a column address Ax from the address register 130; and a page buffer / sensing circuit 160, which stores the read data of a page selected by the word line selection circuit or stores the data to be programmed to the selected page. programming data; a row selection circuit 170, which selects a row of the page buffer / sensing circuit 160 according to the row address information Ay from the address register 130; a register 180, for example, a non-volatile register; a voltage detection unit 190, which detects whether the power supply voltage VCC supplied from the outside reaches the power-on detection level, and provides the detection signal DET to the controller 140; an internal voltage generation circuit 200, which generates various voltages required for reading, programming and erasing (programming voltage Vpgm, read voltage Vread, erase voltage Vers, pass voltage Vpass, etc.).

[0036] The memory cell array 110 has m blocks BLK(0), BLK(1), ..., BLK(m-1), one block is formed by a plurality of NAND strings, and a plurality of memory cells are connected in series in one NAND string. In addition, the memory cell array 110 includes a fuse memory, which stores setting information for setting parameters such as the operating voltage or timing of the flash memory in an area not used by the user (or an area that cannot be accessed by the user). In addition, in addition to storing such setting information, the fuse memory also stores characteristic data at a specific address. The characteristic data is data used to verify whether the fuse memory is correctly read during the power-on action. In one embodiment, the data is, for example, "AAh" or "55h".

[0037] In addition to receiving command data from the input / output buffer 120, the controller 140 also receives the setting information for setting the parameters such as the operating voltage or timing of the flash memory from the fuse memory, and writes the setting information into the CF register (not shown) in the controller 140 to control various actions performed on the flash memory according to the setting information stored in the CF register.

[0038] The register 180 stores data showing various states of the flash memory 100. In this embodiment, a portion of the register 180 stores identification data POFAIL for identifying whether the reading of the fuse memory is correctly completed during the power-on operation. In one embodiment, the controller 140 receives an instruction for reading the register 180 from the outside, reads the identification data stored in the register 180, and outputs the read identification data to the outside.

[0039] The voltage detection unit 190 detects whether the power supply voltage VCC reaches the power-on detection level. For example, the power supply voltage VCC is 3.0V. After the power supply is input, when the power supply voltage VCC reaches the power-on detection level (e.g., 2.2V), the voltage detection unit 190 outputs a detection signal DET to the controller 140. The power-on detection level is lower than the operation guarantee voltage (e.g., 2.7V to 3.3V) of the flash memory during normal operation.

[0040] For example, the controller 140 includes a microcontroller such as a CPU or ROM / RAM, or a state machine. For example, the ROM stores programs for executing booting actions, reading actions, programming actions, erasing actions, etc. The controller 140 controls each action by executing these programs.

[0041] When the controller 140 receives the detection signal DET from the voltage detection unit 190, the power-on action is performed. In addition, when the controller 140 receives a read instruction, a programming instruction, or an erase instruction from the outside, these actions are performed. In the read action, a positive voltage is applied to the bit line, a voltage such as 0V is applied to the selected word line, a pass voltage is applied to the non-selected line, the bit line side selection transistor and the source line side selection transistor are turned on, and 0V is applied to the common source line. In the programming action, a high voltage programming voltage Vpgm is applied to the selected word line, an intermediate potential is applied to the non-selected word line, the bit line side selection transistor is turned on, the source line side selection transistor is turned off, and a voltage responding to the data "0" or "1" is supplied to the bit line. In the erase action, 0V is applied to the selected word line in the block, a high voltage is applied to the P-type well, and the data is erased in units of blocks.

[0042] Figure 4 The flowchart of the power-on action of this embodiment is shown. When the power is input, the voltage detection unit 190 provides a detection signal DET to the controller 140 after detecting that the power voltage VCC reaches the power-on detection level (2.2V) (S200). In response to the detection signal DET, the controller 140 starts to read the fuse memory in the memory cell array to read out the setting information and characteristic data stored in the fuse memory (S210).

[0043] The controller 140 compares the read characteristic data with a preset value to determine whether the characteristic data is correct (S220). If the characteristic value is the same as the preset value, the identification data POFAIL=0 is written into the register 180, and the setting data read from the fuse memory is written into the CF register (S230), and the reading of the fuse memory is terminated (S240).

[0044] On the other hand, if the characteristic data is different from the preset value in step S220, it indicates that an error occurs in reading the fuse memory. The controller 140 first confirms whether the number of times the fuse memory is read has reached a maximum value (S250). If not, the controller 140 returns to steps S210 to S220 to read the fuse memory and determine the characteristic data again. If the number of times the fuse memory is read has reached the maximum value, the identification data POFAIL=1 is written in the register 180, and the setting data read from the fuse memory is written in the CF register (S260), and the reading of the fuse memory is terminated (S270).

[0045] It is worth mentioning that in this embodiment, the identification data POFAIL is used to indicate whether the reading of the fuse memory is correctly completed before reaching the maximum value. Specifically, the identification data POFAIL=0 indicates that the reading of the fuse memory is correctly completed before reaching the maximum value, which means that the setting information written to the CF register is reliable; in contrast, the identification data POFAIL=1 indicates that the reading of the fuse memory is not correctly completed before reaching the maximum value (the characteristic data is different from the expected value), so an error may occur in the setting information written to the CF register.

[0046] After the power-on action, when the power supply voltage VCC reaches the action guarantee voltage, the flash memory 100 becomes ready to respond to external instructions to perform actions. If the user inputs an instruction to read the register 180 at any timing, the controller 140 will respond to the read instruction, read the data of the register 180, and output the read data through the external terminal. By checking the identification data POFAIL of the register 180, the user can know whether the reading of the fuse memory during the power-on action is completed correctly. If the identification data POFAIL=1, because the reading of the fuse memory during the power-on action is not completed correctly, the setting information written into the CF register may be wrong, and the user can restart the power-on action, etc.

[0047] According to this embodiment, whether the reading of the fuse memory is completed correctly can be determined based on the identification data POFAIL stored in the register 180. When the flash memory malfunctions due to the setting information error in the CF register, the user can easily know the cause of the malfunction.

[0048] Figure 5 If a reset command is input from the outside (S300), the controller 140 will confirm whether the flash memory is in operation (ie busy) (S310), and if it is in operation, the operation will be stopped (S320), and the internal circuits including the registers will be reset.

[0049] Figure 6 The flowchart of a reset operation according to an embodiment of the present invention is shown. The embodiment responds to a reset command from a user to re-read the fuse memory. Figure 6 Steps S400 to S420 and Figure 5The steps S300 to S320 are the same and will not be described again. Furthermore, in the present embodiment, the controller 140 checks whether the identification data POFAIL of the register 180 is 0 (S430) before resetting the internal circuit. If the identification data POFAIL=0, the internal circuit is directly reset (S440). If the identification data POFAIL=1, the fuse memory is read again, and the read setting information is written into the CF register 180 (S460), and then the internal circuit is reset (S440).

[0050] It is worth mentioning that when the reset instruction is implemented, since the power supply voltage VCC of the flash memory has reached the action guarantee voltage, the reading of the fuse memory during the reset action is more stable than the reading of the fuse memory during the power-on action, and a higher reliability reading can be performed. Therefore, if the identification data POFAIL=1 is detected during the reset action (i.e., the reading of the fuse memory during the power-on action is not completed correctly), the setting information can be rewritten to the setting information read during the reset action by re-reading the fuse memory during the reset action, thereby reducing the occurrence of erroneous actions of the flash memory.

[0051] Figure 7 A flowchart showing the internal reset action of another embodiment of the present invention is shown. In this embodiment, after the power-on action, the internal reset command is responded to to re-read the fuse memory. Figure 7 After the power-on action is completed (S500), if the power supply voltage VCC of the flash memory 100 reaches the operation guarantee voltage, the controller 140 implements the internal reset instruction (S510). In one embodiment, the internal reset instruction can be automatically implemented after a predetermined time has passed since the power-on action. Next, the controller 140 checks whether the identification data POFAIL of the register 180 is 0 (S520). If the identification data POFAIL=0, the action is terminated directly. If the identification data POFAIL=1, the fuse memory is read again, and the read setting information is written to the CF register (S530), and then the action is terminated.

[0052] According to the present embodiment, by automatically performing an internal reset action after the power-on action (i.e., the power supply voltage VCC reaches the operation guarantee voltage), when it is found that the reading of the fuse memory is not correctly completed during the power-on action, the fuse memory is read again, and the setting information with higher reliability is rewritten into the CF register, thereby preventing the flash memory from erroneous action.

[0053] Figure 8 A flowchart showing a power-on retry action according to another embodiment of the present invention is shown. This embodiment responds to a preset user command different from a reset command to re-read the fuse memory. Figure 8When a power-on retry command is input from the outside (S600), the controller 140 checks whether the identification data POFAIL of the register 180 is 0 according to the power-on retry command (S610). If the identification data POFAIL=0, the operation is terminated directly. If the identification data POFAIL=1, the fuse memory is read again, and the read setting information is written into the CF register (S620), and the operation is terminated.

[0054] In this embodiment, because the flash memory is also operated with the action guarantee voltage when the power-on retry instruction is implemented, the read reliability of the fuse memory is higher than that during the power-on action, and the correct setting information can be written into the CF register.

[0055] Fig. 9 A flowchart showing a read, program or erase operation according to an embodiment of the present invention is shown. This embodiment responds to read, program or erase commands.

[0056] To read the fuse memory again. Fig. 9 When the controller 140 receives a read, program or erase command from the outside (S700), before starting these actions, it checks whether the identification data POFAIL of the register 180 is 0 (S710). If the identification data POFAIL=0, the read, program or erase actions are performed directly (S730). If the identification data POFAIL=1, the fuse memory is read again, and the read setting information is written to the CF register (S720), and then the read, program or erase actions are performed (S730).

[0057] According to the present embodiment, before reading, programming or erasing is performed, it can be confirmed whether the setting information in the CF register may be erroneous based on the identification data POFAIL. When it is detected that the identification data POFAIL=1, the fuse memory is read again to rewrite the setting data in the CF register. Therefore, the action voltage or action timing of the reading, programming or erasing action can be set based on more reliable setting information, thereby preventing the erroneous action of the flash memory.

[0058] In the above embodiment, although NAND flash memory is used as an example, the present invention can also be applied to a semiconductor memory device that performs a power-on operation. In addition, in the above embodiment, although the fuse memory is disposed within the memory cell array, it can also be disposed in a non-volatile storage area different from the memory cell array.

[0059] The present invention has been described in detail with respect to the preferred embodiments. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor storage device, characterized in that: include: A memory cell array; a storage device including a storage area configured to store setting information related to setting of the action; as well as A controller that does the following: When the power supply voltage at the time of the power-on action is detected to be at the power-on detection level, the setting information is read from the storage device, the read setting information is written into the register, and in response to an external instruction, identification data configured to identify whether the reading of the setting information is completed correctly is stored in the register; as well as The controller determines whether the reading of the setting information is completed correctly, and if it is determined that the reading of the setting information is not completed correctly, re-reads the setting information; The value of the identification data is determined according to whether the number of times the setting information is read reaches a maximum value; When the value of the identification data indicates that the reading of the setting information reaches the maximum value, the controller re-reads the setting information from the storage device and writes the read setting information into the register.

2. The semiconductor memory device according to claim 1, wherein The controller reads the identification data from the register in response to an external instruction, and outputs the read identification data to the outside.

3. The semiconductor memory device according to claim 1, wherein: The controller performs a reset in response to an external reset command, wherein the controller checks the value of the identification data stored in the register before performing the reset.

4. The semiconductor memory device according to claim 1, wherein: After the power-on action is performed, the controller responds to an internal reset instruction.

5. The semiconductor memory device according to claim 1, wherein: The controller performs a specific action in response to an external specific instruction, wherein the controller checks the value of the identification data stored in the register before performing the specific action, and when the value of the identification data shows that the reading of the setting information has reached the maximum value, executes the operation of re-reading the setting information from the storage device and writing the read setting information into the register.

6. The semiconductor memory device according to claim 5, wherein: The specific command is a read command, a program command, an erase command or a power-on retry command.

7. The semiconductor memory device according to any one of claims 1 to 6, wherein: The power-on detection level is lower than the action voltage when executing the command.

8. A method for operating a semiconductor memory device, characterized in that: include: Pre-storing setting information related to the setting of the action in a non-volatile storage area; detecting a power supply voltage during a power-on action, and when it is detected that the power supply voltage reaches a power-on detection level, reading the setting information from the storage area, determining whether the reading of the setting information is completed correctly, and re-reading the setting information if it is determined that the reading of the setting information is not completed correctly; Writing the setting information read from the storage area into the temporary register; storing identification data in a readable register, wherein the identification data is configured to identify whether the number of times the setting information is read from the storage area has reached a maximum value; as well as In response to the reset command, the value of the identification data is checked, and when the value of the identification data shows that the number of times the setting information is read reaches the maximum value, the setting information is read again from the storage area, and the read setting information is written into the register.

9. The operating method of a semiconductor memory device according to claim 8, wherein: Also includes: In response to an external command, the identification data is read from the register, and the read identification data is output to the outside.

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