Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and an operating method thereof are disclosed. A semiconductor memory device includes a pre-charge block, a selection block, a peripheral circuit, and control logic. The pre-charge block is connected to bit lines and includes memory cells in an erased state. The selection block shares the bit lines with the pre-charge block and includes memory cells in a programmed state. The peripheral circuit performs an erase operation on the selection block. The control logic controls the peripheral circuit to turn on a first circuit connected to the pre-charge block when an erase voltage is applied to a source line commonly connected to the pre-charge block and the selection block, and to apply a first voltage to a global line connected to the first circuit. The memory cells of the pre-charge block are turned on by the first voltage applied from the global line, and the erase voltage applied to the source line is transmitted to the plurality of bit lines through the pre-charge block.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. BACKGROUND

[0002] A memory device can be formed in a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate, or in a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. A three-dimensional memory device addresses the integration limit of a two-dimensional memory device and can include a plurality of memory cells vertically stacked on a semiconductor substrate. SUMMARY

[0003] Embodiments of the disclosure aim to provide a semiconductor memory device having an improved erase operation speed and a method of operating the same.

[0004] A semiconductor memory device according to an embodiment of the disclosure includes a pre-charge block, a selection block, a peripheral circuit, and a control logic. The pre-charge block is connected to a plurality of bit lines and includes memory cells in an erase state. The selection block shares the plurality of bit lines with the pre-charge block and includes memory cells in a program state. The peripheral circuit performs an erase operation on the selection block. The control logic controls the peripheral circuit to turn on a first block selection circuit connected to the pre-charge block when an erase voltage is applied to a source line commonly connected to the pre-charge block and the selection block, and to apply a first voltage to a global line connected to the first block selection circuit. The memory cells of the pre-charge block are turned on by the first voltage applied from the global line, and the erase voltage applied to the source line is transmitted to the plurality of bit lines through the memory cells of the pre-charge block.

[0005] A semiconductor memory device according to another embodiment of the disclosure includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory blocks connected to a plurality of bit lines. The peripheral circuit performs an erase operation on a selection block among the plurality of memory blocks. The control logic controls the peripheral circuit to turn on a first block selection circuit connected to the selection block by applying a first voltage to the first block selection circuit when an erase voltage is applied to a source line connected to the selection block, and to apply a second voltage to a global line connected to the first block selection circuit. The memory cells of the selection block are turned on by the second voltage applied from the global line, and the erase voltage applied to the source line is transmitted to the plurality of bit lines through the memory cells of the selection block.

[0006] According to still another embodiment of the present disclosure, according to a method of operating a semiconductor memory device including a plurality of memory blocks, a first block selection circuit connected to a first memory block among the plurality of memory blocks is turned on; memory cells included in the first memory block are turned on by applying a first voltage to a global line connected to the first block selection circuit; and an erase voltage is transmitted to a bit line connected to the first memory block by starting to apply the erase voltage to a common source line connected to the first memory block.

[0007] A semiconductor memory device according to another embodiment of the present disclosure includes a target block, an erased block, first and second circuits, and a control circuit, a memory cell array, a peripheral circuit, and a control logic. The target block and the erased block respectively include first and second cell strings commonly coupled to a source line and a bit line. The first and second circuits are configured to, when turned on, respectively couple the target block and the erased block to a global line. The control circuit is configured to perform an erase operation on the target block by: during a set time period, turning on the second circuit by a second voltage and providing a third voltage to the global line to turn on the second cell string, while turning on the first circuit by a first voltage lower than the second voltage, providing an erase voltage to the source line to pre-charge the bit line by the turned-on second cell string, and after the set time period, providing a fourth voltage to a select line among the global line.

[0008] A semiconductor memory device according to another embodiment of the present disclosure includes a target block, a selection circuit, and a control circuit. The target block includes a cell string coupled to a source line and a bit line. The selection circuit is configured to, when turned on, couple the target block to a global line. The control circuit is configured to perform an erase operation on the target block by: during a set time period, applying a first voltage to turn on the selection circuit and applying a second voltage to the global line to turn on the cell string, the second voltage being lower than the first voltage; applying an erase voltage to the source line to pre-charge the bit line by the turned-on cell string; after the set time period, applying a third voltage lower than the first voltage to turn on the selection circuit; and after the set time period, applying a fourth voltage to a select line among the global line.

[0009] The present technology can provide a semiconductor memory device having an improved erase operation speed and a method of operating the same. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating an embodiment of a memory cell array of Figure 1 .

[0012] Figure 3 is a circuit diagram illustrating any one of memory blocks BLK1 to BLKz of Figure 2

[0013] Figure 4 is a circuit diagram illustrating another embodiment of any one of memory blocks BLK1 to BLKz of Figure 2

[0014] Figure 5 is a circuit diagram illustrating an embodiment of any one of memory blocks BLK1 to BLKz included in a memory cell array of Figure 1

[0015] Figure 6 is a block diagram illustrating an address decoder.

[0016] Figure 7 is a graph illustrating an erase operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 8 is a timing chart illustrating a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 9 is a flowchart illustrating a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 10 is a graph illustrating a precharging of a bit line of a block in a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 11 is a graph illustrating an erase operation of a semiconductor memory device according to another embodiment of the present disclosure.

[0021] Figure 12 is a timing chart illustrating a method of erasing data in a semiconductor memory device according to another embodiment of the present disclosure.

[0022] Figure 13 is a flowchart illustrating a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Figure 14 is a graph illustrating a precharging of a bit line of a block in a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Figure 15 is a block diagram illustrating a semiconductor memory device (such as a memory card) including a semiconductor memory device according to an embodiment of the present disclosure. Figure 1 ​​​A block diagram of an embodiment of a memory system of a semiconductor memory device).

[0025] Figure 16 is an example of a memory system such as Figure 15 A block diagram of an application example of a memory system).

[0026] Figure 17 is an example of a system including a memory system such as Figure 16 A block diagram of a computing system having a memory system. DETAILED DESCRIPTION

[0027] The specific structural and functional descriptions provided herein are only for the purpose of describing the embodiments of the present disclosure. However, the present invention can be implemented in various forms and can be implemented in various ways; therefore, the present invention is not limited to the disclosed embodiments. Moreover, throughout the specification, references to "an embodiment", "another embodiment", etc. do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily to the same embodiment. Moreover, the use of indefinite articles (i.e., "one" or "a") means one or more, unless it is clearly intended that only one is intended. Similarly, when the terms "comprise", "comprising", "having", etc. are used in this article, in addition to the elements mentioned, the presence or addition of one or more other elements is not excluded.

[0028] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read / write circuit 130 , a control logic 140 , a voltage generator 150 , and a current sensing circuit 160 .

[0030] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells that can have a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional structure. According to an embodiment, the memory cell array 110 can be configured as a three-dimensional structure. Each of the plurality of memory cells included in the memory cell array can store at least one bit of data. In an embodiment, each of the plurality of memory cells in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data. According to an embodiment, the memory cell array 110 can include a plurality of memory cells each storing five or more bits of data.

[0031] The address decoder 120 is connected to the memory cell array 110 through the word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) inside the semiconductor memory device 100.

[0032] The address decoder 120 is configured to decode a block address among the received address. The address decoder 120 selects at least one memory block according to the decoded block address. In addition, the address decoder 120 applies a read voltage Vread generated in the voltage generator 150 to a selected word line of the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines at a read voltage application operation during a read operation. In addition, during a program verify operation, the address decoder 120 applies a verify voltage generated in the voltage generator 150 to the selected word line of the selected memory block and applies the pass voltage Vpass to the remaining unselected word lines.

[0033] The address decoder 120 can be configured to decode a column address among the received address. The address decoder 120 transmits the decoded column address to the read / write circuit 130.

[0034] Read and program operations of the semiconductor memory device 100 are performed in units of pages. Addresses received at the time of requesting read and program operations include a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder 120 and is supplied to the read-write circuit 130. In the present specification, a memory cell connected to one word line can be referred to as a "physical page".

[0035] The read-write circuit 130 includes a plurality of page buffers PB1 to PBm. The read-write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110, and can operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verify operation, in order to sense a threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense a change in an amount of current flowing according to a programmed state of a corresponding memory cell through a sense node while continuously supplying a sense current to a bit line connected to the memory cell, and latch the sensed change as sense data. The read-write circuit 130 operates in response to a page buffer control signal output from the control logic 140. In the present specification, the terms write operation and program operation can be the same.

[0036] During a read operation, the read-write circuit 130 senses data of a memory cell, temporarily stores the read data, and outputs the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In an embodiment, the read-write circuit 130 can include a column selection circuit or the like in addition to a page buffer (or a page register).

[0037] The control logic 140 is connected to the address decoder 120, the read-write circuit 130, the voltage generator 150, and the current sense circuit 160. The control logic 140 receives a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 is configured to control overall operations of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal for adjusting a sense node pre-charge potential level of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read-write circuit 130 to perform a read operation of the memory cell array 110.

[0038] The control logic 140 can determine whether a verify operation for a specific target programmed state is passed or failed in response to a pass signal PASS or a fail signal FAIL received from the current sense circuit 160.

[0039] The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from the control logic 140. To generate a plurality of voltages having various voltage levels, the voltage generator 150 can include a plurality of pump capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pump capacitors in response to control of the control logic 140.

[0040] The current sensing circuit 160 can generate a reference current during a verify operation in response to an enable bit VRY_BTI<#> received from the control logic 140, and can output a pass signal PASS or a fail signal FAIL by comparing a reference voltage generated by the reference current with a sense voltage VPB received from page buffers PB1 to PBm included in the read-write circuit 130.

[0041] More specifically, the current sensing circuit 160 can determine whether a verify operation corresponding to a certain target program state is completed by comparing a voltage generated according to a value of a bit line sense latch included in each of the page buffers PB1 to PBm with a reference voltage generated by the reference current. Referring to Figure 6 The bit line sense latch included in each of the page buffers PB1 to PBm is described below.

[0042] The address decoder 120, the read-write circuit 130, and the voltage generator 150 can function as "peripheral circuits" that perform a read operation, a write operation, and an erase operation on the memory cell array 110. The peripheral circuits perform the read operation, the write operation, and the erase operation on the memory cell array 110 based on control of the control logic 140.

[0043] Figure 2 is a circuit diagram illustrating an embodiment of Figure 1 a memory cell array.

[0044] Referring to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block can have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged in a +X direction, a +Y direction, and a +Z direction. Referring to Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0045] Figure 3 is a circuit diagram illustrating any one of Figure 2 the memory blocks BLK1 to BLKz of

[0046] Referring to Figure 3The memory block BLK includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the memory block BLK, m cell strings are arranged in a row direction (i.e., +X direction). In Figure 3 In an embodiment, two cell strings are arranged in a column direction (i.e., +Y direction). This is for the purpose of clarity, however, three or more cell strings can be arranged in the column direction.

[0047] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0048] Each of the select transistors SST and DST and the memory cells MC1 to MCn can have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film. In an embodiment, a pillar for providing the channel layer can be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating film, the charge storage film, and the blocking insulating film can be provided in each cell string.

[0049] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0050] In an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. In Figure 3 In an embodiment, the source select transistors of the cell strings CS11 to CS1m of the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to a second source select line SSL2.

[0051] In another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m can be commonly connected to one source select line.

[0052] The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

[0053] The first to n-th memory cells MC1 to MCn can be divided into first to p-th memory cells MC1 to MCp and (p+1)th to n-th memory cells MCp+1 to MCn. The first to p-th memory cells MC1 to MCp are arranged in the -Z direction in order and connected in series between the source selection transistor SST and the tubular transistor PT. The (p+1)th to n-th memory cells MCp+1 to MCn are arranged in the +Z direction in order and connected in series between the tubular transistor PT and the drain selection transistor DST. The first to p-th memory cells MC1 to MCp and the (p+1)th to n-th memory cells MCp+1 to MCn are connected to each other through the tubular transistor PT. The gates of the first to n-th memory cells MC1 to MCn of each cell string are connected to the first to n-th word lines WL1 to WLn, respectively.

[0054] The gate of the tubular transistor PT of each cell string is connected to the pipe line PL.

[0055] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The drain selection transistors DST of the cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain selection line DSL2.

[0056] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. In Figure 3 The cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0057] The memory cells connected to the same word line among the cell strings arranged in the row direction constitute a page. For example, the memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m of the first row constitute a page. The memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m of the second row constitute another page. The cell strings arranged in one row direction can be selected by selecting any one of the drain selection lines DSL1 and DSL2. A page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0058] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the mth bit line BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines, respectively.

[0059] In an embodiment, at least one of the first memory cell MC1 to the n-th memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLK is improved, but the size of the memory block BLK increases. As fewer memory cells are provided, the size of the memory block BLK can be reduced, but the operation reliability of the memory block BLK can be degraded.

[0060] To effectively control the dummy memory cells, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation of the memory block BLK, a program operation can be performed on all or part of the dummy memory cells. When the erase operation is performed after the program operation is performed, the dummy memory cells can have the desired threshold voltage by controlling a voltage applied to a dummy word line connected to the respective dummy memory cells.

[0061] Figure 4 is a circuit diagram illustrating another embodiment of any one of the memory blocks BLK1 to BLKz of Figure 2

[0062] Referring to Figure 4 , the memory block BLK' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends in the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, first memory cells MC1 to n-th memory cells MCn, and at least one drain select transistor DST stacked on a substrate (not shown) under the memory block BLK1'.

[0063] ​The source select transistor SST of each cell string is connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11′ to CS1m′ arranged in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21′ to CS2m′ arranged in the second row are connected to a second source select line SSL2. In another embodiment, the source select transistors of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ can be connected in common to one source select line.

[0064] The first to nth memory cells MC1 to MCn of each cell string are connected in series between a source select transistor SST and a drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0065] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11′ to CS1m′ in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21′ to CS2m′ in the second row are connected to the second drain select line DSL2.

[0066] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 4 The memory block BLK′ has Figure 3 The equivalent circuit of the memory block BLK is similar to the equivalent circuit.

[0067] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to the even bit lines, and odd cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to the odd bit lines, respectively.

[0068] In an embodiment, at least one of the first memory cell MC1 to the nth memory cell MCn can function as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLK' is improved, but the size of the memory block BLK' increases. As fewer memory cells are provided, the size of the memory block BLK' can be reduced, but the operation reliability of the memory block BLK' can be degraded.

[0069] To effectively control the dummy memory cells, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation on the memory block BLK', a program operation can be performed on all or part of the dummy memory cells. When the erase operation is performed after the program operation is performed, the dummy memory cells can have the desired threshold voltage by controlling a voltage applied to a dummy word line connected to the respective dummy memory cell.

[0070] Figure 5 is a circuit diagram illustrating an embodiment of any one of the memory blocks BLK1 to BLKz included in the memory cell array 110 of Figure 1 .

[0071] Referring to Figure 5 , the memory block BKL" includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm can be connected to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0072] Each of the select transistors SST and DST and the memory cells MC1 to MCn can have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film. In an embodiment, a pillar for providing the channel layer can be disposed in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating film, the charge storage film, and the blocking insulating film can be disposed in each cell string.

[0073] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn.

[0074] The first memory cell MC1 to the n-th memory cell MCn of each cell string is connected between the source select transistor SST and the drain select transistor DST.

[0075] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn.

[0076] The memory cells connected to the same word line constitute one page. The cell strings CS1 to CSm can be selected by selecting the drain select line DSL. One page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0077] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Even-numbered cell strings among the cell strings CS1 to CSm can be connected to the even-numbered bit lines, and odd-numbered cell strings can be connected to the odd-numbered bit lines, respectively.

[0078] As described above, the memory cells connected to one word line can configure one physical page. In the example shown in FIG. 1, the m memory cells connected to any one of the plurality of word lines WL1 to WLn among the memory cells belonging to the memory block BLK" configure one physical page. Figure 5

[0079] As shown in FIG. 1, the memory cell array 110 of the semiconductor memory device 100 can be configured in a three-dimensional structure. Alternatively, the memory cell array 110 can also be configured in a two-dimensional structure as shown in FIG. 2. Figure 2 to Figure 4 Figure 5

[0080] Figure 6 is a block diagram illustrating an address decoder.

[0081] Referring to Figure 6 The global lines GL include the global drain select line GDSL, the global source select line GSSL, and the global word lines GWL1 to GWL32, and the voltages of various levels generated by the voltage generator 150 are transmitted to the global lines GL.

[0082] The address decoder 120 includes the block selection circuits BSCK1 to BSCKz. The block selection circuits BSCK1 to BSCKz are connected to the corresponding memory blocks BLK1 to BLKz, respectively.

[0083] The address decoder 120 transmits the voltages applied to the global lines to the local lines DSL, SSL, and WL1 to WL32 of the selected memory block in response to the block selection signals BLSLC1 to BLSLCz.

[0084] ​​​Specifically, each of the block selection circuits BSCK1 to BSCKz included in the address decoder 120 is configured to transfer a voltage applied to the global line GL to the local lines DSL, SSL, and WL1 to WL32 by connecting the global line and the local lines DSL, SSL, and WL1 to WL32 in response to the block selection signals BLSLC1 to BLSLCz.

[0085] For example, when the memory cell array 110 includes z (z is a positive integer) memory blocks, the address decoder 120 includes z block selection circuits BSCK1 to BSCKz. During an erase operation, the block selection circuit connected to a selected memory block to be erased can be turned on, and thus the global line GL and the local lines DSL, SSL, and WL1 to WL32 can be connected. The block selection circuits connected to unselected memory blocks not subjected to the erase operation can be turned off.

[0086] Figure 7 is a diagram illustrating an erase operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0087] Referring to Figure 7 , the a-th memory block BLKa to the d-th memory block BLKd are commonly connected to the first bit line BL1 to the m-th bit line BLm. The a-th memory block BLKa to the d-th memory block BLKd can be included in the memory cell array 110. The memory cell array 110 can include more memory blocks than the four memory blocks shown in Figure 7 ; the four memory blocks BLKa to BLKd are shown as an example in Figure 7 . The gates of the memory cells included in the a-th memory block BLKa to the d-th memory block BLKd can be connected to local word lines, respectively, and the local word lines can be connected to a global word line through corresponding block selection circuits BSCKa to BSCKd.

[0088] The local word line LWL of the a-th memory block BLKa can be connected to the global word line GWL through the block selection circuit BSCKa. The local word line LWL of the b-th memory block BLKb can be connected to the global word line GWL through the block selection circuit BSCKb. The local word line LWL of the c-th memory block BLKc can be connected to the global word line GWL through the block selection circuit BSCKc. The local word line LWL of the d-th memory block BLKd can be connected to the global word line GWL through the block selection circuit BSCKd.

[0089] The local selection lines SSL and DSL of the a-th memory block BLKa can be connected to the global selection lines GSSL and GDSL through the block selection circuit BSCKa. The local selection lines SSL and DSL of the b-th memory block BLKb can be connected to the global selection lines GSSL and GDSL through the block selection circuit BSCKb. The local selection lines SSL and DSL of the c-th memory block BLKc can be connected to the global selection lines GSSL and GDSL through the block selection circuit BSCKc. The local selection lines SSL and DSL of the d-th memory block BLKd can be connected to the global selection lines GSSL and GDSL through the block selection circuit BSCKd.

[0090] The a-th block selection circuit BSCKa to the d-th block selection circuit BSCKd corresponding to the a-th memory block BLKa to the d-th memory block BLKd, respectively, can be connected to the a-th block selection signal BLSLCa to the d-th block selection signal BLSLCd, respectively. The common source line CSL can be commonly connected to the a-th memory block BLKa to the d-th memory block BLKd.

[0091] In Figure 7 In an embodiment of the present disclosure, it is assumed that the c-th memory block BLKc is selected for erasing among the a-th memory block BLKa to the d-th memory block BLKd.

[0092] Accordingly, the c-th memory block BLKc is a selected block, and the b-th memory block BLKb and the d-th memory block BLKd are unselected blocks. In addition, the a-th memory block BLKa among the unselected blocks for pre-charging a bit line is a pre-charging block. According to an embodiment of the present disclosure, the pre-charging block can be in an erase state. That is, any one of the memory blocks BLKa, BLKb, and BLKd in an erase state can be the pre-charging block during an erase operation of the selected memory block BLKc.

[0093] Figure 8 is a timing diagram illustrating a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure.

[0094] Referring to Figure 8 At time t0, the c-th block selection signal BLSLCc applied to the c-th block selection circuit BSCKc connected to the c-th memory block BLKc which is a selected block is activated from 0 V to a V1 level. The V1 level can be a voltage level for turning on a transistor included in the c-th block selection circuit BSCKc. In an embodiment, the V1 level can be a voltage level higher than a voltage for turning on the transistor included in the c-th block selection circuit BSCKc by a set value.

[0095] As the c-th block selection signal BLSLCc is activated to the V1 level, the global word line GWL is connected to the local word line LWL of the c-th memory block BLKc, and the global selection lines GDSL and GSSL are connected to the local selection lines DSL and SSL of the c-th memory block BLKc.

[0096] The b-th block selection signal BLSLCb and the d-th block selection signal BLSLCd applied to the b-th block selection circuit BSCKb and the d-th block selection circuit BSCKd connected to the b-th memory block BLKb and the d-th memory block BLKd as unselected blocks, respectively, can be a relatively low voltage. For example, the b-th block selection signal BLSLCb and the d-th block selection signal BLSLCd can be 0 V. Accordingly, the transistors included in the b-th block selection circuit BSCKb and the d-th block selection circuit BSCKd can be in an off state. Accordingly, the local word line LWL and the selection lines DSL and SSL connected to the b-th memory block BLKb and the d-th memory block BLKd can be in a floating state.

[0097] At time t0, the a-th block selection signal BLSLCa applied to the a-th block selection circuit BSCKa connected to the a-th memory block BLKa as a pre-charge block is activated from 0 V to a V2 level. The V2 level can turn on the transistors included in the a-th block selection circuit BSCKa. In an embodiment, the V2 level can be a signal equal to or greater than the V1 level. Accordingly, the transistors included in the a-th block selection circuit BSCKa can be turned on more strongly than the transistors included in the c-th block selection circuit BSCKc.

[0098] At time t0 or immediately after time t0, the source bias applied to the common source line CSL can start to increase toward the erase voltage Verase.

[0099] At time t0, a voltage of V3 level is applied to the global word line GWL and the global selection lines GDSL and GSSL. As described above, since the a-th block selection signal BLSLCa is activated from 0 V to the V2 level at time t0, the transistors included in the a-th block selection circuit BSCKa are strongly turned on. Accordingly, the voltage V3 applied to the global word line GWL and the global selection lines GDSL and GSSL is transferred to the local word line LWL and the local selection lines DSL and SSL connected to the a-th block selection circuit BSCKa. As described above, since the pre-charge block is a memory block in an erased state, the selection transistors and the memory cells included in the pre-charge block are all turned on. Accordingly, the voltage applied to the common source line as a source bias is transferred to the first to m-th bit lines BL1 to BLm through the pre-charge block.

[0100] That is, at the start of the erase operation for the selected block BLKc, when the memory cells in the pre-charge block BLKa in the erase state and the select transistors are turned on for a short time (short turn-on), the erase voltage Verase is smoothly transferred from the common source line CSL to the first to mth bit lines BL1 to BLm through the cell strings in the pre-charge block BLKa. Thus, the first to mth bit lines BL1 to BLm commonly connected to the memory block are pre-charged. As a result, the erase operation can be performed quickly. The improvement of the erase operation speed by pre-charging the bit lines is described below.

[0101] Since the cth block selection signal BLSLCc is activated from OV to the Vl level at time tO, the transistors included in the cth block selection circuit BSCKc are turned on. Thus, the voltages applied to the global word line GWL and the global selection lines GDSL and GSSL are applied to the local word line LWL and the local selection lines DSL and SSL connected to the cth block selection circuit BSCKc. Since the memory cells included in the cth memory block as the selected block include a plurality of program cells, even if the voltage of the V3 level is transferred to the selected block BLKc through the local word line LWL, the source bias of the common source line CSL can not be transferred to the first to mth bit lines BL1 to BLm through the selected block BLKc.

[0102] At time tl, the a th block selection signal BLSLca applied to the a th block selection circuit BSCKa connected to the a th memory block BLKa as the pre-charge block is deactivated from the V2 level to OV. Thus, the transistors included in the a th block selection circuit BSCKa can be turned off, and the local word line LWL and the selection lines DSL and SSL connected to the a th memory block BLKa can be kept in a floating state.

[0103] The voltages of the global word line GWL and the global selection lines GDSL and GSSL can be lowered at time tl. For example, the voltages of the global word line GWL and the global selection lines GDSL and GSSL can be lowered to OV at time tl. In another embodiment, as shown by the dotted line of FIG. 6, the voltages of the global selection lines GDSL and GSSL can be maintained at the V3 level between time tl and time t2. Figure 8

[0104] ​Thereafter, at time t2, the voltages of the global select lines GDSL and GSSL increase to the V4 level, and erasing of the memory cells of the selected block is started. After time t2, a ground voltage can be applied to the local word lines of the selected block. Thereafter, the potential level of the channel increases according to the potential level of the common source line CSL, and the data stored in the memory cells is erased by the increased potential level of the channel. That is, the electrons stored in the charge storage layer of the memory cell by the FN tunneling phenomenon are de-trapped by the potential of the channel. More specifically, the electrons stored in the charge storage layer of the memory cell move to the channel and are de-trapped according to the difference between the increased potential level of the channel and the potential level of the local word line having the ground level, or the hot holes generated in the channel flow into the charge storage layer of the memory cell and de-trap the electrons stored in the charge storage layer.

[0105] After the data of the memory cell is erased by the erase operation, the erase voltage Verase applied to the common source line CSL is blocked, and the potential of the common source line CSL is discharged.

[0106] In the erase operation, when a relatively high erase voltage Verase is applied to the common source line CSL, gate-induced current (gate-induced drain leakage (GIDL)) can occur in the source select transistor, hot holes can be generated and flow in the direction of the channel, and the potential of the channel can increase.

[0107] According to the existing erase method, at this time, the voltage of the bit line can be formed to be lower than the erase voltage of the common source line CSL. Thus, due to the potential difference between the common source line CSL and the bit line, the potentials of the channel and the holes can flow in the direction of the bit line, and thus the erase characteristics can be deteriorated.

[0108] According to the embodiment of the disclosure, at the time when the memory cells and the select transistors in the pre-charge block in the erase state are turned on (short turn-on) for a short time at the start of the erase operation for the selected block, the erase voltage Verase is smoothly transferred from the common source line to the first bit line BL1 to the mth bit line BLm through the cell string in the pre-charge block. Thus, the first bit line BL1 to the mth bit line BLm commonly connected to the memory block are pre-charged. As a result, the erase operation can be performed quickly.

[0109] Figure 9 is a flowchart illustrating a method of erasing data in a semiconductor memory device according to an embodiment of the disclosure. Figure 10 is a diagram illustrating pre-charging of bit lines by a pre-charge block in a method of erasing data in a semiconductor memory device according to an embodiment of the disclosure. This method will be described below with reference to Figure 8 to Figure 10 ​

[0110] Reference Figure 9 In the method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure, first, a first voltage is applied to a first block selection circuit connected to a selected block as an erase target (S110). Figure 7 and Figure 8 In the example shown, the selected block may be the cth memory block BLKc. The first block selection circuit may be Figure 7 In operation S110, the c-th block selection circuit BSCKc may be applied via a block word line connected to the c-th block selection circuit BSCKc. That is, the c-th block selection signal BLSLCc may be applied to the gates of transistors in the c-th block selection circuit BSCKc. Figure 8 As shown, at time t0, the c-th block selection signal BLSLCc increases to V1 level. The first voltage of operation S110 may correspond to Figure 8 Through operation S110, transistors included in the c-th block selection circuit BSCKc connected to the c-th memory block BLKc as a selected block are turned on.

[0111] Then, a second voltage is applied to the second block selection circuit connected to the precharge block in the erase state, and a third voltage is applied to the global word line and the global selection line (S130). The precharge block in the erase state may correspond to Figure 7 and Figure 8 The second block selection circuit may be Figure 7 The a-th block selection circuit BSCKa is shown. In operation S130, the a-th block selection signal BLSLCa may be applied through the block word line connected to the a-th block selection circuit BSCKa. The second voltage and the third voltage of operation S130 may correspond to Figure 8 V2 level and V3 level. Figure 8 Activating the a-th block selection signal BLSLCa to the V2 level and activating the voltages of the global word line GWL and the global selection lines GDSL and GSSL to the V3 level at time t0 may correspond to Figure 9 Therefore, through operation S130, the transistors in the a-th block selection circuit BSCKa connected to the a-th memory block BLKa as the precharge block are turned on. That is, the second block selection circuit connected to the precharge block is turned on.

[0112] Thereafter, an erase voltage is applied to the common source line (S150). Thus, the source bias applied to the common source line CSL increases. As described above, since the memory cells and the selection transistors included in the pre-charge block (i.e., the a-th memory block BLKa) are turned on at time tO, the source bias can be transferred to the first to m-th bit lines BL1 to BLm. Thus, the first to m-th bit lines BL1 to BLm are pre-charged.

[0113] Thereafter, a ground voltage is applied to the second block selection circuit and the global word line (S170). Referring to Figure 8 At time t1, the a-th block selection signal BLSLCa applied to the a-th block selection circuit BSCKa connected to the a-th memory block BLKa as the pre-charge block decreases to 0 V. Thus, the local word line and the selection line connected to the pre-charge block can be floated.

[0114] Thereafter, a fourth voltage is applied to the global selection line (S190). Referring to Figure 8 The voltages of the global selection lines GDSL and GSSL increase to the V4 level at time t2. As the source bias increases to the erase voltage Verase, gate-induced current (gate-induced drain leakage (GIDL)) can occur in the source selection transistor and the drain selection transistor of the c-th memory block BLKc as the selected block, and hot holes can flow in the channel direction. Thus, while the channel potential increases, the voltage of the local word line of the c-th memory block BLKc (i.e., the selected block) is maintained at 0 V, and thus the memory cells included in the c-th memory block BLKc are erased.

[0115] In addition, it is shown that the operations S170 and S190 are sequentially performed in the method of operating the semiconductor memory device according to the embodiment. However, the present application is not limited to this sequence. In another embodiment, the operations S170 and S190 can be performed in reverse order. In yet another embodiment, some of the operations S170 and S190 can be performed simultaneously, while the others are performed in any suitable order consistent with the teachings herein.

[0116] Referring to Figure 10 , the voltage application situation between time tO and time t1 and the bit line pre-charge operation according to the voltage application situation are shown. As described above, between time tO and time t1, the c-th block selection signal BLSLCc is activated to the V1 level, and the a-th block selection signal BLSLCa is activated to the V2 level. Thus, the local word lines LWL connected to the c-th memory block BLKc (i.e., the selected block) and the first memory block BLKa (i.e., the pre-charge block) are connected to the global word line, and the selection lines DSL and SSL connected to the c-th memory block BLKc and the a-th memory block BLKa are connected to the global selection lines GDSL and GSSL, respectively.

[0117] In a case where the cth memory block BLKc is a selected block, since there is a program unit, the plurality of memory cells included in the cth memory block BLKc are turned off. Therefore, the source bias applied to the common source line CSL is not transmitted to the first to mth bit lines BL1 to BLm through the cth memory block BLKc.

[0118] On the other hand, in a case where the ath memory block BLKa is a precharge block, since the ath memory block BLKa is in an erased state, all of the memory cells included in the ath memory block BLKa are turned on. Therefore, the source bias applied to the common source line CSL is rapidly transmitted to the first to mth bit lines BL1 to BLm through the ath memory block BLKa. Therefore, the first to mth bit lines BL1 to BLm are precharged.

[0119] Figure 11 is a timing chart illustrating an erase operation of a semiconductor memory device according to another embodiment of the present disclosure. Comparing Figure 7 and Figure 11 embodiments, in a case of the embodiment illustrated in Figure 7 , the ath memory block BLKa is a precharge block, while in a case of the embodiment illustrated in Figure 11 , there is no precharge block. That is, in Figure 11 , the cth memory block BLKc is a selected block, while the ath memory block BLKa, the bth memory block BLKb, and the dth memory block BLKd are unselected blocks.

[0120] In the embodiment according to Figure 11 , the first to mth bit lines BL1 to BLm are precharged by a selected block without using a precharge block. A detailed method of precharging the first to mth bit lines BL1 to BLm by a selected block will be described below with reference to Figure 12 to Figure 14 .

[0121] Figure 12 is a timing chart illustrating a method of erasing a semiconductor memory device according to another embodiment of the present disclosure.

[0122] Referring to Figure 12 , at time t3, the cth block selection signal BLSLCc applied to the cth block selection circuit BSCKc connected to the cth memory block BLKc which is a selected block is activated from 0 V to a V5 level. The V5 level can be greater than the V1 level illustrated in Figure 8 . For example, the V5 level can be a set value higher than a voltage for turning on a transistor included in the cth block selection circuit BSCKc. In an embodiment, the V5 level can be substantially the same as the V2 level illustrated in Figure 8 .

[0123] As the c-th block selection signal BLSLCc is activated to the V5 level, the global word line GWL is connected to the local word line LWL of the c-th memory block BLKc, and the global selection lines GDSL and GSSL are connected to the local selection lines DSL and SSL of the c-th memory block BLKc.

[0124] The block selection signals BLSLCa, BLSLCb and BLSLCd applied to the block selection circuits BSCKa, BSCKb and BSCKd connected to the memory blocks BLKa, BLKb and BLKd as unselected blocks, respectively, can be 0 V. Accordingly, the local word line LWL and the selection lines DSL and SSL connected to the memory blocks BLKa, BLKb and BLKd can be maintained in a floating state.

[0125] At time t3 or immediately after time t3, the source bias applied to the common source line CSL can start to increase toward the erase voltage Verase.

[0126] At time t3, a voltage of the V6 level is applied to the global word line GWL and the global selection lines GDSL and GSSL. In an embodiment, the V6 level can be equal to or less than the V5 level. As described above, since the c-th block selection signal BLSLCc is activated from 0 V to the V5 level at time t3, the transistor included in the c-th block selection circuit BSCKc is turned on. Accordingly, the voltage V6 applied to the global word line GWL and the global selection lines GDSL and GSSL is transferred to the local word line LWL and the local selection lines DSL and SSL connected to the c-th block selection circuit BSCKc.

[0127] The voltage of the V6 level transferred to the global word line GWL can be capable of turning on all the memory cells included in the selected block BLKc. That is, among the memory cells included in BLKc, the voltage higher than the threshold voltage of the memory cell in the programmed state can be the V6 level. Accordingly, the memory cells in the programmed state are turned off, and the memory cells in the erased state are turned on. Figure 8 Unlike the embodiment of Figure 12 In the embodiment of

[0128] That is, at the start of the erase operation for the selected block BLKc, when the memory cells and the selection transistors in BLKc are turned on for a short time (short conduction), the erase voltage Verase is smoothly transferred from the common source line CSL to the first to mth bit lines BL1 to BLm through the cell strings in BLKc. Thus, the first to mth bit lines BL1 to BLm commonly connected to the memory block are pre-charged. As a result, the erase operation can be performed quickly.

[0129] At time t4, the cth block selection signal BLSLCc applied to the cth block selection circuit BSCKc connected to the cth memory block BLKc as the selected block is decreased from the V5 level to the V7 level. The V7 level can turn on the transistors included in the cth block selection circuit BSCKc. At time t4, the voltage of the global word line GWL and the global selection lines GDSL and GSSL can be decreased. For example, at time t4, the voltage of the global word line GWL and the global selection lines GDSL and GSSL can be decreased to 0 V. In another embodiment, as shown by the dotted line, the voltage of the global selection lines GDSL and GSSL can be maintained at the V6 level between time t4 and time t5. Figure 12

[0130] Thereafter, at time t5, the voltage of the global selection lines GDSL and GSSL is increased to the V8 level, and the erase of the memory cells of the selected block is started. The V8 level can be substantially the same as the V4 level of Figure 8 After time t5, a ground voltage can be applied to the local word line of the selected block. Thereafter, the potential level of the channel is increased according to the potential level of the common source line CSL, and the data stored in the memory cell is erased by the increased potential level of the channel. That is, the electrons stored in the charge storage layer of the memory cell by the FN tunneling phenomenon are de-trapped by the potential of the channel. More specifically, the electrons stored in the charge storage layer of the memory cell move to the channel according to the difference between the increased potential level of the channel and the potential level of the local word line having the ground level, and are de-trapped, or the hot holes generated in the channel flow into the charge storage layer of the memory cell, and de-trap the electrons stored in the charge storage layer.

[0131] According to another embodiment of the present disclosure, at the start of the erase operation for the selected block, when the memory cells and the selection transistors in the selected block are turned on for a short time (short conduction), the erase voltage Verase is smoothly transferred from the common source line to the first to mth bit lines BL1 to BLm through the cell strings in the selected block. Thus, the first to mth bit lines BL1 to BLm commonly connected to the memory block are pre-charged. As a result, the erase operation can be performed quickly.

[0132] Figure 13 ​is a flowchart illustrating a method of erasing a semiconductor memory device according to an embodiment of the present disclosure. Figure 14 is a diagram illustrating precharging of a bit line by a precharge block in a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure. Reference is made to Figure 12 to Figure 14 together describe such a method.

[0133] Reference is made to Figure 12 In a method of erasing data in a semiconductor memory device according to an embodiment of the present disclosure, first, a fifth voltage is applied to a first block selection circuit connected to a selected block that is an object of erasure (S210). In Figure 11 and Figure 12 In the example shown in Figure 11 , the selected block can be the cth memory block BLKc shown in Figure 11 . The first block selection circuit can be the cth block selection circuit BSCKc shown in Figure 12 In operation S210, the cth block selection signal BLSLCc can be applied through a block word line connected to the cth block selection circuit BSCKc. Through operation S210, a transistor included in the cth block selection circuit BSCKc connected to the cth memory block BLKc that is the selected block is turned on. That is, the first block selection circuit connected to the selected block is turned on. At Figure 12 time t3, the cth block selection signal BLSLCc increases from 0 V to a V5 level. The fifth voltage of operation S210 can correspond to the V5 level of

[0134] Then, a sixth voltage lower than the fifth voltage is applied to the global word line and the global selection line (S230). Figure 12 The activation of the voltage of the global word line GWL and the global selection lines GDSL and GSSL to the V6 level at time t3 in Figure 13 corresponds to operation S230 of

[0135] Thereafter, application of an erase voltage to the common source line is started (S250). Accordingly, a source bias applied to the common source line CSL increases. As described above, since the memory cells and the selection transistors in the selected block (i.e., the first memory block) are turned on at time t3, the source bias can be transferred to the first bit line BL1 to the mth bit line BLm. Accordingly, the first bit line BL1 to the mth bit line BLm are precharged.

[0136] Thereafter, the voltage applied to the first block selection circuit is decreased to a seventh voltage, and a ground voltage is applied to the global word line (S270). Reference is made to Figure 12 At time t4, the cth block selection signal BLSLCc decreases from the V5 level to a V7 level.

[0137] Thereafter, an eighth voltage is applied to the global selection line (S290). Referring to Figure 12 The voltages of the global selection lines GDSL and GSSL are increased to the V8 level at time t5. As the source bias increases toward the erase voltage Verase, gate-induced current (gate-induced drain leakage (GIDL)) can occur in the source selection transistor and the drain selection transistor of the cth memory block BLKc as the selected block, and hot holes can flow in the direction of the channel. Therefore, while the potential of the channel increases, the voltage of the local word line of the first memory block (i.e., the selected block) is maintained at 0 V, and thus the memory cells included in the selected block are erased.

[0138] Referring to Figure 13 , it is shown that the operations S210, S230, and S250 are sequentially performed in the method of operating a semiconductor memory device according to an embodiment of the disclosure. However, the present application is not limited to this timing. In another embodiment, the operations S210, S230, and S250 can be performed in a different order. In yet another embodiment, some of the operations S210, S230, and S250 can be performed simultaneously, while the other operations are performed in any suitable order consistent with the teachings herein.

[0139] In addition, it is shown that the operations S270 and S290 are sequentially performed in the method of operating a semiconductor memory device according to an embodiment of the disclosure. However, the present application is not limited to this timing. In another embodiment, the operations S270 and S290 can be performed in the reverse order. In yet another embodiment, some of the operations S270 and S290 can be performed simultaneously, while the other operations are performed in any suitable order consistent with the teachings herein.

[0140] Referring to Figure 14 , it is shown that the voltage application situation between time t3 and time t4 and the bit line pre-charge operation according to the voltage application situation. As described above, between time t3 and time t4, the memory cells included in the cth memory block BLKc as the selected block are all turned on. Therefore, the source bias applied to the common source line CSL is quickly transmitted to the first bit line BL1 through the mth bit line BLm through the cth memory block BLKc. Therefore, the first bit line BL1 through the mth bit line BLm are pre-charged.

[0141] Figure 15 is a block diagram illustrating an embodiment of a memory system 1000 including Figure 1 a semiconductor memory device.

[0142] Referring to Figure 15 , the memory system 1000 includes a semiconductor memory device 100, which can be the semiconductor memory device 100 described with reference to Figure 1A semiconductor memory device is described. The memory system 1000 can further include a controller 1100.

[0143] The controller 1100 is connected to a host and the semiconductor memory device 100. The controller 1100 is configured to access the semiconductor memory device 100 in response to a request from the host. For example, the controller 1100 is configured to control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

[0144] The controller 1100 includes a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 can be used as an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and / or a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the controller 1100. In addition, the controller 1100 can temporarily store program data provided from the host during a write operation.

[0145] The host interface 1130 includes a protocol for performing data exchange between the host and the controller 1100. In an embodiment, the controller 1100 is configured to communicate with the host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and / or a proprietary protocol.

[0146] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0147] The error correction block 1150 is configured to detect and correct errors of data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 1120 can control a read voltage according to an error detection result of the error correction block 1150 and control the semiconductor memory device 100 to perform a re-read. In an embodiment, the error correction block can be provided as a component of the controller 1100.

[0148] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to configure a memory card, such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro-SD), an SD card (SD, mini-SD, micro-SD, or SDHC), and / or a universal flash storage (UFS).

[0149] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as the semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is greatly improved.

[0150] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an electronic book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a 3-dimensional TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID device, or one of various components configured for a computing system.

[0151] In an embodiment, the semiconductor memory device 100 or the memory system 1000 can be mounted as various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 can be packaged and mounted in a method such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), wafer-level fabricated chip, wafer on wafer, wafer level chip scale, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), or wafer-level stacked package (WSP).

[0152] Figure 16 is a block diagram illustrating an application example of a memory system including the semiconductor memory device 100 described with reference to Figure 15 .

[0153] Referring to Figure 16 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips is divided into a plurality (e.g., k) of groups.

[0154] In each group, the semiconductor memory chips are configured and operated similarly to the semiconductor memory device 100 described with reference to Figure 16 . Figure 1

[0155] Each group is configured to communicate with the controller 2200 through its designated channel. The controller 2200 is configured similarly to the controller 1100 described with reference to Figure 15 , and is configured to control the plurality of memory chips of the semiconductor memory device 2100 through the plurality of channels CH1 to CHk.

[0156] Figure 17 is a block diagram illustrating a computing system including the memory system described with reference to Figure 16 .

[0157] The computing system 3000 includes a central processing device 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and the memory system 2000.

[0158] ​The memory system 2000 is electrically connected to the central processing device 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing device 3100 is stored in the memory system 2000.

[0159] In Figure 17 , the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 can be configured to be directly connected to the system bus 3500. The functions of the controller 2200 are performed by the central processing device 3100 and the RAM 3200.

[0160] In Figure 17 , the memory system 2000 described with reference to Figure 16 is provided. However, the memory system 2000 can be replaced with the memory system 1000 described with reference to Figure 15 . In an embodiment, the computing system 3000 can be configured to include both the memory systems 1000 and 2000 described with reference to Figure 15 and Figure 16 .

[0161] The disclosed embodiments are merely specific examples that describe the technical contents of the present disclosure and facilitate the understanding of the present invention, and the present invention is not limited by any such embodiments or is not limited to any such embodiments. It will be apparent to those skilled in the art to which the present disclosure pertains that various modifications can be made based on the technical spirit of the present disclosure. The present invention encompasses all such modifications falling within the scope of the claims.

[0162] Cross Reference to Related Applications

[0163] This application claims priority to Korean Patent Application No. 10-2020-0100170, filed on August 10, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a precharge block connected to the plurality of bit lines and including memory cells in an erased state; a selection block that shares the plurality of bit lines with the precharge block and includes memory cells in a programmed state; a peripheral circuit configured to perform an erase operation on the selected block; as well as control logic configured to control the peripheral circuit to turn on a first block selection circuit connected to the precharge block and apply a first voltage to a global line connected to the first block selection circuit when an erase voltage is applied to a source line commonly connected to the precharge block and the selection block, wherein the memory cells of the precharge block are turned on by the first voltage applied from the global line, and the erase voltage applied to the source line is transmitted to the plurality of bit lines through the memory cells of the precharge block, The global lines include global word lines and global selection lines. Wherein, after the ground voltage is initially applied to the global word line, the control logic increases the voltage applied to the global selection line from a first voltage to a second voltage.

2. The semiconductor memory device according to claim 1, wherein When the first block selection circuit is turned on, the control logic controls the peripheral circuit to turn on a second block selection circuit connected to the selection block.

3. The semiconductor memory device according to claim 1, wherein After the erase voltage is transferred to the bit line, the control logic controls the peripheral circuit to turn off the first block selection circuit and apply the ground voltage to the global word line.

4. A semiconductor memory device, comprising: a memory cell array comprising a plurality of memory blocks connected to a plurality of bit lines; a peripheral circuit configured to perform an erase operation on a selected block among the plurality of memory blocks; as well as control logic configured to control the peripheral circuit to, when an erase voltage is applied to a source line connected to the selection block, turn on a first block selection circuit connected to the selection block by applying a first voltage to the first block selection circuit and to apply a second voltage to a global line connected to the first block selection circuit, wherein the memory cells of the selection block are turned on by the second voltage applied from the global line, and the erase voltage applied to the source line is transmitted to the plurality of bit lines through the memory cells of the selection block, Wherein, the global lines include global word lines and global selection lines, After the ground voltage is initially applied to the global word line, the control logic increases the voltage applied to the global selection line from the second voltage to a fourth voltage.

5. The semiconductor memory device according to claim 4, wherein When the first block selection circuit is turned on, the control logic controls the peripheral circuit to turn off a second block selection circuit connected to at least one other block that is not an erase target among the plurality of memory blocks.

6. The semiconductor memory device according to claim 4, wherein After the erase voltage is transferred to the bit line, the control logic controls the peripheral circuit to reduce the voltage applied to the first block selection circuit from the first voltage to a third voltage and apply the ground voltage to the global word line.

7. A method of operating a semiconductor memory device comprising a plurality of memory blocks, the method comprising the steps of: turning on a first block selection circuit connected to a first memory block among the plurality of memory blocks; turning on memory cells included in the first memory block by applying a first voltage to a global line connected to the first block selection circuit; transferring an erase voltage to a bit line connected to the first memory block by starting to apply the erase voltage to a common source line connected to the first memory block; applying a ground voltage to a global word line among the global lines after transmitting the erase voltage to the bit line connected to the first memory block; as well as A voltage of a global selection line among the global lines is increased from the first voltage to a second voltage.

8. The method according to claim 7, in, The first memory block is a precharge block in an erased state, and The method further includes the step of turning off the first block selection circuit after transmitting the erase voltage to a bit line connected to the first memory block.

9. The method according to claim 8, further comprising the steps of: A second block selection circuit connected to a second memory block to be erased among the plurality of memory blocks is turned on.

10. The method according to claim 7, in, The first memory block is a selected block to be erased, and The method further includes reducing a voltage applied to the first block selection circuit from the first voltage to a third voltage after transmitting the erase voltage to a bit line connected to the first memory block.

11. The method according to claim 10, wherein: The first voltage is greater than a maximum threshold voltage among threshold voltages of memory cells in the selection block.

12. A semiconductor memory device, comprising: a target block and an erased block, the target block and the erased block respectively including a first cell string and a second cell string commonly coupled to a source line and a bit line; a first circuit and a second circuit configured to couple the target block and the erased block to a global line, respectively, when turned on; as well as A control circuit configured to perform an erase operation on the target block by: During a set time period, the second circuit is turned on by a second voltage and a third voltage is provided to the global line to turn on the second cell string, while the first circuit is turned on by a first voltage lower than the second voltage, and providing an erase voltage to the source line to precharge the bit line through the turned-on second cell string, Wherein, the global lines include global word lines and global selection lines, After the ground voltage starts to be applied to the global word line, the control circuit increases the voltage applied to the global selection line from the third voltage to a fourth voltage.

13. A semiconductor memory device, comprising: a target block including cell strings coupled to a source line and a bit line; a selection circuit configured to couple the target block to a global line when turned on; as well as A control circuit configured to perform an erase operation on the target block by: During a set time period, a first voltage is applied to turn on the selection circuit, and a second voltage is applied to the global line to turn on the cell string, the second voltage being lower than the first voltage. applying an erase voltage to the source line to precharge the bit line through the turned-on cell string, After the set time period, applying a third voltage lower than the first voltage to turn on the selection circuit, After the set time period, applying a ground voltage to a global word line among the global lines, and After the set time period, the voltage of the global selection line among the global lines is increased from the second voltage to a fourth voltage.

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