Memory data correction using multiple error control operations

Abstract

This application relates to memory data correction using multiple error control operations. A single command can be received to correct errors detected in data stored by a memory array. A first error control operation and a second error control operation can be implemented based on the single command. The first error control operation can be performed on the data stored by the memory array by reading the data using one or more different reference voltages. It can be determined that the error still exists in the data after performing the first error control operation. The second error control operation can then be performed on the data stored by the memory array. The second error control operation can use one or more voltage distributions associated with memory cells of the memory array.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 996,305, filed August 18, 2020, by He et al., entitled “Memory Data Correction Using Multiple Error Control Operations,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to memory data correction using multiple error control operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller is configured such that the device: receives a single command to correct an error detected in data stored by the memory array; performs a first error control operation on the data stored by the memory array based on receiving the single command; determines, after performing the first error control operation, that the error is still in the data; and performs a second error control operation on the data stored by the memory array, different from the first error control operation, based on receiving the single command and determining that the error is still in the data. The first error control operation may use one or more different reference voltages stored by the memory array to read the data. The second error control operation may use one or more voltage distributions associated with memory cells storing information in the memory array.

[0007] A method is described. The method may be performed by a memory system. The method may include: receiving a single command to correct an error detected in data stored by a memory device; performing a first error control operation on the data stored by the memory device based on receiving the single command; determining, after performing the first error control operation, that the error still exists in the data; and performing a second error control operation on the data stored by the memory device, different from the first error control operation, based on receiving the single command and determining that the error still exists in the data. The first error control operation may use one or more different reference voltages stored by the memory device to read the data. The second error control operation may use one or more voltage distributions associated with memory cells of stored information in the memory device.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a single command to correct an error detected in data stored in a memory device; perform a first error control operation on the data stored in the memory device based on receiving the single command; determine, after performing the first error control operation, that the error still exists in the data; and perform a second error control operation on the data stored in the memory device, different from the first error control operation, based on receiving the single command and determining that the error still exists in the data. The first error control operation may use one or more different reference voltages stored in the memory device to read the data. The second error control operation may use one or more voltage distributions associated with memory cells of stored information in the memory device. Attached Figure Description

[0009] Figure 1This document describes an example of a system that supports memory data correction using multiple error control operations, based on examples disclosed herein.

[0010] Figure 2 This document illustrates an example of a voltage distribution graph that supports techniques for data programming, as shown in the examples disclosed herein.

[0011] Figure 3 This document describes an example of a flowchart illustrating a memory data correction process that supports multiple error control operations, based on examples disclosed herein.

[0012] Figure 4 A block diagram illustrating a memory device that supports memory data correction using multiple error control operations, based on examples disclosed herein.

[0013] Figure 5 and 6 The flowchart illustrates a method for memory data correction using multiple error control operations, based on examples disclosed herein. Detailed Implementation

[0014] Some memory systems have two or more different error control commands that can be issued by the host system. To use different error control commands, the host system can track various parameters and then determine which error control command to issue. However, handling two or more different error handlers can complicate the performance of the host system.

[0015] The system, apparatus, and technology are described in response to a single error control command issued by the host system, which initiates a program that may include two or more error control procedures. Upon receiving the single error control command, the memory system may initiate one or more first error control procedures. If the error persists, the memory system may initiate one or more second error control procedures based on a single command (e.g., if a second error control command is not received or is not required to be received).

[0016] Initially in reference Figure 1 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 2 and 3 The features of this disclosure are described in the context of the voltage distribution graphs and flowcharts. These and other features of this disclosure are illustrated in references to [reference needed]. Figures 4 to 6 The device diagrams and flowcharts described in connection with memory data correction using multiple error control operations are further illustrated and described with reference to the device diagrams and flowcharts.

[0017] Figure 1An example of a system 100 that supports memory data correction using multiple error control operations, as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0019] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0020] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110 (e.g., to write data to and read data from the memory system 110). Although Figure 1 The diagram shows a memory system 110, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR), Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR). In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Although in Figure 1 The example shows a memory device 130 and a memory device 140, but it should be understood that the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may lack either memory device 130 or memory device 140.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with memory device 130 or memory device 140 to perform operations generally referred to as access operations at memory device 130 or memory device 140, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130 or memory device 140. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 or memory devices 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 or memory device 140 into corresponding signals for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for the operation of the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to memory device 130 or memory device 140, data may be stored in local memory 120 and may be available within local memory 120 for subsequent retrieval or manipulation (updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130 or memory device 140).

[0027] Although Figure 1 The example of memory system 110 has been described as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or may perform the functions attributed herein to memory system controller 115, which may be located within memory device 130 or memory device 140, respectively. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or local controller 145, or any combination thereof.

[0028] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may (e.g., by host system 105) support random access operations with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0030] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, which can perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a memory array and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] System 100 may include any number of non-transitory computer-readable media that support memory data correction using multiple error control operations. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, memory device 130, or memory device 140. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, memory device 130 (e.g., by local controller 135), or memory device 140 (e.g., by local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform one or more associated functions as described herein.

[0037] Figure 2This document illustrates an example of a voltage distribution curve 200 supporting memory data correction using multiple error control operations, based on examples disclosed herein. Voltage distribution curve 200 illustrates a voltage distribution 205-a that can be associated with a signal output from a memory cell storing a logic value '1' and a voltage distribution 205-b that can be associated with a signal output from a memory cell storing a logic value '0'. The voltage distribution of the memory cell may include voltage distribution 205-a corresponding to logic value '1' and bounded by data thresholds v1 and v2, and voltage distribution 205-b corresponding to logic value '0' and bounded by data thresholds v3 and v4. A valley 215 may occur between voltage distributions 205-a and 205-b. Voltage distribution curve 200 also illustrates a reference voltage 210 within the valley 215. In some cases, the memory system may perform one or more read operations on a set of memory cells, each using a different reference voltage 210. Voltage distribution curve 200 illustrates the distribution of an SLC memory device. The principles described in this article can be applied to memory devices that operate using MLC, TLC, QLC or other types of memory.

[0038] During a read operation, the memory array can output a set of signals based on the logic values ​​stored in the set of accessed memory cells. For example, if the logic value '1' is stored in a memory cell, then the memory cell can output a voltage between data thresholds v1 and v2. Similarly, if the memory cell has stored the logic value '0', then the memory cell can output a voltage between data thresholds v3 and v4.

[0039] To determine the logic value stored in a memory cell, the sense amplifier receives a signal (i.e., a voltage level) from the memory cell and compares the signal with a reference voltage 210. If the signal value is less than the reference voltage, the sense amplifier determines that the memory cell represents the logic value '1'. Similarly, if the signal value is greater than the reference voltage, the sense amplifier determines that the signal represents the logic value '0'. The sense amplifier outputs a codeword containing a set of bits associated with one of the memory cells in the set of accessed memory cells.

[0040] In the example of voltage distribution curve 200, if a memory cell storing logic value '1' outputs a signal with a voltage less than reference voltage 210 (e.g., within voltage distribution 205-a) and a read operation is performed using reference voltage 210, then the sense amplifier can output a bit with logic value '1'. Conversely, if a memory cell storing logic value '0' outputs a signal with a voltage greater than reference voltage 210 (e.g., within voltage distribution 205-b) and a read operation is performed using reference voltage 210, then the sense amplifier can output a bit with logic value '0'.

[0041] In other instances, the logic value can be inverted, such that if the signal value is less than the reference voltage 210, the sense amplifier can be changed to determine the logic value '0', and if the signal value is greater than the reference voltage 210, the logic value '1' can be determined.

[0042] Sometimes, one or more of the voltage distributions in a memory cell may change, for example, due to age, voltage spikes, etc. Any one or two of the voltage distributions may be expanded, shifted, etc. Because the signal value of the memory cell can be compared with a reference voltage (e.g., a static reference signal), the data represented by the memory cell may be unaffected by the changes, as long as the voltage distributions corresponding to logic values ​​'0' and '1' remain on opposite sides of the reference voltage. For example, voltage distributions 205-a or 205-b, or both, may be shifted and / or expanded relative to the voltage without causing data problems as long as both remain on opposite sides of the reference voltage 210.

[0043] However, if any portion of any voltage distribution crosses the reference voltage so that it lies on the same side of the reference voltage line as another voltage distribution, a data error can occur. For example, if voltage distribution 205-b shifts and extends into voltage distribution 205-b' (shown as a dashed line and bounded by data thresholds v5 and v6), then if a memory cell has a stored logic value '0', the memory cell can output a voltage between v5 and v6. Therefore, a portion 220 of voltage distribution 205-b' between v5 and the reference voltage 210 becomes positioned on the same side of the reference voltage 210 as voltage distribution 205-a. Therefore, if a memory cell storing logic '0' outputs a signal within portion 220 of voltage distribution 205-b', the sensing amplifier may incorrectly determine that the memory cell represents a logic value '1' because the signal value is less than the reference voltage 210.

[0044] To correct data errors, the memory system can shift the reference voltage. For example, reference voltage 210 can be shifted within valley 215' to reference voltage 210', such that portion 220 of voltage distribution 205-b' is no longer on the same side of the reference voltage as voltage distribution 205-a. If reference voltage 210' is then used during a read operation, the sense amplifier can determine that any signal value within voltage distribution 205-b' (including portion 220) represents the logic value '0'.

[0045] A new value for the reference voltage can be determined in different ways. In one example, the reference voltage can be gradually increased or decreased from an initial reference voltage or another voltage until a value is reached that does not produce errors when reading memory cells. In another example, the voltage distribution of the memory cells can be analyzed to determine the valleys between the voltage distribution levels, and then the reference voltage can be set within these valleys. In some cases, if errors persist, and if the reference voltage is within a valley, then the reference voltage can then be gradually increased or decreased. Other types of error control may also be possible.

[0046] Figure 3 This document describes an example flowchart of a method 300 for memory data correction using multiple error control operations, based on examples disclosed herein. The operation of method 300 can be implemented by a memory device or its components as described herein. For example, the operation of method 300 can be implemented by... (See reference...) Figure 4 The described memory system performs the functions described. In some instances, the memory system can execute a set of instructions to control the functional elements of the memory system to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0047] Using method 300, a host system can issue a single error control command to initiate a program that may contain two or more error control procedures. Upon receiving the single error control command, the memory system can initiate a first error control procedure. If the error persists, the memory system can initiate a second error control procedure based on a single command (e.g., if a second error control command is not received or is not required to be received).

[0048] Method 300 may include a first error control operation 305 and a second error control operation 310. In some cases, the first error control operation 305 may include a read retry operation. The read retry operation may use different read options that can be internally stored within the memory system for page reads. For each retry, the reference voltage used to read the memory location may be increased or decreased by a set value. In some cases, the second error control operation 310 may be an example of a recovery operation (e.g., an automatic read calibration operation) that calibrates a reference voltage based on the voltage distribution of the memory cell. The second error control operation 310 may find a valley between voltage distribution levels by analyzing the data threshold distribution of the page. The optimal read level may occur at the valley. (Refer to the above) Figure 2More information regarding the data threshold distribution is provided. The second error control operation 310 can be performed "in the case of persistence" or "in the case of non-persistence." When performed "in the case of non-persistence," the second error control operation 310 can be a single operation, allowing only one shift of the reference voltage used to read the memory location. When performed "in the case of persistence," the second error control operation 310 can be a repetitive operation, allowing the shift of the reference voltage to continue until the error disappears. Both types of the second error control operation 310 can be used in method 300.

[0049] In method 300, the first error control operation 305 may include one or more of steps 320 to 340, and the second error control operation 310 may include one or more of steps 345 to 365. Figure 3 As shown, method 300 can flow from the first error control operation 305 to the second error control operation 310.

[0050] At 315, a command to correct data errors can be received. In some cases, the command may be a single command to correct errors detected in data stored in the memory array. A single command may contain a single opcode configured to optionally perform two or more error control operations. The command may contain a memory address value indicating the location within the memory array where a data error has occurred and / or the data value written to that location in the memory array. In some cases, the command may be a read recovery command, such as an address loop read retry operation. In some cases, the memory system may receive the command from a source external to the memory system, such as a host device or memory controller.

[0051] In some cases, a command may be an instance of a read command containing one or more indices indicating what various error control operations can be performed to retrieve correct data. In such instances, a single index may initiate one or more error recovery operations. Some indices may be configured to initiate a first error control operation 305, multiple examples of the first error control operation 305, a second error control operation 310, multiple examples of the second error control operation 310, both the first error control operation 305 and the second error control operation 310, any number of examples of the first error control operation 305 or the second error control operation 310, or any combination thereof. Thus, a command may cause the first error control operation 305 to be performed, the second error control operation 310 to be performed, or a combination thereof. Table 1 shows the various indices associated with the various error control operations. Indices RR0 to RR8 may refer to error control operations as examples of the first error control operation 305, which may be examples of a read retry operation, and indices RR10 to RR11 may refer to error control operations as examples of the second error control operation 310, which may be examples of a recovery operation based on a distributed calibration reference voltage of a memory cell. Having a single index (e.g., RR11) associated with three different error control operations (although similar in type) can be an example of how a single index can indicate multiple error control operations and thus simplify the interface with the host system.

[0052] Error control operation index First error control operation 0 RR0 First error control operation 1 RR1 First error control operation 2 RR2 First error control operation 3 RR3 First error control operation 4 RR4 First error control operation 5 RR5 First error control operation 6 RR6 First error control operation 7 RR7 First error control operation 8 RR8 Second error control operation in non-continuous situations RR10 Second error control operation 0 in the case of continuous error RR11 Second error control operation 1 in continuous situations RR11 Second error control operation 2 in continuous situations RR11

[0053] Table 1

[0054] Upon receiving a command, a first error control operation 305 may be initiated. The first error control operation may include a first loop, which includes one or more of steps 320 to 340. Each pass through the first loop may include reading data and comparing it with data written using a specific reference voltage. Step 320 may be the entry point for the first loop. The first error control operation 305 may be an example of a read retry operation, which uses one or more predetermined reference voltages to adjust the read operation to correct one or more errors in the codeword.

[0055] At 320, the reference voltage can be selected by the memory system. An initial value can be selected for the reference voltage upon first passage through the first loop (e.g., when entering 320 from 315). In some cases, the initial value can be selected as the reference voltage currently being used for the memory cell. In some cases, the initial value can be close to Vcc or Vss. Other initial values ​​can also be used.

[0056] After the first control operation (e.g., when moving from 340 to 320), a new value for the reference voltage can be selected, different from the reference voltage value selected during previous loop passes. In some cases, the new reference voltage can be selected based on a previous reference voltage. For example, as described herein, the new reference voltage can be incrementally increased or decreased each time the loop is passed. In some cases, the selectable reference voltage value can be stored in a memory array.

[0057] At 325, the memory system can use the reference voltage selected at 320 to read the memory cell corresponding to the data error. For example, such as the reference... Figure 2 As described, a signal corresponding to a memory address stored in a memory cell can be received by a sensing amplifier, which can compare the signal with a recently selected reference voltage at 320. For each memory cell, if the signal value is less than the selected reference voltage, the sensing amplifier can determine that the memory cell represents the logic value '1'. Similarly, if the signal value is greater than the selected reference voltage, the sensing amplifier can determine that the signal represents the logic value '0'. The memory cell to be read can be determined by information received in a command (e.g., a memory address value).

[0058] At position 330, an ECC decoder check can be performed. For example, data read by the memory system at position 325 may contain the applied ECC program. In some instances, to determine whether an error still exists in the data, the data read by the memory system at position 325 can be compared with data previously written to the memory cell. The previously written data used for comparison can be reflected in the information received in the command.

[0059] At 335, if, as determined at 330, the error is no longer in the data, then the error has been corrected and the method can be completed. In some cases, the error control operation associated with receiving the command can be stopped. For example, if the error is corrected using the first error control operation, then the second error control operation (or other subsequent control operation) may not be initiated. The latest reference voltage used to read the memory cell at 325 can be used backwards. The reference voltage can be stored in memory or otherwise remembered for continued use when reading the memory cell. If, as determined at 330, the error is still in the data, then the error has not been corrected and the method can continue to 340.

[0060] At 340, the number of times the method has looped through the first loop is determined. As mentioned above, the first loop may include steps 320 to 340, and may include reading data each time and comparing it with data written using different reference voltages. If the number of loop cycles is equal to or less than a threshold number n, then the method may return to 320 to repeat the first loop. If the number of cycles is greater than n, then the method may continue to 345 to begin the second error control operation 310.

[0061] The second error control operation 310 may be an example of an automatic read calibration operation that identifies possible voltage distributions associated with different logic states stored in memory cells. Once a possible voltage distribution is identified, the second error control operation 310 may include selecting one or more reference voltages for the read operation based on the identified voltage distribution. In some instances, the memory system may test multiple memory cells with multiple reference voltages. Using information from multiple readings at multiple reference voltages, possible voltage distributions of other relevant memory cells in the memory system can be extrapolated.

[0062] At position 345, the voltage distribution associated with the memory cell where a data error has occurred can be determined. For example, relative to... Figure 2 As described, the voltage distribution of memory cells can be analyzed to determine the valleys between voltage distribution levels. In one case, reference... Figure 2 It can determine the voltage distribution 205 corresponding to logic value '1' and logic value '0', and identify the valley value between the two voltage distributions 205.

[0063] The second error control operation 310 may include a second loop, which includes one or more of steps 350 to 365. Each pass through the second loop may include reading data and comparing it with data written using a specific reference voltage based on the voltage distribution. Step 350 may be the entry point for the second loop.

[0064] At 350, the reference voltage can be selected by the memory system based on the voltage distribution determined at 345. Upon first traversal of the second loop (e.g., when entering 350 from 345), an initial value can be selected for the reference voltage based on the voltage distribution. In some cases, the initial value can be selected as a reference voltage value within the valley between the voltage distributions of logic '1' and logic '0'. Other initial values ​​may also be used.

[0065] After the first pass (e.g., when moving from 365 to 350), a new reference voltage value can be selected, different from the reference voltage value selected when passing through the second loop at a previous time. In some cases, the new reference voltage can be selected based on a previous reference voltage. For example, as described herein, the new reference voltage can be gradually increased or decreased each time the loop is passed. In some cases, the new reference voltage can be within a valley determined at 345.

[0066] At 355, the memory system can use a reference voltage selected at 350 to read the memory cell corresponding to the data error. For example, such as the reference... Figure 2 As described, signals stored in memory cells can be received by a sensing amplifier, which compares the signals with a recently selected reference voltage at 320. For each memory cell, if the signal value is less than the selected reference voltage, the sensing amplifier determines that the memory cell represents a logic value '1'. Similarly, if the signal value is greater than the selected reference voltage, the sensing amplifier determines that the signal represents a logic value '0'. The memory cell to be read can be determined by information received in a command (e.g., a memory address value).

[0067] At position 360, to determine whether the error is still present in the data, the data read by the memory system at position 355 can be compared with the data previously written to the memory cell. The previously written data used for comparison can be reflected in the information received in the command.

[0068] At 365, if, as determined at 360, the error is still in the data, then the error has not been corrected and the method can return to 350 to repeat the second loop. If, as determined at 360, the error is no longer in the data, then the error has been corrected and the method can complete. The latest reference voltage used to read the memory cell at 355 can be used backwards. The reference voltage can be stored in memory or otherwise remembered for continued use when reading the memory cell. In some cases, different examples of starting the second error control operation 310 can be based on this determination. For example, different techniques can be used to determine the voltage distribution or different starting reference voltages using information from previous iterations of the second error control operation 310 (or the first error control operation 305) when selecting the reference voltage, thereby activating or deactivating the persistence, or any combination thereof.

[0069] In some cases, method 300 may include additional steps. For example, method 300 may include additional steps in which the number of times the method has traversed the second loop is determined before returning to 350. If the number is equal to or less than a predetermined number m, then the method may return to 350 to repeat the second loop. If the number is greater than m, then the error has not been corrected and the memory cell may be disabled.

[0070] In some cases, a message may be sent to, for example, the host system upon completion of method 300. The message may contain information about data error correction, such as corrected data, whether the error has been corrected, whether the error persists in the data, an indication of data corruption, or other types of messages. In some cases, a message may be sent only if the error persists after method 300 has completed.

[0071] Method 300 offers several advantages when performing memory data correction. For example, memory data correction can be performed using a single error control command. This is beneficial for the host system because multiple commands may not be necessary. As another example, memory data correction can be requested without specifying which type of error control operation to use. This is beneficial for the memory system because it allows the memory system to determine itself which type of error control operation to use, and it allows the memory system to continue using different types until the error is corrected. It is also beneficial for the host system because it allows the host system to request memory data correction from the memory system without the host system needing to instruct the memory system to use or track a specific type of error control. Other benefits can also be provided by using method 300.

[0072] Figure 4 A block diagram 400 illustrates a memory system 405 that supports memory data correction using multiple error control operations, based on examples disclosed herein. The memory system 405 may be as described in the references... Figures 1 to 3 Examples of aspects of the described memory system or memory device. Memory system 405 may include a receiving component 410, a determining component 415, a first error control component 420, and a second error control component 425. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0073] The receiving component 410 may receive a command (e.g., a single command) to correct errors detected in data stored in the memory device. In some cases, the single command may contain a single opcode associated with both performing a first error control operation and a second error control operation.

[0074] The determination component 415 can determine that an error still exists in the data after the first error control operation has been performed. In some instances, the determination component 415 can determine that an error still exists in the data after a reference voltage has been selected to read the data.

[0075] The first error control component 420 can perform a first error control operation on data stored in the memory device based on a received single command. The first error control operation can read the data using one or more different reference voltages stored in the memory array. The one or more different reference voltages may include a first reference voltage and a previous reference voltage. In some instances, the first error control component 420 can compare a first reference voltage, different from a previous reference voltage, with a signal output from a memory cell associated with data in the memory device. In some instances, the first error control component 420 can compare a set of reference voltages with signals output from memory cells in the memory device. In some instances, the first error control component 420 can identify data stored in the memory cell each time a different reference voltage is compared with a signal.

[0076] The second error control component 425 may perform a second error control operation on the data stored by the memory device based on receiving a single command and determining that an error still exists in the data. The second error control operation may differ from the first error control operation. The second error control operation may use one or more voltage distributions associated with memory cells storing information in the memory array. In some instances, the second error control component 425 may identify one or more voltage distributions associated with memory cells storing information in the memory device. In some instances, the second error control component 425 may select a reference voltage based on one or more voltage distributions to read the data stored by the memory device. In some instances, the second error control component 425 may select a second reference voltage different from the reference voltage based on one or more voltage distributions to read the data stored by the memory device. In some instances, the second error control component 425 may analyze the data threshold distribution of memory cells associated with data in the memory device. In some instances, the second error control component 425 may select different reference voltages based on one or more voltage distributions to compare with the data stored by the memory device until an error is corrected in the data.

[0077] Figure 5 The flowchart illustrates a method 500 for memory data correction using multiple error control operations, based on examples disclosed herein. The operation of method 500 can be implemented by a memory system or memory device or its components as described herein. For example, the operation of method 500 can be implemented by, as referenced... Figure 4 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described. Alternatively, the memory device may use dedicated hardware to perform aspects of the functions described.

[0078] At point 505, a single command can be received to correct errors detected in data stored in the memory device. In some cases, the single command can be received by the memory device itself. Operation of point 505 can be performed according to the methods described herein. In some instances, it can be performed by, as referenced... Figure 4 The described aspect of the receiving component performing 505 operations.

[0079] At 510, a first error control operation can be performed on data stored in the memory device based on a received single command. The first error control operation can read data using one or more different reference voltages stored in the memory array. The operation of 510 can be performed according to the method described herein. In some instances, it can be performed using, for example, a reference voltage... Figure 4 The first error control component described performs the operation of 510.

[0080] At point 515, it can be determined that an error still exists in the data after the first error control operation. The operation at point 515 can be performed according to the methods described in this document. In some instances, it can be done as per the reference... Figure 4 The described aspect of determining the operation of the component is 515.

[0081] At point 520, a second error control operation can be performed on the data stored by the memory device based on receiving a single command and determining that the error is still present in the data. The second error control operation may differ from the first error control operation and may use one or more voltage distributions associated with memory cells storing information in the memory array. The operation at point 520 can be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 4 The second error control component described performs the 520 operation.

[0082] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a single command to correct an error detected in data stored by a memory device; performing a first error control operation on the data stored by the memory device based on receiving the single command, the first error control operation reading the data using one or more different reference voltages stored by the memory array; determining, after performing the first error control operation, that the error is still in the data; and performing a second error control operation on the data stored by the memory device, different from the first error control operation, based on receiving the single command and determining that the error is still in the data, the second error control operation using one or more voltage distributions associated with memory cells storing information in the memory array.

[0083] In some instances of the method 500 and apparatus described herein, performing the first error control operation may include operations, features, components, or instructions for comparing a first reference voltage, which is different from a previous reference voltage, with a signal output from a memory cell associated with the data in the memory device, wherein the one or more different reference voltages include the first reference voltage and the previous reference voltage.

[0084] In some instances of the method 500 and apparatus described herein, performing the first error control operation may include operations, features, components, or instructions for: comparing a set of reference voltages with a signal output from a memory cell of the memory device; and identifying data stored in the memory cell whenever a different reference voltage can be compared with the signal.

[0085] In some instances of the method 500 and apparatus described herein, performing the second error control operation may further include operations, features, components, or instructions for: identifying one or more voltage distributions associated with the memory cells storing information in the memory device; and selecting a reference voltage based on the one or more voltage distributions to read the data stored by the memory device.

[0086] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: determining that the error is still in the data after selecting the reference voltage to read the data; and selecting a second reference voltage different from the reference voltage based on the one or more voltage distributions to read the data stored by the memory device.

[0087] In some instances of the method 500 and apparatus described herein, performing the second error control operation may include operations, features, components, or instructions for: analyzing the data threshold distribution of memory cells of the memory device that can be associated with the data; and selecting different reference voltages based on the one or more voltage distributions to compare with the data stored by the memory device until the error can be corrected in the data.

[0088] In some instances of the method 500 and device described herein, the single command may contain a single opcode associated with both the first error control operation and the second error control operation.

[0089] Figure 6The flowchart illustrates a method 600 for memory data correction using multiple error control operations, based on examples disclosed herein. Operation of method 600 can be implemented by a memory device or its components as described herein. For example, operation of method 600 can be performed as described in the reference... Figure 4 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described. Alternatively, the memory device may use dedicated hardware to perform aspects of the functions described.

[0090] At 605, a single command can be received to correct errors detected in data stored by the memory device. In some cases, the single command can be received by the memory device itself. Operation of 605 can be performed according to the methods described herein. In some instances, it can be performed by, as referenced... Figure 4 The described aspect of the receiving component performing operation 605.

[0091] At 610, a set of reference voltages stored in the memory array can be compared with a signal output from a memory cell of the memory device based on a received single command. In some cases, this comparison can be performed by the memory device itself. Operation of 610 can be performed according to the methods described herein. In some instances, it can be performed by, for example, a reference... Figure 4 The first error control component described performs the operation of 610.

[0092] At 615, data stored by the memory cell can be identified whenever a different reference voltage is compared with the signal. In some cases, this identification can be performed by a memory device. 615 can be operated according to the methods described herein. In some instances, it can be performed by a reference... Figure 4 The first error control component described performs the operation of 615.

[0093] At 620, it can be determined that an error still exists in the data after the reference voltage has been compared with the signal. In some cases, this determination can be made by a memory device. 620 can be operated according to the method described herein. In some instances, it can be determined by a reference... Figure 4 The described aspect of determining the component's operation of 620.

[0094] At 625, the data threshold distribution of memory cells associated with data in the memory device can be analyzed based on the receipt of a single command and the determination that an error still exists in the data. In some cases, this analysis can be performed by the memory device itself. Operation of 625 can be performed according to the methods described herein. In some instances, it can be performed by, as referenced... Figure 4 The second error control component described performs the operation of 625.

[0095] At 630, different reference voltages can be selected based on one or more voltage distributions to compare with data stored by a memory device until errors are corrected in the data. Operation of 630 can be performed according to the method described herein. In some instances, a reference voltage can be used as... Figure 4 The second error control component described performs the operation of 630.

[0096] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0097] Describe a device. The device may include: a memory array; a controller coupled to the memory array and configured such that the device: performs a first error control operation on data stored in the memory array based on receiving a single command, the first error control operation reading the data using one or more different reference voltages stored in the memory array; determines, after performing the first error control operation, that the error is still present in the data; and performs a second error control operation on the data stored in the memory array, different from the first error control operation, based on receiving the single command and determining that the error is still present in the data, the second error control operation using one or more voltage distributions associated with memory cells storing information in the memory array.

[0098] In some instances, performing the first error control operation may include operations, features, components, or instructions for comparing a first reference voltage, which is different from a previous reference voltage, with a signal output from a memory cell of the memory array associated with the data, wherein the one or more different reference voltages may include the first reference voltage and the previous reference voltage.

[0099] In some instances, performing the first error control operation may include operations, features, components, or instructions for: comparing a set of reference voltages with signals output from memory cells of the memory array; and identifying data stored in the memory cells whenever a different reference voltage can be compared with the signals.

[0100] In some instances, performing the second error control operation may further include operations, features, components, or instructions for: identifying one or more voltage distributions associated with the memory cells storing information in the memory array; and selecting a reference voltage based on the one or more voltage distributions to read the data stored by the memory array.

[0101] Some examples may further include determining that the error is still in the data after selecting the reference voltage to read the data; and selecting a second reference voltage different from the reference voltage based on the one or more voltage distributions to read the data stored by the memory array.

[0102] In some instances, performing the second error control operation may include operations, features, components, or instructions for: analyzing the data threshold distribution of memory cells in the memory array that can be associated with the data; and selecting different reference voltages based on the one or more voltage distributions to compare with the data stored by the memory array until the error can be corrected in the data.

[0103] In some instances, the single command may contain a single opcode associated with both the first error control operation and the second error control operation. In some instances, the first error control operation may include a read retry operation, and the second error control operation may include an automatic read calibration operation. In some instances, the single command may be a read recovery command.

[0104] The information and signals described herein can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0105] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of a signal between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of a signal at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the flow of a signal between connected components for a period of time.

[0106] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0107] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0108] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0109] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0110] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0111] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0112] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0113] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0114] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributions such that portions of the functions are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0115] Computer-readable media encompasses both non-transitory computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0116] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is intended to be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory array; and a controller coupled with the memory array and configured to cause the memory device to: receive a single command to correct an error detected in data stored by a plurality of single-level cell (SLC) memory cells of the memory array, wherein the single command comprises a single opcode associated with performing both a first error control operation and a second error control operation, the second error control operation being different than the first error control operation; perform the first error control operation on the data stored by the plurality of SLC memory cells based at least in part on receiving the single command, the first error control operation reading the data from the plurality of SLC memory cells using one or more different reference voltages stored by the memory array; determine that the error is still in the data after performing the first error control operation; and perform the second error control operation on the data stored by the plurality of SLC memory cells based at least in part on receiving the single command and determining that the error is still in the data stored by the plurality of SLC memory cells, the second error control operation comprising: identifying one or more voltage distributions associated with the plurality of SLC memory cells; and selecting a second reference voltage to read the data stored by the plurality of SLC memory cells based at least in part on the one or more voltage distributions.

2. The memory device of claim 1, wherein performing the first error control operation comprises the controller configured to cause the memory device to: compare a first reference voltage different than a previous reference voltage to signals output from the plurality of SLC memory cells associated with the data, wherein the one or more different reference voltages comprise the first reference voltage and the previous reference voltage.

3. The memory device of claim 1, wherein performing the first error control operation comprises the controller configured to cause the memory device to: compare a plurality of reference voltages to signals output from the plurality of SLC memory cells associated with the data; and identify data stored by the plurality of SLC memory cells each time a different reference voltage is compared to the signals output from the plurality of SLC memory cells.

4. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: determine that the error is still in the data after selecting the second reference voltage to read the data; and select a third reference voltage different than the second reference voltage to read the data stored by the plurality of SLC memory cells based at least in part on the one or more voltage distributions.

5. The memory device of claim 1, wherein performing the second error control operation comprises the controller configured to cause the memory device to: analyze data threshold distributions of the plurality of SLC memory cells associated with the data; and perform the second error control operation on the data stored by the plurality of SLC memory cells based at least in part on the one or more voltage distributions. selecting a different reference voltage to compare to the data stored in the plurality of SLC memory cells based at least in part on the one or more voltage profiles until the error in the data is corrected.

6. The memory device of claim 1, wherein: the first error control operation comprises a read retry operation; and the second error control operation comprises an automatic read calibration operation.

7. The memory device of claim 1, wherein the single command is a read resume command.

8. The memory device of claim 1, wherein the single command includes an indication of a data value to write to the plurality of SLC memory cells.

9. The memory device of claim 8, wherein determining that the error is still in the data stored in the plurality of SLC memory cells after performing the first error control operation comprises the controller configured to cause the memory device to: compare the data value to write to the plurality of SLC memory cells to the data read from the plurality of SLC memory cells.

10. A method by a memory system, the method comprising: receiving a single command to correct an error detected in data stored by a plurality of single level cell (SLC) memory cells of a memory device, wherein the single command includes a single opcode associated with performing both a first error control operation and a second error control operation, the second error control operation being different than the first error control operation; performing the first error control operation on the data stored in the plurality of SLC memory cells based at least in part on receiving the single command, the first error control operation reading the data from the plurality of SLC memory cells using one or more different reference voltages stored by the memory device; determining that the error is still in the data after performing the first error control operation; and performing the second error control operation on the data stored in the plurality of SLC memory cells based at least in part on receiving the single command and determining that the error is still in the data stored in the plurality of SLC memory cells, the second error control operation comprising: identifying one or more voltage profiles associated with the plurality of SLC memory cells; and selecting a second reference voltage to read the data stored in the plurality of SLC memory cells based at least in part on the one or more voltage profiles.

11. The method of claim 10, wherein performing the first error control operation comprises: comparing a first reference voltage different than a previous reference voltage to a signal output from the plurality of SLC memory cells associated with the data, wherein the one or more different reference voltages include the first reference voltage and the previous reference voltage.

12. The method of claim 10, wherein performing the first error control operation comprises: comparing a plurality of reference voltages to a signal output from the plurality of SLC memory cells; and ​ identifying data stored at the plurality of SLC memory cells each time a different reference voltage is compared to the signals output from the plurality of SLC memory cells.

13. The method of claim 10, further comprising: determining that the error is still in the data after selecting the second reference voltage to read the data; and selecting, based at least in part on the one or more voltage distributions, a third reference voltage different from the second reference voltage to read the data stored by the memory device.

14. The method of claim 10, wherein performing the second error control operation comprises: analyzing data threshold distributions of the plurality of SLC memory cells associated with the data; and selecting, based at least in part on the one or more voltage distributions, different reference voltages to compare to the data stored at the plurality of SLC memory cells until the error in the data is corrected.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a single command to correct an error detected in data stored by a plurality of single-level cell (SLC) memory cells of a memory device, wherein the single command comprises a single opcode associated with performing both a first error control operation and a second error control operation, the second error control operation being different from the first error control operation; perform, based at least in part on receiving the single command, the first error control operation on the data stored at the plurality of SLC memory cells, the first error control operation reading the data from the plurality of SLC memory cells using one or more different reference voltages stored by the memory device; determine, after performing the first error control operation, that the error is still in the data stored at the plurality of SLC memory cells; and perform, based at least in part on receiving the single command and determining that the error is still in the data stored at the plurality of SLC memory cells, the second error control operation on the data stored at the plurality of SLC memory cells, the second error control operation comprising: identifying one or more voltage distributions associated with the plurality of SLC memory cells; and selecting, based at least in part on the one or more voltage distributions, a second reference voltage to read the data stored at the plurality of SLC memory cells.

16. The non-transitory computer-readable medium of claim 15, wherein performing the first error control operation comprises causing the electronic device to: compare a plurality of reference voltages to signals output from the plurality of SLC memory cells; and identify data stored at the plurality of SLC memory cells each time a different reference voltage is compared to the signals output from the plurality of SLC memory cells.

17. The non-transitory computer-readable medium of claim 15, wherein performing the second error control operation comprises causing the electronic device to: analyze a data threshold distribution of the plurality of SLC memory cells associated with the data; and select a different reference voltage to compare to the data stored in the plurality of SLC memory cells based at least in part on one or more voltage distributions associated with the plurality of SLC memory cells until the error in the data is corrected.

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