Storage device and method of operating a storage device

Abstract

A storage device and a method of operating the storage device are provided. The storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and a data signal, and outputs read data based on the data strobe signal and the data signal. The storage controller transmits the data strobe signal and the data signal in parallel to the semiconductor memory device via signal lines. The storage controller includes a first delay circuit that delays the data signal such that some edges of a window of the data signal on the signal lines are desynchronized by different first skew offsets.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0100259, filed on August 11, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to storage, and more specifically, to storage devices and methods of operating storage devices. Background Technology

[0003] A storage device is a means for storing data under the control of a host device (such as a computer, smartphone, and / or tablet). Storage devices include means for storing data on disks (such as hard disk drives (HDDs) and means for storing data on semiconductor memories (such as solid-state drives (SSDs) and memory cards), i.e., non-volatile memories.

[0004] The use of storage devices, including non-volatile memory, has expanded from personal computers to business computers (such as data servers). With the expansion of storage device use, various functions and form factors of storage devices are required in various fields. Storage devices connect to various hosts and transmit high-frequency signals to them, thus the signal characteristics output from the storage device are enhanced. Summary of the Invention

[0005] One aspect is to provide a storage device capable of reducing crosstalk between a storage controller and a memory that exchange data signals in parallel.

[0006] On the other hand, a method for operating a storage device is provided, which can reduce crosstalk occurring between a storage controller and a memory that exchange data signals in parallel.

[0007] According to one aspect of one or more exemplary embodiments, a storage device is provided, the storage device including a storage controller and at least one semiconductor memory device. The at least one semiconductor memory device receives write data based on a data strobe signal and a plurality of data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the plurality of data signals in parallel to the at least one semiconductor memory device via a plurality of signal lines. The storage controller includes a first delay circuit that delays the data signals such that at least some edges of windows of the data signals on the plurality of signal lines are desynchronized by different first skew offsets.

[0008] According to another aspect of one or more example embodiments, a method of operating a storage device is provided, the storage device including a storage controller and at least one semiconductor memory device, the storage controller being configured to control the at least one semiconductor memory device. The method may include: performing training by the storage controller while transmitting a training mode to the at least one semiconductor memory device via signal lines to search for a first skew offset for minimizing crosstalk occurring between signal lines; storing the first skew offset as skew information in a register in the storage controller based on the training result; transmitting the skew information to the at least one semiconductor memory device by the storage controller; delaying a data signal by a first delay circuit of the storage controller such that at least some first edges of the data signal are desynchronized by the first skew offset; transmitting the delayed data signal and a data strobe signal to the at least one semiconductor memory device via signal lines by the storage controller; and providing the original data signal by a second delay circuit of the at least one semiconductor memory device based on the skew information and a second skew offset for eliminating the first skew offset.

[0009] According to another aspect of one or more example embodiments, a storage device is provided, the storage device including a storage controller and at least one non-volatile memory device. The at least one non-volatile memory device is configured to receive write data based on a data strobe signal and a plurality of data signals, and is configured to output read data based on the data strobe signal and the plurality of data signals; a memory controller is configured to transmit the data strobe signal and the plurality of data signals in parallel to the at least one non-volatile memory device via a plurality of signal lines, wherein each of the plurality of data signals has a window defined by a first edge and a second edge; the memory controller includes a first delay circuit configured to delay the plurality of data signals such that at least some edges of the plurality of data signals are desynchronized by a first skew offset that is different from each other; the memory controller is configured to transmit skew information including the first skew offset to the at least one non-volatile memory device; and the at least one non-volatile memory device includes a second delay circuit configured to receive the skew information and configured to delay the plurality of data signals by a second skew offset based on the skew information for eliminating the first skew offset, to provide the original data signal. Attached Figure Description

[0010] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment;

[0012] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the host of the storage system;

[0013] Figure 3 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller for a storage system;

[0014] Figure 4 Showing according to an example embodiment Figure 1 The storage controller, first delay circuit, and non-volatile memory device in the storage device of the storage system;

[0015] Figure 5 This illustrates an example embodiment. Figure 4 A block diagram of an example of the first delay circuit;

[0016] Figure 6 This illustrates an example embodiment. Figure 5 A block diagram of an example of a voltage-controlled delay line (VCDL) for the first delay circuit;

[0017] Figure 7 This illustrates an example embodiment. Figure 6 Circuit diagram of the unit delay unit of VCDL;

[0018] Figure 8 Showing according to an example embodiment Figure 4 The non-volatile memory interface in the memory controller and Figure 4 Non-volatile memory devices;

[0019] Figure 9 Show Figure 8 An example of the first register of a non-volatile memory interface;

[0020] Figure 10 Show Figure 8 An example of the second register of a non-volatile memory device;

[0021] Figure 11 The example embodiment is shown in Figure 4 Data signals and data strobe signals during communication between the memory controller and the non-volatile memory device;

[0022] Figure 12 This illustrates an example embodiment. Figure 1 A block diagram of a non-volatile memory device in a storage system;

[0023] Figure 13 Show Figure 12A block diagram of a memory cell array in a non-volatile memory device;

[0024] Figure 14 Show Figure 13 The circuit diagram of the memory block of the memory cell array;

[0025] Figure 15 and Figure 16 These are a plan view and a cross-sectional view of a printed circuit board (PCB) on which a storage device is mounted, according to an example embodiment;

[0026] Figure 17 and Figure 18 These are a plan view and a cross-sectional view of a storage device according to an example embodiment;

[0027] Figure 19 This illustrates an example embodiment. Figure 1 A block diagram of an example storage device in a storage system;

[0028] Figure 20 An example of the operation of a storage device according to an example embodiment is shown;

[0029] Figure 21 An example of the operation of a storage device according to an example embodiment is shown;

[0030] Figure 22 and Figure 23 This is a diagram used to explain the operation of a storage device according to an example embodiment;

[0031] Figure 24 Showing according to an example embodiment Figure 1 volatile memory devices in storage systems and Figure 3 The volatile memory interface of the memory controller;

[0032] Figure 25 This is a block diagram illustrating a storage device according to an example embodiment;

[0033] Figure 26 This illustrates an example embodiment. Figure 25 A flowchart of the operation of the storage device; and

[0034] Figure 27 This is a block diagram illustrating a storage system according to an example embodiment. Detailed Implementation

[0035] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some exemplary embodiments.

[0036] According to various example embodiments, a memory controller including delay circuitry delays data signals to be transmitted to a semiconductor memory device via signal lines, such that at least some of the first edges of the data signals are desynchronized by a skew offset, and the data signals are transmitted to the semiconductor memory device. The semiconductor memory device receives skew information associated with the skew offset and aligns the data signals by eliminating the skew offset based on the skew information. Therefore, the memory device can increase signal integrity and enhance performance by reducing crosstalk occurring in the data signals on the signal lines.

[0037] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0038] Reference Figure 1 The storage system 10 may include a host 100 and a storage device 200. The host 100 may include a storage interface (I / F) 140.

[0039] exist Figure 1 In this example, storage device 200 is shown as a solid-state drive (SSD) device. However, the example embodiment is not limited to this. According to some example embodiments, storage device 200 can be any kind of storage device.

[0040] Storage device 200 may include a storage controller 300, a plurality of non-volatile memory devices (NVMs) 400a to 400k (where k is an integer greater than 2), a power supply circuit 500, and a connector 240. Connector 240 may include a signal connector 241 and a power connector 243. Storage device 200 may also include volatile memory devices (VMs) 250. The plurality of non-volatile memory devices (NVMs) 400a to 400k and volatile memory devices (VMs) 250 may be referred to as semiconductor memory devices.

[0041] Multiple non-volatile memory devices 400a to 400k may be used as storage media for storage device 200. In some example embodiments, each of the multiple non-volatile memory devices 400a to 400k may include flash memory or vertical NAND memory devices. Storage controller 300 may be coupled to the multiple non-volatile memory devices 400a to 400k respectively through multiple channels CHG1 to CHGk.

[0042] Through signal connector 241, the storage controller 300 can receive a receive signal RX from the host 100, send a transmit signal TX to the host 100, and exchange a clock signal CLK with the host 100. The receive signal RX may include command signals, address signals, and data.

[0043] The storage controller 300 can write data to or read data from multiple non-volatile memory devices 400a to 400k based on command signals and address signals. In other words, the storage controller 300 can communicate with the host 100 via connector 240.

[0044] Each of the non-volatile memory devices 400a to 400k can receive write data from the memory controller 300 based on a data strobe signal and a data signal, and can output read data to the memory controller 300 based on the data strobe signal and the data signal. In this case, the memory controller 300 can delay the data signal such that at least some edges of the data signal are desynchronized by a skew offset, and can send the delayed data signal to each of the non-volatile memory devices 400a to 400k. This structure and operation will be described in more detail below.

[0045] The memory controller 300 may use the volatile memory device 250 as an input / output buffer to transmit data signals with the host 100. In some example embodiments, the volatile memory device 250 may include dynamic random access memory (DRAM). Each of the non-volatile memory devices 400a to 400k and the volatile memory device 250 may be referred to as a semiconductor memory device.

[0046] The power supply circuit 500 can be configured to receive a power supply voltage VES (i.e., an external power supply voltage) from the host 100 via a power connector 243. The power supply circuit 500 can adaptively generate, based on the power supply voltage VES, at least one first operating voltage VOP1 used by a plurality of non-volatile memory devices 400a to 400k, at least one second operating voltage VOP2 used by the memory controller 300, and at least one third operating voltage VOP3 used by the volatile memory device 250.

[0047] The power supply circuit 500 can provide at least one first operating voltage VOP1 to a plurality of non-volatile memory devices 400a to 400k, can provide at least one second operating voltage VOP2 to the memory controller 300, and can provide at least one third operating voltage VOP3 to the volatile memory device 250.

[0048] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the host of the storage system.

[0049] Reference Figure 2 The host 100 may include a central processing unit (CPU) 110, a read-only memory (ROM) 120, a main memory 130, a storage interface 140, a user interface 150, and a bus 160.

[0050] Bus 160 can represent a transmission channel for data transfer between the CPU 110, ROM 120, main memory 130, storage interface 140 and user interface 150 of host 100.

[0051] ROM 120 can store various applications. For example, it can store applications that support storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), Embedded Multimedia Card (eMMC), and / or Unix File System (UFS) protocols.

[0052] Main memory 130 may temporarily store data or programs. User interface 150 may be a physical or virtual medium, computer program, etc., used for exchanging information between user and host 100, and includes physical hardware and logical software. For example, user interface 150 may include input devices for allowing user to manipulate host 100 and output devices for outputting the results of processing user input.

[0053] CPU 110 can control the overall operation of host 100. CPU 110 can generate commands for storing data in storage device 200 or requests (or commands) for reading data from storage device 200 by using applications stored in ROM 120, and send the requests to storage device 200 via storage interface 140.

[0054] Figure 3 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller for a storage system.

[0055] Reference Figure 3 The storage controller 300 may include a processor 310, an error correction code (ECC) engine 320, a ROM 330, a randomizer 335, a host interface 340, a volatile memory (VM) interface 360, and a non-volatile memory (NVM) interface 350 connected via a bus 305.

[0056] Processor 310 controls the overall operation of storage controller 300. Processor 310 may include training manager (TRM) 311. Training manager 311 can perform training such that at least some edges of data signals exchanged between storage controller 300 and each of non-volatile memory devices 400a to 400k are desynchronized by a first skew offset that is different from each other.

[0057] The skew offset can correspond to the difference in the edge of the data signal, which can reduce crosstalk between the data signals provided to each of the non-volatile memory devices 400a to 400k via signal lines, such that the eye window of the data signal is equal to or greater than a reference value. For example, the area of ​​the eye window of the data signal can be equal to or greater than the reference area. As another example, the length of the eye window of the data signal can be equal to or greater than the reference length. The training manager 311 can store the skew offset as skew information in the register of the storage controller 300.

[0058] The memory cells of the non-volatile memory devices 400a to 400k may have physical characteristics where the threshold voltage distribution varies due to various factors, such as programming elapsed time, temperature, programming interference, read interference, etc. For example, data stored in the non-volatile memory devices 400a to 400k may become incorrect due to one or more of these factors. The memory controller 300 utilizes various error correction techniques to correct such errors. For example, the memory controller 300 may include an ECC engine 320. The ECC engine 320 can correct errors in the data read from the non-volatile memory devices 400a to 400k.

[0059] ROM 330 may store firmware that can be read and executed by processor 310, the firmware being loaded into volatile memory device 250 and executed by processor 310. ROM 330 may store training manager code (TRM code) 333 as firmware. In other words, training manager code (TRM code) 333 can be read and executed by processor 310, which acts as training manager 311.

[0060] Randomizer 335 randomizes the data to be stored in non-volatile memory devices 400a to 400k. For example, randomizer 335 may randomize the data to be stored in non-volatile memory devices 400a to 400k on a word-line basis.

[0061] The data randomization step processes the data so that the programming states of the memory cells connected to a word line have the same ratio. For example, if the memory cells connected to a word line are multi-level cells (MLCs) that each store 2 bits of data, then each memory cell has an erase state and one of the first to third programming states. In this case, randomizer 335 randomizes the data so that the number of memory cells with the erase state, the number of memory cells with the first programming state, the number of memory cells with the second programming state, and the number of memory cells with the third programming state are substantially the same among the memory cells connected to a word line. For example, the memory cells storing the randomized data have an equal number of programming states.

[0062] Randomizer 335 derandomizes the data read from non-volatile memory devices 400a to 400k.

[0063] The storage controller 300 can communicate with the host 100 via the host interface 340 and with the non-volatile memory devices 400a to 400k via the non-volatile memory (NVM) interface 350. The storage controller 300 can control the volatile memory device 250 via the volatile memory (VM) interface 360.

[0064] Figure 4 Showing according to an example embodiment Figure 1 It is a storage controller and a non-volatile memory device in the storage device of a storage system.

[0065] Reference Figure 4 The storage controller 300 can exchange data signals DQ1 to DQm (m is an integer greater than 3) with the non-volatile memory device 400a through a transmission line including multiple signal lines 361 to 36m, and can exchange data strobe signal DQS with the non-volatile memory device 400a through signal line 355.

[0066] Multiple signal lines 361 to 36m and signal line 355 can form a channel and can be arranged (formed) in a printed circuit board (PCB). Therefore, when the gap between signal lines 361 to 36m is reduced, if the data signals DQ1 to DQm on signal lines 361 to 36m have the same edge, crosstalk or noise caused by crosstalk may occur in the data signals DQ1 to DQm on signal lines 361 to 36m.

[0067] The storage controller 300 may include a first delay circuit 370 that delays data signals DQ1 to DQm such that at least some edges of the data signals DQ1 to DQm on signal lines 361 to 36m are desynchronized by a first skew offset that is different from each other. In some example embodiments, the first delay circuit 370 may be a first extended delay-locked loop (SDLL) circuit 370 and may be referred to as a delay-locked loop circuit.

[0068] The storage controller 300 may include a first register 390, which stores a first skew offset as skew information associated with data signals DQ1 to DQm. The storage controller 300 may send the skew information SKI stored in the first register 390 to the non-volatile memory device 400a by using at least one of a setting feature command, a mode register setting, and a test mode register setting.

[0069] The non-volatile memory device 400a may include a second delay circuit 480 and a second register 405. In some example embodiments, the second delay circuit 480 may be a second extended delay-locked loop (SDLL) circuit and may be referred to as a delay-locked loop circuit.

[0070] The second register 405 can store the skew information SKI received from the storage controller 300. The second delay circuit 480 can delay the data signals DQ1 to DQm by using a second skew offset to eliminate the first skew offset, so as to provide the original data signal based on the skew information SKI. It can also sample the original data signal based on the data strobe signal DQS to provide the sampled original data signal to the inside of the non-volatile memory device 400a.

[0071] Each of the data signals DQ1 to DQm may have a unit interval (UI) defined by a first edge (left edge LE) and a second edge (right edge RE). That is, the first edge and the second edge define the unit interval. The first edge (left edge) represents the left (or earlier) closed portion of the unit interval UI of the eye diagram for each of the data signals DQ1 to DQm. The second edge (right edge) represents the right (or later) closed portion of the unit interval UI of each of the data signals DQ1 to DQm. Furthermore, the term "unit interval UI" may be used interchangeably with the term "window of data signals".

[0072] exist Figure 4 In this configuration, the data signals DQ1 to DQm on signal lines 361 to 36m are desynchronized with each other by different first skews. That is, the first edges of the data signals DQ1 to DQm on signal lines 361 to 36m have differences due to the offset of the first skew. Therefore, crosstalk occurring in the data signals DQ1 to DQm on signal lines 361 to 36m can be reduced.

[0073] When storage device 200 is started or initialized Figure 3 The processor 310 (i.e., the execution training manager 311) can send training patterns (e.g., training samples) to the non-volatile memory device 400a via signal lines 361 to 36m. Training can be performed to search for skew offsets that minimize crosstalk (i.e., maximize the eye window) occurring between training patterns on signal lines 361 to 36m, such that the eye window of the training pattern is equal to or greater than a reference value. Based on the training results, the first skew offset can be stored as skew information SKI in the first register 390. The processor 310 can search for skew offsets by sequentially performing training on the training patterns on signal lines 361 to 36m.

[0074] Figure 5This illustrates an example embodiment. Figure 4 A block diagram of an example of the first delay circuit 370.

[0075] Reference Figure 5 The first delay circuit 370 may include a buffer (BUF) 371, a voltage-controlled delay line (VCDL) 380, a phase detector (PD) 373, a charge pump (CP) 375, and a selection signal generator 378.

[0076] Buffer 371 buffers the input data signal DQ_IN corresponding to the data signal prior to the delay. Phase detector 373 detects the phase difference between the input data signal DQ_IN and the output data signal DQ_OUT, and outputs an upper signal UP and / or a lower signal DN based on the detected phase difference. Charge pump 375 performs a charging / discharging operation based on the upper signal UP and / or the lower signal DN to output a control voltage VCTL. Charge pump 375 can perform a charging operation based on the upper signal UP and can perform a discharging operation based on the lower signal DN.

[0077] The VCDL 380 can adjust the delay of the input data signal DQ_IN output from the buffer 371 based on the control voltage VCTL to provide an output data signal DQ_OUT corresponding to the data signal DQ. The selection signal generator 378 generates a selection signal SS based on the skew information SKI and provides the selection signal SS to the VCDL 380.

[0078] Figure 6 This illustrates an example embodiment. Figure 5 A block diagram of an example of a voltage-controlled delay line (VCDL) 380.

[0079] Reference Figure 6 The VCDL 380 may include multiple unit delay units (UDCs) 381 to 38n (n is an integer greater than 2), a multiplexer (MUX) 380b, and a bias generator 380c.

[0080] Multiple unit delay units 381 to 38n are connected in series. Each of the unit delay units 381 to 38n delays the output from the preceding unit delay unit to output a corresponding one of the internal data signals IDQ1 to IDQn based on a bias voltage PBIAS and / or NBIAS, and provides the output to the next unit delay unit. Multiplexer 380b selects one of the internal data signals IDQ1 to IDQn based on a selection signal SS, and outputs the selected internal data signal as the output data signal DQ_OUT. Bias generator 380c can generate bias voltages PBIAS and / or NBIAS based on a control voltage VCTL, and can provide the bias voltages PBIAS and / or NBIAS to the multiple unit delay units 381 to 38n.

[0081] Figure 4 The configuration of the second delay circuit 480 shown can have the same as... Figure 5 The first delay circuit 370 has essentially the same configuration and operation, so for the sake of brevity, its repeated description is omitted.

[0082] Figure 7 This illustrates an example embodiment. Figure 6 The circuit diagram of the unit delay unit of the voltage-controlled delay line (VCDL) 380 in the circuit. Figure 7 Unit delay unit 381 is shown as an example among a plurality of unit delay units 381 to 38n. However, it will be understood that the remaining unit delay units 382 to 38n have similar configurations and operations to unit delay unit 381, and therefore, for the sake of brevity, their repeated descriptions are omitted.

[0083] Reference Figure 7 The unit delay unit 381 may include a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors MP1, MP2, MP3 and MP4 and a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors MN1, MN2, MN3 and MN4.

[0084] PMOS transistors MP1 and MP3 are connected between the power supply voltage VDD and node N11 and between the power supply voltage VDD and node N12, respectively, and are connected in parallel. PMOS transistor MP2 is connected between node N11 and node N15, and PMOS transistor MP4 is connected between node N12 and node N16. NMOS transistor MN2 is connected between node N15 and node N13, NMOS transistor MN4 is connected between node N16 and node N14, NMOS transistor MN1 is connected between node N13 and ground, and NMOS transistor NM3 is connected between node N14 and ground.

[0085] A bias voltage PBIAS is applied to the gates of PMOS transistors MP1 and MP3, and a bias voltage NBIAS is applied to the gates of NMOS transistors MN1 and MN3. A first inverter, implemented using PMOS transistor MP2 and NMOS transistor MN2, inverts the input data signal DQ_IN to provide the inverted input data signal to node N15. A second inverter, implemented using PMOS transistor MP4 and NMOS transistor MN4, inverts the voltage at node N15 to provide the internal data signal IDQ1 at node N16.

[0086] The delay characteristics of the first and second inverters can be determined by the bias voltages PBIAS and NBIAS. Furthermore, since the first and second inverters are connected in series, the unit delay unit 381 operates as a buffer to delay the input data signal DQ_IN.

[0087] Figure 8 Showing according to an example embodiment Figure 4 The non-volatile memory interface in the memory controller and Figure 4 Non-volatile memory devices.

[0088] Reference Figure 8 The non-volatile memory (NVM) interface 350 is interfaced with the non-volatile memory device (NVM) 400a and may include a first delay circuit 370 and a first register 390. The non-volatile memory interface 350 may also include a plurality of transmit latches TR1 to TRm and a plurality of delay units DC11 to DC1m (m is an integer greater than 2). In some example embodiments, the plurality of delay units DC11 to DC1m may be included as part of the first delay circuit 370.

[0089] As described above, the first register 390 can store a first skew offset based on the training result, and the first delay circuit 370 can adjust the delay amount of the corresponding delay units in delay units DC11 to DC1m based on the first skew offset stored in the first register 390. Each of the delay units DC11 to DC1m can delay the clock signal CK1 based on the adjusted delay amount, so as to provide the corresponding delayed clock signal in the delayed clock signal to the transmit latches TR1 to TRm. A clock generator (not shown) in the non-volatile memory interface 350 can generate the clock signal CK1.

[0090] Each of the transmit latches TR1 to TRm can sample or latch a corresponding one of the original data signals DT1 to DTm synchronously with a corresponding one of the delayed clock signals to output a corresponding one of the data signals DQ1 to DQm. Each of the transmit latches TR1 to TRm transmits a corresponding one of the delayed clock signals to output the corresponding one of the data signals to the non-volatile memory device 400a via signal lines 361 to 36m. Therefore, as shown, the first edges of the windows of the data signals DQ1 to DQm on signal lines 361 to 36m are desynchronized, and crosstalk occurring between the data signals DQ1 to DQm on signal lines 361 to 36m is reduced.

[0091] The non-volatile memory interface 350 can send the data strobe signal DQS and the skew information SKI about the first skew offset to the non-volatile memory device 400a.

[0092] The non-volatile memory device 400a may include data input / output (I / O) circuitry 420 and page buffer circuitry 410. The data input / output (I / O) circuitry 420 may include a reference... Figure 4 The second delay circuit 480 and the second register 405 are described. The data I / O circuit 420 may also include multiple receive latches RR1 to RRm, multiple delay units DC21 to DC2m (m is an integer greater than 2), and sampling circuitry 490. In some example embodiments, the multiple delay units DC21 to DC2m may be included as part of the second delay circuit 480.

[0093] The second register 405 can store skew information SKI received from the non-volatile memory (NVM) interface 350. The second delay circuit 480 can adjust the delay amount of a corresponding delay unit DC11 to DC1m based on the skew information SKI via a second skew offset to eliminate the first skew offset. Each of the delay units DC21 to DC2m can delay the clock signal CK2 based on the adjusted delay amount to provide a corresponding delayed clock signal to the receive latches RR1 to RRm. Each of the receive latches RR1 to RRm can sample a corresponding data signal DQ1 to DQm synchronously with the corresponding delayed clock signal to provide a corresponding original data signal DT1 to DTm to the sampling circuit 490.

[0094] The sampling circuit 490 samples the original data signals DT1 to DTm based on the data strobe signal DQS to align the original data signals DT1 to DTm, and provides the sampled data signals SDT1 to SDTm to the page buffer circuit 410. The page buffer circuit 410 buffers the sampled data signals SDT1 to SDTm before output.

[0095] The clock generator (not shown) in the data I / O circuit 420 can generate the clock signal CK2.

[0096] Figure 9 Show Figure 8 Example of the first register 390 in the code.

[0097] Reference Figure 9The first register 390 can store the first skew offsets OFS1 of data signals DQ1 to DQm in a table format. When the first skew offset of data signal DQ1 is set to "0", the first register 390 can store the first skew offset of data signal DQ2 as "+a", the first skew offset of data signal DQ3 as "+b", and the first skew offset of data signal DQm as "+p". In other words, the first skew offset of data signal DQ2 can be 0+a, the first skew offset of data signal DQ3 can be 0+b, and so on. However, this is only an example, and various other methods of storing the first skew offsets are expected.

[0098] Figure 10 Show Figure 8 Example of the second register 405 in the example.

[0099] Reference Figure 10 The second register 405 can store, in tabular form, the second skew offset OFS2 used to eliminate the first skew offset OFS1 of data signals DQ1 to DQm. When the second skew offset of data signal DQ1 is set to "0", the second register 405 can store the second skew offset of data signal DQ2 as "-a", the second skew offset of data signal DQ3 as "-b", and the second skew offset of data signal DQm as "-p". In other words, the second skew offset of data signal DQ2 can be 0-a, the first skew offset of data signal DQ3 can be 0-b, and so on. However, this is only an example, and various other methods of storing the second skew offset are contemplated.

[0100] Figure 11 The example embodiment is shown in Figure 4 Data signals and data strobe signals during communication between the memory controller and the non-volatile memory device.

[0101] exist Figure 11 In the diagram, for ease of explanation, data signals DQ1, DQ2, and DQ3, as well as the data strobe signal DQS, are shown. The first skew offset, indicated by reference numeral 541, is related to... Figure 9 The first skew offset OFS1 is the same as that in the reference numeral 545, and the second skew offset is the same as that in the reference numeral 545. Figure 10 The second skew offset OFS2 is the same.

[0102] Additionally, I / O interface 395 may be included. Figure 8 In the non-volatile memory interface 350, the I / O interface 495 may be included. Figure 8 In the data I / O circuit 420.

[0103] Reference Figure 11At position 542 between I / O interface 395 and signal lines 361, 362, and 363, at position 543 on signal lines 361, 362, and 363, and at position 544 between signal lines 361, 362, and 363 and I / O interface 495, data signal DQ2 has a skew offset of "+a" relative to data signal DQ1, and data signal DQ3 has a skew offset of "+b" relative to data signal DQ1. The first edges of data signals DQ1, DQ2, and DQ3 are synchronized with each other at position 546 corresponding to the output of the second delay circuit 480.

[0104] and Figure 11 As shown in the diagram, when data signals DQ1, DQ2, and DQ3 are not desynchronized, crosstalk XTALK may occur at position 543 on signal lines 361, 362, and 363. According to... Figure 11 In the example embodiment shown, since the first edges of data signals DQ1, DQ2, and DQ3 are desynchronized by a first offset at position 543 on signal lines 361, 362, and 363, crosstalk XTALK occurring between data signals DQ1, DQ2, and DQ3 can be reduced.

[0105] Figure 12 This illustrates an example embodiment. Figure 1 A block diagram of a non-volatile memory device in a storage system.

[0106] Reference Figure 12 The non-volatile memory device (NVM) 400a includes a memory cell array 430, an address decoder 460, a page buffer circuit 410, a data input / output circuit 420, a control circuit 450, and a voltage generator 470. The control circuit 450 may include a mode register (MR) 455 for storing a second skew offset.

[0107] The memory cell array 430 is connected to the address decoder 460 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Additionally, the memory cell array 430 is connected to the page buffer circuit 410 via multiple bit lines BL. The memory cell array 430 includes multiple memory cells connected to the multiple word lines WL and the multiple bit lines BL. The memory cell array 430 may also include multiple memory cells connected to multiple word lines WL stacked in a vertical direction perpendicular to the substrate.

[0108] Figure 13 Show Figure 12 Block diagram of memory cell array 430 in non-volatile memory device (NVM) 400a.

[0109] Reference Figure 13The memory cell array 430 may include multiple memory blocks BLK1 to BLKz. Memory blocks BLK1 to BLKz extend along a first direction D1, a second direction D2, and a third direction D3. In some example embodiments, memory blocks BLK1 to BLKz are... Figure 12 The address decoder 460 selects the memory block corresponding to the block address from memory blocks BLK1 to BLKz.

[0110] Figure 14 Show Figure 13 The circuit diagram of the memory block of the memory cell array 430.

[0111] Figure 14 The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. For example, multiple strings of memory cells included in the memory block BLKi can be formed in a direction PD perpendicular to the substrate SUB.

[0112] Reference Figure 14 The memory block BLKi may include memory cell strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 (hereinafter referred to as memory cell strings NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the memory cell strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 (hereinafter referred to as memory cells MC1 to MC8), and a ground select transistor GST. Figure 14 In the example, each of the memory cell strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0113] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1 to MC8 can be connected to the corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 (hereinafter referred to as word lines WL to WL8). The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common-source line CSL.

[0114] Word lines of the same height (e.g., WL1) can be connected together, while ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. Figure 14 In the example, memory block BLKi is shown connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, the example embodiment is not limited to this. In some example embodiments, memory cell array 430 may be connected to any number of word lines and bit lines.

[0115] Return to reference Figure 12 The control circuit 450 can receive command signal CMD and address signal ADDR from the memory controller 300, and control the erase operation, programming operation and read operation of the non-volatile memory device 400a based on the command signal CMD and address signal ADDR.

[0116] For example, control circuit 450 can generate control signal CTL for controlling voltage generator 470 based on command signal CMD, and generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 450 can provide row address R_ADDR to address decoder 460, and provide column address C_ADDR to data input / output circuit 420.

[0117] In one example embodiment, the address decoder 460 is connected to the memory cell array 430 via the serial select line SSL, the multiple word line WL, and the ground select line GSL.

[0118] In one example embodiment, voltage generator 470 uses a first operating voltage VOP1 based on control signal CTL to generate word line voltage VWL for operation of non-volatile memory device 400a. Word line voltage VWL is applied to multiple word lines WL via address decoder 460.

[0119] In one example embodiment, page buffer circuitry 410 is connected to memory cell array 430 via multiple bit lines BL. Page buffer circuitry 410 may include multiple page buffers. In an exemplary embodiment, a page buffer may be connected to one bit line. In other exemplary embodiments, a page buffer may be connected to two or more bit lines. Page buffer circuitry 410 may temporarily store data to be programmed into a selected page or data read from a selected page. Page buffer circuitry 410 is controlled in response to a control signal PCTL received from control circuitry 450.

[0120] In one example embodiment, the data input / output circuit 420 is connected to the page buffer circuit 410 via a data line DL. During a programming operation, the data input / output circuit 420 may receive programming data DTA from the memory controller 300 and provide the programming data DTA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 may provide the read data DTA stored in the page buffer circuit 410 to the memory controller 300 based on the column address C_ADDR received from the control circuit 450.

[0121] Figure 15 and Figure 16 These are a plan view and a cross-sectional view of a printed circuit board (PCB) on which a storage device is mounted, according to an example embodiment.

[0122] Reference Figure 15 and Figure 16 PCB 10 is shown as including a first channel pattern CHP1, a second channel pattern CHP2, a third channel pattern CHP3, and a fourth channel pattern CHP4. Additionally, PCB 10 may include a connector 240 comprising multiple connection terminals and an indented structure 230 corresponding to the connector 240. Exposed patterns may be formed on the edges of the indented structure 230 and may be connected to electrical conductors of the host 100 when mounted on the host 100. For example, the patterns formed on the edges of the indented structure 230 may correspond to a grounding node of the storage device 200 and may be connected to electrical conductors corresponding to the grounding node of the host 100 when mounted on the host 100.

[0123] PCB 10 may include a main body layer 11, a top protective layer 13, and a bottom protective layer 15. PCB 10 may include wiring units that can be electrically connected to the storage controller 300 and non-volatile storage devices 400a to 400k. PCB 10 may be electrically connected to a module substrate, system board, motherboard, etc., via connectors 240 on which PCB 10 is mounted.

[0124] In the main body layer 11, multi-layer or single-layer wiring units can be formed, and through the wiring units, the PCB 10 can be electrically connected to the memory controller 300 and non-volatile memory devices 400a to 400k. The top protective layer 13 and the bottom protective layer 15 perform protective functions and can be formed with solder resist.

[0125] Alternatively, the main body layer 11 can typically be achieved by pressing a polymer material (such as thermosetting resin, epoxy resin, or phenolic resin (such as flame retardant 4 (FR-4), bismaleimide triazine (BT), and Ajinomoto deposited film (ABF))) to a specific thickness, forming the pressed product into a thin layer, coating copper foil on both sides of the formed thin layer, and patterning wiring units as electrical signal transmission paths.

[0126] Additionally, in some example embodiments, PCB 10 may be configured as a single-layer PCB with wiring formed on one side, while in other example embodiments, PCB 10 may be configured as a double-layer PCB with wiring formed on both sides. Furthermore, the number of thin layers may be three or more and can be formed using an insulating material (such as prepreg), and a PCB including multi-layer wiring can be implemented by forming three or more wiring layers depending on the number of thin layers formed.

[0127] PCB 10 may be a substrate on which semiconductor packages are mounted, and includes an insulating layer and wiring units. The wiring units may include a first conductive trace CT1 and a second conductive trace CT2 formed in the insulating layer, and may include one or more first conductive vias CV1 passing through the insulating layer and connected to the first conductive trace CT1, and one or more second conductive vias CV2 passing through the insulating layer and connected to the second conductive trace CT2.

[0128] The first channel pattern CHP1 may be a first wiring unit and may include a first conductive trace CT1 extending in the second direction D2, a first conductive via CV1 extending in the third direction D3, and a first conductive pad CP1 formed on the top side of the first conductive via CV1.

[0129] The second channel pattern CHP2 may be a second wiring unit and may include a second conductive trace CT2 extending in the second direction D2, a second conductive via CV2 extending in the third direction D3, and a second conductive pad CP2 formed on the top side of the second conductive via CV2.

[0130] In some example embodiments, the reason why the second channel pattern CHP2 formed in a daisy chain manner / topology has different wiring lengths in the first mounting area MR1 and the second mounting area MR2 is that it may be desirable to provide a method for compensating for signal loss in only one of the first mounting area MR1 and the second mounting area MR2.

[0131] In some exemplary embodiments, a semiconductor package in the first mounting region MR1 may be electrically connected to a first channel pattern CHP1 to a fourth channel pattern CHP4, and a semiconductor package in the second mounting region MR2 may be electrically connected to a second channel pattern CHP2 and a third channel pattern CHP3.

[0132] Although for the sake of ease of description, in Figure 16 Only the first channel pattern CHP1 and the second channel pattern CHP2 are shown. However, the first channel pattern CHP1 and the fourth channel pattern CHP4 can be configured in a point-to-point manner / topologically identical to each other (or can be configured as a group of channel patterns). The second channel pattern CHP2 and the third channel pattern CHP3 can be configured in a daisy chain manner / topologically identical to each other (or can be configured as another group of channel patterns). The second channel pattern CHP2 and the third channel pattern CHP3 can be formed to face each other and be adjacent to each other. The first channel pattern CHP1 and the fourth channel pattern CHP4 can be formed to face each other, and the second channel pattern CHP2 and the third channel pattern CHP3 are located between the first channel pattern CHP1 and the fourth channel pattern CHP4. In other words, for ease of circuit design, since the second channel pattern CHP2 and the third channel pattern CHP3 are formed in a daisy-chain manner / topology and have branch points in the middle, the branch points can be arranged in the shape described above, so that the branch points do not overlap with the first channel pattern CHP1 and the fourth channel pattern CHP4.

[0133] exist Figure 16 In the diagram, the first channel pattern CHP1 is shown to be formed on a layer closer to the bottom protective layer 15 than the second channel pattern CHP2. However, the second channel pattern CHP2 may be formed on a layer closer to the bottom protective layer 15 than the first channel pattern CHP1, and in some exemplary embodiments, the first channel pattern CHP1 and the second channel pattern CHP2 may also be formed on the same layer.

[0134] The storage controller region CR and the first mounting region MR1 may include all of the first conductive via CV1 and the second conductive via CV2, as well as the first conductive pad CP1 and the second conductive pad CP2, included in the first channel pattern CHP1 to the fourth channel pattern CHP4. The second mounting region MR2 may include only a portion of the first conductive via CV1 and the second conductive via CV2, as well as the first conductive pad CP1 and the second conductive pad CP2, included in the second channel pattern CHP2 and the third channel pattern CHP3.

[0135] Additionally, PCB 10 may include a power supply area PR adjacent to the memory controller area CR. The memory controller area CR and connector 240 may be connected via conductive pattern 261.

[0136] Figure 17 and Figure 18 These are a plan view and a cross-sectional view of a storage device according to an example embodiment.

[0137] Reference Figure 17 and Figure 18 A storage device 200a is provided, in which a first memory package 401 may be mounted only in a first mounting area MR1 of a PCB 10, and a second memory package 402 may be mounted only in a second mounting area MR2 of a PCB 10. A first channel CH1 and a fourth channel CH4 are connected to the first memory package 401, and a second channel CH2 and a third channel CH3 are connected to the second memory package 402.

[0138] Each of the first memory package 401 and the second memory package 402 can be stacked. Figure 1 The storage system is formed by at least some of the non-volatile memory devices 400a to 400k. A first memory package 401 is connected to a first channel CH1 and a second channel CH2 via solder balls SB11 and SB12, a second memory package 402 is connected to the second channel CH2 via solder ball SB22, and a memory controller 300 is connected to the first channel CH1 and the second channel CH2 via solder balls SB31 and SB32.

[0139] Conductive patterns 261 and 281 connecting connector 240 and memory controller 300 can be provided in PCB 10. Conductive pattern 261 can be connected to memory controller 300 via solder ball SB33.

[0140] Figure 19 This illustrates an example embodiment. Figure 1 A block diagram of an example storage device in a storage system.

[0141] Reference Figure 19 The storage device 200b may include a storage controller 300 and a package (PKG) 400, the package (PKG) 400 including a plurality of non-volatile memory devices (NVMs) 400a to 400k disposed on the PCB 10.

[0142] The memory controller 300 and the non-volatile memory devices 400a to 400k can be electrically connected to each other via transmission line 50. Through transmission line 50, the memory controller 300 can send command signals and address signals to the non-volatile memory devices 400a to 400k, and can exchange data with them. Transmission line 50 may include signal lines 361 to 36m and signal line 355.

[0143] As discussed above, the memory controller 300 may include a first delay circuit and a first register, and at least a portion of the non-volatile memory devices 400a to 400k may include a second delay circuit and a second register. Therefore, the memory controller 300 can delay the data signal such that at least some first edges of the window of the data signal are desynchronized by different first skew offsets, and the delayed data signal can be sent to one of the non-volatile memory devices 400a to 400k via the transmission line 50. Thus, the memory controller 300 can reduce crosstalk occurring in the data signal on the transmission line 50.

[0144] The storage device 200b may also include a conductive pattern set as part of the PCB 10, the conductive pattern connecting the connector 240 and the storage controller 300.

[0145] Despite Figure 19 In the diagram, storage device 200b is shown as including storage controller 300 and package 400 including a plurality of non-volatile memory devices 400a to 400k, but storage device 200b may also include other components (such as power supply circuitry and / or volatile memory devices).

[0146] Storage device 200b may include flash-based data storage media (such as memory cards, smart cards, universal serial bus (USB) memory, solid-state drives (SSDs)).

[0147] Package 400 may include non-volatile memory devices 400a to 400k. If the non-volatile memory devices 400a to 400k are included in package 400 in the form of multiple stacked chips, the stacked non-volatile memory devices 400a to 400k are connected to memory controller 300 through the same channel.

[0148] Figure 20 An example of the operation of a storage device according to an example embodiment is shown.

[0149] Reference Figures 3 to 18 and Figure 20 A method for operating a storage device 200 is provided, the storage device 200 including at least one non-volatile memory device (NVM) 400a and a storage controller 300 for controlling at least one non-volatile memory device (NVM) 400a.

[0150] According to the method, the storage controller 300 stores the first skew offset OFS1 as skew information SKI in the first register 390 (operation S110). The first skew offset OFS1 is associated with data signals DQ1 to DQm that will be sent to at least one non-volatile memory device (NVM) 400a via signal lines 361 to 36m.

[0151] The storage controller 300 sends the skew information SKI to at least one non-volatile memory device (NVM) 400a (operation S120).

[0152] At least one non-volatile memory device (NVM) 400a stores the skew information SKI received from the memory controller 300 in a second register 405 (operation S130).

[0153] The first delay circuit 370 in the memory controller 300 delays the original data signals DT1 to DTm by different delay amounts based on the skew information SKI stored in the first register 390, so as to output data signals DQ1 to DQm. The memory controller 300 sends the data strobe signal DQS and the data signals DQ1 to DQm with the first skew offset in parallel to at least one non-volatile memory device (NVM) 400a via signal lines 361 to 36m and 355 (operation S140).

[0154] A second delay circuit 480 in at least one non-volatile memory device (NVM) 400a aligns the data signals based on the stored skew information SKI (operation S150). For example, the second delay circuit 480 delays the data signals DQ1 to DQm by using a second skew offset stored in the second register 405 to eliminate the first skew offset, thereby aligning the data signals DQ1 to DQm and outputting the original data signals DT1 to DTm.

[0155] A sampling circuit 490 in at least one non-volatile memory device (NVM) 400a samples an aligned data signal based on a data strobe signal (operation S160). For example, the sampling circuit 490 samples the original data signals DT1 to DTm based on the data strobe signal DQS (operation S160) and provides the sampled data signal to the interior of at least one non-volatile memory device (NVM) 400a.

[0156] During the idle time interval of the storage device 200, the storage controller 300 performs training to search for skew offsets to minimize crosstalk occurring between training patterns on signal lines 361 to 36m, thereby increasing the eye window of the training pattern (operation S170), and the storage controller 300 updates the skew information SKI stored in the first register 390 (operation S175).

[0157] The storage controller 300 sends the updated skew information to at least one non-volatile memory device (NVM) 400a (operation S180), and the at least one non-volatile memory device (NVM) 400a stores the updated skew information in a second register 405.

[0158] Figure 21 An example of the operation of a storage device according to an example embodiment is shown.

[0159] Reference Figures 3 to 18 , Figure 20 and Figure 21 A method for operating a storage device 200 is provided, the storage device 200 including at least one non-volatile memory device (NVM) 400a and a storage controller 300 for controlling at least one non-volatile memory device (NVM) 400a.

[0160] Figure 21 The method includes operations S200 and S310, S320, S330, S340, S350, S360, S370, S375, and S380, and each of operations S310, S320, S330, S340, S350, S360, S370, S375, and S380 is respectively associated with... Figure 20 Operations S110, S120, S130, S140, S150, S160, S170, S175, and S180 are essentially the same. Therefore, for the sake of brevity, detailed descriptions of operations S310, S320, S330, S340, S350, S360, S370, S375, and S380 will be omitted.

[0161] The storage controller 300 performs automatic data training (operation S200). For example, the storage controller 300 performs training by sending training patterns to at least one non-volatile memory device (NVM) 400a via signal lines 361 to 36m, and searches for skew offsets to minimize crosstalk occurring in the training patterns on signal lines 361 to 36m (i.e., maximize eye diagrams) such that the eye window of the training patterns is equal to or greater than a reference value, and stores the skew offsets as skew information SKI in the first register 390 based on the training results (operation S310).

[0162] The storage controller 300 can sequentially perform training on the training modes on signal lines 361 to 36m, and can store the skew offset as skew information SKI in the first register 390 based on the results of the sequentially performed training.

[0163] For example, suppose that data signals DQ1 to DQm are sent in parallel to a non-volatile memory device (also referred to as "at least one semiconductor memory device") via signal lines 361 to 36m.

[0164] Since the number of data signals DQ1 to DQm and the number of signal lines 361 to 36m correspond to m, the resolution of the skew offset between data signals DQ1 to DQm is set to 360 degrees / m = A.

[0165] The skew offset for the training mode of data signal DQ1 is set to "0", the skew offset for the training mode of data signal DQ2 is changed sequentially from "A" to "m*A", and the skew offset that makes the eye window of the training mode of data signal DQ2 on signal line 362 the maximum value is stored in the first register 390.

[0166] With the skew offset of data signal DQ2 fixed, the skew offset of the training mode for data signal DQ3 is changed sequentially from "A" to "m*A", and the skew offset that makes the eye window of the training mode for data signal DQ3 on signal line 363 the maximum value is stored in the first register 390.

[0167] The above processing is performed sequentially on data signals DQ4 to DQm. Training ends when the skew offsets of data signals DQ2 to DQm are stored in the first register 390. That is, the skew offsets of data signals DQ1 to DQm can be determined sequentially and stored in the first register 390. Additionally, it can be... Figure 3 The processor 310 measures the training mode relative to the eye window of each of the data signals DQ2 to DQm.

[0168] When data signals DQ1 to DQm are sent to non-volatile memory device 400a, the data signals DQ1 to DQm are desynchronized relative to each other by a skew offset determined during training, so that crosstalk that may occur in the data signals DQ1 to DQm on signal lines 361 to 36m can be reduced.

[0169] Figure 22 and Figure 23 This is a diagram used to explain the operation of a storage device according to an example embodiment.

[0170] Figure 22 show when Figure 4 The eye diagram of the data signals DQ1 to DQm transmitted in parallel from the storage controller 300 when the storage controller 300 does not adjust the skew offset of the data signals DQ1 to DQm. Figure 23 show when Figure 4 The eye diagram of the data signals DQ1 to DQm sent in parallel from the storage controller 300 when the storage controller 300 adjusts the skew offset of the data signals DQ1 to DQm.

[0171] exist Figure 22 and Figure 23In the diagram, the horizontal axis represents time, and the vertical axis represents the voltage level of the data signal.

[0172] Reference Figure 4 , Figure 22 and Figure 23 Note that the storage controller 300 adjusts the skew offset of data signals DQ1 to DQm such that the eye window 520 for desynchronizing data signals DQ1 to DQm is larger than the eye window 510 for which the storage controller 300 does not adjust the skew offset of data signals DQ1 to DQm. For example, the area of ​​eye window 520 may be larger than the area of ​​eye window 510. As another example, the length of eye window 520 on the x-axis may be greater than the length of eye window 510 on the x-axis.

[0173] According to the example embodiment, when the storage controller 300 adjusts the skew offset of the parallel transmitted data signals DQ1 to DQm so that the data signals DQ1 to DQm are desynchronized, the signal integrity of the data signals DQ1 to DQm output from the storage controller 300 is enhanced.

[0174] Figure 24 Showing according to an example embodiment Figure 1 The volatile memory device 250 of the storage system and Figure 3 The volatile memory interface 360 ​​in the memory controller.

[0175] Reference Figure 24 The volatile memory interface 360 ​​can exchange data signals VDQ1 to VDQq (q is an integer greater than 3) with the volatile memory device 250 via multiple signal lines 221 to 22q, and can exchange the data strobe signal DQS1 with the volatile memory device 400a via signal line 231. Signal lines 221 to 22q and signal line 231 are formed in the PCB and connect the memory controller 300 and the volatile memory device 250. Therefore, as shown in the reference... Figure 4 The gap between signal lines 221 to 22q is reduced. If the data signals VDQ1 to VDQq on signal lines 221 to 22q have the same edge, crosstalk or noise caused by crosstalk may occur in the data signals VDQ1 to VDQq on signal lines 221 to 22q.

[0176] To reduce crosstalk, the volatile memory interface 360 ​​includes a first delay circuit 361 and a first register 363, and the volatile memory device 250 includes a second delay circuit 251 and a second register 253. The volatile memory interface 360 ​​can store the skew offset associated with the data signals VDQ1 to VDQm as skew information SKI1 in the first register 363, and can send the skew information SKI1 to the volatile memory device 250.

[0177] Therefore, the volatile memory interface 360 ​​and the volatile memory device 250 can intentionally generate skew between data signals VDQ1 to VDQm, and can reduce crosstalk occurring between data signals VDQ1 to VDQ on signal lines 221 to 22q. The volatile memory device 250 may include a memory cell array (MCA) 255 having a plurality of volatile memory cells connected to word lines and bit lines.

[0178] According to an example embodiment, a memory controller including delay circuitry delays a data signal to be transmitted to a semiconductor memory device via a signal line, such that at least some of the first edges of the data signal are desynchronized by a skew offset, and the data signal is then transmitted to the semiconductor memory device. The semiconductor memory device receives skew information associated with the skew offset and aligns the data signal by eliminating the skew offset based on the skew information. Therefore, the memory device can increase signal integrity and enhance performance by reducing crosstalk occurring in the data signal on the signal line.

[0179] Figure 25 This is a block diagram illustrating a storage device according to an example embodiment.

[0180] Reference Figure 25 The storage device 600 may include a storage controller 700 and a non-volatile memory device 800. The non-volatile memory device 800 may be configured to perform write operations, read operations, or erase operations under the control of the storage controller 700.

[0181] The storage controller 700 may include a host interface 710, a processor 720, a volatile memory device (VM) 730, and a non-volatile memory (NVM) interface 740 connected via a bus 705.

[0182] The host interface 710 can communicate with an external host and can transmit requests from the host to the processor 720. The processor 720 may include one or more microprocessors and can control the overall operation of the storage controller 700. The processor 720 may include a training manager (TRM) 721 and an error handler (ERHND) 723. The training manager 721 and the error handler 723 may be implemented in the form of circuitry of the processor 720 and / or in the form of code executable by the circuitry.

[0183] The volatile memory device (VM) 730 can be used as the working memory of the processor 720. The volatile memory device 730 can also be used as a buffer memory or cache memory between an external host and a non-volatile memory device 800.

[0184] The non-volatile memory (NVM) interface 740 can operate in response to requests from the processor 720. The NVM interface 740 can send commands CMD and addresses ADDR to the non-volatile memory device 800 via control lines, and can exchange data DTA and data strobe signals DQS with the non-volatile memory device 800 via signal lines.

[0185] The non-volatile memory (NVM) interface 740 may include an ECC engine 741, a first delay circuit 743, and a first register 745. The ECC engine 741 performs operations related to... Figure 3 The operation is similar to that of the ECC engine 320, and the first delay circuit 743 has the same... Figure 4 The first delay circuit 370 in the middle has a similar structure and performs the same function as the first delay circuit 370. Figure 4 The first delay circuit 370 operates similarly to the first register 745, which has the same characteristics as the first delay circuit 370. Figure 4 The first register 390 in the structure is similar to the one in the middle and performs the same operation. Figure 4 The operation is similar to that of the first register 390 in the code, so for the sake of brevity, its repeated description is omitted.

[0186] The non-volatile memory device 800 may include a memory cell array (MCA) 830, an address decoder 860, a page buffer circuit 810, a data input / output (I / O) circuit 820, and a control circuit 850.

[0187] The memory cell array (MCA) 830 is connected to the address decoder 860 via a serial select line (not shown), multiple word lines WL, and a ground select line (not shown). Additionally, the memory cell array 830 is connected to the page buffer circuit 810 via multiple bit lines BL. The memory cell array 830 includes multiple memory cells connected to the multiple word lines WL and the multiple bit lines BL.

[0188] The data input / output circuit 820 is connected to the page buffer circuit 810 via the data line DL. The data input / output circuit 820 may include a second delay circuit 821 and a second register 823. The second delay circuit 821 has... Figure 4 The second delay circuit 480 in the middle has a similar structure and performs the same function as the second delay circuit 480. Figure 4 The second delay circuit 480 operates similarly to the second register 823, which has the same characteristics as the second delay circuit 480. Figure 4 The second register 405 in the structure is similar to and performs the same operation as... Figure 4 Similar to the operation of the second register 405 in the middle.

[0189] The control circuit 850 can control the operation of the non-volatile memory device 800 based on the command CMD and address ADDR received from the non-volatile memory interface 740. The data I / O circuit 820 exchanges data DTA and data strobe signal DQS with the non-volatile memory interface 740.

[0190] Figure 26 This illustrates an example embodiment. Figure 25 A flowchart of the operation of the storage device.

[0191] Reference Figure 25 and Figure 26 When storage device 600 is started or initialized, processor 720 (i.e., training manager 721) can perform data training to store skew offsets (operation S410). For example, processor 720 can send training patterns to non-volatile memory device 800 via signal lines, perform training to search for skew offsets to minimize crosstalk between training patterns on the signal lines, and store the skew offsets as skew information in first register 745 based on the training results. The training sequence can be compared with a reference... Figure 21 The training sequences described are the same.

[0192] The non-volatile memory interface 740 delays the data signal so that the data signal being written is desynchronized by a skew offset, and then transmits the data signal to the non-volatile memory device 800.

[0193] The storage controller 700 reads data, including data signals, from the non-volatile memory device 800 (operation S420).

[0194] Processor 720 determines whether the number of read data errors exceeds a first threshold TV1 (operation S430). Processor 720 can detect read data errors by using ECC engine 741.

[0195] When the number of errors exceeds the first threshold TV1 ("Yes" in S430), the processor 720 (error processor 723) determines whether the errors include timing errors caused by changes in signal transmission timing (operation S440). For example, after the delay amount of the VCDL of the first delay circuit 743 is locked (or fixed), the delay amount of the VCDL of the first delay circuit 743 may change over time or with temperature. The processor 720 can determine whether timing errors caused by changes in delay (i.e., changes in signal transmission timing) exist.

[0196] When the error is determined to include a timing error ("Yes" in S440), the processor 720 may adjust the skew offset (operation S450). For example, the processor 720 may perform a training operation to adjust the skew offset. The adjusted skew offset may be stored as updated skew information in the first register 745 and the second register 823.

[0197] The processor 720 may terminate when the number of errors is not greater than the first threshold TV1 ("No" in S430), or when it is determined that the errors do not include timing errors ("No" in S440). Figure 26 The processing.

[0198] Figure 27 This is a block diagram illustrating a storage system according to an example embodiment.

[0199] Reference Figure 27 The storage system 1000 may include a host 1100 and a storage device 1200. The storage device 1200 can be connected to the host 1100 via a connector 1201 including multiple connection terminals and can communicate with the host 1100. (See reference...) Figure 1 The connector 1201 may include a signal connector and a power connector.

[0200] The host 1100 includes an application 1110, a device driver 1120, a host controller 1130, and a buffered random access memory (RAM) 1140. The host controller 1130 includes a command (CMD) manager 1131, a host direct memory access (DMA) 1132, and a power manager 1133.

[0201] In operation, system-level commands (e.g., write commands) are generated by application 1110 and device driver 1120 of host 1100 and then provided to command manager 1131 of host controller 1130. Command manager 1131 can be used to generate corresponding storage device commands (i.e., corresponding commands or command sets consistent with the protocol implemented by storage system 1000) provided to storage device 1200 using device driver 1120. Commands generated by command manager 1131 can also be provided to host DMA 1132, which sends the commands to storage device 1200 via storage interface 1101.

[0202] Storage device 1200 includes a flash memory device (NVM) 1210, a device controller 1230, and a buffered random access memory (RAM) 1240. Device controller 1230 may include a central processing unit (CPU) 1231, a device DMA 1232, a flash memory DMA 1233, a command (CMD) manager 1234, a buffer manager 1235, a flash translation layer (FTL) 1236, a flash memory manager 1237, and a power supply circuit (PSC) 1238. Power supply circuit 1238 can generate an operating voltage based on the power supply voltage VES from host 1100.

[0203] The flash memory device 1210, the device controller 1230, and the buffer RAM 1240 can be mounted on the PCB.

[0204] Commands transmitted from host 1100 to storage device 1200 can be provided to device DMA1232 via connector 1201.

[0205] Then, the DMA device 1232 can transmit the received command to the command manager 1234. The command manager 1234 can be used to allocate memory space in the buffer RAM 1240 so as to receive the corresponding write data via the buffer manager 1235. Once the storage device 1200 is ready to receive write data, the command manager 1234 can transmit a transmission "ready" signal to the host 1100.

[0206] Upon receiving a transmission ready signal, host 1100 transmits write data to storage device 1200. The write data can be sent to storage device 1200 using host DMA 1132 and storage interface 1101. Storage device 1200 can then use device DMA 1232 and buffer manager 1235 to store the received write data in buffer RAM 1240. The write data stored in buffer RAM 1240 can then be provided to flash manager 1237 via flash DMA 1233. Flash manager 1237 can be used to program the write data according to the address of flash device 1210 obtained from the address mapping table by flash translation layer 1236.

[0207] Once the data transfer and programming are complete, the storage device 1200 can send a response to the host 1100, notifying the host 1100 that the write command has been successfully executed. Based on the received response signal, the host 1100 indicates to the device driver 1120 and the application 1110 that the command is complete, and then terminates the execution of the operation corresponding to the command.

[0208] As described above, the host 1100 and the storage device 1200 can exchange data, corresponding commands, and / or (one or more) control signals (e.g., ready signals and response signals) via data lines (e.g., data lines DIN and DOUT).

[0209] According to an example embodiment, the device controller 1230 exchanges data signals with each of the non-volatile memory devices (NVMs) 1210 via multiple signal lines. The flash DMA 1233 includes delay circuitry and registers. The flash DMA 1233 stores a skew offset, delaying the data signals such that at least some of the edges of the data signals are desynchronized by the skew offset, and transmits the data signals to each of the NVMs 1210. Therefore, the storage device 1200 can reduce crosstalk occurring on the signal lines connecting the device controller 1230 and each of the NVMs 1210, and can increase signal integrity.

[0210] Various package types or package configurations can be used to package the storage device or storage system according to the example embodiments.

[0211] This disclosure can be applied to various electronic devices, including storage devices.

[0212] The foregoing is a description of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: At least one semiconductor memory device is configured to receive write data based on a data strobe signal and a plurality of data signals, and is configured to output read data based on the data strobe signal and the plurality of data signals; and The memory controller is configured to transmit a data strobe signal and a plurality of data signals in parallel to the at least one semiconductor memory device via multiple signal lines. The storage controller includes a first delay circuit configured to delay the plurality of data signals such that at least some edges of the windows of the plurality of data signals on the plurality of signal lines are desynchronized by different first skew offsets. The memory controller is configured to send skew information, including a first skew offset, to the at least one semiconductor memory device. The at least one semiconductor memory device includes a second delay circuit configured to receive skew information and configured to delay the plurality of data signals based on the skew information by a second skew offset for eliminating the first skew offset, in order to provide the original data signal.

2. The storage device according to claim 1, wherein, The storage controller also includes a first register configured to store a first skew offset as skew information; Each of the plurality of data signals has a window defined by a first edge and a second edge; The at least some edges correspond to a portion of the first edge; and The first skew offset corresponds to the difference in the first edge of the plurality of data signals, and the difference in the first edge reduces the crosstalk occurring between the plurality of data signals on the plurality of signal lines, such that the eye window of the plurality of data signals is equal to or greater than the reference value.

3. The storage device according to claim 2, wherein, When the storage device is started or initialized, the storage controller is configured to: The training mode is sent to the at least one semiconductor memory device via the multiple signal lines; Based on the transmitted training pattern, training is performed to search for a skew offset as a first skew offset to minimize crosstalk occurring between the training patterns on the multiple signal lines. and Based on the training results, the first skew offset is stored as skew information in the first register.

4. The storage device according to claim 3, wherein, The storage controller is configured to search for skew offsets by sequentially performing training on training patterns on the multiple signal lines.

5. The storage device according to claim 1, wherein, The memory controller is configured to send skew information, including a first skew offset, to the at least one semiconductor memory device by using at least one of a setting feature command, a mode register setting, and a test mode register setting.

6. The storage device of claim 5, wherein the at least one semiconductor memory device further comprises a sampling circuit configured to sample the original data signal based on a data strobe signal.

7. The storage device according to claim 1, wherein, The at least one semiconductor memory device includes a non-volatile memory device, and The storage controller also includes: The processor is configured to control the overall operation of the memory controller; and A non-volatile memory interface is configured to interface with a processor-based control non-volatile memory device, the non-volatile memory interface including a first delay circuit and a first register.

8. The storage device according to claim 7, wherein, Each of the plurality of data signals has a window defined by a first edge and a second edge; The at least some edges correspond to a portion of the first edge; The first register is configured to store a first skew offset as skew information; and The first skew offset corresponds to the difference in the first edge of the plurality of data signals, and the difference in the first edge reduces the crosstalk occurring between the plurality of data signals on the plurality of signal lines, such that the eye window of the plurality of data signals is equal to or greater than the reference value.

9. The storage device according to claim 7, wherein, When the storage device is started or initialized, the storage controller is configured to: The training mode is sent to the at least one semiconductor memory device via the multiple signal lines; Based on the transmitted training pattern, training is performed to search for a skew offset as a first skew offset to minimize crosstalk occurring between the training patterns on the multiple signal lines. and Based on the training results, the first skew offset is stored as skew information in the first register.

10. The storage device according to claim 9, wherein, The processor is configured to perform training to update skew information during idle time intervals of the non-volatile memory device, and is configured to send the updated skew information to the non-volatile memory device.

11. The storage device according to claim 7, wherein, The first delay circuit includes: A phase detector is configured to detect the phase difference between each input data signal input to the first delay circuit and a corresponding one of the plurality of data signals, and is configured to output an upper signal and a lower signal based on the phase difference; A charge pump is configured to perform charging / discharging operations based on upper and lower signals to output a control voltage; and The voltage-controlled delay line is configured to adjust the delay of the input data signal based on the control voltage in order to output a corresponding one of the plurality of data signals.

12. The storage device according to claim 7, wherein, The non-volatile memory interface includes multiple transmit latches; Each of the plurality of transmit latches is configured to synchronously latch a corresponding one of the plurality of data signals with a corresponding one of the delayed clock signals generated by delaying the clock signal through a first skew offset; and The first delay circuit is configured to delay the clock signal by a first skew offset based on the skew information stored in the first register.

13. The storage device according to claim 7, wherein, Non-volatile memory devices include: A memory cell array, comprising multiple memory blocks, each memory block comprising multiple non-volatile memory cells connected to word lines and bit lines; A data input / output circuit is configured to receive write data to be programmed into the memory cell array from the memory controller via the plurality of signal lines, and is configured to provide read data from the memory cell array to the memory controller via the plurality of signal lines; and The control circuit is configured to control the data input / output circuit.

14. The storage device according to claim 13, wherein, The data input / output circuit includes: The second register is configured to receive and store skew information; and Second delay circuit.

15. The storage device according to claim 13, wherein, At least one of the plurality of memory blocks includes a NAND string, the NAND string comprising at least a portion of the plurality of nonvolatile memory cells sequentially stacked on a substrate.

16. The storage device according to any one of claims 1 to 15, wherein, The at least one semiconductor memory device includes a volatile memory device having a plurality of volatile memory cells connected to word lines and bit lines.

17. The storage device according to any one of claims 1 to 15, wherein, The memory controller and the at least one semiconductor memory device are mounted on a printed circuit board, and The multiple signal lines are arranged in a printed circuit board and connect the memory controller and the at least one semiconductor memory device.

18. A method of operating a storage device, wherein, The storage device includes a storage controller and at least one semiconductor memory device, the storage controller being configured to control the at least one semiconductor memory device, the method comprising: Training is performed by the memory controller when the training mode is sent to the at least one semiconductor memory device via signal lines to search for a first skew offset to minimize crosstalk occurring between signal lines; The storage controller stores the first skew offset as skew information in the register of the storage controller based on the training results; The skew information is sent by the memory controller to the at least one semiconductor memory device. The data signal is delayed by the first delay circuit of the storage controller, such that at least some of the first edges of the data signal are desynchronized by a first skew offset; The memory controller sends the delayed data signal and the data strobe signal to the at least one semiconductor memory device via signal lines; and The second delay circuit of the at least one semiconductor memory device delays the data signal based on skew information by using a second skew offset to eliminate the first skew offset, in order to provide the original data signal.

19. The method according to claim 18, wherein, The storage controller is configured to search for skew offsets by sequentially performing training on training patterns on the signal lines.

20. A storage device, comprising: At least one non-volatile memory device is configured to receive write data based on a data strobe signal and a plurality of data signals, and is configured to output read data based on the data strobe signal and the plurality of data signals; and The storage controller is configured to send a data strobe signal and the plurality of data signals in parallel to the at least one non-volatile memory device via multiple signal lines. in, Each of the plurality of data signals has a window defined by a first edge and a second edge; The storage controller includes a first delay circuit configured to delay the plurality of data signals such that at least some edges of the plurality of data signals are desynchronized by a first skew offset that is different from each other. The storage controller is configured to send skew information, including a first skew offset, to the at least one non-volatile memory device; and The at least one non-volatile memory device includes a second delay circuit configured to receive skew information and configured to delay the plurality of data signals based on the skew information by a second skew offset for eliminating the first skew offset, in order to provide the original data signal.

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