Multi-layer ceramic electronic component

Abstract

The present disclosure provides a multilayer ceramic electronic component. The multilayer ceramic electronic component includes a ceramic body, the ceramic body includes a dielectric layer, a first internal electrode and a second internal electrode, and the dielectric layer is interposed between the first internal electrode and the second internal electrode. The dielectric layer, the first internal electrode and the second internal electrode are arranged to be stacked to form a capacitance portion, and a first covering portion is provided on the capacitance portion, a second covering portion is provided under the capacitance portion, a first external electrode is connected to the first internal electrode, and a second external electrode is connected to the second internal electrode. The first covering portion and the second covering portion include a covering strengthening layer containing graphene.

Description

[0001] This application claims the benefit of priority to Korean Patent Application Nos. 10-2020-0102691, filed on August 14, 2020, and 10-2021-0000553, filed on January 4, 2021, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a multilayer ceramic electronic component. Background Art

[0003] Due to the thinning of multilayer ceramic capacitors (MLCCs) and the increase in their capacitance, the thickness of the dielectric layer between electrodes has also decreased, such that the allowable voltage per unit dielectric unit thickness has tended to continuously increase. However, in order to increase the effective volume, not only the thickness of the dielectric layer has decreased, but also the thickness of the cover layer and the thickness of the edges have tended to decrease, which reduces the strength of the MLCC. Cracks in the MLCC due to deformation of the substrate in the mounted state or cracks that occur after mounting may be due to cracks that occur during the sintering of the MLCC, but these cracks may also be due to a reduction in the strength of the MLCC itself caused by a decrease in the thickness of the cover layer and the thickness of the edges. Therefore, a method is needed to suppress the growth and propagation of cracks in the cover layer and edges having a reduced thickness. Summary of the Invention

[0004] Exemplary embodiments provide a multilayer ceramic electronic component having improved mechanical strength.

[0005] Exemplary embodiments provide a multilayer ceramic electronic component that suppresses the occurrence of cracks.

[0006] Exemplary embodiments provide a multilayer ceramic electronic component that suppresses the growth of pre-formed cracks.

[0007] According to one aspect of the present disclosure, a multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and a first internal electrode and a second internal electrode, the first internal electrode and the second internal electrode being arranged to face each other with the dielectric layer therebetween, a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode. The ceramic body includes a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction, and the ceramic body includes: a capacitor portion including the first internal electrode and the second internal electrode stacked in the third direction to form a capacitor; a first covering portion provided on one surface of the capacitor portion in the third direction; and a second covering portion provided on the other surface of the capacitor portion in the third direction. The first covering portion and / or the second covering portion includes a covering reinforcing layer containing graphene, and an average thickness of the covering reinforcing layer is 5% or more of an average thickness of the first covering portion or the second covering portion.

[0008] According to one aspect of the present disclosure, a multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and a first internal electrode and a second internal electrode, the first internal electrode and the second internal electrode being arranged to face each other with the dielectric layer therebetween, a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode. The ceramic body includes a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction, and the ceramic body includes: a capacitor portion including the first internal electrode and the second internal electrode stacked in the third direction to form a capacitor; a first edge portion provided on one surface of the capacitor portion in the second direction; and a second edge portion provided on the other surface of the capacitor portion in the second direction. The first edge portion and / or the second edge portion includes an edge reinforcing layer containing graphene, and an average thickness of the edge reinforcing layer is 5% or more of an average thickness of the first edge portion or the second edge portion. Description of the Drawings

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood by combining the drawings and the following detailed description. In the drawings:

[0010] Figure 1 is a perspective view schematically showing a multilayer ceramic electronic component according to an exemplary embodiment in the present disclosure;

[0011] Figure 2 is a perspective view schematically showing a capacitance portion of a multilayer ceramic electronic component according to an exemplary embodiment in the present disclosure;

[0012] Figure 3A is a cross-sectional view schematically showing an example in which a covering reinforcing layer is provided on the innermost side of a covering portion;

[0013] Figure 3B is a cross-sectional view schematically showing an example in which a covering reinforcing layer is provided on the outermost side of a covering portion;

[0014] Figure 3C is a cross-sectional view schematically showing an example in which a covering reinforcing layer is provided inside a covering portion;

[0015] Figure 4A is a cross-sectional view schematically showing an example in which an edge reinforcing layer is provided on the innermost side of an edge portion;

[0016] Figure 4B is a cross-sectional view schematically showing an example in which an edge reinforcing layer is provided on the outermost side of an edge portion; and

[0017] Figure 4C is a cross-sectional view schematically showing an example in which an edge reinforcing layer is provided inside an edge portion. Detailed Description

[0018] The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatuses, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will be readily apparent to those of ordinary skill in the art. The order of operations described herein is merely an example and is not limited to the order set forth herein, but rather, except for operations that must occur in a particular order, changes that will be readily apparent to those of ordinary skill in the art may be made. Additionally, descriptions of functions and constructions that are well known in the art may be omitted for the sake of clarity and conciseness.

[0019] The features described herein may be implemented in different forms and will not be construed as limited to the examples described herein. Rather, the examples described herein are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those of ordinary skill in the art.

[0020] Here, it should be noted that the use of the term "may" with respect to an example or exemplary embodiment (e.g., with respect to what an example or exemplary embodiment may include or implement) means that there is at least one example or exemplary embodiment that includes or implements such a feature, and is not limited to all examples or exemplary embodiments including or implementing such a feature.

[0021] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element can be directly "on" the other element, directly "connected to" the other element, or directly "coupled to" the other element, or there can be one or more other elements intervening between them. In contrast, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there are no other elements intervening between them.

[0022] As used herein, the term "and / or" includes any one or any combination of any two or more of the associated listed items.

[0023] Although terms such as "first", "second", and "third" may be used herein to describe various components, elements, regions, layers, or sections, these components, elements, regions, layers, or sections will not be limited by these terms. Rather, these terms are only used to distinguish one component, element, region, layer, or section from another component, element, region, layer, or section. Thus, a first component, first element, first region, first layer, or first section as referred to in the examples described herein may also be referred to as a second component, second element, second region, second layer, or second section without departing from the teachings of the examples.

[0024] For ease of description, spatial relative terms such as "above", "upper", "below", and "lower" may be used herein to describe the relationship of one element to another element as shown in the figures. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "above" or "upper" relative to another element will then be "below" or "lower" relative to the other element. Thus, the term "above" includes both the orientation of "above" and "below" depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0025] The terms used herein are for the purpose of describing various examples only and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. The terms "comprising", "including", and "having" enumerate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0026] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Accordingly, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

[0027] The features of the examples described herein can be combined in various ways that will be readily understood after understanding the disclosure of the present application. Additionally, while the examples described herein have various configurations, other configurations that will be readily understood after understanding the disclosure of the present application are possible.

[0028] The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative dimensions, proportions, and depictions of elements in the drawings may be exaggerated.

[0029] In the present disclosure, the X direction may be defined as the first direction, the L direction, or the length direction, the Y direction may be defined as the second direction, the W direction, or the width direction, and the Z direction may be defined as the third direction, the T direction, or the thickness direction.

[0030] Figure 1 is a perspective view schematically showing a multi-layer ceramic electronic component according to an exemplary embodiment in the present disclosure. Figure 2 is a perspective view schematically showing a capacitance portion of a multi-layer ceramic electronic component according to an exemplary embodiment in the present disclosure. Figure 3A is a cross-sectional view schematically showing an example in which a cover reinforcement layer is provided on the innermost side of a cover portion. Figure 3B is a cross-sectional view schematically showing an example in which a cover reinforcement layer is provided on the outermost side of a cover portion. Figure 3C is a cross-sectional view schematically showing an example in which a cover reinforcement layer is provided inside a cover portion. Figure 4A is a cross-sectional view schematically showing an example in which an edge reinforcement layer is provided on the innermost side of an edge portion. Figure 4B is a cross-sectional view schematically showing an example in which an edge reinforcement layer is provided on the outermost side of an edge portion. Figure 4C is a cross-sectional view schematically showing an example in which an edge reinforcement layer is provided inside an edge portion.

[0031] Referring to the accompanying drawings, a multilayer ceramic electronic component 100 according to the present disclosure includes a ceramic body 110, a first external electrode 131, and a second external electrode 132. The ceramic body 110 includes a dielectric layer 111, a first internal electrode 121, and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged to face each other, and the dielectric layer 111 is interposed between the first internal electrode 121 and the second internal electrode 122. The first external electrode 131 is connected to the first internal electrode 121, and the second external electrode 132 is connected to the second internal electrode 122. The ceramic body 110 may include a first surface S1 and a second surface S2 facing each other in a first direction, a third surface S3 and a fourth surface S4 facing each other in a second direction, and a fifth surface S5 and a sixth surface S6 facing each other in a third direction. The ceramic body 110 may include a capacitive portion A1 for forming a capacitor. The capacitive portion A1 includes the first internal electrode 121 and the second internal electrode 122 stacked in the third direction.

[0032] In an exemplary embodiment of the present disclosure, the multilayer ceramic electronic component may include a first covering portion C1 and a second covering portion C2. The first covering portion C1 is disposed on one surface of the capacitive portion A1 of the ceramic body 110 in the third direction and provides the fifth surface S5 of the ceramic body 110. The second covering portion C2 is disposed on the other surface of the capacitive portion A1 in the third direction and provides the sixth surface S6 of the ceramic body 110. The first covering portion C1 and / or the second covering portion C2 may include a covering strengthening layer R1 containing graphene.

[0033] In the present disclosure, "graphene" may refer to a material having a thickness corresponding to a single carbon atom layer while forming an arrangement in which carbon atoms are connected in a two-dimensional hexagonal shape through sp 2 bonds, and may refer to a material having the following structure: carbon atoms exfoliated from graphite having a three-dimensional structure as an allotrope are connected to each other in a hexagonal honeycomb shape to form a two-dimensional planar structure.

[0034] In the multilayer ceramic electronic component 100 of the present disclosure according to the exemplary embodiment, the covering portion C1 / C2 may include the covering strengthening layer R1 to improve the mechanical strength of the multilayer ceramic electronic component 100. The covering strengthening layer R1 can prevent cracks from appearing in the multilayer ceramic electronic component. In addition, the covering strengthening layer R1 may contain graphene to improve the compressive strength and tensile strength of the covering strengthening layer, and can inhibit the propagation of cracks that have already appeared to other regions.

[0035] In the above exemplary embodiment, the average thickness t1 of the cover reinforcement layer R1 may be 5% or more of the average thickness t2 of the first cover portion C1 or the second cover portion C2. In the present disclosure, the "thickness" of the cover portion C1 / C2 and / or the cover reinforcement layer R1 may refer to the thickness of the cover portion C1 / C2 and / or the cover reinforcement layer R1 measured in a direction perpendicular to the surface of the cover portion C1 / C2 and / or the cover reinforcement layer R1. The "average thickness" may be a value measured in the X-Z cutting plane (or Y-Z cutting plane) passing through the center of the multilayer ceramic electronic component for either the first cover portion C1 or the second cover portion C2, and a value measured for the cover reinforcement layer R1 disposed at the outermost position in the third direction, and may refer to the arithmetic mean of the thicknesses measured at ten equally spaced positions of the cover portion C1 / C2 and / or the cover reinforcement layer R1 in the first direction (or, if it is the Y-Z cutting plane, the second direction). The average thickness can be measured by, for example, a scanning electron microscope (SEM) or an optical microscope, but the measurement method or tool is not limited thereto. Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0036] The average thickness t1 of the cover reinforcement layer R1 being 5% or more of the average thickness of the first cover portion C1 or the second cover portion C2 means that the average thickness t1 of the cover reinforcement layer R1 is 0.05 times or more of the average thickness t2 of the first cover portion C1 or the second cover portion C2. If the average thickness t1 of the cover reinforcement layer R1 is less than 5% of the average thickness t2 of the first cover portion C1 or the second cover portion C2, the effect of improving the strength by using the cover reinforcement layer R1 cannot be sufficiently obtained.

[0037] In an example, the average thickness t1 of the cover reinforcement layer R1 included in the first cover portion C1 and / or the second cover portion C2 may be 50% or less of the average thickness t2 of the first cover portion C1 or the second cover portion C2. Since the average thickness t2 of the cover portion C1 / C2 and the average thickness t1 of the cover reinforcement layer R1 are the same as those described above, the description thereof will be omitted. If the average thickness t1 of the cover reinforcement layer R1 exceeds 50% of the average thickness t2 of the cover portion C1 / C2, mechanical strength deterioration will occur due to the difference in the shrinkage behavior between the cover reinforcement layer R1 and the cover portion C1 / C2 during the sintering process.

[0038] In another exemplary embodiment of the present disclosure, the multilayer ceramic electronic component may include a first edge portion M1 and a second edge portion M2. The first edge portion M1 is disposed on one surface of the capacitive portion A1 of the ceramic body 110 in the second direction and provides a fourth surface S4 of the ceramic body 110. The second edge portion M2 is disposed on the other surface of the capacitive portion A1 in the second direction and provides a third surface S3 of the ceramic body 110. And the first edge portion M1 and / or the second edge portion M2 may include an edge reinforcing layer R2 containing graphene. In the above exemplary embodiment, the average thickness of the edge reinforcing layer R2 may be 5% or more of the average thickness of the first edge portion M1 or the second edge portion M2.

[0039] In the above exemplary embodiment, the average thickness t3 of the edge reinforcing layer R2 may be 5% or more of the average thickness t4 of the first edge portion M1 or the second edge portion M2. In the present disclosure, the "thickness" of the edge portion M1 / M2 and / or the edge reinforcing layer R2 may refer to the thickness of the edge portion M1 / M2 and / or the edge reinforcing layer R2 measured in a direction perpendicular to the surface of the edge portion M1 / M2 and / or the edge reinforcing layer R2. The "average thickness" may be a value measured in the X-Y cutting plane (or Y-Z cutting plane) passing through the center of the multilayer ceramic electronic component for any one of the first edge portion M1 and the second edge portion M2, and a value measured for the edge reinforcing layer R2 disposed at the outermost position in the second direction, and may refer to the arithmetic average of the thicknesses measured at ten equally spaced positions of the edge portion M1 / M2 and / or the edge reinforcing layer R2 in the third direction (or the first direction).

[0040] The average thickness t3 of the edge reinforcing layer R2 being 5% or more of the average thickness of the first edge portion M1 or the second edge portion M2 means that the average thickness t3 of the edge reinforcing layer R2 is 0.05 times or more of the average thickness of the first edge portion M1 or the second edge portion M2. If the average thickness t3 of the edge reinforcing layer R2 is less than 5% of the average thickness t4 of the first edge portion M1 or the second edge portion M2, the effect of improving the strength by using the edge reinforcing layer cannot be fully obtained.

[0041] In the example, the average thickness t3 of the edge reinforcing layer R2 included in the first edge portion M1 and / or the second edge portion M2 may be 50% or less of the average thickness t4 of the first edge portion M1 or the second edge portion M2. Since the average thickness t4 of the edge portion M1 / M2 and the average thickness t3 of the edge reinforcing layer R2 are the same as those described above, their descriptions will be omitted. If the average thickness t3 of the edge reinforcing layer R2 exceeds 50% of the average thickness t4 of the edge portion M1 / M2, mechanical strength deterioration will occur due to the difference in shrinkage behavior between the edge reinforcing layer and the edge portion during the sintering process.

[0042] In an example, the multi-layer ceramic electronic component of the present disclosure may include both the above-described cover reinforcing layer R1 and the edge reinforcing layer R2. Since the cover reinforcing layer R1 and the edge reinforcing layer R2 are the same as those described above, their descriptions will be omitted.

[0043] The ceramic body 110 of the multi-layer ceramic electronic component 100 according to the present disclosure may include a capacitance portion A1.

[0044] There is no particular limitation on the specific shape of the capacitance portion A1, and the capacitance portion A1 may have a hexahedral shape or a similar shape as shown in the figure. Due to the shrinkage of the ceramic powder particles included in the capacitance portion during sintering, the capacitance portion A1 may not have a perfect straight hexahedral shape, but may have a generally hexahedral shape. If necessary, the corners of the capacitance portion A1 may be rounded so that the corners are not angular. Rounding can be performed using, for example, barrel polishing, but is not limited thereto.

[0045] In the capacitance portion of the multi-layer ceramic electronic component according to the present disclosure, the dielectric layer 111, the first internal electrode 121, and the second internal electrode 122 may be alternately stacked. The dielectric layer 111, the first internal electrode 121, and the second internal electrode 122 may be stacked in the third direction (Z direction). The plurality of dielectric layers 111 forming the capacitance portion are in a sintered state, and adjacent dielectric layers 111 may be integrated such that their boundaries are not obvious without using a scanning electron microscope (SEM).

[0046] According to an exemplary embodiment of the present disclosure, the material for forming the dielectric layer 111 is not limited as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material may be used, or a composition represented by (Ba 1-x Ca x )(Ti 1-y (Zr, Sn, Hf) y )O 3 (0 ≤ x ≤ 1, 0 ≤ y ≤ 0.5) may be used. For the purpose of the present disclosure, various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be added to powder particles (such as barium titanate (BaTiO 3 ) etc.) as the material for forming the dielectric layer 111.

[0047] In an exemplary embodiment of the present disclosure, the dielectric layer of the capacitance portion of the multi-layer ceramic electronic component of the present disclosure may include crystal grains and grain boundaries. The dielectric layer of the capacitance portion may include a plurality of crystal grains and grain boundaries provided between two or more crystal grains. The crystal grains may be distinguished by the grain boundaries.

[0048] The dielectric layer 111 can be formed by adding necessary additives to a slurry containing the above materials, coating the slurry onto a carrier film, and drying the slurry to prepare a plurality of ceramic sheets. The ceramic sheets can be formed by making the slurry into sheets with a thickness of several micrometers using a doctor blade method, but it is not limited thereto.

[0049] In the example, the average thickness of the dielectric layer 111 can be 0.4 μm or less. The average thickness of the dielectric layer 111 can be the average value of the values measured at five different positions of the fired dielectric layer 111. The lower limit of the average thickness of the dielectric layer 111 is not particularly limited, but can be, for example, 0.01 μm or more.

[0050] The first internal electrode 121 and the second internal electrode 122 can be stacked such that their respective cross-sections are exposed at opposite ends of the capacitor portion. For example, the cross-section of the first internal electrode 121 and the cross-section of the second internal electrode 122 can extend from, be connected to, and / or contact opposite ends of the capacitor portion. Specifically, the first internal electrode 121 and the second internal electrode 122 can be exposed at, connected to, extend from, and / or contact two surfaces of the capacitor portion in the first direction (X direction). The first internal electrode 121 can be exposed to, connected to, extend from, and / or contact the first surface S1. The second internal electrode 122 can be exposed to, connected to, extend from, and / or contact the second surface S2.

[0051] The materials for forming the first internal electrode 121 and the second internal electrode 122 are not particularly limited. For example, the first internal electrode 121 and the second internal electrode 122 can be formed using a conductive paste including at least one of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), titanium (Ti), and their alloys.

[0052] The capacitor portion A1 can be formed by alternately stacking green ceramic sheets printed with the first internal electrode 121 and green ceramic sheets printed with the second internal electrode 122 in the third direction (Z direction). A screen printing method or a gravure printing method can be used to print the first internal electrode 121 and the second internal electrode 122, but it is not limited thereto.

[0053] The average thickness of the first internal electrode 121 and the second internal electrode 122 can be 0.4 μm or less. The average thickness of the internal electrodes can be the average value of the values measured at five different positions of the fired internal electrodes. The lower limit of the average thickness of the first internal electrode and the second internal electrode is not particularly limited, but can be, for example, 0.01 μm or more.

[0054] In an exemplary embodiment of the present disclosure, a multilayer ceramic electronic component according to the present disclosure may include a first covering portion C1 and a second covering portion C2. The first covering portion C1 and the second covering portion C2 may be disposed on two surfaces of the capacitor portion A1 in a third direction. Specifically, the first covering portion C1 may be disposed on the upper surface of the capacitor portion A1 in the third direction, and the second covering portion C2 may be disposed on the lower surface of the capacitor portion A1 in the third direction.

[0055] Here, the first covering portion C1 and the second covering portion C2 may include components identical to those of the dielectric layer, and may be formed by stacking at least one dielectric layer not including internal electrodes on two surfaces of the capacitor portion in a third direction. The first covering portion and the second covering portion may be substantially used to prevent damage to the internal electrodes due to physical stress or chemical stress.

[0056] The first covering portion C1 and the second covering portion C2 may include a plurality of crystal grains and grain boundaries disposed between adjacent crystal grains. The covering portion may contain graphene and a ceramic material identical to the ceramic material of the dielectric layer. Similar to the above dielectric layer, the ceramic material identical to the ceramic material of the dielectric layer may include a plurality of crystal grains and grain boundaries disposed between two or more crystal grains.

[0057] In an example of the present disclosure, the average grain size of the crystal grains of the first covering portion C1 of the multilayer ceramic electronic component 100 of the present disclosure and / or the average grain size of the crystal grains of the second covering portion C2 may be smaller than the average grain size of the crystal grains included in the dielectric layer 111 of the above capacitor portion. In the present disclosure, the "average grain size" may refer to the arithmetic average of the grain sizes measured at ten positions on a cutting plane passing through the center of the multilayer ceramic electronic component 100. The ten positions of the dielectric layer may be ten equally spaced positions on the center line of the dielectric layer in a first direction along the X-Z cutting plane closest to the center of the multilayer ceramic electronic component. In addition, the ten positions of the covering portion may be ten equally spaced positions on the center line of the first covering portion and / or the second covering portion in a first direction in the X-Z cutting plane passing through the center of the multilayer ceramic electronic component. The average grain size may refer to the D50 grain size. The measured grain size of the crystal grains may be calculated by an image analysis program (ImageProPlus ver4.5 of Mediacybernetics) after capturing images of the cutting planes of the dielectric layer 111 and the covering portions C1 and C2 using a scanning electron microscope (SEM) (JSM-7400F of Jeol). Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0058] The maximum thickness of the first covering portion C1 and the second covering portion C2 may be, for example, 50 μm or less. The lower limit of the maximum thickness of the first covering portion C1 and the second covering portion C2 is not particularly limited, but may be, for example, 0.1 μm or more.

[0059] In a multilayer ceramic electronic component according to an exemplary embodiment of the present disclosure, the first covering portion C1 and the second covering portion C2 may include a covering reinforcing layer R1. The covering reinforcing layer R1 may include an insulating material and graphene, and the insulating material may be formed of a ceramic material such as barium titanate. In this case, the covering reinforcing layer R1 may include the same ceramic material as the ceramic material included in the dielectric layer 111, or the covering reinforcing layer R1 may include the same material as the material of the dielectric layer 111. Similar to the above dielectric layer, the ceramic material the same as the ceramic material of the dielectric layer 111 may include a plurality of crystal grains and grain boundaries disposed between two or more crystal grains. In this case, the graphene included in the covering reinforcing layer R1 may be located at the grain boundaries. The graphene may be discontinuously dispersed in the grain boundaries.

[0060] The graphene may be one or more selected from the group consisting of graphene, high-quality graphene (HQG), graphene oxide (GO), and reduced graphene oxide (RGO), and the high-quality graphene may refer to graphene in which the formation of domain boundaries is suppressed.

[0061] In an example, based on the weight of the ceramic material (such as barium titanate) included in the covering reinforcing layer R1, the proportion of graphene included in the covering reinforcing layer may be 0.001 w% to 50 w%. This value may be a value measured for the covering reinforcing layer at the outermost position in the third direction in the X-Z cutting plane passing through the center of the multilayer ceramic electronic component, and this value may be a value measured at 10 equally spaced positions in the first direction, and this value may be a value measured by oxidizing the covering reinforcing layer in an oxygen atmosphere.

[0062] In addition, based on the number of 50-nm-sized crystal grains in the dielectric layer 111, the number of graphene included in the covering reinforcing layer R1 may be greater than or equal to 10 ppm and less than or equal to 200,000 ppm.

[0063] In an exemplary embodiment of the present disclosure, the covering reinforcing layer R1 of the multilayer ceramic electronic component of the present disclosure may have a 2D peak separated from the G peak in a Raman spectrum. The Raman spectrum may be a value measured using a Raman spectrometer LabRamHR-800 manufactured by HORIBA, Ltd., Japan. The presence of graphene can be determined through the Raman spectrum, and graphene can be distinguished from other carbon allotropes, and in the grain boundaries of a multilayer capacitor according to another aspect of the present disclosure, when Raman analysis is performed, peaks are detected in the 2D band and the G band. However, the shape and intensity of the 2D band may vary depending on the group of graphene applied (for example, a group composed of graphene and other materials). Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0064] In an exemplary embodiment of the present disclosure, the covering reinforcement layer R1 included in the covering part C1 / C2 may have a plate-like shape. The covering reinforcement layer R1 may be formed of a ceramic sheet prepared by coating a slurry including a dielectric material and graphene on a carrier film and drying the slurry.

[0065] In an exemplary embodiment of the present disclosure, as Figure 3A shown, the covering reinforcement layer R1 may be disposed at the innermost side of the covering part C1 / C2. When the covering reinforcement layer R1 is disposed on the innermost side of the covering part, this may mean that the covering reinforcement layer R1 is disposed to contact the capacitance part A1. In this case, the covering reinforcement layer R1 of the upper covering part (i.e., the first covering part) C1 may be located at the bottom of the upper covering part C1, and the covering reinforcement layer R1 of the lower covering part (i.e., the second covering part) C2 may be located at the top of the lower covering part C2.

[0066] In another exemplary embodiment of the present disclosure, as Figure 3B shown, the covering reinforcement layer R1 may be disposed on the outermost side of the covering part C1 / C2. When the covering reinforcement layer R1 is disposed on the outermost side of the covering part C1 / C2, this may mean that the covering reinforcement layer R1 is disposed to be exposed to, connected to, extend from, or in contact with the outer surface of the ceramic body, or is disposed as at least a part of the outer surface of the ceramic body. In this case, the covering reinforcement layer R1 of the upper covering part C1 may be located at the top of the upper covering part C1, and the covering reinforcement layer R1 of the lower covering part C2 may be located at the bottom of the lower covering part C2.

[0067] In an example, as Figure 3C shown, the covering reinforcement layer R1 may be disposed inside the covering part. When the covering reinforcement layer R1 is disposed inside the covering part C1 / C2, this may mean that the covering reinforcement layer R1 is disposed in the space between the interface between the capacitance part A1 and the covering part C1 / C2 and the outer surface of the ceramic body, and may mean that the covering reinforcement layer R1 is disposed to be spaced apart from the capacitance part A1 and the outer surface of the ceramic body in a third direction.

[0068] According to an exemplary embodiment of the present disclosure, the maximum thickness of the covering reinforcement layer R1 may be in the range of greater than or equal to 0.1 μm and less than or equal to 50 μm. The maximum thickness of the covering reinforcement layer R1 may be a value measured for the covering reinforcement layer at the outermost position disposed in the third direction in the X-Z cutting plane passing through the center of the multilayer ceramic electronic component, and may refer to the maximum value of the thickness of the covering reinforcement layer at the outermost position.

[0069] In an example, in a multilayer ceramic electronic component according to the present disclosure, a plurality of covering reinforcement layers R1 may be provided in one covering portion C1 / C2. When a plurality of covering reinforcement layers are provided in one covering portion, this may mean that two or more covering reinforcement layers R1 separated from the covering portion C1 / C2 are provided in the covering portion C1 / C2. Two or more covering reinforcement layers R1 may be included in one covering portion C1 / C2. For example, less than or equal to 50 covering reinforcement layers R1 may be included.

[0070] According to another exemplary embodiment of the present disclosure, a multilayer ceramic electronic component of the present disclosure may include a ceramic body, a first external electrode 131, and a second external electrode 132. The ceramic body includes a capacitive portion A2, a first edge portion M1, and a second edge portion M2. The capacitive portion A2 includes a dielectric layer 111, a first internal electrode 121, and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged and stacked in a third direction so as to face each other, and the dielectric layer 111 is interposed between the first internal electrode 121 and the second internal electrode 122. The capacitive portion A2 includes a first surface S1 and a second surface S2 facing each other in a first direction (X direction), a third surface S3 and a fourth surface S4 facing each other in a second direction (Y direction), and a fifth surface S5 and a sixth surface S6 facing each other in a third direction (Z direction). The first edge portion M1 is provided on the fourth surface S4 of the capacitive portion, and the second edge portion M2 is provided on the third surface S3 of the capacitive portion. The first external electrode 131 is connected to the first internal electrode 121, and the second external electrode 132 is connected to the second internal electrode 122.

[0071] In this case, the first edge portion M1 and the second edge portion M2 may include an edge reinforcement layer R2 containing graphene. In a multilayer ceramic electronic component of the present disclosure according to an exemplary embodiment of the present disclosure, the edge portions M1 / M2 may include an edge reinforcement layer R2 to improve the mechanical strength of the multilayer ceramic electronic component. The edge reinforcement layer may prevent cracks from appearing in the multilayer ceramic electronic component. In addition, the edge reinforcement layer may include graphene to improve the compressive strength and tensile strength of the edge reinforcement layer, and may inhibit the propagation of cracks that have already appeared to other regions.

[0072] In an exemplary embodiment of the present disclosure, a multilayer ceramic electronic component according to the present disclosure may include a first edge portion M1 and a second edge portion M2. The first edge portion M1 and the second edge portion M2 may be provided on two surfaces of the capacitive portion A2 in a second direction. Specifically, the first edge portion M1 may be provided on the fourth surface S4 of the capacitive portion A2, and the second edge portion M2 may be provided on the third surface S3 of the capacitive portion A2.

[0073] In this case, the first edge portion M1 and the second edge portion M2 may include the same components as those of the dielectric layer 111, and may be formed by stacking at least one dielectric layer not including an inner electrode on both sides of the capacitor portion A2 in the second direction, respectively.

[0074] The first edge portion M1 and the second edge portion M2 may include a plurality of crystal grains and grain boundaries disposed between adjacent crystal grains. The edge portions M1 / M2 may include graphene and the same ceramic material as the ceramic material of the dielectric layer. Similar to the above dielectric layer, the same ceramic material as the ceramic material of the dielectric layer may include a plurality of crystal grains and grain boundaries disposed between two or more crystal grains.

[0075] In an example of the present disclosure, the average grain size of the crystal grains of the first edge portion M1 and / or the second edge portion M2 of the multilayer ceramic electronic component 100 of the present disclosure may be smaller than the average grain size of the crystal grains included in the dielectric layer 111 of the above capacitor portion. In the present disclosure, the "average grain size" may refer to the arithmetic average of the grain sizes measured at ten positions on the cutting plane of the multilayer ceramic electronic component 100. The ten positions of the dielectric layer may be ten equally spaced positions on the center line of the dielectric layer in the second direction along the Y-Z cutting plane closest to the center passing through the center of the multilayer ceramic electronic component. In addition, the ten positions of the edge portion may be ten equally spaced positions on the center line of the first edge portion and / or the second edge portion in the third direction in the Y-Z cutting plane passing through the center of the multilayer ceramic electronic component. The average grain size may refer to the D50 grain size. The measured grain size of the crystal grains may be calculated by an image analysis program (ImageProPlus ver4.5 of Mediacybernetics) after capturing an image of the cutting plane of the dielectric layer 111 / edge portion using a scanning electron microscope (SEM) (JSM-7400F of Jeol). Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0076] The maximum thickness of the first edge portion M1 and the second edge portion M2 may be, for example, 50 μm or less. The lower limit of the maximum thickness of the first edge portion M1 and the second edge portion M2 is not particularly limited, but may be, for example, 0.1 μm or more.

[0077] In a multilayer ceramic electronic component according to an exemplary embodiment of the present disclosure, a first edge portion M1 and a second edge portion M2 may include an edge reinforcing layer R2. The edge reinforcing layer R2 may include an insulating material and graphene, and the insulating material may be formed of a ceramic material such as barium titanate. In this case, the edge reinforcing layer R2 may include the same ceramic material as that included in the dielectric layer, or may include the same material as the material of the dielectric layer. Similar to the dielectric layer described above, the ceramic material having the same material as the dielectric layer may include a plurality of crystal grains and grain boundaries disposed between two or more crystal grains. In this case, the graphene included in the edge reinforcing layer R2 may be located at the grain boundaries. The graphene may be discontinuously dispersed in the grain boundaries.

[0078] The graphene may be one or more selected from the group consisting of graphene, high-quality graphene (HQG), graphene oxide (GO), and reduced graphene oxide (RGO), and the high-quality graphene may refer to graphene in which the formation of domain boundaries is suppressed.

[0079] In an example, based on the weight of the ceramic material (such as barium titanate) included in the edge reinforcing layer, the proportion of graphene included in the edge reinforcing layer R2 may be 0.001 w% to 50 w%. This value may be a value measured for the edge reinforcing layer at the outermost position in the second direction in a Y-Z cutting plane passing through the center of the multilayer ceramic electronic component, and this value may be a value measured at 10 equally spaced positions in the third direction, and this value may be a value measured by oxidizing the edge reinforcing layer in an oxygen atmosphere.

[0080] In addition, based on the number of 50-nm-sized crystal grains in the dielectric layer, the number of graphene included in the edge reinforcing layer R2 may be greater than or equal to 10 ppm and less than or equal to 200,000 ppm.

[0081] In an exemplary embodiment of the present disclosure, the edge reinforcing layer R2 of the multilayer ceramic electronic component of the present disclosure may have a 2D peak separated from the G peak in a Raman spectrum. The Raman spectrum may be a value measured using a Raman spectrometer LabRamHR-800 manufactured by HORIBA, Ltd., Japan. The presence of graphene can be determined by the Raman spectrum, and graphene can be distinguished from other carbon allotropes. In the grain boundaries of a multilayer capacitor according to another aspect of the present disclosure, when Raman analysis is performed, peaks are detected in the 2D band and the G band. However, the shape and intensity of the 2D band may vary depending on the group of graphene applied. Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0082] In an exemplary embodiment of the present disclosure, the edge reinforcement layer included in the edge portion may have a plate-like shape. The edge reinforcement layer may be formed of a ceramic sheet, which is prepared by coating a slurry including a dielectric material and graphene on a carrier film and drying the slurry.

[0083] In an exemplary embodiment of the present disclosure, as Figure 4A shown, the edge reinforcement layer may be disposed at the innermost side of the edge portion M1 / M2. When the edge reinforcement layer R2 is disposed at the innermost side of the edge portion M1 / M2, this may mean that the edge reinforcement layer R2 is disposed in contact with the capacitor portion A2. In this case, the edge reinforcement layers R2 of the edge portions M1 and M2 may be disposed in contact with the fourth surface and the third surface of the capacitor portion A2, respectively.

[0084] In another exemplary embodiment of the present disclosure, as Figure 4B shown, the edge reinforcement layer R2 may be disposed at the outermost side of the edge portion M1 / M2. When the edge reinforcement layer R2 is disposed at the outermost side of the edge portion M1 / M2, this may mean that the edge reinforcement layer R2 is disposed to be exposed to, connected to, extending from, or in contact with the outer surface of the ceramic body, or the edge reinforcement layer R2 is disposed as at least a part of the outer surface of the ceramic body. In this case, the edge reinforcement layer R2 may be disposed to be exposed to, connected to, extending from, or in contact with the two surfaces of the ceramic body in the second direction.

[0085] In an example, as Figure 4C shown, the edge reinforcement layer R2 may be disposed inside the edge portion M1 / M2. When the edge reinforcement layer R2 is disposed inside the edge portion M1 / M2, this may mean that the edge reinforcement layer R2 is disposed in the space between the interface between the capacitor portion A2 and the edge portion M1 / M2 and the outer surface of the ceramic body, and the edge reinforcement layer R2 is disposed to be spaced apart from the outer surfaces of the capacitor portion and the ceramic body in the second direction.

[0086] According to an exemplary embodiment of the present disclosure, the maximum thickness of the edge reinforcement layer R2 may be in the range of greater than or equal to 0.1 μm and less than or equal to 50 μm. The maximum thickness of the edge reinforcement layer R2 may be a value measured for the edge reinforcement layer R2 at the outermost position in the second direction in a Y-Z cutting plane passing through the center of the multilayer ceramic electronic component, and may refer to the maximum value of the thickness of the edge reinforcement layer at the outermost position.

[0087] In an example, in a multilayer ceramic electronic component according to the present disclosure, a plurality of edge reinforcing layers R2 may be provided in one edge portion M1 / M2. When a plurality of edge reinforcing layers R2 are provided in one edge portion M1 / M2, this may mean that two or more edge reinforcing layers R2 separated from the edge portion M1 / M2 are provided in the edge portion M1 / M2. Two or more edge reinforcing layers R2 may be included in one edge portion M1 / M2. For example, less than or equal to 50 edge reinforcing layers R2 may be included.

[0088] In the above exemplary embodiment, the descriptions of the dielectric layer, the internal electrode, the ceramic body, etc. are the same as above, and thus their detailed descriptions will be omitted.

[0089] In another exemplary embodiment of the present disclosure, the multilayer ceramic electronic component of the present disclosure may include a first edge portion and a second edge portion respectively provided on two surfaces of the capacitive portion in the second direction, and a first covering portion and a second covering portion respectively provided on two surfaces of the capacitive portion in the third direction. The first covering portion and / or the second covering portion may include a covering reinforcing layer containing graphene, and the first edge portion and / or the second edge portion may include an edge reinforcing layer containing graphene.

[0090] In the above exemplary embodiment, the edge portion may include an edge reinforcing layer, and the covering portion may include a covering reinforcing layer. In this case, the covering portion may be attached after the edge portion is first attached to the capacitive portion, but is not limited thereto, and the edge portion may be attached after the covering portion is first attached.

[0091] In the above exemplary embodiment, the descriptions of the edge reinforcing layer and the covering reinforcing layer are the same as above, and thus their detailed descriptions will be omitted.

[0092] The multilayer ceramic electronic component according to the present disclosure may include a first external electrode 131 connected to the first internal electrode 121 and a second external electrode 132 connected to the second internal electrode 122. The first external electrode 131 may be provided on the first surface S1. Additionally, the second external electrode 132 may be provided on the second surface S2.

[0093] The first external electrode 131 and the second external electrode 132 may be formed using a conductive paste containing a conductive metal and glass. The first external electrode 131 and the second external electrode 132 may be sintered electrodes formed by firing the conductive paste. The conductive metal included in the first external electrode 131 and the second external electrode 132 is not particularly limited, and may be, for example, one or more of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and their alloys.

[0094] The glass may be, for example, one or more selected from the group consisting of silicon (Si), boron (B), aluminum (Al), transition metals, alkali metals, alkaline earth metals, their nitrides, carbides, and carbonates, but is not limited thereto. The transition metals may be one or more selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), and the alkali metals may be one or more selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metals may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0095] According to an exemplary embodiment of the present disclosure, the first outer electrode 131 and the second outer electrode 132 of the present disclosure may be formed by transferring a conductive paste sheet. In the multilayer ceramic electronic component according to the present disclosure, since the first outer electrode 131 and the second outer electrode 132 are formed by a transfer method, the first outer electrode and the second outer electrode may have a uniform thickness, and even at the corners of the ceramic body, the first outer electrode and the second outer electrode may be uniformly formed.

[0096] In another exemplary embodiment of the present disclosure, the first outer electrode 131 and the second outer electrode 132 of the present disclosure may be formed by dipping the ceramic body into a conductive paste.

[0097] In an example of the present disclosure, a plating layer may be provided on the first outer electrode and the second outer electrode of the multilayer ceramic electronic component according to the present disclosure. The plating layer may be formed as a single layer or may include multiple layers. The plating layer may include at least one of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), palladium (Pd), titanium (Ti), and their alloys, but is not limited thereto. The plating layer may be formed by sputtering or electroplating, but is not limited thereto.

[0098] As described above, one of several effects according to the present disclosure may provide a multilayer ceramic electronic component having improved mechanical strength.

[0099] One of several effects according to the present disclosure may provide a multilayer ceramic electronic component capable of suppressing the occurrence of cracks.

[0100] One of various effects of the present disclosure may provide a multilayer ceramic electronic component capable of suppressing the growth of pre-formed cracks.

[0101] Although the exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. A multilayer ceramic electronic component, comprising: a ceramic body including a dielectric layer, a first internal electrode, and a second internal electrode, the first internal electrode and the second internal electrode being arranged to face each other and the dielectric layer being interposed between the first internal electrode and the second internal electrode; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein the ceramic body includes a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction, and the ceramic body includes: a capacitor portion including the first internal electrode and the second internal electrode stacked in the third direction to form a capacitor; a first covering portion provided on one surface of the capacitor portion in the third direction; and a second covering portion provided on the other surface of the capacitor portion in the third direction, wherein the first covering portion and / or the second covering portion includes a covering strengthening layer containing graphene, and the average thickness of the covering strengthening layer is 5% or more and 50% or less of the average thickness of the first covering portion, or the average thickness of the covering strengthening layer is 5% or more and 50% or less of the average thickness of the second covering portion.

2. The multilayer ceramic electronic component according to claim 1, wherein, the ceramic body further includes: a first edge portion provided on one surface of the capacitor portion in the second direction, and a second edge portion provided on the other surface of the capacitor portion in the second direction, wherein the first edge portion and / or the second edge portion includes an edge strengthening layer containing graphene, and the average thickness of the edge strengthening layer is 5% or more of the average thickness of the first edge portion or 5% or more of the average thickness of the second edge portion.

3. The multilayer ceramic electronic component according to claim 2, wherein, the average thickness of the edge strengthening layer is 50% or less of the average thickness of the first edge portion or 50% or less of the average thickness of the second edge portion.

4. The multilayer ceramic electronic component according to any one of claims 1-3, wherein, the covering strengthening layer is arranged to be in contact with the capacitor portion.

5. The multilayer ceramic electronic component according to any one of claims 1-3, wherein, the covering strengthening layer provides at least a part of one of the fifth surface and the sixth surface of the ceramic body.

6. The multilayer ceramic electronic component according to any one of claims 1-3, wherein, the covering strengthening layer is spaced apart from the surface of the ceramic body and the capacitor portion.

7. The multilayer ceramic electronic component according to claim 1, wherein, the covering strengthening layer is arranged in a plurality.

8. The multilayer ceramic electronic component according to claim 1, wherein, the capacitor portion does not contain graphene.

9. The multilayer ceramic electronic component according to any one of claims 1-3, wherein, The dielectric layer in the capacitor portion, the first covering portion, and the second covering portion all include crystal grains and grain boundaries, and the average grain size of the crystal grains in at least one of the first covering portion and the second covering portion is smaller than the average grain size of the crystal grains in the dielectric layer in the capacitor portion.

10. The multilayer ceramic electronic component according to any one of claims 1-3, wherein, the covering strengthening layer includes crystal grains and grain boundaries, and the graphene is disposed in the grain boundaries.

11. The multilayer ceramic electronic component according to claim 1, wherein, the average thickness of the dielectric layer is greater than or equal to 0.01 μm and less than or equal to 0.4 μm.

12. The multilayer ceramic electronic component according to claim 1, wherein, the average thickness of the first inner electrode and the second inner electrode is greater than or equal to 0.01 μm and less than or equal to 0.4 μm.

13. A multilayer ceramic electronic component, comprising: a ceramic body including a dielectric layer, a first inner electrode, and a second inner electrode, the first inner electrode and the second inner electrode being arranged to face each other and the dielectric layer being interposed between the first inner electrode and the second inner electrode; a first outer electrode connected to the first inner electrode; and a second outer electrode connected to the second inner electrode, wherein the ceramic body includes a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction, and the ceramic body includes: a capacitor portion including the first inner electrode and the second inner electrode stacked in the third direction to form a capacitor, a first edge portion provided on one surface of the capacitor portion in the second direction, and a second edge portion provided on the other surface of the capacitor portion in the second direction, wherein the first edge portion and / or the second edge portion includes an edge strengthening layer containing graphene, and the average thickness of the edge strengthening layer is 5% or more and 50% or less of the average thickness of the first edge portion, or the average thickness of the edge strengthening layer is 5% or more and 50% or less of the average thickness of the second edge portion.

14. The multilayer ceramic electronic component according to claim 13, wherein, the edge strengthening layer is arranged to be in contact with the capacitor portion.

15. The multilayer ceramic electronic component according to claim 13, wherein, the edge strengthening layer provides at least a part of one of the third surface and the fourth surface of the ceramic body.

16. The multilayer ceramic electronic component according to claim 13, wherein, the edge strengthening layer is spaced apart from the surface of the ceramic body and the capacitor portion.

17. The multilayer ceramic electronic component according to claim 13, wherein, the edge strengthening layer is provided in a plurality.

18. The multilayer ceramic electronic component according to claim 13, wherein, the capacitor portion does not contain graphene.

19. The multilayer ceramic electronic component according to claim 13, wherein, The dielectric layer in the capacitor portion, the first edge portion, and the second edge portion all include grains and grain boundaries, and the average grain size of the grains in at least one of the first edge portion and the second edge portion is smaller than the average grain size of the grains in the dielectric layer in the capacitor portion.

20. The multilayer ceramic electronic component according to claim 13, wherein, the edge strengthening layer includes grains and grain boundaries, and the graphene is disposed in the grain boundaries.

21. The multilayer ceramic electronic component according to claim 13, wherein, the average thickness of the dielectric layer is greater than or equal to 0.01 μm and less than or equal to 0.4 μm.

22. The multilayer ceramic electronic component according to claim 13, wherein, the average thickness of the first inner electrode and the second inner electrode is greater than or equal to 0.01 μm and less than or equal to 0.4 μm.

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